1 /* 2 * Copyright (c) 2015-2024, Broadcom. All rights reserved. The term 3 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Description: Uverbs ABI header file 29 */ 30 31 #ifndef __BNXT_RE_UVERBS_ABI_H__ 32 #define __BNXT_RE_UVERBS_ABI_H__ 33 34 #include <asm/types.h> 35 #include <linux/types.h> 36 37 #define BNXT_RE_ABI_VERSION 7 38 39 enum { 40 BNXT_RE_COMP_MASK_UCNTX_WC_DPI_ENABLED = 0x01, 41 BNXT_RE_COMP_MASK_UCNTX_POW2_DISABLED = 0x02, 42 BNXT_RE_COMP_MASK_UCNTX_RSVD_WQE_DISABLED = 0x04, 43 BNXT_RE_COMP_MASK_UCNTX_MQP_EX_SUPPORTED = 0x08, 44 BNXT_RE_COMP_MASK_UCNTX_DBR_PACING_ENABLED = 0x10, 45 BNXT_RE_COMP_MASK_UCNTX_DBR_RECOVERY_ENABLED = 0x20, 46 BNXT_RE_COMP_MASK_UCNTX_HW_RETX_ENABLED = 0x40, 47 BNXT_RE_COMP_MASK_UCNTX_CMASK_HAVE_MODE = 0x80, 48 }; 49 50 enum { 51 BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT = 0x01, 52 BNXT_RE_COMP_MASK_REQ_UCNTX_RSVD_WQE = 0x02, 53 BNXT_RE_COMP_MASK_REQ_UCNTX_VAR_WQE_SUPPORT = 0x03 54 }; 55 56 struct bnxt_re_uctx_req { 57 __aligned_u64 comp_mask; 58 }; 59 60 #define BNXT_RE_CHIP_ID0_CHIP_NUM_SFT 0x00 61 #define BNXT_RE_CHIP_ID0_CHIP_REV_SFT 0x10 62 #define BNXT_RE_CHIP_ID0_CHIP_MET_SFT 0x18 63 struct bnxt_re_uctx_resp { 64 __u32 dev_id; 65 __u32 max_qp; 66 __u32 pg_size; 67 __u32 cqe_sz; 68 __u32 max_cqd; 69 __u32 chip_id0; 70 __u32 chip_id1; 71 __u32 mode; 72 __aligned_u64 comp_mask; 73 } __attribute__((packed)); 74 75 enum { 76 BNXT_RE_COMP_MASK_PD_HAS_WC_DPI = 0x01, 77 BNXT_RE_COMP_MASK_PD_HAS_DBR_BAR_ADDR = 0x02, 78 }; 79 80 struct bnxt_re_pd_resp { 81 __u32 pdid; 82 __u32 dpi; 83 __u64 dbr; 84 __u64 comp_mask; 85 __u32 wcdpi; 86 __u64 dbr_bar_addr; 87 } __attribute__((packed)); 88 89 enum { 90 BNXT_RE_COMP_MASK_CQ_HAS_DB_INFO = 0x01, 91 BNXT_RE_COMP_MASK_CQ_HAS_WC_DPI = 0x02, 92 BNXT_RE_COMP_MASK_CQ_HAS_CQ_PAGE = 0x04, 93 }; 94 95 enum { 96 BNXT_RE_COMP_MASK_CQ_REQ_HAS_CAP_MASK = 0x1 97 }; 98 99 enum { 100 BNXT_RE_COMP_MASK_CQ_REQ_CAP_DBR_RECOVERY = 0x1, 101 BNXT_RE_COMP_MASK_CQ_REQ_CAP_DBR_PACING_NOTIFY = 0x2 102 }; 103 104 #define BNXT_RE_IS_DBR_PACING_NOTIFY_CQ(_req) \ 105 (_req.comp_mask & BNXT_RE_COMP_MASK_CQ_REQ_HAS_CAP_MASK && \ 106 _req.cq_capability & BNXT_RE_COMP_MASK_CQ_REQ_CAP_DBR_PACING_NOTIFY) 107 108 #define BNXT_RE_IS_DBR_RECOV_CQ(_req) \ 109 (_req.comp_mask & BNXT_RE_COMP_MASK_CQ_REQ_HAS_CAP_MASK && \ 110 _req.cq_capability & BNXT_RE_COMP_MASK_CQ_REQ_CAP_DBR_RECOVERY) 111 112 struct bnxt_re_cq_req { 113 __u64 cq_va; 114 __u64 cq_handle; 115 __aligned_u64 comp_mask; 116 __u16 cq_capability; 117 } __attribute__((packed)); 118 119 struct bnxt_re_cq_resp { 120 __u32 cqid; 121 __u32 tail; 122 __u32 phase; 123 __u32 rsvd; 124 __aligned_u64 comp_mask; 125 __u32 dpi; 126 __u64 dbr; 127 __u32 wcdpi; 128 __u64 uctx_cq_page; 129 } __attribute__((packed)); 130 131 struct bnxt_re_resize_cq_req { 132 __u64 cq_va; 133 } __attribute__((packed)); 134 135 struct bnxt_re_qp_req { 136 __u64 qpsva; 137 __u64 qprva; 138 __u64 qp_handle; 139 __u64 comp_mask; 140 __u32 sq_slots; 141 } __attribute__((packed)); 142 143 struct bnxt_re_qp_resp { 144 __u32 qpid; 145 } __attribute__((packed)); 146 147 struct bnxt_re_srq_req { 148 __u64 srqva; 149 __u64 srq_handle; 150 } __attribute__((packed)); 151 152 struct bnxt_re_srq_resp { 153 __u32 srqid; 154 } __attribute__((packed)); 155 156 /* Modify QP */ 157 enum { 158 BNXT_RE_COMP_MASK_MQP_EX_PPP_REQ_EN_MASK = 0x1, 159 BNXT_RE_COMP_MASK_MQP_EX_PPP_REQ_EN = 0x1, 160 BNXT_RE_COMP_MASK_MQP_EX_PATH_MTU_MASK = 0x2 161 }; 162 163 struct bnxt_re_modify_qp_ex_req { 164 __aligned_u64 comp_mask; 165 __u32 dpi; 166 __u32 rsvd; 167 } __packed; 168 169 struct bnxt_re_modify_qp_ex_resp { 170 __aligned_u64 comp_mask; 171 __u32 ppp_st_idx; 172 __u32 path_mtu; 173 } __packed; 174 175 enum bnxt_re_shpg_offt { 176 BNXT_RE_BEG_RESV_OFFT = 0x00, 177 BNXT_RE_AVID_OFFT = 0x10, 178 BNXT_RE_AVID_SIZE = 0x04, 179 BNXT_RE_END_RESV_OFFT = 0xFF0 180 }; 181 #endif 182