1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41 #include <sys/cdefs.h>
42 #include "opt_cpu.h"
43
44 #include <sys/param.h>
45 #include <sys/bus.h>
46 #include <sys/cpu.h>
47 #include <sys/eventhandler.h>
48 #include <sys/limits.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
51 #include <sys/sysctl.h>
52 #include <sys/power.h>
53
54 #include <vm/vm.h>
55 #include <vm/pmap.h>
56
57 #include <machine/asmacros.h>
58 #include <machine/clock.h>
59 #include <machine/cputypes.h>
60 #include <machine/frame.h>
61 #include <machine/intr_machdep.h>
62 #include <machine/md_var.h>
63 #include <machine/segments.h>
64 #include <machine/specialreg.h>
65
66 #include <amd64/vmm/intel/vmx_controls.h>
67 #include <x86/isa/icu.h>
68 #include <x86/vmware.h>
69
70 #ifdef XENHVM
71 #include <xen/xen-os.h>
72 #endif
73
74 #ifdef __i386__
75 #define IDENTBLUE_CYRIX486 0
76 #define IDENTBLUE_IBMCPU 1
77 #define IDENTBLUE_CYRIXM2 2
78
79 static void identifycyrix(void);
80 static void print_transmeta_info(void);
81 #endif
82 static u_int find_cpu_vendor_id(void);
83 static void print_AMD_info(void);
84 static void print_INTEL_info(void);
85 static void print_INTEL_TLB(u_int data);
86 static void print_hypervisor_info(void);
87 static void print_svm_info(void);
88 static void print_via_padlock_info(void);
89 static void print_vmx_info(void);
90
91 #ifdef __i386__
92 int cpu; /* Are we 386, 386sx, 486, etc? */
93 int cpu_class;
94 #endif
95 u_int cpu_feature; /* Feature flags */
96 u_int cpu_feature2; /* Feature flags */
97 u_int amd_feature; /* AMD feature flags */
98 u_int amd_feature2; /* AMD feature flags */
99 u_int amd_rascap; /* AMD RAS capabilities */
100 u_int amd_pminfo; /* AMD advanced power management info */
101 u_int amd_extended_feature_extensions;
102 u_int via_feature_rng; /* VIA RNG features */
103 u_int via_feature_xcrypt; /* VIA ACE features */
104 u_int cpu_high; /* Highest arg to CPUID */
105 u_int cpu_exthigh; /* Highest arg to extended CPUID */
106 u_int cpu_id; /* Stepping ID */
107 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
108 u_int cpu_procinfo2; /* Multicore info */
109 u_int cpu_procinfo3;
110 char cpu_vendor[20]; /* CPU Origin code */
111 u_int cpu_vendor_id; /* CPU vendor ID */
112 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
113 u_int cpu_clflush_line_size = 32;
114 /* leaf 7 %ecx = 0 */
115 u_int cpu_stdext_feature; /* %ebx */
116 u_int cpu_stdext_feature2; /* %ecx */
117 u_int cpu_stdext_feature3; /* %edx */
118 /* leaf 7 %ecx = 1 */
119 u_int cpu_stdext_feature4; /* %eax */
120 uint64_t cpu_ia32_arch_caps;
121 u_int cpu_max_ext_state_size;
122 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
123 u_int cpu_mon_mwait_edx; /* MONITOR/MWAIT supported on AMD (CPUID.05H.EDX) */
124 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
125 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
126 u_int cpu_maxphyaddr; /* Max phys addr width in bits */
127 u_int cpu_power_eax; /* 06H: Power management leaf, %eax */
128 u_int cpu_power_ebx; /* 06H: Power management leaf, %ebx */
129 u_int cpu_power_ecx; /* 06H: Power management leaf, %ecx */
130 u_int cpu_power_edx; /* 06H: Power management leaf, %edx */
131 const char machine[] = MACHINE;
132
133 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
134 &via_feature_rng, 0,
135 "VIA RNG feature available in CPU");
136 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
137 &via_feature_xcrypt, 0,
138 "VIA xcrypt feature available in CPU");
139
140 #ifdef __amd64__
141 #ifdef SCTL_MASK32
142 extern int adaptive_machine_arch;
143 #endif
144
145 static int
sysctl_hw_machine(SYSCTL_HANDLER_ARGS)146 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
147 {
148 #ifdef SCTL_MASK32
149 static const char machine32[] = "i386";
150 #endif
151 int error;
152
153 #ifdef SCTL_MASK32
154 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
155 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
156 else
157 #endif
158 error = SYSCTL_OUT(req, machine, sizeof(machine));
159 return (error);
160
161 }
162 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
163 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
164 #else
165 SYSCTL_CONST_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD | CTLFLAG_CAPRD,
166 machine, "Machine class");
167 #endif
168
169 char cpu_model[128];
170 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_CAPRD,
171 cpu_model, 0, "Machine model");
172
173 static int hw_clockrate;
174 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
175 &hw_clockrate, 0, "CPU instruction clock rate");
176
177 u_int hv_base;
178 u_int hv_high;
179 char hv_vendor[16];
180 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor,
181 0, "Hypervisor vendor");
182
183 static eventhandler_tag tsc_post_tag;
184
185 static char cpu_brand[48];
186
187 #ifdef __i386__
188 #define MAX_BRAND_INDEX 8
189
190 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
191 NULL, /* No brand */
192 "Intel Celeron",
193 "Intel Pentium III",
194 "Intel Pentium III Xeon",
195 NULL,
196 NULL,
197 NULL,
198 NULL,
199 "Intel Pentium 4"
200 };
201
202 static struct {
203 char *cpu_name;
204 int cpu_class;
205 } cpus[] = {
206 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
207 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
208 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
209 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
210 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
211 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
212 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
213 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
214 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
215 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
216 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
217 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
218 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
219 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
220 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
221 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
222 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
223 };
224 #endif
225
226 static struct {
227 char *vendor;
228 u_int vendor_id;
229 } cpu_vendors[] = {
230 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
231 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
232 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine */
233 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
234 #ifdef __i386__
235 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
236 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
237 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
238 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
239 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
240 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
241 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
242 #if 0
243 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
244 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
245 #endif
246 #endif
247 };
248
249 void
printcpuinfo(void)250 printcpuinfo(void)
251 {
252 u_int regs[4], i;
253 char *brand;
254
255 printf("CPU: ");
256 #ifdef __i386__
257 cpu_class = cpus[cpu].cpu_class;
258 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
259 #else
260 strncpy(cpu_model, "Hammer", sizeof (cpu_model));
261 #endif
262
263 /* Check for extended CPUID information and a processor name. */
264 if (cpu_exthigh >= 0x80000004) {
265 brand = cpu_brand;
266 for (i = 0x80000002; i < 0x80000005; i++) {
267 do_cpuid(i, regs);
268 memcpy(brand, regs, sizeof(regs));
269 brand += sizeof(regs);
270 }
271 }
272
273 switch (cpu_vendor_id) {
274 case CPU_VENDOR_INTEL:
275 #ifdef __i386__
276 if ((cpu_id & 0xf00) > 0x300) {
277 u_int brand_index;
278
279 cpu_model[0] = '\0';
280
281 switch (cpu_id & 0x3000) {
282 case 0x1000:
283 strcpy(cpu_model, "Overdrive ");
284 break;
285 case 0x2000:
286 strcpy(cpu_model, "Dual ");
287 break;
288 }
289
290 switch (cpu_id & 0xf00) {
291 case 0x400:
292 strcat(cpu_model, "i486 ");
293 /* Check the particular flavor of 486 */
294 switch (cpu_id & 0xf0) {
295 case 0x00:
296 case 0x10:
297 strcat(cpu_model, "DX");
298 break;
299 case 0x20:
300 strcat(cpu_model, "SX");
301 break;
302 case 0x30:
303 strcat(cpu_model, "DX2");
304 break;
305 case 0x40:
306 strcat(cpu_model, "SL");
307 break;
308 case 0x50:
309 strcat(cpu_model, "SX2");
310 break;
311 case 0x70:
312 strcat(cpu_model,
313 "DX2 Write-Back Enhanced");
314 break;
315 case 0x80:
316 strcat(cpu_model, "DX4");
317 break;
318 }
319 break;
320 case 0x500:
321 /* Check the particular flavor of 586 */
322 strcat(cpu_model, "Pentium");
323 switch (cpu_id & 0xf0) {
324 case 0x00:
325 strcat(cpu_model, " A-step");
326 break;
327 case 0x10:
328 strcat(cpu_model, "/P5");
329 break;
330 case 0x20:
331 strcat(cpu_model, "/P54C");
332 break;
333 case 0x30:
334 strcat(cpu_model, "/P24T");
335 break;
336 case 0x40:
337 strcat(cpu_model, "/P55C");
338 break;
339 case 0x70:
340 strcat(cpu_model, "/P54C");
341 break;
342 case 0x80:
343 strcat(cpu_model, "/P55C (quarter-micron)");
344 break;
345 default:
346 /* nothing */
347 break;
348 }
349 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
350 /*
351 * XXX - If/when Intel fixes the bug, this
352 * should also check the version of the
353 * CPU, not just that it's a Pentium.
354 */
355 has_f00f_bug = 1;
356 #endif
357 break;
358 case 0x600:
359 /* Check the particular flavor of 686 */
360 switch (cpu_id & 0xf0) {
361 case 0x00:
362 strcat(cpu_model, "Pentium Pro A-step");
363 break;
364 case 0x10:
365 strcat(cpu_model, "Pentium Pro");
366 break;
367 case 0x30:
368 case 0x50:
369 case 0x60:
370 strcat(cpu_model,
371 "Pentium II/Pentium II Xeon/Celeron");
372 cpu = CPU_PII;
373 break;
374 case 0x70:
375 case 0x80:
376 case 0xa0:
377 case 0xb0:
378 strcat(cpu_model,
379 "Pentium III/Pentium III Xeon/Celeron");
380 cpu = CPU_PIII;
381 break;
382 default:
383 strcat(cpu_model, "Unknown 80686");
384 break;
385 }
386 break;
387 case 0xf00:
388 strcat(cpu_model, "Pentium 4");
389 cpu = CPU_P4;
390 break;
391 default:
392 strcat(cpu_model, "unknown");
393 break;
394 }
395
396 /*
397 * If we didn't get a brand name from the extended
398 * CPUID, try to look it up in the brand table.
399 */
400 if (cpu_high > 0 && *cpu_brand == '\0') {
401 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
402 if (brand_index <= MAX_BRAND_INDEX &&
403 cpu_brandtable[brand_index] != NULL)
404 strcpy(cpu_brand,
405 cpu_brandtable[brand_index]);
406 }
407 }
408 #else
409 /* Please make up your mind folks! */
410 strcat(cpu_model, "EM64T");
411 #endif
412 break;
413 case CPU_VENDOR_AMD:
414 /*
415 * Values taken from AMD Processor Recognition
416 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
417 * (also describes ``Features'' encodings.
418 */
419 strcpy(cpu_model, "AMD ");
420 #ifdef __i386__
421 switch (cpu_id & 0xFF0) {
422 case 0x410:
423 strcat(cpu_model, "Standard Am486DX");
424 break;
425 case 0x430:
426 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
427 break;
428 case 0x470:
429 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
430 break;
431 case 0x480:
432 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
433 break;
434 case 0x490:
435 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
436 break;
437 case 0x4E0:
438 strcat(cpu_model, "Am5x86 Write-Through");
439 break;
440 case 0x4F0:
441 strcat(cpu_model, "Am5x86 Write-Back");
442 break;
443 case 0x500:
444 strcat(cpu_model, "K5 model 0");
445 break;
446 case 0x510:
447 strcat(cpu_model, "K5 model 1");
448 break;
449 case 0x520:
450 strcat(cpu_model, "K5 PR166 (model 2)");
451 break;
452 case 0x530:
453 strcat(cpu_model, "K5 PR200 (model 3)");
454 break;
455 case 0x560:
456 strcat(cpu_model, "K6");
457 break;
458 case 0x570:
459 strcat(cpu_model, "K6 266 (model 1)");
460 break;
461 case 0x580:
462 strcat(cpu_model, "K6-2");
463 break;
464 case 0x590:
465 strcat(cpu_model, "K6-III");
466 break;
467 case 0x5a0:
468 strcat(cpu_model, "Geode LX");
469 break;
470 default:
471 strcat(cpu_model, "Unknown");
472 break;
473 }
474 #else
475 if ((cpu_id & 0xf00) == 0xf00)
476 strcat(cpu_model, "AMD64 Processor");
477 else
478 strcat(cpu_model, "Unknown");
479 #endif
480 break;
481 #ifdef __i386__
482 case CPU_VENDOR_CYRIX:
483 strcpy(cpu_model, "Cyrix ");
484 switch (cpu_id & 0xff0) {
485 case 0x440:
486 strcat(cpu_model, "MediaGX");
487 break;
488 case 0x520:
489 strcat(cpu_model, "6x86");
490 break;
491 case 0x540:
492 cpu_class = CPUCLASS_586;
493 strcat(cpu_model, "GXm");
494 break;
495 case 0x600:
496 strcat(cpu_model, "6x86MX");
497 break;
498 default:
499 /*
500 * Even though CPU supports the cpuid
501 * instruction, it can be disabled.
502 * Therefore, this routine supports all Cyrix
503 * CPUs.
504 */
505 switch (cyrix_did & 0xf0) {
506 case 0x00:
507 switch (cyrix_did & 0x0f) {
508 case 0x00:
509 strcat(cpu_model, "486SLC");
510 break;
511 case 0x01:
512 strcat(cpu_model, "486DLC");
513 break;
514 case 0x02:
515 strcat(cpu_model, "486SLC2");
516 break;
517 case 0x03:
518 strcat(cpu_model, "486DLC2");
519 break;
520 case 0x04:
521 strcat(cpu_model, "486SRx");
522 break;
523 case 0x05:
524 strcat(cpu_model, "486DRx");
525 break;
526 case 0x06:
527 strcat(cpu_model, "486SRx2");
528 break;
529 case 0x07:
530 strcat(cpu_model, "486DRx2");
531 break;
532 case 0x08:
533 strcat(cpu_model, "486SRu");
534 break;
535 case 0x09:
536 strcat(cpu_model, "486DRu");
537 break;
538 case 0x0a:
539 strcat(cpu_model, "486SRu2");
540 break;
541 case 0x0b:
542 strcat(cpu_model, "486DRu2");
543 break;
544 default:
545 strcat(cpu_model, "Unknown");
546 break;
547 }
548 break;
549 case 0x10:
550 switch (cyrix_did & 0x0f) {
551 case 0x00:
552 strcat(cpu_model, "486S");
553 break;
554 case 0x01:
555 strcat(cpu_model, "486S2");
556 break;
557 case 0x02:
558 strcat(cpu_model, "486Se");
559 break;
560 case 0x03:
561 strcat(cpu_model, "486S2e");
562 break;
563 case 0x0a:
564 strcat(cpu_model, "486DX");
565 break;
566 case 0x0b:
567 strcat(cpu_model, "486DX2");
568 break;
569 case 0x0f:
570 strcat(cpu_model, "486DX4");
571 break;
572 default:
573 strcat(cpu_model, "Unknown");
574 break;
575 }
576 break;
577 case 0x20:
578 if ((cyrix_did & 0x0f) < 8)
579 strcat(cpu_model, "6x86"); /* Where did you get it? */
580 else
581 strcat(cpu_model, "5x86");
582 break;
583 case 0x30:
584 strcat(cpu_model, "6x86");
585 break;
586 case 0x40:
587 if ((cyrix_did & 0xf000) == 0x3000) {
588 cpu_class = CPUCLASS_586;
589 strcat(cpu_model, "GXm");
590 } else
591 strcat(cpu_model, "MediaGX");
592 break;
593 case 0x50:
594 strcat(cpu_model, "6x86MX");
595 break;
596 case 0xf0:
597 switch (cyrix_did & 0x0f) {
598 case 0x0d:
599 strcat(cpu_model, "Overdrive CPU");
600 break;
601 case 0x0e:
602 strcpy(cpu_model, "Texas Instruments 486SXL");
603 break;
604 case 0x0f:
605 strcat(cpu_model, "486SLC/DLC");
606 break;
607 default:
608 strcat(cpu_model, "Unknown");
609 break;
610 }
611 break;
612 default:
613 strcat(cpu_model, "Unknown");
614 break;
615 }
616 break;
617 }
618 break;
619 case CPU_VENDOR_RISE:
620 strcpy(cpu_model, "Rise ");
621 switch (cpu_id & 0xff0) {
622 case 0x500: /* 6401 and 6441 (Kirin) */
623 case 0x520: /* 6510 (Lynx) */
624 strcat(cpu_model, "mP6");
625 break;
626 default:
627 strcat(cpu_model, "Unknown");
628 }
629 break;
630 #endif
631 case CPU_VENDOR_CENTAUR:
632 #ifdef __i386__
633 switch (cpu_id & 0xff0) {
634 case 0x540:
635 strcpy(cpu_model, "IDT WinChip C6");
636 break;
637 case 0x580:
638 strcpy(cpu_model, "IDT WinChip 2");
639 break;
640 case 0x590:
641 strcpy(cpu_model, "IDT WinChip 3");
642 break;
643 case 0x660:
644 strcpy(cpu_model, "VIA C3 Samuel");
645 break;
646 case 0x670:
647 if (cpu_id & 0x8)
648 strcpy(cpu_model, "VIA C3 Ezra");
649 else
650 strcpy(cpu_model, "VIA C3 Samuel 2");
651 break;
652 case 0x680:
653 strcpy(cpu_model, "VIA C3 Ezra-T");
654 break;
655 case 0x690:
656 strcpy(cpu_model, "VIA C3 Nehemiah");
657 break;
658 case 0x6a0:
659 case 0x6d0:
660 strcpy(cpu_model, "VIA C7 Esther");
661 break;
662 case 0x6f0:
663 strcpy(cpu_model, "VIA Nano");
664 break;
665 default:
666 strcpy(cpu_model, "VIA/IDT Unknown");
667 }
668 #else
669 strcpy(cpu_model, "VIA ");
670 if ((cpu_id & 0xff0) == 0x6f0)
671 strcat(cpu_model, "Nano Processor");
672 else
673 strcat(cpu_model, "Unknown");
674 #endif
675 break;
676 #ifdef __i386__
677 case CPU_VENDOR_IBM:
678 strcpy(cpu_model, "Blue Lightning CPU");
679 break;
680 case CPU_VENDOR_NSC:
681 switch (cpu_id & 0xff0) {
682 case 0x540:
683 strcpy(cpu_model, "Geode SC1100");
684 cpu = CPU_GEODE1100;
685 break;
686 default:
687 strcpy(cpu_model, "Geode/NSC unknown");
688 break;
689 }
690 break;
691 #endif
692 case CPU_VENDOR_HYGON:
693 strcpy(cpu_model, "Hygon ");
694 #ifdef __i386__
695 strcat(cpu_model, "Unknown");
696 #else
697 if ((cpu_id & 0xf00) == 0xf00)
698 strcat(cpu_model, "AMD64 Processor");
699 else
700 strcat(cpu_model, "Unknown");
701 #endif
702 break;
703
704 default:
705 strcat(cpu_model, "Unknown");
706 break;
707 }
708
709 /*
710 * Replace cpu_model with cpu_brand minus leading spaces if
711 * we have one.
712 */
713 brand = cpu_brand;
714 while (*brand == ' ')
715 ++brand;
716 if (*brand != '\0')
717 strcpy(cpu_model, brand);
718
719 printf("%s (", cpu_model);
720 if (tsc_freq != 0) {
721 hw_clockrate = (tsc_freq + 5000) / 1000000;
722 printf("%jd.%02d-MHz ",
723 (intmax_t)(tsc_freq + 4999) / 1000000,
724 (u_int)((tsc_freq + 4999) / 10000) % 100);
725 }
726 #ifdef __i386__
727 switch(cpu_class) {
728 case CPUCLASS_286:
729 printf("286");
730 break;
731 case CPUCLASS_386:
732 printf("386");
733 break;
734 #if defined(I486_CPU)
735 case CPUCLASS_486:
736 printf("486");
737 break;
738 #endif
739 #if defined(I586_CPU)
740 case CPUCLASS_586:
741 printf("586");
742 break;
743 #endif
744 #if defined(I686_CPU)
745 case CPUCLASS_686:
746 printf("686");
747 break;
748 #endif
749 default:
750 printf("Unknown"); /* will panic below... */
751 }
752 #else
753 printf("K8");
754 #endif
755 printf("-class CPU)\n");
756 if (*cpu_vendor)
757 printf(" Origin=\"%s\"", cpu_vendor);
758 if (cpu_id)
759 printf(" Id=0x%x", cpu_id);
760
761 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
762 cpu_vendor_id == CPU_VENDOR_AMD ||
763 cpu_vendor_id == CPU_VENDOR_HYGON ||
764 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
765 #ifdef __i386__
766 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
767 cpu_vendor_id == CPU_VENDOR_RISE ||
768 cpu_vendor_id == CPU_VENDOR_NSC ||
769 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
770 #endif
771 0) {
772 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
773 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
774 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
775 #ifdef __i386__
776 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
777 printf("\n DIR=0x%04x", cyrix_did);
778 #endif
779
780 /*
781 * AMD CPUID Specification
782 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
783 *
784 * Intel Processor Identification and CPUID Instruction
785 * http://www.intel.com/assets/pdf/appnote/241618.pdf
786 */
787 if (cpu_high > 0) {
788 /*
789 * Here we should probably set up flags indicating
790 * whether or not various features are available.
791 * The interesting ones are probably VME, PSE, PAE,
792 * and PGE. The code already assumes without bothering
793 * to check that all CPUs >= Pentium have a TSC and
794 * MSRs.
795 */
796 printf("\n Features=0x%b", cpu_feature,
797 "\020"
798 "\001FPU" /* Integral FPU */
799 "\002VME" /* Extended VM86 mode support */
800 "\003DE" /* Debugging Extensions (CR4.DE) */
801 "\004PSE" /* 4MByte page tables */
802 "\005TSC" /* Timestamp counter */
803 "\006MSR" /* Machine specific registers */
804 "\007PAE" /* Physical address extension */
805 "\010MCE" /* Machine Check support */
806 "\011CX8" /* CMPEXCH8 instruction */
807 "\012APIC" /* SMP local APIC */
808 "\013oldMTRR" /* Previous implementation of MTRR */
809 "\014SEP" /* Fast System Call */
810 "\015MTRR" /* Memory Type Range Registers */
811 "\016PGE" /* PG_G (global bit) support */
812 "\017MCA" /* Machine Check Architecture */
813 "\020CMOV" /* CMOV instruction */
814 "\021PAT" /* Page attributes table */
815 "\022PSE36" /* 36 bit address space support */
816 "\023PN" /* Processor Serial number */
817 "\024CLFLUSH" /* Has the CLFLUSH instruction */
818 "\025<b20>"
819 "\026DTS" /* Debug Trace Store */
820 "\027ACPI" /* ACPI support */
821 "\030MMX" /* MMX instructions */
822 "\031FXSR" /* FXSAVE/FXRSTOR */
823 "\032SSE" /* Streaming SIMD Extensions */
824 "\033SSE2" /* Streaming SIMD Extensions #2 */
825 "\034SS" /* Self snoop */
826 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
827 "\036TM" /* Thermal Monitor clock slowdown */
828 "\037IA64" /* CPU can execute IA64 instructions */
829 "\040PBE" /* Pending Break Enable */
830 );
831
832 if (cpu_feature2 != 0) {
833 printf("\n Features2=0x%b", cpu_feature2,
834 "\020"
835 "\001SSE3" /* SSE3 */
836 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
837 "\003DTES64" /* 64-bit Debug Trace */
838 "\004MON" /* MONITOR/MWAIT Instructions */
839 "\005DS_CPL" /* CPL Qualified Debug Store */
840 "\006VMX" /* Virtual Machine Extensions */
841 "\007SMX" /* Safer Mode Extensions */
842 "\010EST" /* Enhanced SpeedStep */
843 "\011TM2" /* Thermal Monitor 2 */
844 "\012SSSE3" /* SSSE3 */
845 "\013CNXT-ID" /* L1 context ID available */
846 "\014SDBG" /* IA32 silicon debug */
847 "\015FMA" /* Fused Multiply Add */
848 "\016CX16" /* CMPXCHG16B Instruction */
849 "\017xTPR" /* Send Task Priority Messages*/
850 "\020PDCM" /* Perf/Debug Capability MSR */
851 "\021<b16>"
852 "\022PCID" /* Process-context Identifiers*/
853 "\023DCA" /* Direct Cache Access */
854 "\024SSE4.1" /* SSE 4.1 */
855 "\025SSE4.2" /* SSE 4.2 */
856 "\026x2APIC" /* xAPIC Extensions */
857 "\027MOVBE" /* MOVBE Instruction */
858 "\030POPCNT" /* POPCNT Instruction */
859 "\031TSCDLT" /* TSC-Deadline Timer */
860 "\032AESNI" /* AES Crypto */
861 "\033XSAVE" /* XSAVE/XRSTOR States */
862 "\034OSXSAVE" /* OS-Enabled State Management*/
863 "\035AVX" /* Advanced Vector Extensions */
864 "\036F16C" /* Half-precision conversions */
865 "\037RDRAND" /* RDRAND Instruction */
866 "\040HV" /* Hypervisor */
867 );
868 }
869
870 if (amd_feature != 0) {
871 printf("\n AMD Features=0x%b", amd_feature,
872 "\020" /* in hex */
873 "\001<s0>" /* Same */
874 "\002<s1>" /* Same */
875 "\003<s2>" /* Same */
876 "\004<s3>" /* Same */
877 "\005<s4>" /* Same */
878 "\006<s5>" /* Same */
879 "\007<s6>" /* Same */
880 "\010<s7>" /* Same */
881 "\011<s8>" /* Same */
882 "\012<s9>" /* Same */
883 "\013<b10>" /* Undefined */
884 "\014SYSCALL" /* Have SYSCALL/SYSRET */
885 "\015<s12>" /* Same */
886 "\016<s13>" /* Same */
887 "\017<s14>" /* Same */
888 "\020<s15>" /* Same */
889 "\021<s16>" /* Same */
890 "\022<s17>" /* Same */
891 "\023<b18>" /* Reserved, unknown */
892 "\024MP" /* Multiprocessor Capable */
893 "\025NX" /* Has EFER.NXE, NX */
894 "\026<b21>" /* Undefined */
895 "\027MMX+" /* AMD MMX Extensions */
896 "\030<s23>" /* Same */
897 "\031<s24>" /* Same */
898 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
899 "\033Page1GB" /* 1-GB large page support */
900 "\034RDTSCP" /* RDTSCP */
901 "\035<b28>" /* Undefined */
902 "\036LM" /* 64 bit long mode */
903 "\0373DNow!+" /* AMD 3DNow! Extensions */
904 "\0403DNow!" /* AMD 3DNow! */
905 );
906 }
907
908 if (amd_feature2 != 0) {
909 printf("\n AMD Features2=0x%b", amd_feature2,
910 "\020"
911 "\001LAHF" /* LAHF/SAHF in long mode */
912 "\002CMP" /* CMP legacy */
913 "\003SVM" /* Secure Virtual Mode */
914 "\004ExtAPIC" /* Extended APIC register */
915 "\005CR8" /* CR8 in legacy mode */
916 "\006ABM" /* LZCNT instruction */
917 "\007SSE4A" /* SSE4A */
918 "\010MAS" /* Misaligned SSE mode */
919 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
920 "\012OSVW" /* OS visible workaround */
921 "\013IBS" /* Instruction based sampling */
922 "\014XOP" /* XOP extended instructions */
923 "\015SKINIT" /* SKINIT/STGI */
924 "\016WDT" /* Watchdog timer */
925 "\017<b14>"
926 "\020LWP" /* Lightweight Profiling */
927 "\021FMA4" /* 4-operand FMA instructions */
928 "\022TCE" /* Translation Cache Extension */
929 "\023<b18>"
930 "\024NodeId" /* NodeId MSR support */
931 "\025<b20>"
932 "\026TBM" /* Trailing Bit Manipulation */
933 "\027Topology" /* Topology Extensions */
934 "\030PCXC" /* Core perf count */
935 "\031PNXC" /* NB perf count */
936 "\032<b25>"
937 "\033DBE" /* Data Breakpoint extension */
938 "\034PTSC" /* Performance TSC */
939 "\035PL2I" /* L2I perf count */
940 "\036MWAITX" /* MONITORX/MWAITX instructions */
941 "\037ADMSKX" /* Address mask extension */
942 "\040<b31>"
943 );
944 }
945
946 if (cpu_stdext_feature != 0) {
947 printf("\n Structured Extended Features=0x%b",
948 cpu_stdext_feature,
949 "\020"
950 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
951 "\001FSGSBASE"
952 "\002TSCADJ"
953 "\003SGX"
954 /* Bit Manipulation Instructions */
955 "\004BMI1"
956 /* Hardware Lock Elision */
957 "\005HLE"
958 /* Advanced Vector Instructions 2 */
959 "\006AVX2"
960 /* FDP_EXCPTN_ONLY */
961 "\007FDPEXC"
962 /* Supervisor Mode Execution Prot. */
963 "\010SMEP"
964 /* Bit Manipulation Instructions */
965 "\011BMI2"
966 "\012ERMS"
967 /* Invalidate Processor Context ID */
968 "\013INVPCID"
969 /* Restricted Transactional Memory */
970 "\014RTM"
971 "\015PQM"
972 "\016NFPUSG"
973 /* Intel Memory Protection Extensions */
974 "\017MPX"
975 "\020PQE"
976 /* AVX512 Foundation */
977 "\021AVX512F"
978 "\022AVX512DQ"
979 /* Enhanced NRBG */
980 "\023RDSEED"
981 /* ADCX + ADOX */
982 "\024ADX"
983 /* Supervisor Mode Access Prevention */
984 "\025SMAP"
985 "\026AVX512IFMA"
986 /* Formerly PCOMMIT */
987 "\027<b22>"
988 "\030CLFLUSHOPT"
989 "\031CLWB"
990 "\032PROCTRACE"
991 "\033AVX512PF"
992 "\034AVX512ER"
993 "\035AVX512CD"
994 "\036SHA"
995 "\037AVX512BW"
996 "\040AVX512VL"
997 );
998 }
999
1000 if (cpu_stdext_feature2 != 0) {
1001 printf("\n Structured Extended Features2=0x%b",
1002 cpu_stdext_feature2,
1003 "\020"
1004 "\001PREFETCHWT1"
1005 "\002AVX512VBMI"
1006 "\003UMIP"
1007 "\004PKU"
1008 "\005OSPKE"
1009 "\006WAITPKG"
1010 "\007AVX512VBMI2"
1011 "\011GFNI"
1012 "\012VAES"
1013 "\013VPCLMULQDQ"
1014 "\014AVX512VNNI"
1015 "\015AVX512BITALG"
1016 "\016TME"
1017 "\017AVX512VPOPCNTDQ"
1018 "\021LA57"
1019 "\027RDPID"
1020 "\032CLDEMOTE"
1021 "\034MOVDIRI"
1022 "\035MOVDIR64B"
1023 "\036ENQCMD"
1024 "\037SGXLC"
1025 );
1026 }
1027
1028 if (cpu_stdext_feature3 != 0) {
1029 printf("\n Structured Extended Features3=0x%b",
1030 cpu_stdext_feature3,
1031 "\020"
1032 "\003AVX512_4VNNIW"
1033 "\004AVX512_4FMAPS"
1034 "\005FSRM"
1035 "\011AVX512VP2INTERSECT"
1036 "\012MCUOPT"
1037 "\013MD_CLEAR"
1038 "\016TSXFA"
1039 "\023PCONFIG"
1040 "\025IBT"
1041 "\033IBPB"
1042 "\034STIBP"
1043 "\035L1DFL"
1044 "\036ARCH_CAP"
1045 "\037CORE_CAP"
1046 "\040SSBD"
1047 );
1048 }
1049
1050 if (cpu_stdext_feature4 != 0) {
1051 printf("\n Structured Extended Features4=0x%b",
1052 cpu_stdext_feature4,
1053 "\020"
1054 "\007LASS"
1055 "\022FRED"
1056 "\023LKGS"
1057 "\024WRMSRNS"
1058 "\025NMISRC"
1059 "\033LAM"
1060 );
1061 }
1062
1063 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1064 cpuid_count(0xd, 0x1, regs);
1065 if (regs[0] != 0) {
1066 printf("\n XSAVE Features=0x%b",
1067 regs[0],
1068 "\020"
1069 "\001XSAVEOPT"
1070 "\002XSAVEC"
1071 "\003XINUSE"
1072 "\004XSAVES");
1073 }
1074 }
1075
1076 if (cpu_ia32_arch_caps != 0) {
1077 printf("\n IA32_ARCH_CAPS=0x%b",
1078 (u_int)cpu_ia32_arch_caps,
1079 "\020"
1080 "\001RDCL_NO"
1081 "\002IBRS_ALL"
1082 "\003RSBA"
1083 "\004SKIP_L1DFL_VME"
1084 "\005SSB_NO"
1085 "\006MDS_NO"
1086 "\010TSX_CTRL"
1087 "\011TAA_NO"
1088 );
1089 }
1090
1091 if (amd_extended_feature_extensions != 0) {
1092 u_int amd_fe_masked;
1093
1094 amd_fe_masked = amd_extended_feature_extensions;
1095 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1096 amd_fe_masked &=
1097 ~(AMDFEID_IBRS_ALWAYSON |
1098 AMDFEID_PREFER_IBRS);
1099 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1100 amd_fe_masked &=
1101 ~AMDFEID_STIBP_ALWAYSON;
1102
1103 printf("\n "
1104 "AMD Extended Feature Extensions ID EBX="
1105 "0x%b", amd_fe_masked,
1106 "\020"
1107 "\001CLZERO"
1108 "\002IRPerf"
1109 "\003XSaveErPtr"
1110 "\004INVLPGB"
1111 "\005RDPRU"
1112 "\007BE"
1113 "\011MCOMMIT"
1114 "\012WBNOINVD"
1115 "\015IBPB"
1116 "\016INT_WBINVD"
1117 "\017IBRS"
1118 "\020STIBP"
1119 "\021IBRS_ALWAYSON"
1120 "\022STIBP_ALWAYSON"
1121 "\023PREFER_IBRS"
1122 "\024SAMEMODE_IBRS"
1123 "\025NOLMSLE"
1124 "\026INVLPGBNEST"
1125 "\030PPIN"
1126 "\031SSBD"
1127 "\032VIRT_SSBD"
1128 "\033SSB_NO"
1129 "\034CPPC"
1130 "\035PSFD"
1131 "\036BTC_NO"
1132 "\037IBPB_RET"
1133 );
1134 }
1135
1136 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1137 print_via_padlock_info();
1138
1139 if (cpu_feature2 & CPUID2_VMX)
1140 print_vmx_info();
1141
1142 if (amd_feature2 & AMDID2_SVM)
1143 print_svm_info();
1144
1145 if ((cpu_feature & CPUID_HTT) &&
1146 (cpu_vendor_id == CPU_VENDOR_AMD ||
1147 cpu_vendor_id == CPU_VENDOR_HYGON))
1148 cpu_feature &= ~CPUID_HTT;
1149
1150 /*
1151 * If this CPU supports P-state invariant TSC then
1152 * mention the capability.
1153 */
1154 if (tsc_is_invariant) {
1155 printf("\n TSC: P-state invariant");
1156 if (tsc_perf_stat)
1157 printf(", performance statistics");
1158 }
1159 }
1160 #ifdef __i386__
1161 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1162 printf(" DIR=0x%04x", cyrix_did);
1163 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
1164 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
1165 #ifndef CYRIX_CACHE_REALLY_WORKS
1166 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1167 printf("\n CPU cache: write-through mode");
1168 #endif
1169 #endif
1170 }
1171
1172 /* Avoid ugly blank lines: only print newline when we have to. */
1173 if (*cpu_vendor || cpu_id)
1174 printf("\n");
1175
1176 if (bootverbose) {
1177 if (cpu_vendor_id == CPU_VENDOR_AMD ||
1178 cpu_vendor_id == CPU_VENDOR_HYGON)
1179 print_AMD_info();
1180 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1181 print_INTEL_info();
1182 #ifdef __i386__
1183 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1184 print_transmeta_info();
1185 #endif
1186 }
1187
1188 print_hypervisor_info();
1189 }
1190
1191 #ifdef __i386__
1192 void
panicifcpuunsupported(void)1193 panicifcpuunsupported(void)
1194 {
1195
1196 #if !defined(lint)
1197 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1198 #error This kernel is not configured for one of the supported CPUs
1199 #endif
1200 #else /* lint */
1201 #endif /* lint */
1202 /*
1203 * Now that we have told the user what they have,
1204 * let them know if that machine type isn't configured.
1205 */
1206 switch (cpu_class) {
1207 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1208 case CPUCLASS_386:
1209 #if !defined(I486_CPU)
1210 case CPUCLASS_486:
1211 #endif
1212 #if !defined(I586_CPU)
1213 case CPUCLASS_586:
1214 #endif
1215 #if !defined(I686_CPU)
1216 case CPUCLASS_686:
1217 #endif
1218 panic("CPU class not configured");
1219 default:
1220 break;
1221 }
1222 }
1223
1224 static volatile u_int trap_by_rdmsr;
1225
1226 /*
1227 * Special exception 6 handler.
1228 * The rdmsr instruction generates invalid opcodes fault on 486-class
1229 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1230 * function identblue() when this handler is called. Stacked eip should
1231 * be advanced.
1232 */
1233 inthand_t bluetrap6;
1234 __asm
1235 (" \n\
1236 .text \n\
1237 .p2align 2,0x90 \n\
1238 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1239 " __XSTRING(CNAME(bluetrap6)) ": \n\
1240 ss \n\
1241 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1242 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1243 iret \n\
1244 ");
1245
1246 /*
1247 * Special exception 13 handler.
1248 * Accessing non-existent MSR generates general protection fault.
1249 */
1250 inthand_t bluetrap13;
1251 __asm
1252 (" \n\
1253 .text \n\
1254 .p2align 2,0x90 \n\
1255 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1256 " __XSTRING(CNAME(bluetrap13)) ": \n\
1257 ss \n\
1258 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1259 popl %eax /* discard error code */ \n\
1260 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1261 iret \n\
1262 ");
1263
1264 /*
1265 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1266 * support cpuid instruction. This function should be called after
1267 * loading interrupt descriptor table register.
1268 *
1269 * I don't like this method that handles fault, but I couldn't get
1270 * information for any other methods. Does blue giant know?
1271 */
1272 static int
identblue(void)1273 identblue(void)
1274 {
1275
1276 trap_by_rdmsr = 0;
1277
1278 /*
1279 * Cyrix 486-class CPU does not support rdmsr instruction.
1280 * The rdmsr instruction generates invalid opcode fault, and exception
1281 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1282 * bluetrap6() set the magic number to trap_by_rdmsr.
1283 */
1284 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1285 GSEL(GCODE_SEL, SEL_KPL));
1286
1287 /*
1288 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1289 * In this case, rdmsr generates general protection fault, and
1290 * exception will be trapped by bluetrap13().
1291 */
1292 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1293 GSEL(GCODE_SEL, SEL_KPL));
1294
1295 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1296
1297 if (trap_by_rdmsr == 0xa8c1d)
1298 return IDENTBLUE_CYRIX486;
1299 else if (trap_by_rdmsr == 0xa89c4)
1300 return IDENTBLUE_CYRIXM2;
1301 return IDENTBLUE_IBMCPU;
1302 }
1303
1304 /*
1305 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1306 *
1307 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1308 * +-------+-------+---------------+
1309 * | SID | RID | Device ID |
1310 * | (DIR 1) | (DIR 0) |
1311 * +-------+-------+---------------+
1312 */
1313 static void
identifycyrix(void)1314 identifycyrix(void)
1315 {
1316 register_t saveintr;
1317 int ccr2_test = 0, dir_test = 0;
1318 u_char ccr2, ccr3;
1319
1320 saveintr = intr_disable();
1321
1322 ccr2 = read_cyrix_reg(CCR2);
1323 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1324 read_cyrix_reg(CCR2);
1325 if (read_cyrix_reg(CCR2) != ccr2)
1326 ccr2_test = 1;
1327 write_cyrix_reg(CCR2, ccr2);
1328
1329 ccr3 = read_cyrix_reg(CCR3);
1330 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1331 read_cyrix_reg(CCR3);
1332 if (read_cyrix_reg(CCR3) != ccr3)
1333 dir_test = 1; /* CPU supports DIRs. */
1334 write_cyrix_reg(CCR3, ccr3);
1335
1336 if (dir_test) {
1337 /* Device ID registers are available. */
1338 cyrix_did = read_cyrix_reg(DIR1) << 8;
1339 cyrix_did += read_cyrix_reg(DIR0);
1340 } else if (ccr2_test)
1341 cyrix_did = 0x0010; /* 486S A-step */
1342 else
1343 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1344
1345 intr_restore(saveintr);
1346 }
1347 #endif
1348
1349 /* Update TSC freq with the value indicated by the caller. */
1350 static void
tsc_freq_changed(void * arg __unused,const struct cf_level * level,int status)1351 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1352 {
1353
1354 /* If there was an error during the transition, don't do anything. */
1355 if (status != 0)
1356 return;
1357
1358 /* Total setting for this level gives the new frequency in MHz. */
1359 hw_clockrate = level->total_set.freq;
1360 }
1361
1362 static void
hook_tsc_freq(void * arg __unused)1363 hook_tsc_freq(void *arg __unused)
1364 {
1365
1366 if (tsc_is_invariant)
1367 return;
1368
1369 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1370 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1371 }
1372
1373 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1374
1375 static struct {
1376 const char *vm_cpuid;
1377 int vm_guest;
1378 void (*init)(void);
1379 } vm_cpuids[] = {
1380 { "XenVMMXenVMM", VM_GUEST_XEN,
1381 #ifdef XENHVM
1382 &xen_early_init,
1383 #endif
1384 }, /* XEN */
1385 { "Microsoft Hv", VM_GUEST_HV }, /* Microsoft Hyper-V */
1386 { "VMwareVMware", VM_GUEST_VMWARE }, /* VMware VM */
1387 { "KVMKVMKVM", VM_GUEST_KVM }, /* KVM */
1388 { "bhyve bhyve ", VM_GUEST_BHYVE }, /* bhyve */
1389 { "VBoxVBoxVBox", VM_GUEST_VBOX }, /* VirtualBox */
1390 { "___ NVMM ___", VM_GUEST_NVMM }, /* NVMM */
1391 };
1392
1393 static void
identify_hypervisor_cpuid_base(void)1394 identify_hypervisor_cpuid_base(void)
1395 {
1396 void (*init_fn)(void) = NULL;
1397 u_int leaf, regs[4];
1398 int i;
1399
1400 /*
1401 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1402 * http://lkml.org/lkml/2008/10/1/246
1403 *
1404 * KB1009458: Mechanisms to determine if software is running in
1405 * a VMware virtual machine
1406 * http://kb.vmware.com/kb/1009458
1407 *
1408 * Search for a hypervisor that we recognize. If we cannot find
1409 * a specific hypervisor, return the first information about the
1410 * hypervisor that we found, as others may be able to use.
1411 */
1412 for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1413 do_cpuid(leaf, regs);
1414
1415 /*
1416 * KVM from Linux kernels prior to commit
1417 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1418 * to 0 rather than a valid hv_high value. Check for
1419 * the KVM signature bytes and fixup %eax to the
1420 * highest supported leaf in that case.
1421 */
1422 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1423 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1424 regs[0] = leaf + 1;
1425
1426 if (regs[0] >= leaf) {
1427 enum VM_GUEST prev_vm_guest = vm_guest;
1428
1429 for (i = 0; i < nitems(vm_cpuids); i++)
1430 if (strncmp((const char *)®s[1],
1431 vm_cpuids[i].vm_cpuid, 12) == 0) {
1432 vm_guest = vm_cpuids[i].vm_guest;
1433 init_fn = vm_cpuids[i].init;
1434 break;
1435 }
1436
1437 /*
1438 * If this is the first entry or we found a
1439 * specific hypervisor, record the base, high value,
1440 * and vendor identifier.
1441 */
1442 if (vm_guest != prev_vm_guest || leaf == 0x40000000) {
1443 hv_base = leaf;
1444 hv_high = regs[0];
1445 ((u_int *)&hv_vendor)[0] = regs[1];
1446 ((u_int *)&hv_vendor)[1] = regs[2];
1447 ((u_int *)&hv_vendor)[2] = regs[3];
1448 hv_vendor[12] = '\0';
1449
1450 /*
1451 * If we found a specific hypervisor, then
1452 * we are finished.
1453 */
1454 if (vm_guest != VM_GUEST_VM &&
1455 /*
1456 * Xen and other hypervisors can expose the
1457 * HyperV signature in addition to the
1458 * native one in order to support Viridian
1459 * extensions for Windows guests.
1460 *
1461 * Do the full cpuid scan if HyperV is
1462 * detected, as the native hypervisor is
1463 * preferred.
1464 */
1465 vm_guest != VM_GUEST_HV)
1466 break;
1467 }
1468 }
1469 }
1470
1471 if (init_fn != NULL)
1472 init_fn();
1473 }
1474
1475 void
identify_hypervisor(void)1476 identify_hypervisor(void)
1477 {
1478 u_int regs[4];
1479 char *p;
1480
1481 TSENTER();
1482 /*
1483 * If CPUID2_HV is set, we are running in a hypervisor environment.
1484 */
1485 if (cpu_feature2 & CPUID2_HV) {
1486 vm_guest = VM_GUEST_VM;
1487 identify_hypervisor_cpuid_base();
1488
1489 /* If we have a definitive vendor, we can return now. */
1490 if (*hv_vendor != '\0') {
1491 TSEXIT();
1492 return;
1493 }
1494 }
1495
1496 /*
1497 * Examine SMBIOS strings for older hypervisors.
1498 */
1499 p = kern_getenv("smbios.system.serial");
1500 if (p != NULL) {
1501 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1502 vmware_hvcall(0, VMW_HVCMD_GETVERSION,
1503 VMW_HVCMD_DEFAULT_PARAM, regs);
1504 if (regs[1] == VMW_HVMAGIC) {
1505 vm_guest = VM_GUEST_VMWARE;
1506 freeenv(p);
1507 TSEXIT();
1508 return;
1509 }
1510 }
1511 freeenv(p);
1512 }
1513 TSEXIT();
1514 }
1515
1516 bool
fix_cpuid(void)1517 fix_cpuid(void)
1518 {
1519 uint64_t msr;
1520
1521 /*
1522 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1523 * get the largest standard CPUID function number again if it is set
1524 * from BIOS. It is necessary for probing correct CPU topology later
1525 * and for the correct operation of the AVX-aware userspace.
1526 */
1527 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1528 ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1529 CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1530 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1531 CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1532 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1533 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1534 msr &= ~IA32_MISC_EN_LIMCPUID;
1535 wrmsr(MSR_IA32_MISC_ENABLE, msr);
1536 return (true);
1537 }
1538 }
1539
1540 /*
1541 * Re-enable AMD Topology Extension that could be disabled by BIOS
1542 * on some notebook processors. Without the extension it's really
1543 * hard to determine the correct CPU cache topology.
1544 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1545 * Models 60h-6Fh Processors, Publication # 50742.
1546 */
1547 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1548 CPUID_TO_FAMILY(cpu_id) == 0x15) {
1549 msr = rdmsr(MSR_EXTFEATURES);
1550 if ((msr & ((uint64_t)1 << 54)) == 0) {
1551 msr |= (uint64_t)1 << 54;
1552 wrmsr(MSR_EXTFEATURES, msr);
1553 return (true);
1554 }
1555 }
1556 return (false);
1557 }
1558
1559 void
identify_cpu1(void)1560 identify_cpu1(void)
1561 {
1562 u_int regs[4];
1563
1564 do_cpuid(0, regs);
1565 cpu_high = regs[0];
1566 ((u_int *)&cpu_vendor)[0] = regs[1];
1567 ((u_int *)&cpu_vendor)[1] = regs[3];
1568 ((u_int *)&cpu_vendor)[2] = regs[2];
1569 cpu_vendor[12] = '\0';
1570
1571 do_cpuid(1, regs);
1572 cpu_id = regs[0];
1573 cpu_procinfo = regs[1];
1574 cpu_feature = regs[3];
1575 cpu_feature2 = regs[2];
1576 }
1577
1578 void
identify_cpu2(void)1579 identify_cpu2(void)
1580 {
1581 u_int regs[4], cpu_stdext_disable, max_eax_l7;
1582
1583 if (cpu_high >= 6) {
1584 cpuid_count(6, 0, regs);
1585 cpu_power_eax = regs[0];
1586 cpu_power_ebx = regs[1];
1587 cpu_power_ecx = regs[2];
1588 cpu_power_edx = regs[3];
1589 }
1590
1591 if (cpu_high >= 7) {
1592 cpuid_count(7, 0, regs);
1593 cpu_stdext_feature = regs[1];
1594 max_eax_l7 = regs[0];
1595
1596 /*
1597 * Some hypervisors failed to filter out unsupported
1598 * extended features. Allow to disable the
1599 * extensions, activation of which requires setting a
1600 * bit in CR4, and which VM monitors do not support.
1601 */
1602 cpu_stdext_disable = 0;
1603 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1604 cpu_stdext_feature &= ~cpu_stdext_disable;
1605
1606 cpu_stdext_feature2 = regs[2];
1607 cpu_stdext_feature3 = regs[3];
1608
1609 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1610 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1611
1612 if (max_eax_l7 >= 1) {
1613 cpuid_count(7, 1, regs);
1614 cpu_stdext_feature4 = regs[0];
1615 }
1616 }
1617 }
1618
1619 void
identify_cpu_ext_features(void)1620 identify_cpu_ext_features(void)
1621 {
1622 u_int regs[4];
1623
1624 if (cpu_high >= 7) {
1625 cpuid_count(7, 0, regs);
1626 cpu_stdext_feature2 = regs[2];
1627 cpu_stdext_feature3 = regs[3];
1628 }
1629 }
1630
1631 void
identify_cpu_fixup_bsp(void)1632 identify_cpu_fixup_bsp(void)
1633 {
1634 u_int regs[4];
1635
1636 cpu_vendor_id = find_cpu_vendor_id();
1637
1638 if (fix_cpuid()) {
1639 do_cpuid(0, regs);
1640 cpu_high = regs[0];
1641 }
1642 }
1643
1644 /*
1645 * Final stage of CPU identification.
1646 */
1647 void
finishidentcpu(void)1648 finishidentcpu(void)
1649 {
1650 u_int regs[4];
1651 #ifdef __i386__
1652 u_char ccr3;
1653 #endif
1654
1655 identify_cpu_fixup_bsp();
1656
1657 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1658 do_cpuid(5, regs);
1659 cpu_mon_mwait_flags = regs[2];
1660 cpu_mon_mwait_edx = regs[3];
1661 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1662 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1663 }
1664
1665 identify_cpu2();
1666
1667 #ifdef __i386__
1668 if (cpu_high > 0 &&
1669 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1670 cpu_vendor_id == CPU_VENDOR_AMD ||
1671 cpu_vendor_id == CPU_VENDOR_HYGON ||
1672 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1673 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1674 cpu_vendor_id == CPU_VENDOR_NSC)) {
1675 do_cpuid(0x80000000, regs);
1676 if (regs[0] >= 0x80000000)
1677 cpu_exthigh = regs[0];
1678 }
1679 #else
1680 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1681 cpu_vendor_id == CPU_VENDOR_AMD ||
1682 cpu_vendor_id == CPU_VENDOR_HYGON ||
1683 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1684 do_cpuid(0x80000000, regs);
1685 cpu_exthigh = regs[0];
1686 }
1687 #endif
1688 if (cpu_exthigh >= 0x80000001) {
1689 do_cpuid(0x80000001, regs);
1690 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1691 amd_feature2 = regs[2];
1692 }
1693 if (cpu_exthigh >= 0x80000007) {
1694 do_cpuid(0x80000007, regs);
1695 amd_rascap = regs[1];
1696 amd_pminfo = regs[3];
1697 }
1698 if (cpu_exthigh >= 0x80000008) {
1699 do_cpuid(0x80000008, regs);
1700 cpu_maxphyaddr = regs[0] & 0xff;
1701 amd_extended_feature_extensions = regs[1];
1702 cpu_procinfo2 = regs[2];
1703 cpu_procinfo3 = regs[3];
1704 } else {
1705 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1706 }
1707
1708 #ifdef __i386__
1709 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1710 if (cpu == CPU_486) {
1711 /*
1712 * These conditions are equivalent to:
1713 * - CPU does not support cpuid instruction.
1714 * - Cyrix/IBM CPU is detected.
1715 */
1716 if (identblue() == IDENTBLUE_IBMCPU) {
1717 strcpy(cpu_vendor, "IBM");
1718 cpu_vendor_id = CPU_VENDOR_IBM;
1719 cpu = CPU_BLUE;
1720 return;
1721 }
1722 }
1723 switch (cpu_id & 0xf00) {
1724 case 0x600:
1725 /*
1726 * Cyrix's datasheet does not describe DIRs.
1727 * Therefor, I assume it does not have them
1728 * and use the result of the cpuid instruction.
1729 * XXX they seem to have it for now at least. -Peter
1730 */
1731 identifycyrix();
1732 cpu = CPU_M2;
1733 break;
1734 default:
1735 identifycyrix();
1736 /*
1737 * This routine contains a trick.
1738 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1739 */
1740 switch (cyrix_did & 0x00f0) {
1741 case 0x00:
1742 case 0xf0:
1743 cpu = CPU_486DLC;
1744 break;
1745 case 0x10:
1746 cpu = CPU_CY486DX;
1747 break;
1748 case 0x20:
1749 if ((cyrix_did & 0x000f) < 8)
1750 cpu = CPU_M1;
1751 else
1752 cpu = CPU_M1SC;
1753 break;
1754 case 0x30:
1755 cpu = CPU_M1;
1756 break;
1757 case 0x40:
1758 /* MediaGX CPU */
1759 cpu = CPU_M1SC;
1760 break;
1761 default:
1762 /* M2 and later CPUs are treated as M2. */
1763 cpu = CPU_M2;
1764
1765 /*
1766 * enable cpuid instruction.
1767 */
1768 ccr3 = read_cyrix_reg(CCR3);
1769 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1770 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1771 write_cyrix_reg(CCR3, ccr3);
1772
1773 do_cpuid(0, regs);
1774 cpu_high = regs[0]; /* eax */
1775 do_cpuid(1, regs);
1776 cpu_id = regs[0]; /* eax */
1777 cpu_feature = regs[3]; /* edx */
1778 break;
1779 }
1780 }
1781 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1782 /*
1783 * There are BlueLightning CPUs that do not change
1784 * undefined flags by dividing 5 by 2. In this case,
1785 * the CPU identification routine in locore.s leaves
1786 * cpu_vendor null string and puts CPU_486 into the
1787 * cpu.
1788 */
1789 if (identblue() == IDENTBLUE_IBMCPU) {
1790 strcpy(cpu_vendor, "IBM");
1791 cpu_vendor_id = CPU_VENDOR_IBM;
1792 cpu = CPU_BLUE;
1793 return;
1794 }
1795 }
1796 #endif
1797 }
1798
1799 int
pti_get_default(void)1800 pti_get_default(void)
1801 {
1802
1803 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 ||
1804 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0)
1805 return (0);
1806 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1807 return (0);
1808 return (1);
1809 }
1810
1811 static u_int
find_cpu_vendor_id(void)1812 find_cpu_vendor_id(void)
1813 {
1814 int i;
1815
1816 for (i = 0; i < nitems(cpu_vendors); i++)
1817 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1818 return (cpu_vendors[i].vendor_id);
1819 return (0);
1820 }
1821
1822 static void
print_AMD_assoc(int i)1823 print_AMD_assoc(int i)
1824 {
1825 if (i == 255)
1826 printf(", fully associative\n");
1827 else
1828 printf(", %d-way associative\n", i);
1829 }
1830
1831 static void
print_AMD_l2_assoc(int i)1832 print_AMD_l2_assoc(int i)
1833 {
1834 switch (i & 0x0f) {
1835 case 0: printf(", disabled/not present\n"); break;
1836 case 1: printf(", direct mapped\n"); break;
1837 case 2: printf(", 2-way associative\n"); break;
1838 case 4: printf(", 4-way associative\n"); break;
1839 case 6: printf(", 8-way associative\n"); break;
1840 case 8: printf(", 16-way associative\n"); break;
1841 case 15: printf(", fully associative\n"); break;
1842 default: printf(", reserved configuration\n"); break;
1843 }
1844 }
1845
1846 static void
print_AMD_info(void)1847 print_AMD_info(void)
1848 {
1849 #ifdef __i386__
1850 uint64_t amd_whcr;
1851 #endif
1852 u_int regs[4];
1853
1854 if (cpu_exthigh >= 0x80000005) {
1855 do_cpuid(0x80000005, regs);
1856 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1857 print_AMD_assoc(regs[0] >> 24);
1858
1859 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1860 print_AMD_assoc((regs[0] >> 8) & 0xff);
1861
1862 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1863 print_AMD_assoc(regs[1] >> 24);
1864
1865 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1866 print_AMD_assoc((regs[1] >> 8) & 0xff);
1867
1868 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1869 printf(", %d bytes/line", regs[2] & 0xff);
1870 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1871 print_AMD_assoc((regs[2] >> 16) & 0xff);
1872
1873 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1874 printf(", %d bytes/line", regs[3] & 0xff);
1875 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1876 print_AMD_assoc((regs[3] >> 16) & 0xff);
1877 }
1878
1879 if (cpu_exthigh >= 0x80000006) {
1880 do_cpuid(0x80000006, regs);
1881 if ((regs[0] >> 16) != 0) {
1882 printf("L2 2MB data TLB: %d entries",
1883 (regs[0] >> 16) & 0xfff);
1884 print_AMD_l2_assoc(regs[0] >> 28);
1885 printf("L2 2MB instruction TLB: %d entries",
1886 regs[0] & 0xfff);
1887 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1888 } else {
1889 printf("L2 2MB unified TLB: %d entries",
1890 regs[0] & 0xfff);
1891 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1892 }
1893 if ((regs[1] >> 16) != 0) {
1894 printf("L2 4KB data TLB: %d entries",
1895 (regs[1] >> 16) & 0xfff);
1896 print_AMD_l2_assoc(regs[1] >> 28);
1897
1898 printf("L2 4KB instruction TLB: %d entries",
1899 (regs[1] >> 16) & 0xfff);
1900 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1901 } else {
1902 printf("L2 4KB unified TLB: %d entries",
1903 (regs[1] >> 16) & 0xfff);
1904 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1905 }
1906 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1907 printf(", %d bytes/line", regs[2] & 0xff);
1908 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1909 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1910 }
1911
1912 #ifdef __i386__
1913 if (((cpu_id & 0xf00) == 0x500)
1914 && (((cpu_id & 0x0f0) > 0x80)
1915 || (((cpu_id & 0x0f0) == 0x80)
1916 && (cpu_id & 0x00f) > 0x07))) {
1917 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1918 amd_whcr = rdmsr(0xc0000082);
1919 if (!(amd_whcr & (0x3ff << 22))) {
1920 printf("Write Allocate Disable\n");
1921 } else {
1922 printf("Write Allocate Enable Limit: %dM bytes\n",
1923 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1924 printf("Write Allocate 15-16M bytes: %s\n",
1925 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1926 }
1927 } else if (((cpu_id & 0xf00) == 0x500)
1928 && ((cpu_id & 0x0f0) > 0x50)) {
1929 /* K6, K6-2(old core) */
1930 amd_whcr = rdmsr(0xc0000082);
1931 if (!(amd_whcr & (0x7f << 1))) {
1932 printf("Write Allocate Disable\n");
1933 } else {
1934 printf("Write Allocate Enable Limit: %dM bytes\n",
1935 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1936 printf("Write Allocate 15-16M bytes: %s\n",
1937 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1938 printf("Hardware Write Allocate Control: %s\n",
1939 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1940 }
1941 }
1942 #endif
1943 /*
1944 * Opteron Rev E shows a bug as in very rare occasions a read memory
1945 * barrier is not performed as expected if it is followed by a
1946 * non-atomic read-modify-write instruction.
1947 * As long as that bug pops up very rarely (intensive machine usage
1948 * on other operating systems generally generates one unexplainable
1949 * crash any 2 months) and as long as a model specific fix would be
1950 * impractical at this stage, print out a warning string if the broken
1951 * model and family are identified.
1952 */
1953 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1954 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1955 printf("WARNING: This architecture revision has known SMP "
1956 "hardware bugs which may cause random instability\n");
1957 }
1958
1959 static void
print_INTEL_info(void)1960 print_INTEL_info(void)
1961 {
1962 u_int regs[4];
1963 u_int rounds, regnum;
1964 u_int nwaycode, nway;
1965
1966 if (cpu_high >= 2) {
1967 rounds = 0;
1968 do {
1969 do_cpuid(0x2, regs);
1970 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1971 break; /* we have a buggy CPU */
1972
1973 for (regnum = 0; regnum <= 3; ++regnum) {
1974 if (regs[regnum] & (1<<31))
1975 continue;
1976 if (regnum != 0)
1977 print_INTEL_TLB(regs[regnum] & 0xff);
1978 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1979 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1980 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1981 }
1982 } while (--rounds > 0);
1983 }
1984
1985 if (cpu_exthigh >= 0x80000006) {
1986 do_cpuid(0x80000006, regs);
1987 nwaycode = (regs[2] >> 12) & 0x0f;
1988 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1989 nway = 1 << (nwaycode / 2);
1990 else
1991 nway = 0;
1992 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1993 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1994 }
1995 }
1996
1997 static void
print_INTEL_TLB(u_int data)1998 print_INTEL_TLB(u_int data)
1999 {
2000 switch (data) {
2001 case 0x0:
2002 case 0x40:
2003 default:
2004 break;
2005 case 0x1:
2006 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
2007 break;
2008 case 0x2:
2009 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
2010 break;
2011 case 0x3:
2012 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
2013 break;
2014 case 0x4:
2015 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
2016 break;
2017 case 0x6:
2018 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
2019 break;
2020 case 0x8:
2021 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
2022 break;
2023 case 0x9:
2024 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
2025 break;
2026 case 0xa:
2027 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
2028 break;
2029 case 0xb:
2030 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
2031 break;
2032 case 0xc:
2033 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
2034 break;
2035 case 0xd:
2036 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
2037 break;
2038 case 0xe:
2039 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
2040 break;
2041 case 0x1d:
2042 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
2043 break;
2044 case 0x21:
2045 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
2046 break;
2047 case 0x22:
2048 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2049 break;
2050 case 0x23:
2051 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2052 break;
2053 case 0x24:
2054 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
2055 break;
2056 case 0x25:
2057 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2058 break;
2059 case 0x29:
2060 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2061 break;
2062 case 0x2c:
2063 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2064 break;
2065 case 0x30:
2066 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2067 break;
2068 case 0x39: /* De-listed in SDM rev. 54 */
2069 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2070 break;
2071 case 0x3b: /* De-listed in SDM rev. 54 */
2072 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2073 break;
2074 case 0x3c: /* De-listed in SDM rev. 54 */
2075 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2076 break;
2077 case 0x41:
2078 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2079 break;
2080 case 0x42:
2081 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2082 break;
2083 case 0x43:
2084 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2085 break;
2086 case 0x44:
2087 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2088 break;
2089 case 0x45:
2090 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2091 break;
2092 case 0x46:
2093 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2094 break;
2095 case 0x47:
2096 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2097 break;
2098 case 0x48:
2099 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2100 break;
2101 case 0x49:
2102 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2103 CPUID_TO_MODEL(cpu_id) == 0x6)
2104 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2105 else
2106 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2107 break;
2108 case 0x4a:
2109 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2110 break;
2111 case 0x4b:
2112 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2113 break;
2114 case 0x4c:
2115 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2116 break;
2117 case 0x4d:
2118 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2119 break;
2120 case 0x4e:
2121 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2122 break;
2123 case 0x4f:
2124 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2125 break;
2126 case 0x50:
2127 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2128 break;
2129 case 0x51:
2130 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2131 break;
2132 case 0x52:
2133 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2134 break;
2135 case 0x55:
2136 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2137 break;
2138 case 0x56:
2139 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2140 break;
2141 case 0x57:
2142 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2143 break;
2144 case 0x59:
2145 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2146 break;
2147 case 0x5a:
2148 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2149 break;
2150 case 0x5b:
2151 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2152 break;
2153 case 0x5c:
2154 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2155 break;
2156 case 0x5d:
2157 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2158 break;
2159 case 0x60:
2160 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2161 break;
2162 case 0x61:
2163 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2164 break;
2165 case 0x63:
2166 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2167 break;
2168 case 0x64:
2169 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2170 break;
2171 case 0x66:
2172 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2173 break;
2174 case 0x67:
2175 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2176 break;
2177 case 0x68:
2178 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2179 break;
2180 case 0x6a:
2181 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2182 break;
2183 case 0x6b:
2184 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2185 break;
2186 case 0x6c:
2187 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2188 break;
2189 case 0x6d:
2190 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2191 break;
2192 case 0x70:
2193 printf("Trace cache: 12K-uops, 8-way set associative\n");
2194 break;
2195 case 0x71:
2196 printf("Trace cache: 16K-uops, 8-way set associative\n");
2197 break;
2198 case 0x72:
2199 printf("Trace cache: 32K-uops, 8-way set associative\n");
2200 break;
2201 case 0x76:
2202 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2203 break;
2204 case 0x78:
2205 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2206 break;
2207 case 0x79:
2208 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2209 break;
2210 case 0x7a:
2211 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2212 break;
2213 case 0x7b:
2214 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2215 break;
2216 case 0x7c:
2217 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2218 break;
2219 case 0x7d:
2220 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2221 break;
2222 case 0x7f:
2223 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2224 break;
2225 case 0x80:
2226 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2227 break;
2228 case 0x82:
2229 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2230 break;
2231 case 0x83:
2232 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2233 break;
2234 case 0x84:
2235 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2236 break;
2237 case 0x85:
2238 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2239 break;
2240 case 0x86:
2241 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2242 break;
2243 case 0x87:
2244 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2245 break;
2246 case 0xa0:
2247 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2248 break;
2249 case 0xb0:
2250 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2251 break;
2252 case 0xb1:
2253 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2254 break;
2255 case 0xb2:
2256 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2257 break;
2258 case 0xb3:
2259 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2260 break;
2261 case 0xb4:
2262 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2263 break;
2264 case 0xb5:
2265 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2266 break;
2267 case 0xb6:
2268 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2269 break;
2270 case 0xba:
2271 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2272 break;
2273 case 0xc0:
2274 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2275 break;
2276 case 0xc1:
2277 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2278 break;
2279 case 0xc2:
2280 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2281 break;
2282 case 0xc3:
2283 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2284 break;
2285 case 0xc4:
2286 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2287 break;
2288 case 0xca:
2289 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2290 break;
2291 case 0xd0:
2292 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2293 break;
2294 case 0xd1:
2295 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2296 break;
2297 case 0xd2:
2298 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2299 break;
2300 case 0xd6:
2301 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2302 break;
2303 case 0xd7:
2304 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2305 break;
2306 case 0xd8:
2307 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2308 break;
2309 case 0xdc:
2310 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2311 break;
2312 case 0xdd:
2313 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2314 break;
2315 case 0xde:
2316 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2317 break;
2318 case 0xe2:
2319 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2320 break;
2321 case 0xe3:
2322 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2323 break;
2324 case 0xe4:
2325 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2326 break;
2327 case 0xea:
2328 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2329 break;
2330 case 0xeb:
2331 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2332 break;
2333 case 0xec:
2334 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2335 break;
2336 case 0xf0:
2337 printf("64-Byte prefetching\n");
2338 break;
2339 case 0xf1:
2340 printf("128-Byte prefetching\n");
2341 break;
2342 }
2343 }
2344
2345 static void
print_svm_info(void)2346 print_svm_info(void)
2347 {
2348 u_int features, regs[4];
2349 uint64_t msr;
2350 int comma;
2351
2352 printf("\n SVM: ");
2353 do_cpuid(0x8000000A, regs);
2354 features = regs[3];
2355
2356 msr = rdmsr(MSR_VM_CR);
2357 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2358 printf("(disabled in BIOS) ");
2359
2360 if (!bootverbose) {
2361 comma = 0;
2362 if (features & (1 << 0)) {
2363 printf("%sNP", comma ? "," : "");
2364 comma = 1;
2365 }
2366 if (features & (1 << 3)) {
2367 printf("%sNRIP", comma ? "," : "");
2368 comma = 1;
2369 }
2370 if (features & (1 << 5)) {
2371 printf("%sVClean", comma ? "," : "");
2372 comma = 1;
2373 }
2374 if (features & (1 << 6)) {
2375 printf("%sAFlush", comma ? "," : "");
2376 comma = 1;
2377 }
2378 if (features & (1 << 7)) {
2379 printf("%sDAssist", comma ? "," : "");
2380 comma = 1;
2381 }
2382 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2383 return;
2384 }
2385
2386 printf("Features=0x%b", features,
2387 "\020"
2388 "\001NP" /* Nested paging */
2389 "\002LbrVirt" /* LBR virtualization */
2390 "\003SVML" /* SVM lock */
2391 "\004NRIPS" /* NRIP save */
2392 "\005TscRateMsr" /* MSR based TSC rate control */
2393 "\006VmcbClean" /* VMCB clean bits */
2394 "\007FlushByAsid" /* Flush by ASID */
2395 "\010DecodeAssist" /* Decode assist */
2396 "\011<b8>"
2397 "\012<b9>"
2398 "\013PauseFilter" /* PAUSE intercept filter */
2399 "\014EncryptedMcodePatch"
2400 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2401 "\016AVIC" /* virtual interrupt controller */
2402 "\017<b14>"
2403 "\020V_VMSAVE_VMLOAD"
2404 "\021vGIF"
2405 "\022GMET" /* Guest Mode Execute Trap */
2406 "\023<b18>"
2407 "\024<b19>"
2408 "\025GuesSpecCtl" /* Guest Spec_ctl */
2409 "\026<b21>"
2410 "\027<b22>"
2411 "\030<b23>"
2412 "\031<b24>"
2413 "\032<b25>"
2414 "\033<b26>"
2415 "\034<b27>"
2416 "\035<b28>"
2417 "\036<b29>"
2418 "\037<b30>"
2419 "\040<b31>"
2420 );
2421 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2422 }
2423
2424 #ifdef __i386__
2425 static void
print_transmeta_info(void)2426 print_transmeta_info(void)
2427 {
2428 u_int regs[4], nreg = 0;
2429
2430 do_cpuid(0x80860000, regs);
2431 nreg = regs[0];
2432 if (nreg >= 0x80860001) {
2433 do_cpuid(0x80860001, regs);
2434 printf(" Processor revision %u.%u.%u.%u\n",
2435 (regs[1] >> 24) & 0xff,
2436 (regs[1] >> 16) & 0xff,
2437 (regs[1] >> 8) & 0xff,
2438 regs[1] & 0xff);
2439 }
2440 if (nreg >= 0x80860002) {
2441 do_cpuid(0x80860002, regs);
2442 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2443 (regs[1] >> 24) & 0xff,
2444 (regs[1] >> 16) & 0xff,
2445 (regs[1] >> 8) & 0xff,
2446 regs[1] & 0xff,
2447 regs[2]);
2448 }
2449 if (nreg >= 0x80860006) {
2450 char info[65];
2451 do_cpuid(0x80860003, (u_int*) &info[0]);
2452 do_cpuid(0x80860004, (u_int*) &info[16]);
2453 do_cpuid(0x80860005, (u_int*) &info[32]);
2454 do_cpuid(0x80860006, (u_int*) &info[48]);
2455 info[64] = 0;
2456 printf(" %s\n", info);
2457 }
2458 }
2459 #endif
2460
2461 static void
print_via_padlock_info(void)2462 print_via_padlock_info(void)
2463 {
2464 u_int regs[4];
2465
2466 do_cpuid(0xc0000001, regs);
2467 printf("\n VIA Padlock Features=0x%b", regs[3],
2468 "\020"
2469 "\003RNG" /* RNG */
2470 "\007AES" /* ACE */
2471 "\011AES-CTR" /* ACE2 */
2472 "\013SHA1,SHA256" /* PHE */
2473 "\015RSA" /* PMM */
2474 );
2475 }
2476
2477 static uint32_t
vmx_settable(uint64_t basic,int msr,int true_msr)2478 vmx_settable(uint64_t basic, int msr, int true_msr)
2479 {
2480 uint64_t val;
2481
2482 if (basic & (1ULL << 55))
2483 val = rdmsr(true_msr);
2484 else
2485 val = rdmsr(msr);
2486
2487 /* Just report the controls that can be set to 1. */
2488 return (val >> 32);
2489 }
2490
2491 static void
print_vmx_info(void)2492 print_vmx_info(void)
2493 {
2494 uint64_t basic, msr;
2495 uint32_t entry, exit, mask, pin, proc, proc2;
2496 int comma;
2497
2498 printf("\n VT-x: ");
2499 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2500 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2501 printf("(disabled in BIOS) ");
2502 basic = rdmsr(MSR_VMX_BASIC);
2503 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2504 MSR_VMX_TRUE_PINBASED_CTLS);
2505 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2506 MSR_VMX_TRUE_PROCBASED_CTLS);
2507 if (proc & PROCBASED_SECONDARY_CONTROLS)
2508 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2509 MSR_VMX_PROCBASED_CTLS2);
2510 else
2511 proc2 = 0;
2512 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2513 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2514
2515 if (!bootverbose) {
2516 comma = 0;
2517 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2518 entry & VM_ENTRY_LOAD_PAT) {
2519 printf("%sPAT", comma ? "," : "");
2520 comma = 1;
2521 }
2522 if (proc & PROCBASED_HLT_EXITING) {
2523 printf("%sHLT", comma ? "," : "");
2524 comma = 1;
2525 }
2526 if (proc & PROCBASED_MTF) {
2527 printf("%sMTF", comma ? "," : "");
2528 comma = 1;
2529 }
2530 if (proc & PROCBASED_PAUSE_EXITING) {
2531 printf("%sPAUSE", comma ? "," : "");
2532 comma = 1;
2533 }
2534 if (proc2 & PROCBASED2_ENABLE_EPT) {
2535 printf("%sEPT", comma ? "," : "");
2536 comma = 1;
2537 }
2538 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2539 printf("%sUG", comma ? "," : "");
2540 comma = 1;
2541 }
2542 if (proc2 & PROCBASED2_ENABLE_VPID) {
2543 printf("%sVPID", comma ? "," : "");
2544 comma = 1;
2545 }
2546 if (proc & PROCBASED_USE_TPR_SHADOW &&
2547 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2548 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2549 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2550 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2551 printf("%sVID", comma ? "," : "");
2552 comma = 1;
2553 if (pin & PINBASED_POSTED_INTERRUPT)
2554 printf(",PostIntr");
2555 }
2556 return;
2557 }
2558
2559 mask = basic >> 32;
2560 printf("Basic Features=0x%b", mask,
2561 "\020"
2562 "\02132PA" /* 32-bit physical addresses */
2563 "\022SMM" /* SMM dual-monitor */
2564 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2565 "\030TRUE" /* TRUE_CTLS MSRs */
2566 );
2567 printf("\n Pin-Based Controls=0x%b", pin,
2568 "\020"
2569 "\001ExtINT" /* External-interrupt exiting */
2570 "\004NMI" /* NMI exiting */
2571 "\006VNMI" /* Virtual NMIs */
2572 "\007PreTmr" /* Activate VMX-preemption timer */
2573 "\010PostIntr" /* Process posted interrupts */
2574 );
2575 printf("\n Primary Processor Controls=0x%b", proc,
2576 "\020"
2577 "\003INTWIN" /* Interrupt-window exiting */
2578 "\004TSCOff" /* Use TSC offsetting */
2579 "\010HLT" /* HLT exiting */
2580 "\012INVLPG" /* INVLPG exiting */
2581 "\013MWAIT" /* MWAIT exiting */
2582 "\014RDPMC" /* RDPMC exiting */
2583 "\015RDTSC" /* RDTSC exiting */
2584 "\020CR3-LD" /* CR3-load exiting */
2585 "\021CR3-ST" /* CR3-store exiting */
2586 "\024CR8-LD" /* CR8-load exiting */
2587 "\025CR8-ST" /* CR8-store exiting */
2588 "\026TPR" /* Use TPR shadow */
2589 "\027NMIWIN" /* NMI-window exiting */
2590 "\030MOV-DR" /* MOV-DR exiting */
2591 "\031IO" /* Unconditional I/O exiting */
2592 "\032IOmap" /* Use I/O bitmaps */
2593 "\034MTF" /* Monitor trap flag */
2594 "\035MSRmap" /* Use MSR bitmaps */
2595 "\036MONITOR" /* MONITOR exiting */
2596 "\037PAUSE" /* PAUSE exiting */
2597 );
2598 if (proc & PROCBASED_SECONDARY_CONTROLS)
2599 printf("\n Secondary Processor Controls=0x%b", proc2,
2600 "\020"
2601 "\001APIC" /* Virtualize APIC accesses */
2602 "\002EPT" /* Enable EPT */
2603 "\003DT" /* Descriptor-table exiting */
2604 "\004RDTSCP" /* Enable RDTSCP */
2605 "\005x2APIC" /* Virtualize x2APIC mode */
2606 "\006VPID" /* Enable VPID */
2607 "\007WBINVD" /* WBINVD exiting */
2608 "\010UG" /* Unrestricted guest */
2609 "\011APIC-reg" /* APIC-register virtualization */
2610 "\012VID" /* Virtual-interrupt delivery */
2611 "\013PAUSE-loop" /* PAUSE-loop exiting */
2612 "\014RDRAND" /* RDRAND exiting */
2613 "\015INVPCID" /* Enable INVPCID */
2614 "\016VMFUNC" /* Enable VM functions */
2615 "\017VMCS" /* VMCS shadowing */
2616 "\020EPT#VE" /* EPT-violation #VE */
2617 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2618 );
2619 printf("\n Exit Controls=0x%b", exit,
2620 "\020"
2621 "\003DR" /* Save debug controls */
2622 /* Ignore Host address-space size */
2623 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2624 "\020AckInt" /* Acknowledge interrupt on exit */
2625 "\023PAT-SV" /* Save MSR_PAT */
2626 "\024PAT-LD" /* Load MSR_PAT */
2627 "\025EFER-SV" /* Save MSR_EFER */
2628 "\026EFER-LD" /* Load MSR_EFER */
2629 "\027PTMR-SV" /* Save VMX-preemption timer value */
2630 );
2631 printf("\n Entry Controls=0x%b", entry,
2632 "\020"
2633 "\003DR" /* Save debug controls */
2634 /* Ignore IA-32e mode guest */
2635 /* Ignore Entry to SMM */
2636 /* Ignore Deactivate dual-monitor treatment */
2637 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2638 "\017PAT" /* Load MSR_PAT */
2639 "\020EFER" /* Load MSR_EFER */
2640 );
2641 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2642 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2643 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2644 mask = msr;
2645 printf("\n EPT Features=0x%b", mask,
2646 "\020"
2647 "\001XO" /* Execute-only translations */
2648 "\007PW4" /* Page-walk length of 4 */
2649 "\011UC" /* EPT paging-structure mem can be UC */
2650 "\017WB" /* EPT paging-structure mem can be WB */
2651 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2652 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2653 "\025INVEPT" /* INVEPT is supported */
2654 "\026AD" /* Accessed and dirty flags for EPT */
2655 "\032single" /* INVEPT single-context type */
2656 "\033all" /* INVEPT all-context type */
2657 );
2658 mask = msr >> 32;
2659 printf("\n VPID Features=0x%b", mask,
2660 "\020"
2661 "\001INVVPID" /* INVVPID is supported */
2662 "\011individual" /* INVVPID individual-address type */
2663 "\012single" /* INVVPID single-context type */
2664 "\013all" /* INVVPID all-context type */
2665 /* INVVPID single-context-retaining-globals type */
2666 "\014single-globals"
2667 );
2668 }
2669 }
2670
2671 static void
print_hypervisor_info(void)2672 print_hypervisor_info(void)
2673 {
2674
2675 if (*hv_vendor != '\0')
2676 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2677 }
2678
2679 /*
2680 * Returns the maximum physical address that can be used with the
2681 * current system.
2682 */
2683 vm_paddr_t
cpu_getmaxphyaddr(void)2684 cpu_getmaxphyaddr(void)
2685 {
2686
2687 #if defined(__i386__)
2688 if (!pae_mode)
2689 return (0xffffffff);
2690 #endif
2691 return ((1ULL << cpu_maxphyaddr) - 1);
2692 }
2693