1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Contains CPU feature definitions
4 *
5 * Copyright (C) 2015 ARM Ltd.
6 *
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
11 *
12 * The basic problem is that hardware folks have started gluing together CPUs
13 * with distinct architectural features; in some cases even creating SoCs where
14 * user-visible instructions are available only on a subset of the available
15 * cores. We try to address this by snapshotting the feature registers of the
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
19 * known as the "safe" value. This snapshot state can be queried to view the
20 * "sanitised" value of a feature register.
21 *
22 * The sanitised register values are used to decide which capabilities we
23 * have in the system. These may be in the form of traditional "hwcaps"
24 * advertised to userspace or internal "cpucaps" which are used to configure
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
28 *
29 * Some implementation details worth remembering:
30 *
31 * - Mismatched features are *always* sanitised to a "safe" value, which
32 * usually indicates that the feature is not supported.
33 *
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35 * warning when onlining an offending CPU and the kernel will be tainted
36 * with TAINT_CPU_OUT_OF_SPEC.
37 *
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
39 * userspace. FTR_VISIBLE features in registers that are only visible
40 * to EL0 by trapping *must* have a corresponding HWCAP so that late
41 * onlining of CPUs cannot lead to features disappearing at runtime.
42 *
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
45 *
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47 * scheme for fields in ID registers") to understand when feature fields
48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
49 *
50 * - KVM exposes its own view of the feature registers to guest operating
51 * systems regardless of FTR_VISIBLE. This is typically driven from the
52 * sanitised register values to allow virtual CPUs to be migrated between
53 * arbitrary physical CPUs, but some features not present on the host are
54 * also advertised and emulated. Look at sys_reg_descs[] for the gory
55 * details.
56 *
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59 * This is stronger than FTR_HIDDEN and can be used to hide features from
60 * KVM guests.
61 */
62
63 #define pr_fmt(fmt) "CPU features: " fmt
64
65 #include <linux/bsearch.h>
66 #include <linux/cpumask.h>
67 #include <linux/crash_dump.h>
68 #include <linux/kstrtox.h>
69 #include <linux/sort.h>
70 #include <linux/stop_machine.h>
71 #include <linux/sysfs.h>
72 #include <linux/types.h>
73 #include <linux/minmax.h>
74 #include <linux/mm.h>
75 #include <linux/cpu.h>
76 #include <linux/kasan.h>
77 #include <linux/percpu.h>
78 #include <linux/sched/isolation.h>
79
80 #include <asm/cpu.h>
81 #include <asm/cpufeature.h>
82 #include <asm/cpu_ops.h>
83 #include <asm/fpsimd.h>
84 #include <asm/hwcap.h>
85 #include <asm/insn.h>
86 #include <asm/kvm_host.h>
87 #include <asm/mmu_context.h>
88 #include <asm/mte.h>
89 #include <asm/hypervisor.h>
90 #include <asm/processor.h>
91 #include <asm/smp.h>
92 #include <asm/sysreg.h>
93 #include <asm/traps.h>
94 #include <asm/vectors.h>
95 #include <asm/virt.h>
96
97 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
98 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly;
99
100 #ifdef CONFIG_COMPAT
101 #define COMPAT_ELF_HWCAP_DEFAULT \
102 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
103 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
104 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
105 COMPAT_HWCAP_LPAE)
106 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
107 unsigned int compat_elf_hwcap2 __read_mostly;
108 unsigned int compat_elf_hwcap3 __read_mostly;
109 #endif
110
111 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS);
112 EXPORT_SYMBOL(system_cpucaps);
113 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS];
114
115 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS);
116
117 /*
118 * arm64_use_ng_mappings must be placed in the .data section, otherwise it
119 * ends up in the .bss section where it is initialized in early_map_kernel()
120 * after the MMU (with the idmap) was enabled. create_init_idmap() - which
121 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG -
122 * may end up generating an incorrect idmap page table attributes.
123 */
124 bool arm64_use_ng_mappings __read_mostly = false;
125 EXPORT_SYMBOL(arm64_use_ng_mappings);
126
127 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
128
129 /*
130 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs
131 * support it?
132 */
133 static bool __read_mostly allow_mismatched_32bit_el0;
134
135 /*
136 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have
137 * seen at least one CPU capable of 32-bit EL0.
138 */
139 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
140
141 /*
142 * Mask of CPUs supporting 32-bit EL0.
143 * Only valid if arm64_mismatched_32bit_el0 is enabled.
144 */
145 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;
146
dump_cpu_features(void)147 void dump_cpu_features(void)
148 {
149 /* file-wide pr_fmt adds "CPU features: " prefix */
150 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps);
151 }
152
153 #define __ARM64_MAX_POSITIVE(reg, field) \
154 ((reg##_##field##_SIGNED ? \
155 BIT(reg##_##field##_WIDTH - 1) : \
156 BIT(reg##_##field##_WIDTH)) - 1)
157
158 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1)
159
160 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \
161 .sys_reg = SYS_##reg, \
162 .field_pos = reg##_##field##_SHIFT, \
163 .field_width = reg##_##field##_WIDTH, \
164 .sign = reg##_##field##_SIGNED, \
165 .min_field_value = min_value, \
166 .max_field_value = max_value,
167
168 /*
169 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to
170 * an implicit maximum that depends on the sign-ess of the field.
171 *
172 * An unsigned field will be capped at all ones, while a signed field
173 * will be limited to the positive half only.
174 */
175 #define ARM64_CPUID_FIELDS(reg, field, min_value) \
176 __ARM64_CPUID_FIELDS(reg, field, \
177 SYS_FIELD_VALUE(reg, field, min_value), \
178 __ARM64_MAX_POSITIVE(reg, field))
179
180 /*
181 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an
182 * implicit minimal value to max_value. This should be used when
183 * matching a non-implemented property.
184 */
185 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \
186 __ARM64_CPUID_FIELDS(reg, field, \
187 __ARM64_MIN_NEGATIVE(reg, field), \
188 SYS_FIELD_VALUE(reg, field, max_value))
189
190 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
191 { \
192 .sign = SIGNED, \
193 .visible = VISIBLE, \
194 .strict = STRICT, \
195 .type = TYPE, \
196 .shift = SHIFT, \
197 .width = WIDTH, \
198 .safe_val = SAFE_VAL, \
199 }
200
201 /* Define a feature with unsigned values */
202 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
203 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
204
205 /* Define a feature with a signed value */
206 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
207 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
208
209 #define ARM64_FTR_END \
210 { \
211 .width = 0, \
212 }
213
214 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
215
216 static bool __system_matches_cap(unsigned int n);
217
218 /*
219 * NOTE: Any changes to the visibility of features should be kept in
220 * sync with the documentation of the CPU feature register ABI.
221 */
222 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0),
224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0),
225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0),
226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0),
227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0),
228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0),
229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0),
230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0),
231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0),
232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0),
233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0),
234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0),
235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0),
236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0),
237 ARM64_FTR_END,
238 };
239
240 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0),
243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0),
244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0),
245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0),
246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0),
247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0),
248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
249 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0),
250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0),
252 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0),
253 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0),
254 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0),
255 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
256 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0),
257 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
258 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0),
259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0),
260 ARM64_FTR_END,
261 };
262
263 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0),
265 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),
266 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),
267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0),
268 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
269 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0),
270 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
271 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
272 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
273 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0),
274 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0),
275 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0),
276 ARM64_FTR_END,
277 };
278
279 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = {
280 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0),
281 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0),
282 ARM64_FTR_END,
283 };
284
285 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0),
287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0),
288 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0),
289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0),
290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0),
291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0),
292 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
293 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0),
294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0),
295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0),
296 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI),
297 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI),
298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0),
299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0),
300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP),
301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP),
302 ARM64_FTR_END,
303 };
304
305 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
306 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS),
307 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0),
308 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
309 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0),
310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0),
311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0),
312 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
313 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI),
314 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI),
315 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
316 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0),
317 ARM64_FTR_END,
318 };
319
320 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = {
321 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0),
322 ARM64_FTR_END,
323 };
324
325 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
326 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
327 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0),
328 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
329 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0),
330 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
331 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0),
332 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
333 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0),
334 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
335 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0),
336 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
337 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0),
338 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
339 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0),
340 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
341 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0),
342 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
343 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0),
344 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
345 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0),
346 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
347 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0),
348 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
349 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0),
350 ARM64_FTR_END,
351 };
352
353 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
354 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
355 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0),
356 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
357 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0),
358 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
359 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0),
360 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
361 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0),
362 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
363 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0),
364 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
365 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0),
366 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
367 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0),
368 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
369 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0),
370 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
371 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0),
372 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
373 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0),
374 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
375 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0),
376 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
377 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0),
378 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
379 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0),
380 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
381 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0),
382 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
383 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0),
384 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
385 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0),
386 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
387 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0),
388 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
389 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0),
390 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
391 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0),
392 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
393 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0),
394 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
395 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0),
396 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
397 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0),
398 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
399 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0),
400 ARM64_FTR_END,
401 };
402
403 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = {
404 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0),
405 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0),
406 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0),
407 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0),
408 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0),
409 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0),
410 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0),
411 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0),
412 ARM64_FTR_END,
413 };
414
415 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
416 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0),
417 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0),
418 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0),
419 /*
420 * Page size not being supported at Stage-2 is not fatal. You
421 * just give up KVM if PAGE_SIZE isn't supported there. Go fix
422 * your favourite nesting hypervisor.
423 *
424 * There is a small corner case where the hypervisor explicitly
425 * advertises a given granule size at Stage-2 (value 2) on some
426 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
427 * vCPUs. Although this is not forbidden by the architecture, it
428 * indicates that the hypervisor is being silly (or buggy).
429 *
430 * We make no effort to cope with this and pretend that if these
431 * fields are inconsistent across vCPUs, then it isn't worth
432 * trying to bring KVM up.
433 */
434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1),
435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1),
436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1),
437 /*
438 * We already refuse to boot CPUs that don't support our configured
439 * page size, so we can only detect mismatches for a page size other
440 * than the one we're currently using. Unfortunately, SoCs like this
441 * exist in the wild so, even though we don't like it, we'll have to go
442 * along with it and treat them as non-strict.
443 */
444 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI),
445 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI),
446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI),
447
448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0),
449 /* Linux shouldn't care about secure memory */
450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0),
451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0),
452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0),
453 /*
454 * Differing PARange is fine as long as all peripherals and memory are mapped
455 * within the minimum PARange of all CPUs
456 */
457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0),
458 ARM64_FTR_END,
459 };
460
461 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0),
463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0),
464 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0),
465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0),
466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0),
467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0),
468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0),
469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0),
470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0),
471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0),
472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0),
473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0),
474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0),
475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0),
476 ARM64_FTR_END,
477 };
478
479 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0),
481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0),
482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0),
483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0),
484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0),
485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0),
486 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0),
487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0),
488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0),
489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0),
490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0),
491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0),
492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0),
493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0),
494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0),
495 ARM64_FTR_END,
496 };
497
498 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = {
499 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE),
500 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0),
501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0),
502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0),
503 ARM64_FTR_END,
504 };
505
506 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = {
507 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0),
508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0),
509 ARM64_FTR_END,
510 };
511
512 static const struct arm64_ftr_bits ftr_ctr[] = {
513 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
514 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1),
515 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1),
516 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0),
517 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0),
518 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1),
519 /*
520 * Linux can handle differing I-cache policies. Userspace JITs will
521 * make use of *minLine.
522 * If we have differing I-cache policies, report it as the weakest - VIPT.
523 */
524 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */
525 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0),
526 ARM64_FTR_END,
527 };
528
529 static struct arm64_ftr_override __ro_after_init no_override = { };
530
531 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
532 .name = "SYS_CTR_EL0",
533 .ftr_bits = ftr_ctr,
534 .override = &no_override,
535 };
536
537 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
538 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf),
539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0),
540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0),
541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0),
542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0),
543 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf),
544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0),
545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0),
546 ARM64_FTR_END,
547 };
548
549 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
550 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0),
551 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0),
552 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0),
553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0),
554 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0),
555 /*
556 * We can instantiate multiple PMU instances with different levels
557 * of support.
558 */
559 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0),
560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6),
561 ARM64_FTR_END,
562 };
563
564 static const struct arm64_ftr_bits ftr_mvfr0[] = {
565 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0),
566 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0),
567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0),
568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0),
569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0),
570 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0),
571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0),
572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0),
573 ARM64_FTR_END,
574 };
575
576 static const struct arm64_ftr_bits ftr_mvfr1[] = {
577 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0),
578 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0),
579 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0),
580 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0),
581 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0),
582 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0),
583 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0),
584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0),
585 ARM64_FTR_END,
586 };
587
588 static const struct arm64_ftr_bits ftr_mvfr2[] = {
589 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0),
590 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0),
591 ARM64_FTR_END,
592 };
593
594 static const struct arm64_ftr_bits ftr_dczid[] = {
595 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1),
596 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0),
597 ARM64_FTR_END,
598 };
599
600 static const struct arm64_ftr_bits ftr_gmid[] = {
601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0),
602 ARM64_FTR_END,
603 };
604
605 static const struct arm64_ftr_bits ftr_id_isar0[] = {
606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0),
607 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0),
608 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0),
609 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0),
610 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0),
611 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0),
612 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0),
613 ARM64_FTR_END,
614 };
615
616 static const struct arm64_ftr_bits ftr_id_isar5[] = {
617 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0),
618 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0),
619 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0),
620 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0),
621 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0),
622 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0),
623 ARM64_FTR_END,
624 };
625
626 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
627 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0),
628 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0),
629 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0),
630 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0),
631 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0),
632 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0),
633 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0),
634
635 /*
636 * SpecSEI = 1 indicates that the PE might generate an SError on an
637 * external abort on speculative read. It is safe to assume that an
638 * SError might be generated than it will not be. Hence it has been
639 * classified as FTR_HIGHER_SAFE.
640 */
641 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0),
642 ARM64_FTR_END,
643 };
644
645 static const struct arm64_ftr_bits ftr_id_isar4[] = {
646 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0),
647 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0),
648 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0),
649 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0),
650 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0),
651 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0),
652 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0),
653 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0),
654 ARM64_FTR_END,
655 };
656
657 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0),
659 ARM64_FTR_END,
660 };
661
662 static const struct arm64_ftr_bits ftr_id_isar6[] = {
663 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0),
664 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0),
665 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0),
666 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0),
667 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0),
668 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0),
669 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0),
670 ARM64_FTR_END,
671 };
672
673 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
674 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0),
675 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0),
676 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0),
677 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0),
678 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0),
679 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0),
680 ARM64_FTR_END,
681 };
682
683 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
684 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0),
685 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0),
686 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0),
687 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0),
688 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0),
689 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0),
690 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0),
691 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0),
692 ARM64_FTR_END,
693 };
694
695 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
696 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0),
697 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0),
698 ARM64_FTR_END,
699 };
700
701 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
702 /* [31:28] TraceFilt */
703 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0),
704 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0),
705 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0),
706 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0),
707 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0),
708 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0),
709 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0),
710 ARM64_FTR_END,
711 };
712
713 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
714 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0),
715 ARM64_FTR_END,
716 };
717
718 static const struct arm64_ftr_bits ftr_mpamidr[] = {
719 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0),
720 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0),
721 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0),
722 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0),
723 ARM64_FTR_END,
724 };
725
726 /*
727 * Common ftr bits for a 32bit register with all hidden, strict
728 * attributes, with 4bit feature fields and a default safe value of
729 * 0. Covers the following 32bit registers:
730 * id_isar[1-3], id_mmfr[1-3]
731 */
732 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
733 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
734 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
735 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
736 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
737 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
738 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
739 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
740 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
741 ARM64_FTR_END,
742 };
743
744 /* Table for a single 32bit feature value */
745 static const struct arm64_ftr_bits ftr_single32[] = {
746 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
747 ARM64_FTR_END,
748 };
749
750 static const struct arm64_ftr_bits ftr_raz[] = {
751 ARM64_FTR_END,
752 };
753
754 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \
755 .sys_id = id, \
756 .reg = &(struct arm64_ftr_reg){ \
757 .name = id_str, \
758 .override = (ovr), \
759 .ftr_bits = &((table)[0]), \
760 }}
761
762 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \
763 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr)
764
765 #define ARM64_FTR_REG(id, table) \
766 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override)
767
768 struct arm64_ftr_override id_aa64mmfr0_override;
769 struct arm64_ftr_override id_aa64mmfr1_override;
770 struct arm64_ftr_override id_aa64mmfr2_override;
771 struct arm64_ftr_override id_aa64pfr0_override;
772 struct arm64_ftr_override id_aa64pfr1_override;
773 struct arm64_ftr_override id_aa64zfr0_override;
774 struct arm64_ftr_override id_aa64smfr0_override;
775 struct arm64_ftr_override id_aa64isar1_override;
776 struct arm64_ftr_override id_aa64isar2_override;
777
778 struct arm64_ftr_override arm64_sw_feature_override;
779
780 static const struct __ftr_reg_entry {
781 u32 sys_id;
782 struct arm64_ftr_reg *reg;
783 } arm64_ftr_regs[] = {
784
785 /* Op1 = 0, CRn = 0, CRm = 1 */
786 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
787 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
788 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
789 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
790 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
791 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
792 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
793
794 /* Op1 = 0, CRn = 0, CRm = 2 */
795 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
796 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
797 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
798 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
799 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
800 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
801 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
802 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
803
804 /* Op1 = 0, CRn = 0, CRm = 3 */
805 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0),
806 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1),
807 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
808 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
809 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
810 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
811
812 /* Op1 = 0, CRn = 0, CRm = 4 */
813 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0,
814 &id_aa64pfr0_override),
815 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,
816 &id_aa64pfr1_override),
817 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2),
818 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0,
819 &id_aa64zfr0_override),
820 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0,
821 &id_aa64smfr0_override),
822 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0),
823
824 /* Op1 = 0, CRn = 0, CRm = 5 */
825 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
826 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
827
828 /* Op1 = 0, CRn = 0, CRm = 6 */
829 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
830 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
831 &id_aa64isar1_override),
832 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2,
833 &id_aa64isar2_override),
834 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3),
835
836 /* Op1 = 0, CRn = 0, CRm = 7 */
837 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0,
838 &id_aa64mmfr0_override),
839 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
840 &id_aa64mmfr1_override),
841 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2,
842 &id_aa64mmfr2_override),
843 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3),
844 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4),
845
846 /* Op1 = 0, CRn = 10, CRm = 4 */
847 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr),
848
849 /* Op1 = 1, CRn = 0, CRm = 0 */
850 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
851
852 /* Op1 = 3, CRn = 0, CRm = 0 */
853 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
854 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
855
856 /* Op1 = 3, CRn = 14, CRm = 0 */
857 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
858 };
859
search_cmp_ftr_reg(const void * id,const void * regp)860 static int search_cmp_ftr_reg(const void *id, const void *regp)
861 {
862 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
863 }
864
865 /*
866 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
867 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
868 * ascending order of sys_id, we use binary search to find a matching
869 * entry.
870 *
871 * returns - Upon success, matching ftr_reg entry for id.
872 * - NULL on failure. It is upto the caller to decide
873 * the impact of a failure.
874 */
get_arm64_ftr_reg_nowarn(u32 sys_id)875 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
876 {
877 const struct __ftr_reg_entry *ret;
878
879 ret = bsearch((const void *)(unsigned long)sys_id,
880 arm64_ftr_regs,
881 ARRAY_SIZE(arm64_ftr_regs),
882 sizeof(arm64_ftr_regs[0]),
883 search_cmp_ftr_reg);
884 if (ret)
885 return ret->reg;
886 return NULL;
887 }
888
889 /*
890 * get_arm64_ftr_reg - Looks up a feature register entry using
891 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
892 *
893 * returns - Upon success, matching ftr_reg entry for id.
894 * - NULL on failure but with an WARN_ON().
895 */
get_arm64_ftr_reg(u32 sys_id)896 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
897 {
898 struct arm64_ftr_reg *reg;
899
900 reg = get_arm64_ftr_reg_nowarn(sys_id);
901
902 /*
903 * Requesting a non-existent register search is an error. Warn
904 * and let the caller handle it.
905 */
906 WARN_ON(!reg);
907 return reg;
908 }
909
arm64_ftr_set_value(const struct arm64_ftr_bits * ftrp,s64 reg,s64 ftr_val)910 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
911 s64 ftr_val)
912 {
913 u64 mask = arm64_ftr_mask(ftrp);
914
915 reg &= ~mask;
916 reg |= (ftr_val << ftrp->shift) & mask;
917 return reg;
918 }
919
arm64_ftr_safe_value(const struct arm64_ftr_bits * ftrp,s64 new,s64 cur)920 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
921 s64 cur)
922 {
923 s64 ret = 0;
924
925 switch (ftrp->type) {
926 case FTR_EXACT:
927 ret = ftrp->safe_val;
928 break;
929 case FTR_LOWER_SAFE:
930 ret = min(new, cur);
931 break;
932 case FTR_HIGHER_OR_ZERO_SAFE:
933 if (!cur || !new)
934 break;
935 fallthrough;
936 case FTR_HIGHER_SAFE:
937 ret = max(new, cur);
938 break;
939 default:
940 BUG();
941 }
942
943 return ret;
944 }
945
sort_ftr_regs(void)946 static void __init sort_ftr_regs(void)
947 {
948 unsigned int i;
949
950 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
951 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
952 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
953 unsigned int j = 0;
954
955 /*
956 * Features here must be sorted in descending order with respect
957 * to their shift values and should not overlap with each other.
958 */
959 for (; ftr_bits->width != 0; ftr_bits++, j++) {
960 unsigned int width = ftr_reg->ftr_bits[j].width;
961 unsigned int shift = ftr_reg->ftr_bits[j].shift;
962 unsigned int prev_shift;
963
964 WARN((shift + width) > 64,
965 "%s has invalid feature at shift %d\n",
966 ftr_reg->name, shift);
967
968 /*
969 * Skip the first feature. There is nothing to
970 * compare against for now.
971 */
972 if (j == 0)
973 continue;
974
975 prev_shift = ftr_reg->ftr_bits[j - 1].shift;
976 WARN((shift + width) > prev_shift,
977 "%s has feature overlap at shift %d\n",
978 ftr_reg->name, shift);
979 }
980
981 /*
982 * Skip the first register. There is nothing to
983 * compare against for now.
984 */
985 if (i == 0)
986 continue;
987 /*
988 * Registers here must be sorted in ascending order with respect
989 * to sys_id for subsequent binary search in get_arm64_ftr_reg()
990 * to work correctly.
991 */
992 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id);
993 }
994 }
995
996 /*
997 * Initialise the CPU feature register from Boot CPU values.
998 * Also initiliases the strict_mask for the register.
999 * Any bits that are not covered by an arm64_ftr_bits entry are considered
1000 * RES0 for the system-wide value, and must strictly match.
1001 */
init_cpu_ftr_reg(u32 sys_reg,u64 new)1002 static void init_cpu_ftr_reg(u32 sys_reg, u64 new)
1003 {
1004 u64 val = 0;
1005 u64 strict_mask = ~0x0ULL;
1006 u64 user_mask = 0;
1007 u64 valid_mask = 0;
1008
1009 const struct arm64_ftr_bits *ftrp;
1010 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
1011
1012 if (!reg)
1013 return;
1014
1015 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
1016 u64 ftr_mask = arm64_ftr_mask(ftrp);
1017 s64 ftr_new = arm64_ftr_value(ftrp, new);
1018 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val);
1019
1020 if ((ftr_mask & reg->override->mask) == ftr_mask) {
1021 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new);
1022 char *str = NULL;
1023
1024 if (ftr_ovr != tmp) {
1025 /* Unsafe, remove the override */
1026 reg->override->mask &= ~ftr_mask;
1027 reg->override->val &= ~ftr_mask;
1028 tmp = ftr_ovr;
1029 str = "ignoring override";
1030 } else if (ftr_new != tmp) {
1031 /* Override was valid */
1032 ftr_new = tmp;
1033 str = "forced";
1034 } else {
1035 /* Override was the safe value */
1036 str = "already set";
1037 }
1038
1039 pr_warn("%s[%d:%d]: %s to %llx\n",
1040 reg->name,
1041 ftrp->shift + ftrp->width - 1,
1042 ftrp->shift, str,
1043 tmp & (BIT(ftrp->width) - 1));
1044 } else if ((ftr_mask & reg->override->val) == ftr_mask) {
1045 reg->override->val &= ~ftr_mask;
1046 pr_warn("%s[%d:%d]: impossible override, ignored\n",
1047 reg->name,
1048 ftrp->shift + ftrp->width - 1,
1049 ftrp->shift);
1050 }
1051
1052 val = arm64_ftr_set_value(ftrp, val, ftr_new);
1053
1054 valid_mask |= ftr_mask;
1055 if (!ftrp->strict)
1056 strict_mask &= ~ftr_mask;
1057 if (ftrp->visible)
1058 user_mask |= ftr_mask;
1059 else
1060 reg->user_val = arm64_ftr_set_value(ftrp,
1061 reg->user_val,
1062 ftrp->safe_val);
1063 }
1064
1065 val &= valid_mask;
1066
1067 reg->sys_val = val;
1068 reg->strict_mask = strict_mask;
1069 reg->user_mask = user_mask;
1070 }
1071
1072 extern const struct arm64_cpu_capabilities arm64_errata[];
1073 static const struct arm64_cpu_capabilities arm64_features[];
1074
1075 static void __init
init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities * caps)1076 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
1077 {
1078 for (; caps->matches; caps++) {
1079 if (WARN(caps->capability >= ARM64_NCAPS,
1080 "Invalid capability %d\n", caps->capability))
1081 continue;
1082 if (WARN(cpucap_ptrs[caps->capability],
1083 "Duplicate entry for capability %d\n",
1084 caps->capability))
1085 continue;
1086 cpucap_ptrs[caps->capability] = caps;
1087 }
1088 }
1089
init_cpucap_indirect_list(void)1090 static void __init init_cpucap_indirect_list(void)
1091 {
1092 init_cpucap_indirect_list_from_array(arm64_features);
1093 init_cpucap_indirect_list_from_array(arm64_errata);
1094 }
1095
1096 static void __init setup_boot_cpu_capabilities(void);
1097
init_32bit_cpu_features(struct cpuinfo_32bit * info)1098 static void init_32bit_cpu_features(struct cpuinfo_32bit *info)
1099 {
1100 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
1101 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
1102 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
1103 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
1104 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
1105 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
1106 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
1107 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
1108 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
1109 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
1110 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
1111 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
1112 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
1113 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
1114 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
1115 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
1116 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
1117 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
1118 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
1119 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
1120 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
1121 }
1122
1123 #ifdef CONFIG_ARM64_PSEUDO_NMI
1124 static bool enable_pseudo_nmi;
1125
early_enable_pseudo_nmi(char * p)1126 static int __init early_enable_pseudo_nmi(char *p)
1127 {
1128 return kstrtobool(p, &enable_pseudo_nmi);
1129 }
1130 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1131
detect_system_supports_pseudo_nmi(void)1132 static __init void detect_system_supports_pseudo_nmi(void)
1133 {
1134 struct device_node *np;
1135
1136 if (!enable_pseudo_nmi)
1137 return;
1138
1139 /*
1140 * Detect broken MediaTek firmware that doesn't properly save and
1141 * restore GIC priorities.
1142 */
1143 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3");
1144 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) {
1145 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n");
1146 enable_pseudo_nmi = false;
1147 }
1148 of_node_put(np);
1149 }
1150 #else /* CONFIG_ARM64_PSEUDO_NMI */
detect_system_supports_pseudo_nmi(void)1151 static inline void detect_system_supports_pseudo_nmi(void) { }
1152 #endif
1153
init_cpu_features(struct cpuinfo_arm64 * info)1154 void __init init_cpu_features(struct cpuinfo_arm64 *info)
1155 {
1156 /* Before we start using the tables, make sure it is sorted */
1157 sort_ftr_regs();
1158
1159 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
1160 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
1161 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
1162 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
1163 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
1164 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
1165 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
1166 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
1167 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3);
1168 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
1169 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
1170 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
1171 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3);
1172 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4);
1173 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
1174 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
1175 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2);
1176 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
1177 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0);
1178 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0);
1179
1180 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
1181 init_32bit_cpu_features(&info->aarch32);
1182
1183 if (IS_ENABLED(CONFIG_ARM64_SVE) &&
1184 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
1185 unsigned long cpacr = cpacr_save_enable_kernel_sve();
1186
1187 vec_init_vq_map(ARM64_VEC_SVE);
1188
1189 cpacr_restore(cpacr);
1190 }
1191
1192 if (IS_ENABLED(CONFIG_ARM64_SME) &&
1193 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
1194 unsigned long cpacr = cpacr_save_enable_kernel_sme();
1195
1196 vec_init_vq_map(ARM64_VEC_SME);
1197
1198 cpacr_restore(cpacr);
1199 }
1200
1201 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0))
1202 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr);
1203
1204 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
1205 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
1206 }
1207
update_cpu_ftr_reg(struct arm64_ftr_reg * reg,u64 new)1208 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
1209 {
1210 const struct arm64_ftr_bits *ftrp;
1211
1212 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
1213 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
1214 s64 ftr_new = arm64_ftr_value(ftrp, new);
1215
1216 if (ftr_cur == ftr_new)
1217 continue;
1218 /* Find a safe value */
1219 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
1220 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
1221 }
1222
1223 }
1224
check_update_ftr_reg(u32 sys_id,int cpu,u64 val,u64 boot)1225 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
1226 {
1227 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1228
1229 if (!regp)
1230 return 0;
1231
1232 update_cpu_ftr_reg(regp, val);
1233 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
1234 return 0;
1235 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
1236 regp->name, boot, cpu, val);
1237 return 1;
1238 }
1239
relax_cpu_ftr_reg(u32 sys_id,int field)1240 static void relax_cpu_ftr_reg(u32 sys_id, int field)
1241 {
1242 const struct arm64_ftr_bits *ftrp;
1243 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1244
1245 if (!regp)
1246 return;
1247
1248 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
1249 if (ftrp->shift == field) {
1250 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
1251 break;
1252 }
1253 }
1254
1255 /* Bogus field? */
1256 WARN_ON(!ftrp->width);
1257 }
1258
lazy_init_32bit_cpu_features(struct cpuinfo_arm64 * info,struct cpuinfo_arm64 * boot)1259 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,
1260 struct cpuinfo_arm64 *boot)
1261 {
1262 static bool boot_cpu_32bit_regs_overridden = false;
1263
1264 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)
1265 return;
1266
1267 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))
1268 return;
1269
1270 boot->aarch32 = info->aarch32;
1271 init_32bit_cpu_features(&boot->aarch32);
1272 boot_cpu_32bit_regs_overridden = true;
1273 }
1274
update_32bit_cpu_features(int cpu,struct cpuinfo_32bit * info,struct cpuinfo_32bit * boot)1275 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
1276 struct cpuinfo_32bit *boot)
1277 {
1278 int taint = 0;
1279 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1280
1281 /*
1282 * If we don't have AArch32 at EL1, then relax the strictness of
1283 * EL1-dependent register fields to avoid spurious sanity check fails.
1284 */
1285 if (!id_aa64pfr0_32bit_el1(pfr0)) {
1286 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT);
1287 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT);
1288 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT);
1289 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT);
1290 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT);
1291 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT);
1292 }
1293
1294 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
1295 info->reg_id_dfr0, boot->reg_id_dfr0);
1296 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
1297 info->reg_id_dfr1, boot->reg_id_dfr1);
1298 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
1299 info->reg_id_isar0, boot->reg_id_isar0);
1300 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
1301 info->reg_id_isar1, boot->reg_id_isar1);
1302 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
1303 info->reg_id_isar2, boot->reg_id_isar2);
1304 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
1305 info->reg_id_isar3, boot->reg_id_isar3);
1306 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
1307 info->reg_id_isar4, boot->reg_id_isar4);
1308 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
1309 info->reg_id_isar5, boot->reg_id_isar5);
1310 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
1311 info->reg_id_isar6, boot->reg_id_isar6);
1312
1313 /*
1314 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
1315 * ACTLR formats could differ across CPUs and therefore would have to
1316 * be trapped for virtualization anyway.
1317 */
1318 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1319 info->reg_id_mmfr0, boot->reg_id_mmfr0);
1320 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1321 info->reg_id_mmfr1, boot->reg_id_mmfr1);
1322 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1323 info->reg_id_mmfr2, boot->reg_id_mmfr2);
1324 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1325 info->reg_id_mmfr3, boot->reg_id_mmfr3);
1326 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1327 info->reg_id_mmfr4, boot->reg_id_mmfr4);
1328 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1329 info->reg_id_mmfr5, boot->reg_id_mmfr5);
1330 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1331 info->reg_id_pfr0, boot->reg_id_pfr0);
1332 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1333 info->reg_id_pfr1, boot->reg_id_pfr1);
1334 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1335 info->reg_id_pfr2, boot->reg_id_pfr2);
1336 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1337 info->reg_mvfr0, boot->reg_mvfr0);
1338 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1339 info->reg_mvfr1, boot->reg_mvfr1);
1340 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1341 info->reg_mvfr2, boot->reg_mvfr2);
1342
1343 return taint;
1344 }
1345
1346 /*
1347 * Update system wide CPU feature registers with the values from a
1348 * non-boot CPU. Also performs SANITY checks to make sure that there
1349 * aren't any insane variations from that of the boot CPU.
1350 */
update_cpu_features(int cpu,struct cpuinfo_arm64 * info,struct cpuinfo_arm64 * boot)1351 void update_cpu_features(int cpu,
1352 struct cpuinfo_arm64 *info,
1353 struct cpuinfo_arm64 *boot)
1354 {
1355 int taint = 0;
1356
1357 /*
1358 * The kernel can handle differing I-cache policies, but otherwise
1359 * caches should look identical. Userspace JITs will make use of
1360 * *minLine.
1361 */
1362 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1363 info->reg_ctr, boot->reg_ctr);
1364
1365 /*
1366 * Userspace may perform DC ZVA instructions. Mismatched block sizes
1367 * could result in too much or too little memory being zeroed if a
1368 * process is preempted and migrated between CPUs.
1369 */
1370 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1371 info->reg_dczid, boot->reg_dczid);
1372
1373 /* If different, timekeeping will be broken (especially with KVM) */
1374 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1375 info->reg_cntfrq, boot->reg_cntfrq);
1376
1377 /*
1378 * The kernel uses self-hosted debug features and expects CPUs to
1379 * support identical debug features. We presently need CTX_CMPs, WRPs,
1380 * and BRPs to be identical.
1381 * ID_AA64DFR1 is currently RES0.
1382 */
1383 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1384 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1385 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1386 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1387 /*
1388 * Even in big.LITTLE, processors should be identical instruction-set
1389 * wise.
1390 */
1391 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1392 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1393 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1394 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1395 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
1396 info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
1397 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu,
1398 info->reg_id_aa64isar3, boot->reg_id_aa64isar3);
1399
1400 /*
1401 * Differing PARange support is fine as long as all peripherals and
1402 * memory are mapped within the minimum PARange of all CPUs.
1403 * Linux should not care about secure memory.
1404 */
1405 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1406 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1407 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1408 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1409 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1410 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1411 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu,
1412 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3);
1413
1414 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1415 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1416 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1417 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1418 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu,
1419 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2);
1420
1421 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1422 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1423
1424 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu,
1425 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0);
1426
1427 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu,
1428 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0);
1429
1430 /* Probe vector lengths */
1431 if (IS_ENABLED(CONFIG_ARM64_SVE) &&
1432 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
1433 if (!system_capabilities_finalized()) {
1434 unsigned long cpacr = cpacr_save_enable_kernel_sve();
1435
1436 vec_update_vq_map(ARM64_VEC_SVE);
1437
1438 cpacr_restore(cpacr);
1439 }
1440 }
1441
1442 if (IS_ENABLED(CONFIG_ARM64_SME) &&
1443 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
1444 unsigned long cpacr = cpacr_save_enable_kernel_sme();
1445
1446 /* Probe vector lengths */
1447 if (!system_capabilities_finalized())
1448 vec_update_vq_map(ARM64_VEC_SME);
1449
1450 cpacr_restore(cpacr);
1451 }
1452
1453 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0)) {
1454 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu,
1455 info->reg_mpamidr, boot->reg_mpamidr);
1456 }
1457
1458 /*
1459 * The kernel uses the LDGM/STGM instructions and the number of tags
1460 * they read/write depends on the GMID_EL1.BS field. Check that the
1461 * value is the same on all CPUs.
1462 */
1463 if (IS_ENABLED(CONFIG_ARM64_MTE) &&
1464 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {
1465 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
1466 info->reg_gmid, boot->reg_gmid);
1467 }
1468
1469 /*
1470 * If we don't have AArch32 at all then skip the checks entirely
1471 * as the register values may be UNKNOWN and we're not going to be
1472 * using them for anything.
1473 *
1474 * This relies on a sanitised view of the AArch64 ID registers
1475 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1476 */
1477 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
1478 lazy_init_32bit_cpu_features(info, boot);
1479 taint |= update_32bit_cpu_features(cpu, &info->aarch32,
1480 &boot->aarch32);
1481 }
1482
1483 /*
1484 * Mismatched CPU features are a recipe for disaster. Don't even
1485 * pretend to support them.
1486 */
1487 if (taint) {
1488 pr_warn_once("Unsupported CPU feature variation detected.\n");
1489 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1490 }
1491 }
1492
read_sanitised_ftr_reg(u32 id)1493 u64 read_sanitised_ftr_reg(u32 id)
1494 {
1495 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1496
1497 if (!regp)
1498 return 0;
1499 return regp->sys_val;
1500 }
1501 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1502
1503 #define read_sysreg_case(r) \
1504 case r: val = read_sysreg_s(r); break;
1505
1506 /*
1507 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1508 * Read the system register on the current CPU
1509 */
__read_sysreg_by_encoding(u32 sys_id)1510 u64 __read_sysreg_by_encoding(u32 sys_id)
1511 {
1512 struct arm64_ftr_reg *regp;
1513 u64 val;
1514
1515 switch (sys_id) {
1516 read_sysreg_case(SYS_ID_PFR0_EL1);
1517 read_sysreg_case(SYS_ID_PFR1_EL1);
1518 read_sysreg_case(SYS_ID_PFR2_EL1);
1519 read_sysreg_case(SYS_ID_DFR0_EL1);
1520 read_sysreg_case(SYS_ID_DFR1_EL1);
1521 read_sysreg_case(SYS_ID_MMFR0_EL1);
1522 read_sysreg_case(SYS_ID_MMFR1_EL1);
1523 read_sysreg_case(SYS_ID_MMFR2_EL1);
1524 read_sysreg_case(SYS_ID_MMFR3_EL1);
1525 read_sysreg_case(SYS_ID_MMFR4_EL1);
1526 read_sysreg_case(SYS_ID_MMFR5_EL1);
1527 read_sysreg_case(SYS_ID_ISAR0_EL1);
1528 read_sysreg_case(SYS_ID_ISAR1_EL1);
1529 read_sysreg_case(SYS_ID_ISAR2_EL1);
1530 read_sysreg_case(SYS_ID_ISAR3_EL1);
1531 read_sysreg_case(SYS_ID_ISAR4_EL1);
1532 read_sysreg_case(SYS_ID_ISAR5_EL1);
1533 read_sysreg_case(SYS_ID_ISAR6_EL1);
1534 read_sysreg_case(SYS_MVFR0_EL1);
1535 read_sysreg_case(SYS_MVFR1_EL1);
1536 read_sysreg_case(SYS_MVFR2_EL1);
1537
1538 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1539 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1540 read_sysreg_case(SYS_ID_AA64PFR2_EL1);
1541 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1542 read_sysreg_case(SYS_ID_AA64SMFR0_EL1);
1543 read_sysreg_case(SYS_ID_AA64FPFR0_EL1);
1544 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1545 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1546 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1547 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1548 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1549 read_sysreg_case(SYS_ID_AA64MMFR3_EL1);
1550 read_sysreg_case(SYS_ID_AA64MMFR4_EL1);
1551 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1552 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1553 read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
1554 read_sysreg_case(SYS_ID_AA64ISAR3_EL1);
1555
1556 read_sysreg_case(SYS_CNTFRQ_EL0);
1557 read_sysreg_case(SYS_CTR_EL0);
1558 read_sysreg_case(SYS_DCZID_EL0);
1559
1560 default:
1561 BUG();
1562 return 0;
1563 }
1564
1565 regp = get_arm64_ftr_reg(sys_id);
1566 if (regp) {
1567 val &= ~regp->override->mask;
1568 val |= (regp->override->val & regp->override->mask);
1569 }
1570
1571 return val;
1572 }
1573
1574 #include <linux/irqchip/arm-gic-v3.h>
1575
1576 static bool
has_always(const struct arm64_cpu_capabilities * entry,int scope)1577 has_always(const struct arm64_cpu_capabilities *entry, int scope)
1578 {
1579 return true;
1580 }
1581
1582 static bool
feature_matches(u64 reg,const struct arm64_cpu_capabilities * entry)1583 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1584 {
1585 int val, min, max;
1586 u64 tmp;
1587
1588 val = cpuid_feature_extract_field_width(reg, entry->field_pos,
1589 entry->field_width,
1590 entry->sign);
1591
1592 tmp = entry->min_field_value;
1593 tmp <<= entry->field_pos;
1594
1595 min = cpuid_feature_extract_field_width(tmp, entry->field_pos,
1596 entry->field_width,
1597 entry->sign);
1598
1599 tmp = entry->max_field_value;
1600 tmp <<= entry->field_pos;
1601
1602 max = cpuid_feature_extract_field_width(tmp, entry->field_pos,
1603 entry->field_width,
1604 entry->sign);
1605
1606 return val >= min && val <= max;
1607 }
1608
1609 static u64
read_scoped_sysreg(const struct arm64_cpu_capabilities * entry,int scope)1610 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope)
1611 {
1612 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1613 if (scope == SCOPE_SYSTEM)
1614 return read_sanitised_ftr_reg(entry->sys_reg);
1615 else
1616 return __read_sysreg_by_encoding(entry->sys_reg);
1617 }
1618
1619 static bool
has_user_cpuid_feature(const struct arm64_cpu_capabilities * entry,int scope)1620 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1621 {
1622 int mask;
1623 struct arm64_ftr_reg *regp;
1624 u64 val = read_scoped_sysreg(entry, scope);
1625
1626 regp = get_arm64_ftr_reg(entry->sys_reg);
1627 if (!regp)
1628 return false;
1629
1630 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask,
1631 entry->field_pos,
1632 entry->field_width);
1633 if (!mask)
1634 return false;
1635
1636 return feature_matches(val, entry);
1637 }
1638
1639 static bool
has_cpuid_feature(const struct arm64_cpu_capabilities * entry,int scope)1640 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1641 {
1642 u64 val = read_scoped_sysreg(entry, scope);
1643 return feature_matches(val, entry);
1644 }
1645
system_32bit_el0_cpumask(void)1646 const struct cpumask *system_32bit_el0_cpumask(void)
1647 {
1648 if (!system_supports_32bit_el0())
1649 return cpu_none_mask;
1650
1651 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
1652 return cpu_32bit_el0_mask;
1653
1654 return cpu_possible_mask;
1655 }
1656
task_cpu_fallback_mask(struct task_struct * p)1657 const struct cpumask *task_cpu_fallback_mask(struct task_struct *p)
1658 {
1659 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_TICK));
1660 }
1661
parse_32bit_el0_param(char * str)1662 static int __init parse_32bit_el0_param(char *str)
1663 {
1664 allow_mismatched_32bit_el0 = true;
1665 return 0;
1666 }
1667 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param);
1668
aarch32_el0_show(struct device * dev,struct device_attribute * attr,char * buf)1669 static ssize_t aarch32_el0_show(struct device *dev,
1670 struct device_attribute *attr, char *buf)
1671 {
1672 const struct cpumask *mask = system_32bit_el0_cpumask();
1673
1674 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask));
1675 }
1676 static const DEVICE_ATTR_RO(aarch32_el0);
1677
aarch32_el0_sysfs_init(void)1678 static int __init aarch32_el0_sysfs_init(void)
1679 {
1680 struct device *dev_root;
1681 int ret = 0;
1682
1683 if (!allow_mismatched_32bit_el0)
1684 return 0;
1685
1686 dev_root = bus_get_dev_root(&cpu_subsys);
1687 if (dev_root) {
1688 ret = device_create_file(dev_root, &dev_attr_aarch32_el0);
1689 put_device(dev_root);
1690 }
1691 return ret;
1692 }
1693 device_initcall(aarch32_el0_sysfs_init);
1694
has_32bit_el0(const struct arm64_cpu_capabilities * entry,int scope)1695 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)
1696 {
1697 if (!has_cpuid_feature(entry, scope))
1698 return allow_mismatched_32bit_el0;
1699
1700 if (scope == SCOPE_SYSTEM)
1701 pr_info("detected: 32-bit EL0 Support\n");
1702
1703 return true;
1704 }
1705
has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities * entry,int scope)1706 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1707 {
1708 bool has_sre;
1709
1710 if (!has_cpuid_feature(entry, scope))
1711 return false;
1712
1713 has_sre = gic_enable_sre();
1714 if (!has_sre)
1715 pr_warn_once("%s present but disabled by higher exception level\n",
1716 entry->desc);
1717
1718 return has_sre;
1719 }
1720
has_cache_idc(const struct arm64_cpu_capabilities * entry,int scope)1721 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1722 int scope)
1723 {
1724 u64 ctr;
1725
1726 if (scope == SCOPE_SYSTEM)
1727 ctr = arm64_ftr_reg_ctrel0.sys_val;
1728 else
1729 ctr = read_cpuid_effective_cachetype();
1730
1731 return ctr & BIT(CTR_EL0_IDC_SHIFT);
1732 }
1733
cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities * __unused)1734 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1735 {
1736 /*
1737 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1738 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1739 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1740 * value.
1741 */
1742 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT)))
1743 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1744 }
1745
has_cache_dic(const struct arm64_cpu_capabilities * entry,int scope)1746 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1747 int scope)
1748 {
1749 u64 ctr;
1750
1751 if (scope == SCOPE_SYSTEM)
1752 ctr = arm64_ftr_reg_ctrel0.sys_val;
1753 else
1754 ctr = read_cpuid_cachetype();
1755
1756 return ctr & BIT(CTR_EL0_DIC_SHIFT);
1757 }
1758
1759 static bool __maybe_unused
has_useable_cnp(const struct arm64_cpu_capabilities * entry,int scope)1760 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1761 {
1762 /*
1763 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1764 * may share TLB entries with a CPU stuck in the crashed
1765 * kernel.
1766 */
1767 if (is_kdump_kernel())
1768 return false;
1769
1770 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
1771 return false;
1772
1773 return has_cpuid_feature(entry, scope);
1774 }
1775
1776 static bool __meltdown_safe = true;
1777 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1778
unmap_kernel_at_el0(const struct arm64_cpu_capabilities * entry,int scope)1779 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1780 int scope)
1781 {
1782 /* List of CPUs that are not vulnerable and don't need KPTI */
1783 static const struct midr_range kpti_safe_list[] = {
1784 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1785 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1786 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1787 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1788 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1789 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1790 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1791 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1792 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1793 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1794 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1795 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1796 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1797 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1798 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1799 { /* sentinel */ }
1800 };
1801 char const *str = "kpti command line option";
1802 bool meltdown_safe;
1803
1804 meltdown_safe = is_midr_in_range_list(kpti_safe_list);
1805
1806 /* Defer to CPU feature registers */
1807 if (has_cpuid_feature(entry, scope))
1808 meltdown_safe = true;
1809
1810 if (!meltdown_safe)
1811 __meltdown_safe = false;
1812
1813 /*
1814 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1815 * ThunderX leads to apparent I-cache corruption of kernel text, which
1816 * ends as well as you might imagine. Don't even try. We cannot rely
1817 * on the cpus_have_*cap() helpers here to detect the CPU erratum
1818 * because cpucap detection order may change. However, since we know
1819 * affected CPUs are always in a homogeneous configuration, it is
1820 * safe to rely on this_cpu_has_cap() here.
1821 */
1822 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1823 str = "ARM64_WORKAROUND_CAVIUM_27456";
1824 __kpti_forced = -1;
1825 }
1826
1827 /* Useful for KASLR robustness */
1828 if (kaslr_enabled() && kaslr_requires_kpti()) {
1829 if (!__kpti_forced) {
1830 str = "KASLR";
1831 __kpti_forced = 1;
1832 }
1833 }
1834
1835 if (cpu_mitigations_off() && !__kpti_forced) {
1836 str = "mitigations=off";
1837 __kpti_forced = -1;
1838 }
1839
1840 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1841 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1842 return false;
1843 }
1844
1845 /* Forced? */
1846 if (__kpti_forced) {
1847 pr_info_once("kernel page table isolation forced %s by %s\n",
1848 __kpti_forced > 0 ? "ON" : "OFF", str);
1849 return __kpti_forced > 0;
1850 }
1851
1852 return !meltdown_safe;
1853 }
1854
has_nv1(const struct arm64_cpu_capabilities * entry,int scope)1855 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope)
1856 {
1857 /*
1858 * Although the Apple M2 family appears to support NV1, the
1859 * PTW barfs on the nVHE EL2 S1 page table format. Pretend
1860 * that it doesn't support NV1 at all.
1861 */
1862 static const struct midr_range nv1_ni_list[] = {
1863 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD),
1864 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE),
1865 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO),
1866 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),
1867 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),
1868 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),
1869 {}
1870 };
1871
1872 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) &&
1873 !(has_cpuid_feature(entry, scope) ||
1874 is_midr_in_range_list(nv1_ni_list)));
1875 }
1876
1877 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2)
has_lpa2_at_stage1(u64 mmfr0)1878 static bool has_lpa2_at_stage1(u64 mmfr0)
1879 {
1880 unsigned int tgran;
1881
1882 tgran = cpuid_feature_extract_unsigned_field(mmfr0,
1883 ID_AA64MMFR0_EL1_TGRAN_SHIFT);
1884 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2;
1885 }
1886
has_lpa2_at_stage2(u64 mmfr0)1887 static bool has_lpa2_at_stage2(u64 mmfr0)
1888 {
1889 unsigned int tgran;
1890
1891 tgran = cpuid_feature_extract_unsigned_field(mmfr0,
1892 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT);
1893 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2;
1894 }
1895
has_lpa2(const struct arm64_cpu_capabilities * entry,int scope)1896 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope)
1897 {
1898 u64 mmfr0;
1899
1900 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
1901 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0);
1902 }
1903 #else
has_lpa2(const struct arm64_cpu_capabilities * entry,int scope)1904 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope)
1905 {
1906 return false;
1907 }
1908 #endif
1909
1910 #ifdef CONFIG_HW_PERF_EVENTS
has_pmuv3(const struct arm64_cpu_capabilities * entry,int scope)1911 static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope)
1912 {
1913 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1914 unsigned int pmuver;
1915
1916 /*
1917 * PMUVer follows the standard ID scheme for an unsigned field with the
1918 * exception of 0xF (IMP_DEF) which is treated specially and implies
1919 * FEAT_PMUv3 is not implemented.
1920 *
1921 * See DDI0487L.a D24.1.3.2 for more details.
1922 */
1923 pmuver = cpuid_feature_extract_unsigned_field(dfr0,
1924 ID_AA64DFR0_EL1_PMUVer_SHIFT);
1925 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
1926 return false;
1927
1928 return pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP;
1929 }
1930 #endif
1931
1932 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1933 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT))
1934
1935 extern
1936 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt,
1937 phys_addr_t size, pgprot_t prot,
1938 phys_addr_t (*pgtable_alloc)(int), int flags);
1939
1940 static phys_addr_t __initdata kpti_ng_temp_alloc;
1941
kpti_ng_pgd_alloc(int shift)1942 static phys_addr_t __init kpti_ng_pgd_alloc(int shift)
1943 {
1944 kpti_ng_temp_alloc -= PAGE_SIZE;
1945 return kpti_ng_temp_alloc;
1946 }
1947
__kpti_install_ng_mappings(void * __unused)1948 static int __init __kpti_install_ng_mappings(void *__unused)
1949 {
1950 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long);
1951 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1952 kpti_remap_fn *remap_fn;
1953
1954 int cpu = smp_processor_id();
1955 int levels = CONFIG_PGTABLE_LEVELS;
1956 int order = order_base_2(levels);
1957 u64 kpti_ng_temp_pgd_pa = 0;
1958 pgd_t *kpti_ng_temp_pgd;
1959 u64 alloc = 0;
1960
1961 if (levels == 5 && !pgtable_l5_enabled())
1962 levels = 4;
1963 else if (levels == 4 && !pgtable_l4_enabled())
1964 levels = 3;
1965
1966 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1967
1968 if (!cpu) {
1969 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order);
1970 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE);
1971 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd);
1972
1973 //
1974 // Create a minimal page table hierarchy that permits us to map
1975 // the swapper page tables temporarily as we traverse them.
1976 //
1977 // The physical pages are laid out as follows:
1978 //
1979 // +--------+-/-------+-/------ +-/------ +-\\\--------+
1980 // : PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[] :
1981 // +--------+-\-------+-\------ +-\------ +-///--------+
1982 // ^
1983 // The first page is mapped into this hierarchy at a PMD_SHIFT
1984 // aligned virtual address, so that we can manipulate the PTE
1985 // level entries while the mapping is active. The first entry
1986 // covers the PTE[] page itself, the remaining entries are free
1987 // to be used as a ad-hoc fixmap.
1988 //
1989 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc),
1990 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL,
1991 kpti_ng_pgd_alloc, 0);
1992 }
1993
1994 cpu_install_idmap();
1995 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA);
1996 cpu_uninstall_idmap();
1997
1998 if (!cpu) {
1999 free_pages(alloc, order);
2000 arm64_use_ng_mappings = true;
2001 }
2002
2003 return 0;
2004 }
2005
kpti_install_ng_mappings(void)2006 static void __init kpti_install_ng_mappings(void)
2007 {
2008 /* Check whether KPTI is going to be used */
2009 if (!arm64_kernel_unmapped_at_el0())
2010 return;
2011
2012 /*
2013 * We don't need to rewrite the page-tables if either we've done
2014 * it already or we have KASLR enabled and therefore have not
2015 * created any global mappings at all.
2016 */
2017 if (arm64_use_ng_mappings)
2018 return;
2019
2020 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask);
2021 }
2022
2023 #else
kpti_install_ng_mappings(void)2024 static inline void kpti_install_ng_mappings(void)
2025 {
2026 }
2027 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
2028
cpu_enable_kpti(struct arm64_cpu_capabilities const * cap)2029 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap)
2030 {
2031 if (__this_cpu_read(this_cpu_vector) == vectors) {
2032 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
2033
2034 __this_cpu_write(this_cpu_vector, v);
2035 }
2036
2037 }
2038
parse_kpti(char * str)2039 static int __init parse_kpti(char *str)
2040 {
2041 bool enabled;
2042 int ret = kstrtobool(str, &enabled);
2043
2044 if (ret)
2045 return ret;
2046
2047 __kpti_forced = enabled ? 1 : -1;
2048 return 0;
2049 }
2050 early_param("kpti", parse_kpti);
2051
2052 #ifdef CONFIG_ARM64_HW_AFDBM
2053 static struct cpumask dbm_cpus __read_mostly;
2054
__cpu_enable_hw_dbm(void)2055 static inline void __cpu_enable_hw_dbm(void)
2056 {
2057 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
2058
2059 write_sysreg(tcr, tcr_el1);
2060 isb();
2061 local_flush_tlb_all();
2062 }
2063
cpu_has_broken_dbm(void)2064 static bool cpu_has_broken_dbm(void)
2065 {
2066 /* List of CPUs which have broken DBM support. */
2067 static const struct midr_range cpus[] = {
2068 #ifdef CONFIG_ARM64_ERRATUM_1024718
2069 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
2070 /* Kryo4xx Silver (rdpe => r1p0) */
2071 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
2072 #endif
2073 #ifdef CONFIG_ARM64_ERRATUM_2051678
2074 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
2075 #endif
2076 {},
2077 };
2078
2079 return is_midr_in_range_list(cpus);
2080 }
2081
cpu_can_use_dbm(const struct arm64_cpu_capabilities * cap)2082 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
2083 {
2084 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
2085 !cpu_has_broken_dbm();
2086 }
2087
cpu_enable_hw_dbm(struct arm64_cpu_capabilities const * cap)2088 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
2089 {
2090 if (cpu_can_use_dbm(cap)) {
2091 __cpu_enable_hw_dbm();
2092 cpumask_set_cpu(smp_processor_id(), &dbm_cpus);
2093 }
2094 }
2095
has_hw_dbm(const struct arm64_cpu_capabilities * cap,int __unused)2096 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
2097 int __unused)
2098 {
2099 /*
2100 * DBM is a non-conflicting feature. i.e, the kernel can safely
2101 * run a mix of CPUs with and without the feature. So, we
2102 * unconditionally enable the capability to allow any late CPU
2103 * to use the feature. We only enable the control bits on the
2104 * CPU, if it is supported.
2105 */
2106
2107 return true;
2108 }
2109
2110 #endif
2111
2112 #ifdef CONFIG_ARM64_AMU_EXTN
2113
2114 /*
2115 * The "amu_cpus" cpumask only signals that the CPU implementation for the
2116 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
2117 * information regarding all the events that it supports. When a CPU bit is
2118 * set in the cpumask, the user of this feature can only rely on the presence
2119 * of the 4 fixed counters for that CPU. But this does not guarantee that the
2120 * counters are enabled or access to these counters is enabled by code
2121 * executed at higher exception levels (firmware).
2122 */
2123 static struct cpumask amu_cpus __read_mostly;
2124
cpu_has_amu_feat(int cpu)2125 bool cpu_has_amu_feat(int cpu)
2126 {
2127 return cpumask_test_cpu(cpu, &amu_cpus);
2128 }
2129
get_cpu_with_amu_feat(void)2130 int get_cpu_with_amu_feat(void)
2131 {
2132 return cpumask_any(&amu_cpus);
2133 }
2134
cpu_amu_enable(struct arm64_cpu_capabilities const * cap)2135 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
2136 {
2137 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
2138 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
2139
2140 /* 0 reference values signal broken/disabled counters */
2141 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168))
2142 update_freq_counters_refs();
2143 }
2144 }
2145
has_amu(const struct arm64_cpu_capabilities * cap,int __unused)2146 static bool has_amu(const struct arm64_cpu_capabilities *cap,
2147 int __unused)
2148 {
2149 /*
2150 * The AMU extension is a non-conflicting feature: the kernel can
2151 * safely run a mix of CPUs with and without support for the
2152 * activity monitors extension. Therefore, unconditionally enable
2153 * the capability to allow any late CPU to use the feature.
2154 *
2155 * With this feature unconditionally enabled, the cpu_enable
2156 * function will be called for all CPUs that match the criteria,
2157 * including secondary and hotplugged, marking this feature as
2158 * present on that respective CPU. The enable function will also
2159 * print a detection message.
2160 */
2161
2162 return true;
2163 }
2164 #else
get_cpu_with_amu_feat(void)2165 int get_cpu_with_amu_feat(void)
2166 {
2167 return nr_cpu_ids;
2168 }
2169 #endif
2170
runs_at_el2(const struct arm64_cpu_capabilities * entry,int __unused)2171 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
2172 {
2173 return is_kernel_in_hyp_mode();
2174 }
2175
cpu_copy_el2regs(const struct arm64_cpu_capabilities * __unused)2176 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
2177 {
2178 /*
2179 * Copy register values that aren't redirected by hardware.
2180 *
2181 * Before code patching, we only set tpidr_el1, all CPUs need to copy
2182 * this value to tpidr_el2 before we patch the code. Once we've done
2183 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
2184 * do anything here.
2185 */
2186 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
2187 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
2188 }
2189
has_nested_virt_support(const struct arm64_cpu_capabilities * cap,int scope)2190 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap,
2191 int scope)
2192 {
2193 if (kvm_get_mode() != KVM_MODE_NV)
2194 return false;
2195
2196 if (!cpucap_multi_entry_cap_matches(cap, scope)) {
2197 pr_warn("unavailable: %s\n", cap->desc);
2198 return false;
2199 }
2200
2201 return true;
2202 }
2203
hvhe_possible(const struct arm64_cpu_capabilities * entry,int __unused)2204 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry,
2205 int __unused)
2206 {
2207 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE);
2208 }
2209
2210 #ifdef CONFIG_ARM64_PAN
cpu_enable_pan(const struct arm64_cpu_capabilities * __unused)2211 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
2212 {
2213 /*
2214 * We modify PSTATE. This won't work from irq context as the PSTATE
2215 * is discarded once we return from the exception.
2216 */
2217 WARN_ON_ONCE(in_interrupt());
2218
2219 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
2220 set_pstate_pan(1);
2221 }
2222 #endif /* CONFIG_ARM64_PAN */
2223
2224 #ifdef CONFIG_ARM64_RAS_EXTN
cpu_clear_disr(const struct arm64_cpu_capabilities * __unused)2225 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
2226 {
2227 /* Firmware may have left a deferred SError in this register. */
2228 write_sysreg_s(0, SYS_DISR_EL1);
2229 }
2230 #endif /* CONFIG_ARM64_RAS_EXTN */
2231
2232 #ifdef CONFIG_ARM64_PTR_AUTH
has_address_auth_cpucap(const struct arm64_cpu_capabilities * entry,int scope)2233 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
2234 {
2235 int boot_val, sec_val;
2236
2237 /* We don't expect to be called with SCOPE_SYSTEM */
2238 WARN_ON(scope == SCOPE_SYSTEM);
2239 /*
2240 * The ptr-auth feature levels are not intercompatible with lower
2241 * levels. Hence we must match ptr-auth feature level of the secondary
2242 * CPUs with that of the boot CPU. The level of boot cpu is fetched
2243 * from the sanitised register whereas direct register read is done for
2244 * the secondary CPUs.
2245 * The sanitised feature state is guaranteed to match that of the
2246 * boot CPU as a mismatched secondary CPU is parked before it gets
2247 * a chance to update the state, with the capability.
2248 */
2249 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
2250 entry->field_pos, entry->sign);
2251 if (scope & SCOPE_BOOT_CPU)
2252 return boot_val >= entry->min_field_value;
2253 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
2254 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
2255 entry->field_pos, entry->sign);
2256 return (sec_val >= entry->min_field_value) && (sec_val == boot_val);
2257 }
2258
has_address_auth_metacap(const struct arm64_cpu_capabilities * entry,int scope)2259 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
2260 int scope)
2261 {
2262 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
2263 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope);
2264 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope);
2265
2266 return apa || apa3 || api;
2267 }
2268
has_generic_auth(const struct arm64_cpu_capabilities * entry,int __unused)2269 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
2270 int __unused)
2271 {
2272 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
2273 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5);
2274 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3);
2275
2276 return gpa || gpa3 || gpi;
2277 }
2278 #endif /* CONFIG_ARM64_PTR_AUTH */
2279
2280 #ifdef CONFIG_ARM64_E0PD
cpu_enable_e0pd(struct arm64_cpu_capabilities const * cap)2281 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
2282 {
2283 if (this_cpu_has_cap(ARM64_HAS_E0PD))
2284 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
2285 }
2286 #endif /* CONFIG_ARM64_E0PD */
2287
2288 #ifdef CONFIG_ARM64_PSEUDO_NMI
can_use_gic_priorities(const struct arm64_cpu_capabilities * entry,int scope)2289 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
2290 int scope)
2291 {
2292 /*
2293 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU
2294 * feature, so will be detected earlier.
2295 */
2296 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS);
2297 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS))
2298 return false;
2299
2300 return enable_pseudo_nmi;
2301 }
2302
has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities * entry,int scope)2303 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry,
2304 int scope)
2305 {
2306 /*
2307 * If we're not using priority masking then we won't be poking PMR_EL1,
2308 * and there's no need to relax synchronization of writes to it, and
2309 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from
2310 * that.
2311 *
2312 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU
2313 * feature, so will be detected earlier.
2314 */
2315 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING);
2316 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING))
2317 return false;
2318
2319 /*
2320 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a
2321 * hint for interrupt distribution, a DSB is not necessary when
2322 * unmasking IRQs via PMR, and we can relax the barrier to a NOP.
2323 *
2324 * Linux itself doesn't use 1:N distribution, so has no need to
2325 * set PMHE. The only reason to have it set is if EL3 requires it
2326 * (and we can't change it).
2327 */
2328 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0;
2329 }
2330 #endif
2331
2332 #ifdef CONFIG_ARM64_BTI
bti_enable(const struct arm64_cpu_capabilities * __unused)2333 static void bti_enable(const struct arm64_cpu_capabilities *__unused)
2334 {
2335 /*
2336 * Use of X16/X17 for tail-calls and trampolines that jump to
2337 * function entry points using BR is a requirement for
2338 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
2339 * So, be strict and forbid other BRs using other registers to
2340 * jump onto a PACIxSP instruction:
2341 */
2342 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
2343 isb();
2344 }
2345 #endif /* CONFIG_ARM64_BTI */
2346
2347 #ifdef CONFIG_ARM64_MTE
cpu_enable_mte(struct arm64_cpu_capabilities const * cap)2348 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
2349 {
2350 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0);
2351
2352 mte_cpu_setup();
2353
2354 /*
2355 * Clear the tags in the zero page. This needs to be done via the
2356 * linear map which has the Tagged attribute.
2357 */
2358 if (try_page_mte_tagging(ZERO_PAGE(0))) {
2359 mte_clear_page_tags(lm_alias(empty_zero_page));
2360 set_page_mte_tagged(ZERO_PAGE(0));
2361 }
2362
2363 kasan_init_hw_tags_cpu();
2364 }
2365 #endif /* CONFIG_ARM64_MTE */
2366
user_feature_fixup(void)2367 static void user_feature_fixup(void)
2368 {
2369 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) {
2370 struct arm64_ftr_reg *regp;
2371
2372 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1);
2373 if (regp)
2374 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK;
2375 }
2376
2377 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) {
2378 struct arm64_ftr_reg *regp;
2379
2380 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1);
2381 if (regp)
2382 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK;
2383 }
2384 }
2385
elf_hwcap_fixup(void)2386 static void elf_hwcap_fixup(void)
2387 {
2388 #ifdef CONFIG_COMPAT
2389 if (cpus_have_cap(ARM64_WORKAROUND_1742098))
2390 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;
2391 #endif /* CONFIG_COMPAT */
2392 }
2393
2394 #ifdef CONFIG_KVM
is_kvm_protected_mode(const struct arm64_cpu_capabilities * entry,int __unused)2395 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
2396 {
2397 return kvm_get_mode() == KVM_MODE_PROTECTED;
2398 }
2399 #endif /* CONFIG_KVM */
2400
cpu_trap_el0_impdef(const struct arm64_cpu_capabilities * __unused)2401 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused)
2402 {
2403 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP);
2404 }
2405
cpu_enable_dit(const struct arm64_cpu_capabilities * __unused)2406 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused)
2407 {
2408 set_pstate_dit(1);
2409 }
2410
cpu_enable_mops(const struct arm64_cpu_capabilities * __unused)2411 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused)
2412 {
2413 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn);
2414 }
2415
2416 #ifdef CONFIG_ARM64_POE
cpu_enable_poe(const struct arm64_cpu_capabilities * __unused)2417 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused)
2418 {
2419 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE);
2420 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE);
2421 }
2422 #endif
2423
2424 #ifdef CONFIG_ARM64_GCS
cpu_enable_gcs(const struct arm64_cpu_capabilities * __unused)2425 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused)
2426 {
2427 /* GCSPR_EL0 is always readable */
2428 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1);
2429 }
2430 #endif
2431
2432 /* Internal helper functions to match cpu capability type */
2433 static bool
cpucap_late_cpu_optional(const struct arm64_cpu_capabilities * cap)2434 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
2435 {
2436 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
2437 }
2438
2439 static bool
cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities * cap)2440 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
2441 {
2442 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
2443 }
2444
2445 static bool
cpucap_panic_on_conflict(const struct arm64_cpu_capabilities * cap)2446 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
2447 {
2448 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
2449 }
2450
2451 static bool
test_has_mpam(const struct arm64_cpu_capabilities * entry,int scope)2452 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope)
2453 {
2454 if (!has_cpuid_feature(entry, scope))
2455 return false;
2456
2457 /* Check firmware actually enabled MPAM on this cpu. */
2458 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN);
2459 }
2460
2461 static void
cpu_enable_mpam(const struct arm64_cpu_capabilities * entry)2462 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry)
2463 {
2464 /*
2465 * Access by the kernel (at EL1) should use the reserved PARTID
2466 * which is configured unrestricted. This avoids priority-inversion
2467 * where latency sensitive tasks have to wait for a task that has
2468 * been throttled to release the lock.
2469 */
2470 write_sysreg_s(0, SYS_MPAM1_EL1);
2471 }
2472
2473 static bool
test_has_mpam_hcr(const struct arm64_cpu_capabilities * entry,int scope)2474 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope)
2475 {
2476 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1);
2477
2478 return idr & MPAMIDR_EL1_HAS_HCR;
2479 }
2480
2481 static const struct arm64_cpu_capabilities arm64_features[] = {
2482 {
2483 .capability = ARM64_ALWAYS_BOOT,
2484 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2485 .matches = has_always,
2486 },
2487 {
2488 .capability = ARM64_ALWAYS_SYSTEM,
2489 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2490 .matches = has_always,
2491 },
2492 {
2493 .desc = "GIC system register CPU interface",
2494 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS,
2495 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2496 .matches = has_useable_gicv3_cpuif,
2497 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP)
2498 },
2499 {
2500 .desc = "Enhanced Counter Virtualization",
2501 .capability = ARM64_HAS_ECV,
2502 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2503 .matches = has_cpuid_feature,
2504 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP)
2505 },
2506 {
2507 .desc = "Enhanced Counter Virtualization (CNTPOFF)",
2508 .capability = ARM64_HAS_ECV_CNTPOFF,
2509 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2510 .matches = has_cpuid_feature,
2511 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF)
2512 },
2513 #ifdef CONFIG_ARM64_PAN
2514 {
2515 .desc = "Privileged Access Never",
2516 .capability = ARM64_HAS_PAN,
2517 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2518 .matches = has_cpuid_feature,
2519 .cpu_enable = cpu_enable_pan,
2520 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP)
2521 },
2522 #endif /* CONFIG_ARM64_PAN */
2523 #ifdef CONFIG_ARM64_EPAN
2524 {
2525 .desc = "Enhanced Privileged Access Never",
2526 .capability = ARM64_HAS_EPAN,
2527 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2528 .matches = has_cpuid_feature,
2529 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3)
2530 },
2531 #endif /* CONFIG_ARM64_EPAN */
2532 #ifdef CONFIG_ARM64_LSE_ATOMICS
2533 {
2534 .desc = "LSE atomic instructions",
2535 .capability = ARM64_HAS_LSE_ATOMICS,
2536 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2537 .matches = has_cpuid_feature,
2538 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP)
2539 },
2540 #endif /* CONFIG_ARM64_LSE_ATOMICS */
2541 {
2542 .desc = "Virtualization Host Extensions",
2543 .capability = ARM64_HAS_VIRT_HOST_EXTN,
2544 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2545 .matches = runs_at_el2,
2546 .cpu_enable = cpu_copy_el2regs,
2547 },
2548 {
2549 .desc = "Nested Virtualization Support",
2550 .capability = ARM64_HAS_NESTED_VIRT,
2551 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2552 .matches = has_nested_virt_support,
2553 .match_list = (const struct arm64_cpu_capabilities []){
2554 {
2555 .matches = has_cpuid_feature,
2556 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2)
2557 },
2558 {
2559 .matches = has_cpuid_feature,
2560 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY)
2561 },
2562 { /* Sentinel */ }
2563 },
2564 },
2565 {
2566 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
2567 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2568 .matches = has_32bit_el0,
2569 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32)
2570 },
2571 #ifdef CONFIG_KVM
2572 {
2573 .desc = "32-bit EL1 Support",
2574 .capability = ARM64_HAS_32BIT_EL1,
2575 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2576 .matches = has_cpuid_feature,
2577 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32)
2578 },
2579 {
2580 .desc = "Protected KVM",
2581 .capability = ARM64_KVM_PROTECTED_MODE,
2582 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2583 .matches = is_kvm_protected_mode,
2584 },
2585 {
2586 .desc = "HCRX_EL2 register",
2587 .capability = ARM64_HAS_HCX,
2588 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2589 .matches = has_cpuid_feature,
2590 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP)
2591 },
2592 #endif
2593 {
2594 .desc = "Kernel page table isolation (KPTI)",
2595 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
2596 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2597 .cpu_enable = cpu_enable_kpti,
2598 .matches = unmap_kernel_at_el0,
2599 /*
2600 * The ID feature fields below are used to indicate that
2601 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
2602 * more details.
2603 */
2604 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP)
2605 },
2606 {
2607 .capability = ARM64_HAS_FPSIMD,
2608 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2609 .matches = has_cpuid_feature,
2610 .cpu_enable = cpu_enable_fpsimd,
2611 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP)
2612 },
2613 #ifdef CONFIG_ARM64_PMEM
2614 {
2615 .desc = "Data cache clean to Point of Persistence",
2616 .capability = ARM64_HAS_DCPOP,
2617 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2618 .matches = has_cpuid_feature,
2619 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP)
2620 },
2621 {
2622 .desc = "Data cache clean to Point of Deep Persistence",
2623 .capability = ARM64_HAS_DCPODP,
2624 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2625 .matches = has_cpuid_feature,
2626 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2)
2627 },
2628 #endif
2629 #ifdef CONFIG_ARM64_SVE
2630 {
2631 .desc = "Scalable Vector Extension",
2632 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2633 .capability = ARM64_SVE,
2634 .cpu_enable = cpu_enable_sve,
2635 .matches = has_cpuid_feature,
2636 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP)
2637 },
2638 #endif /* CONFIG_ARM64_SVE */
2639 #ifdef CONFIG_ARM64_RAS_EXTN
2640 {
2641 .desc = "RAS Extension Support",
2642 .capability = ARM64_HAS_RAS_EXTN,
2643 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2644 .matches = has_cpuid_feature,
2645 .cpu_enable = cpu_clear_disr,
2646 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP)
2647 },
2648 #endif /* CONFIG_ARM64_RAS_EXTN */
2649 #ifdef CONFIG_ARM64_AMU_EXTN
2650 {
2651 .desc = "Activity Monitors Unit (AMU)",
2652 .capability = ARM64_HAS_AMU_EXTN,
2653 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2654 .matches = has_amu,
2655 .cpu_enable = cpu_amu_enable,
2656 .cpus = &amu_cpus,
2657 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP)
2658 },
2659 #endif /* CONFIG_ARM64_AMU_EXTN */
2660 {
2661 .desc = "Data cache clean to the PoU not required for I/D coherence",
2662 .capability = ARM64_HAS_CACHE_IDC,
2663 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2664 .matches = has_cache_idc,
2665 .cpu_enable = cpu_emulate_effective_ctr,
2666 },
2667 {
2668 .desc = "Instruction cache invalidation not required for I/D coherence",
2669 .capability = ARM64_HAS_CACHE_DIC,
2670 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2671 .matches = has_cache_dic,
2672 },
2673 {
2674 .desc = "Stage-2 Force Write-Back",
2675 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2676 .capability = ARM64_HAS_STAGE2_FWB,
2677 .matches = has_cpuid_feature,
2678 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP)
2679 },
2680 {
2681 .desc = "ARMv8.4 Translation Table Level",
2682 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2683 .capability = ARM64_HAS_ARMv8_4_TTL,
2684 .matches = has_cpuid_feature,
2685 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP)
2686 },
2687 {
2688 .desc = "TLB range maintenance instructions",
2689 .capability = ARM64_HAS_TLB_RANGE,
2690 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2691 .matches = has_cpuid_feature,
2692 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE)
2693 },
2694 #ifdef CONFIG_ARM64_HW_AFDBM
2695 {
2696 .desc = "Hardware dirty bit management",
2697 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2698 .capability = ARM64_HW_DBM,
2699 .matches = has_hw_dbm,
2700 .cpu_enable = cpu_enable_hw_dbm,
2701 .cpus = &dbm_cpus,
2702 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM)
2703 },
2704 #endif
2705 #ifdef CONFIG_ARM64_HAFT
2706 {
2707 .desc = "Hardware managed Access Flag for Table Descriptors",
2708 /*
2709 * Contrary to the page/block access flag, the table access flag
2710 * cannot be emulated in software (no access fault will occur).
2711 * Therefore this should be used only if it's supported system
2712 * wide.
2713 */
2714 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2715 .capability = ARM64_HAFT,
2716 .matches = has_cpuid_feature,
2717 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT)
2718 },
2719 #endif
2720 {
2721 .desc = "CRC32 instructions",
2722 .capability = ARM64_HAS_CRC32,
2723 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2724 .matches = has_cpuid_feature,
2725 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP)
2726 },
2727 {
2728 .desc = "Speculative Store Bypassing Safe (SSBS)",
2729 .capability = ARM64_SSBS,
2730 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2731 .matches = has_cpuid_feature,
2732 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP)
2733 },
2734 #ifdef CONFIG_ARM64_CNP
2735 {
2736 .desc = "Common not Private translations",
2737 .capability = ARM64_HAS_CNP,
2738 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2739 .matches = has_useable_cnp,
2740 .cpu_enable = cpu_enable_cnp,
2741 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP)
2742 },
2743 #endif
2744 {
2745 .desc = "Speculation barrier (SB)",
2746 .capability = ARM64_HAS_SB,
2747 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2748 .matches = has_cpuid_feature,
2749 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP)
2750 },
2751 #ifdef CONFIG_ARM64_PTR_AUTH
2752 {
2753 .desc = "Address authentication (architected QARMA5 algorithm)",
2754 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5,
2755 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2756 .matches = has_address_auth_cpucap,
2757 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth)
2758 },
2759 {
2760 .desc = "Address authentication (architected QARMA3 algorithm)",
2761 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3,
2762 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2763 .matches = has_address_auth_cpucap,
2764 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth)
2765 },
2766 {
2767 .desc = "Address authentication (IMP DEF algorithm)",
2768 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2769 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2770 .matches = has_address_auth_cpucap,
2771 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth)
2772 },
2773 {
2774 .capability = ARM64_HAS_ADDRESS_AUTH,
2775 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2776 .matches = has_address_auth_metacap,
2777 },
2778 {
2779 .desc = "Generic authentication (architected QARMA5 algorithm)",
2780 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5,
2781 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2782 .matches = has_cpuid_feature,
2783 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP)
2784 },
2785 {
2786 .desc = "Generic authentication (architected QARMA3 algorithm)",
2787 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3,
2788 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2789 .matches = has_cpuid_feature,
2790 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP)
2791 },
2792 {
2793 .desc = "Generic authentication (IMP DEF algorithm)",
2794 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2795 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2796 .matches = has_cpuid_feature,
2797 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP)
2798 },
2799 {
2800 .capability = ARM64_HAS_GENERIC_AUTH,
2801 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2802 .matches = has_generic_auth,
2803 },
2804 #endif /* CONFIG_ARM64_PTR_AUTH */
2805 #ifdef CONFIG_ARM64_PSEUDO_NMI
2806 {
2807 /*
2808 * Depends on having GICv3
2809 */
2810 .desc = "IRQ priority masking",
2811 .capability = ARM64_HAS_GIC_PRIO_MASKING,
2812 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2813 .matches = can_use_gic_priorities,
2814 },
2815 {
2816 /*
2817 * Depends on ARM64_HAS_GIC_PRIO_MASKING
2818 */
2819 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC,
2820 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2821 .matches = has_gic_prio_relaxed_sync,
2822 },
2823 #endif
2824 #ifdef CONFIG_ARM64_E0PD
2825 {
2826 .desc = "E0PD",
2827 .capability = ARM64_HAS_E0PD,
2828 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2829 .cpu_enable = cpu_enable_e0pd,
2830 .matches = has_cpuid_feature,
2831 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP)
2832 },
2833 #endif
2834 {
2835 .desc = "Random Number Generator",
2836 .capability = ARM64_HAS_RNG,
2837 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2838 .matches = has_cpuid_feature,
2839 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP)
2840 },
2841 #ifdef CONFIG_ARM64_BTI
2842 {
2843 .desc = "Branch Target Identification",
2844 .capability = ARM64_BTI,
2845 #ifdef CONFIG_ARM64_BTI_KERNEL
2846 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2847 #else
2848 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2849 #endif
2850 .matches = has_cpuid_feature,
2851 .cpu_enable = bti_enable,
2852 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP)
2853 },
2854 #endif
2855 #ifdef CONFIG_ARM64_MTE
2856 {
2857 .desc = "Memory Tagging Extension",
2858 .capability = ARM64_MTE,
2859 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2860 .matches = has_cpuid_feature,
2861 .cpu_enable = cpu_enable_mte,
2862 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2)
2863 },
2864 {
2865 .desc = "Asymmetric MTE Tag Check Fault",
2866 .capability = ARM64_MTE_ASYMM,
2867 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2868 .matches = has_cpuid_feature,
2869 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3)
2870 },
2871 #endif /* CONFIG_ARM64_MTE */
2872 {
2873 .desc = "RCpc load-acquire (LDAPR)",
2874 .capability = ARM64_HAS_LDAPR,
2875 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2876 .matches = has_cpuid_feature,
2877 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP)
2878 },
2879 {
2880 .desc = "Fine Grained Traps",
2881 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2882 .capability = ARM64_HAS_FGT,
2883 .matches = has_cpuid_feature,
2884 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP)
2885 },
2886 #ifdef CONFIG_ARM64_SME
2887 {
2888 .desc = "Scalable Matrix Extension",
2889 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2890 .capability = ARM64_SME,
2891 .matches = has_cpuid_feature,
2892 .cpu_enable = cpu_enable_sme,
2893 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP)
2894 },
2895 /* FA64 should be sorted after the base SME capability */
2896 {
2897 .desc = "FA64",
2898 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2899 .capability = ARM64_SME_FA64,
2900 .matches = has_cpuid_feature,
2901 .cpu_enable = cpu_enable_fa64,
2902 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP)
2903 },
2904 {
2905 .desc = "SME2",
2906 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2907 .capability = ARM64_SME2,
2908 .matches = has_cpuid_feature,
2909 .cpu_enable = cpu_enable_sme2,
2910 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2)
2911 },
2912 #endif /* CONFIG_ARM64_SME */
2913 {
2914 .desc = "WFx with timeout",
2915 .capability = ARM64_HAS_WFXT,
2916 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2917 .matches = has_cpuid_feature,
2918 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP)
2919 },
2920 {
2921 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality",
2922 .capability = ARM64_HAS_TIDCP1,
2923 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2924 .matches = has_cpuid_feature,
2925 .cpu_enable = cpu_trap_el0_impdef,
2926 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP)
2927 },
2928 {
2929 .desc = "Data independent timing control (DIT)",
2930 .capability = ARM64_HAS_DIT,
2931 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2932 .matches = has_cpuid_feature,
2933 .cpu_enable = cpu_enable_dit,
2934 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP)
2935 },
2936 {
2937 .desc = "Memory Copy and Memory Set instructions",
2938 .capability = ARM64_HAS_MOPS,
2939 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2940 .matches = has_cpuid_feature,
2941 .cpu_enable = cpu_enable_mops,
2942 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP)
2943 },
2944 {
2945 .capability = ARM64_HAS_TCR2,
2946 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2947 .matches = has_cpuid_feature,
2948 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP)
2949 },
2950 {
2951 .desc = "Stage-1 Permission Indirection Extension (S1PIE)",
2952 .capability = ARM64_HAS_S1PIE,
2953 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2954 .matches = has_cpuid_feature,
2955 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP)
2956 },
2957 {
2958 .desc = "VHE for hypervisor only",
2959 .capability = ARM64_KVM_HVHE,
2960 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2961 .matches = hvhe_possible,
2962 },
2963 {
2964 .desc = "Enhanced Virtualization Traps",
2965 .capability = ARM64_HAS_EVT,
2966 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2967 .matches = has_cpuid_feature,
2968 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP)
2969 },
2970 {
2971 .desc = "52-bit Virtual Addressing for KVM (LPA2)",
2972 .capability = ARM64_HAS_LPA2,
2973 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2974 .matches = has_lpa2,
2975 },
2976 {
2977 .desc = "FPMR",
2978 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2979 .capability = ARM64_HAS_FPMR,
2980 .matches = has_cpuid_feature,
2981 .cpu_enable = cpu_enable_fpmr,
2982 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP)
2983 },
2984 #ifdef CONFIG_ARM64_VA_BITS_52
2985 {
2986 .capability = ARM64_HAS_VA52,
2987 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2988 .matches = has_cpuid_feature,
2989 #ifdef CONFIG_ARM64_64K_PAGES
2990 .desc = "52-bit Virtual Addressing (LVA)",
2991 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52)
2992 #else
2993 .desc = "52-bit Virtual Addressing (LPA2)",
2994 #ifdef CONFIG_ARM64_4K_PAGES
2995 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT)
2996 #else
2997 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT)
2998 #endif
2999 #endif
3000 },
3001 #endif
3002 {
3003 .desc = "Memory Partitioning And Monitoring",
3004 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
3005 .capability = ARM64_MPAM,
3006 .matches = test_has_mpam,
3007 .cpu_enable = cpu_enable_mpam,
3008 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1)
3009 },
3010 {
3011 .desc = "Memory Partitioning And Monitoring Virtualisation",
3012 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
3013 .capability = ARM64_MPAM_HCR,
3014 .matches = test_has_mpam_hcr,
3015 },
3016 {
3017 .desc = "NV1",
3018 .capability = ARM64_HAS_HCR_NV1,
3019 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
3020 .matches = has_nv1,
3021 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1)
3022 },
3023 #ifdef CONFIG_ARM64_POE
3024 {
3025 .desc = "Stage-1 Permission Overlay Extension (S1POE)",
3026 .capability = ARM64_HAS_S1POE,
3027 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
3028 .matches = has_cpuid_feature,
3029 .cpu_enable = cpu_enable_poe,
3030 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP)
3031 },
3032 #endif
3033 #ifdef CONFIG_ARM64_GCS
3034 {
3035 .desc = "Guarded Control Stack (GCS)",
3036 .capability = ARM64_HAS_GCS,
3037 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
3038 .cpu_enable = cpu_enable_gcs,
3039 .matches = has_cpuid_feature,
3040 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP)
3041 },
3042 #endif
3043 #ifdef CONFIG_HW_PERF_EVENTS
3044 {
3045 .desc = "PMUv3",
3046 .capability = ARM64_HAS_PMUV3,
3047 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
3048 .matches = has_pmuv3,
3049 },
3050 #endif
3051 {},
3052 };
3053
3054 #define HWCAP_CPUID_MATCH(reg, field, min_value) \
3055 .matches = has_user_cpuid_feature, \
3056 ARM64_CPUID_FIELDS(reg, field, min_value)
3057
3058 #define __HWCAP_CAP(name, cap_type, cap) \
3059 .desc = name, \
3060 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
3061 .hwcap_type = cap_type, \
3062 .hwcap = cap, \
3063
3064 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \
3065 { \
3066 __HWCAP_CAP(#cap, cap_type, cap) \
3067 HWCAP_CPUID_MATCH(reg, field, min_value) \
3068 }
3069
3070 #define HWCAP_MULTI_CAP(list, cap_type, cap) \
3071 { \
3072 __HWCAP_CAP(#cap, cap_type, cap) \
3073 .matches = cpucap_multi_entry_cap_matches, \
3074 .match_list = list, \
3075 }
3076
3077 #define HWCAP_CAP_MATCH(match, cap_type, cap) \
3078 { \
3079 __HWCAP_CAP(#cap, cap_type, cap) \
3080 .matches = match, \
3081 }
3082
3083 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \
3084 { \
3085 __HWCAP_CAP(#cap, cap_type, cap) \
3086 HWCAP_CPUID_MATCH(reg, field, min_value) \
3087 .matches = match, \
3088 }
3089
3090 #ifdef CONFIG_ARM64_PTR_AUTH
3091 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
3092 {
3093 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth)
3094 },
3095 {
3096 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth)
3097 },
3098 {
3099 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth)
3100 },
3101 {},
3102 };
3103
3104 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
3105 {
3106 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP)
3107 },
3108 {
3109 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP)
3110 },
3111 {
3112 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP)
3113 },
3114 {},
3115 };
3116 #endif
3117
3118 #ifdef CONFIG_ARM64_SVE
has_sve_feature(const struct arm64_cpu_capabilities * cap,int scope)3119 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope)
3120 {
3121 return system_supports_sve() && has_user_cpuid_feature(cap, scope);
3122 }
3123 #endif
3124
3125 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
3126 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL),
3127 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES),
3128 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1),
3129 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2),
3130 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512),
3131 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32),
3132 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
3133 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128),
3134 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
3135 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3),
3136 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3),
3137 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4),
3138 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
3139 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
3140 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
3141 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
3142 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG),
3143 HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT),
3144 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP),
3145 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP),
3146 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
3147 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
3148 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT),
3149 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR),
3150 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
3151 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
3152 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
3153 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA),
3154 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
3155 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
3156 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3),
3157 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT),
3158 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB),
3159 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16),
3160 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16),
3161 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH),
3162 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM),
3163 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT),
3164 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX),
3165 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT),
3166 #ifdef CONFIG_ARM64_SVE
3167 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE),
3168 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2),
3169 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1),
3170 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
3171 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
3172 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
3173 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2),
3174 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
3175 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16),
3176 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE),
3177 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
3178 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16),
3179 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
3180 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
3181 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
3182 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
3183 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
3184 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM),
3185 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM),
3186 #endif
3187 #ifdef CONFIG_ARM64_GCS
3188 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS),
3189 #endif
3190 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS),
3191 #ifdef CONFIG_ARM64_BTI
3192 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI),
3193 #endif
3194 #ifdef CONFIG_ARM64_PTR_AUTH
3195 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
3196 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
3197 #endif
3198 #ifdef CONFIG_ARM64_MTE
3199 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE),
3200 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3),
3201 #endif /* CONFIG_ARM64_MTE */
3202 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV),
3203 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP),
3204 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC),
3205 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR),
3206 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM),
3207 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES),
3208 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
3209 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS),
3210 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC),
3211 #ifdef CONFIG_ARM64_SME
3212 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME),
3213 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
3214 HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2),
3215 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2),
3216 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1),
3217 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2),
3218 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),
3219 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64),
3220 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32),
3221 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16),
3222 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16),
3223 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16),
3224 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32),
3225 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32),
3226 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32),
3227 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32),
3228 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32),
3229 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
3230 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA),
3231 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4),
3232 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2),
3233 HWCAP_CAP(ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM),
3234 HWCAP_CAP(ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES),
3235 HWCAP_CAP(ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA),
3236 HWCAP_CAP(ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP),
3237 HWCAP_CAP(ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4),
3238 #endif /* CONFIG_ARM64_SME */
3239 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT),
3240 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA),
3241 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4),
3242 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2),
3243 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8),
3244 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4),
3245 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3),
3246 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2),
3247 #ifdef CONFIG_ARM64_POE
3248 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE),
3249 #endif
3250 {},
3251 };
3252
3253 #ifdef CONFIG_COMPAT
compat_has_neon(const struct arm64_cpu_capabilities * cap,int scope)3254 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
3255 {
3256 /*
3257 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
3258 * in line with that of arm32 as in vfp_init(). We make sure that the
3259 * check is future proof, by making sure value is non-zero.
3260 */
3261 u32 mvfr1;
3262
3263 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
3264 if (scope == SCOPE_SYSTEM)
3265 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
3266 else
3267 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
3268
3269 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) &&
3270 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) &&
3271 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT);
3272 }
3273 #endif
3274
3275 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
3276 #ifdef CONFIG_COMPAT
3277 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
3278 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
3279 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
3280 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
3281 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
3282 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP),
3283 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP),
3284 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
3285 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
3286 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
3287 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
3288 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
3289 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP),
3290 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM),
3291 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB),
3292 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16),
3293 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM),
3294 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS),
3295 #endif
3296 {},
3297 };
3298
cap_set_elf_hwcap(const struct arm64_cpu_capabilities * cap)3299 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
3300 {
3301 switch (cap->hwcap_type) {
3302 case CAP_HWCAP:
3303 cpu_set_feature(cap->hwcap);
3304 break;
3305 #ifdef CONFIG_COMPAT
3306 case CAP_COMPAT_HWCAP:
3307 compat_elf_hwcap |= (u32)cap->hwcap;
3308 break;
3309 case CAP_COMPAT_HWCAP2:
3310 compat_elf_hwcap2 |= (u32)cap->hwcap;
3311 break;
3312 #endif
3313 default:
3314 WARN_ON(1);
3315 break;
3316 }
3317 }
3318
3319 /* Check if we have a particular HWCAP enabled */
cpus_have_elf_hwcap(const struct arm64_cpu_capabilities * cap)3320 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
3321 {
3322 bool rc;
3323
3324 switch (cap->hwcap_type) {
3325 case CAP_HWCAP:
3326 rc = cpu_have_feature(cap->hwcap);
3327 break;
3328 #ifdef CONFIG_COMPAT
3329 case CAP_COMPAT_HWCAP:
3330 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
3331 break;
3332 case CAP_COMPAT_HWCAP2:
3333 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
3334 break;
3335 #endif
3336 default:
3337 WARN_ON(1);
3338 rc = false;
3339 }
3340
3341 return rc;
3342 }
3343
setup_elf_hwcaps(const struct arm64_cpu_capabilities * hwcaps)3344 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
3345 {
3346 /* We support emulation of accesses to CPU ID feature registers */
3347 cpu_set_named_feature(CPUID);
3348 for (; hwcaps->matches; hwcaps++)
3349 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
3350 cap_set_elf_hwcap(hwcaps);
3351 }
3352
update_cpu_capabilities(u16 scope_mask)3353 static void update_cpu_capabilities(u16 scope_mask)
3354 {
3355 int i;
3356 const struct arm64_cpu_capabilities *caps;
3357
3358 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
3359 for (i = 0; i < ARM64_NCAPS; i++) {
3360 caps = cpucap_ptrs[i];
3361 if (!caps || !(caps->type & scope_mask) ||
3362 cpus_have_cap(caps->capability) ||
3363 !caps->matches(caps, cpucap_default_scope(caps)))
3364 continue;
3365
3366 if (caps->desc && !caps->cpus)
3367 pr_info("detected: %s\n", caps->desc);
3368
3369 __set_bit(caps->capability, system_cpucaps);
3370
3371 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
3372 set_bit(caps->capability, boot_cpucaps);
3373 }
3374 }
3375
3376 /*
3377 * Enable all the available capabilities on this CPU. The capabilities
3378 * with BOOT_CPU scope are handled separately and hence skipped here.
3379 */
cpu_enable_non_boot_scope_capabilities(void * __unused)3380 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
3381 {
3382 int i;
3383 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
3384
3385 for_each_available_cap(i) {
3386 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i];
3387
3388 if (WARN_ON(!cap))
3389 continue;
3390
3391 if (!(cap->type & non_boot_scope))
3392 continue;
3393
3394 if (cap->cpu_enable)
3395 cap->cpu_enable(cap);
3396 }
3397 return 0;
3398 }
3399
3400 /*
3401 * Run through the enabled capabilities and enable() it on all active
3402 * CPUs
3403 */
enable_cpu_capabilities(u16 scope_mask)3404 static void __init enable_cpu_capabilities(u16 scope_mask)
3405 {
3406 int i;
3407 const struct arm64_cpu_capabilities *caps;
3408 bool boot_scope;
3409
3410 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
3411 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
3412
3413 for (i = 0; i < ARM64_NCAPS; i++) {
3414 caps = cpucap_ptrs[i];
3415 if (!caps || !(caps->type & scope_mask) ||
3416 !cpus_have_cap(caps->capability))
3417 continue;
3418
3419 if (boot_scope && caps->cpu_enable)
3420 /*
3421 * Capabilities with SCOPE_BOOT_CPU scope are finalised
3422 * before any secondary CPU boots. Thus, each secondary
3423 * will enable the capability as appropriate via
3424 * check_local_cpu_capabilities(). The only exception is
3425 * the boot CPU, for which the capability must be
3426 * enabled here. This approach avoids costly
3427 * stop_machine() calls for this case.
3428 */
3429 caps->cpu_enable(caps);
3430 }
3431
3432 /*
3433 * For all non-boot scope capabilities, use stop_machine()
3434 * as it schedules the work allowing us to modify PSTATE,
3435 * instead of on_each_cpu() which uses an IPI, giving us a
3436 * PSTATE that disappears when we return.
3437 */
3438 if (!boot_scope)
3439 stop_machine(cpu_enable_non_boot_scope_capabilities,
3440 NULL, cpu_online_mask);
3441 }
3442
3443 /*
3444 * Run through the list of capabilities to check for conflicts.
3445 * If the system has already detected a capability, take necessary
3446 * action on this CPU.
3447 */
verify_local_cpu_caps(u16 scope_mask)3448 static void verify_local_cpu_caps(u16 scope_mask)
3449 {
3450 int i;
3451 bool cpu_has_cap, system_has_cap;
3452 const struct arm64_cpu_capabilities *caps;
3453
3454 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
3455
3456 for (i = 0; i < ARM64_NCAPS; i++) {
3457 caps = cpucap_ptrs[i];
3458 if (!caps || !(caps->type & scope_mask))
3459 continue;
3460
3461 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
3462 system_has_cap = cpus_have_cap(caps->capability);
3463
3464 if (system_has_cap) {
3465 /*
3466 * Check if the new CPU misses an advertised feature,
3467 * which is not safe to miss.
3468 */
3469 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
3470 break;
3471 /*
3472 * We have to issue cpu_enable() irrespective of
3473 * whether the CPU has it or not, as it is enabeld
3474 * system wide. It is upto the call back to take
3475 * appropriate action on this CPU.
3476 */
3477 if (caps->cpu_enable)
3478 caps->cpu_enable(caps);
3479 } else {
3480 /*
3481 * Check if the CPU has this capability if it isn't
3482 * safe to have when the system doesn't.
3483 */
3484 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
3485 break;
3486 }
3487 }
3488
3489 if (i < ARM64_NCAPS) {
3490 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
3491 smp_processor_id(), caps->capability,
3492 caps->desc, system_has_cap, cpu_has_cap);
3493
3494 if (cpucap_panic_on_conflict(caps))
3495 cpu_panic_kernel();
3496 else
3497 cpu_die_early();
3498 }
3499 }
3500
3501 /*
3502 * Check for CPU features that are used in early boot
3503 * based on the Boot CPU value.
3504 */
check_early_cpu_features(void)3505 static void check_early_cpu_features(void)
3506 {
3507 verify_cpu_asid_bits();
3508
3509 verify_local_cpu_caps(SCOPE_BOOT_CPU);
3510 }
3511
3512 static void
__verify_local_elf_hwcaps(const struct arm64_cpu_capabilities * caps)3513 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
3514 {
3515
3516 for (; caps->matches; caps++)
3517 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
3518 pr_crit("CPU%d: missing HWCAP: %s\n",
3519 smp_processor_id(), caps->desc);
3520 cpu_die_early();
3521 }
3522 }
3523
verify_local_elf_hwcaps(void)3524 static void verify_local_elf_hwcaps(void)
3525 {
3526 __verify_local_elf_hwcaps(arm64_elf_hwcaps);
3527
3528 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))
3529 __verify_local_elf_hwcaps(compat_elf_hwcaps);
3530 }
3531
verify_sve_features(void)3532 static void verify_sve_features(void)
3533 {
3534 unsigned long cpacr = cpacr_save_enable_kernel_sve();
3535
3536 if (vec_verify_vq_map(ARM64_VEC_SVE)) {
3537 pr_crit("CPU%d: SVE: vector length support mismatch\n",
3538 smp_processor_id());
3539 cpu_die_early();
3540 }
3541
3542 cpacr_restore(cpacr);
3543 }
3544
verify_sme_features(void)3545 static void verify_sme_features(void)
3546 {
3547 unsigned long cpacr = cpacr_save_enable_kernel_sme();
3548
3549 if (vec_verify_vq_map(ARM64_VEC_SME)) {
3550 pr_crit("CPU%d: SME: vector length support mismatch\n",
3551 smp_processor_id());
3552 cpu_die_early();
3553 }
3554
3555 cpacr_restore(cpacr);
3556 }
3557
verify_hyp_capabilities(void)3558 static void verify_hyp_capabilities(void)
3559 {
3560 u64 safe_mmfr1, mmfr0, mmfr1;
3561 int parange, ipa_max;
3562 unsigned int safe_vmid_bits, vmid_bits;
3563
3564 if (!IS_ENABLED(CONFIG_KVM))
3565 return;
3566
3567 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
3568 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
3569 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
3570
3571 /* Verify VMID bits */
3572 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
3573 vmid_bits = get_vmid_bits(mmfr1);
3574 if (vmid_bits < safe_vmid_bits) {
3575 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
3576 cpu_die_early();
3577 }
3578
3579 /* Verify IPA range */
3580 parange = cpuid_feature_extract_unsigned_field(mmfr0,
3581 ID_AA64MMFR0_EL1_PARANGE_SHIFT);
3582 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
3583 if (ipa_max < get_kvm_ipa_limit()) {
3584 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
3585 cpu_die_early();
3586 }
3587 }
3588
verify_mpam_capabilities(void)3589 static void verify_mpam_capabilities(void)
3590 {
3591 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1);
3592 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
3593 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max;
3594
3595 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) !=
3596 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) {
3597 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id());
3598 cpu_die_early();
3599 }
3600
3601 cpu_idr = read_cpuid(MPAMIDR_EL1);
3602 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1);
3603 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) !=
3604 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) {
3605 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id());
3606 cpu_die_early();
3607 }
3608
3609 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr);
3610 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr);
3611 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr);
3612 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr);
3613 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) {
3614 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id());
3615 cpu_die_early();
3616 }
3617 }
3618
3619 /*
3620 * Run through the enabled system capabilities and enable() it on this CPU.
3621 * The capabilities were decided based on the available CPUs at the boot time.
3622 * Any new CPU should match the system wide status of the capability. If the
3623 * new CPU doesn't have a capability which the system now has enabled, we
3624 * cannot do anything to fix it up and could cause unexpected failures. So
3625 * we park the CPU.
3626 */
verify_local_cpu_capabilities(void)3627 static void verify_local_cpu_capabilities(void)
3628 {
3629 /*
3630 * The capabilities with SCOPE_BOOT_CPU are checked from
3631 * check_early_cpu_features(), as they need to be verified
3632 * on all secondary CPUs.
3633 */
3634 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3635 verify_local_elf_hwcaps();
3636
3637 if (system_supports_sve())
3638 verify_sve_features();
3639
3640 if (system_supports_sme())
3641 verify_sme_features();
3642
3643 if (is_hyp_mode_available())
3644 verify_hyp_capabilities();
3645
3646 if (system_supports_mpam())
3647 verify_mpam_capabilities();
3648 }
3649
check_local_cpu_capabilities(void)3650 void check_local_cpu_capabilities(void)
3651 {
3652 /*
3653 * All secondary CPUs should conform to the early CPU features
3654 * in use by the kernel based on boot CPU.
3655 */
3656 check_early_cpu_features();
3657
3658 /*
3659 * If we haven't finalised the system capabilities, this CPU gets
3660 * a chance to update the errata work arounds and local features.
3661 * Otherwise, this CPU should verify that it has all the system
3662 * advertised capabilities.
3663 */
3664 if (!system_capabilities_finalized())
3665 update_cpu_capabilities(SCOPE_LOCAL_CPU);
3666 else
3667 verify_local_cpu_capabilities();
3668 }
3669
this_cpu_has_cap(unsigned int n)3670 bool this_cpu_has_cap(unsigned int n)
3671 {
3672 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
3673 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n];
3674
3675 if (cap)
3676 return cap->matches(cap, SCOPE_LOCAL_CPU);
3677 }
3678
3679 return false;
3680 }
3681 EXPORT_SYMBOL_GPL(this_cpu_has_cap);
3682
3683 /*
3684 * This helper function is used in a narrow window when,
3685 * - The system wide safe registers are set with all the SMP CPUs and,
3686 * - The SYSTEM_FEATURE system_cpucaps may not have been set.
3687 */
__system_matches_cap(unsigned int n)3688 static bool __maybe_unused __system_matches_cap(unsigned int n)
3689 {
3690 if (n < ARM64_NCAPS) {
3691 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n];
3692
3693 if (cap)
3694 return cap->matches(cap, SCOPE_SYSTEM);
3695 }
3696 return false;
3697 }
3698
cpu_set_feature(unsigned int num)3699 void cpu_set_feature(unsigned int num)
3700 {
3701 set_bit(num, elf_hwcap);
3702 }
3703
cpu_have_feature(unsigned int num)3704 bool cpu_have_feature(unsigned int num)
3705 {
3706 return test_bit(num, elf_hwcap);
3707 }
3708 EXPORT_SYMBOL_GPL(cpu_have_feature);
3709
cpu_get_elf_hwcap(void)3710 unsigned long cpu_get_elf_hwcap(void)
3711 {
3712 /*
3713 * We currently only populate the first 32 bits of AT_HWCAP. Please
3714 * note that for userspace compatibility we guarantee that bits 62
3715 * and 63 will always be returned as 0.
3716 */
3717 return elf_hwcap[0];
3718 }
3719
cpu_get_elf_hwcap2(void)3720 unsigned long cpu_get_elf_hwcap2(void)
3721 {
3722 return elf_hwcap[1];
3723 }
3724
cpu_get_elf_hwcap3(void)3725 unsigned long cpu_get_elf_hwcap3(void)
3726 {
3727 return elf_hwcap[2];
3728 }
3729
setup_boot_cpu_capabilities(void)3730 static void __init setup_boot_cpu_capabilities(void)
3731 {
3732 kvm_arm_target_impl_cpu_init();
3733 /*
3734 * The boot CPU's feature register values have been recorded. Detect
3735 * boot cpucaps and local cpucaps for the boot CPU, then enable and
3736 * patch alternatives for the available boot cpucaps.
3737 */
3738 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
3739 enable_cpu_capabilities(SCOPE_BOOT_CPU);
3740 apply_boot_alternatives();
3741 }
3742
setup_boot_cpu_features(void)3743 void __init setup_boot_cpu_features(void)
3744 {
3745 /*
3746 * Initialize the indirect array of CPU capabilities pointers before we
3747 * handle the boot CPU.
3748 */
3749 init_cpucap_indirect_list();
3750
3751 /*
3752 * Detect broken pseudo-NMI. Must be called _before_ the call to
3753 * setup_boot_cpu_capabilities() since it interacts with
3754 * can_use_gic_priorities().
3755 */
3756 detect_system_supports_pseudo_nmi();
3757
3758 setup_boot_cpu_capabilities();
3759 }
3760
setup_system_capabilities(void)3761 static void __init setup_system_capabilities(void)
3762 {
3763 /*
3764 * The system-wide safe feature register values have been finalized.
3765 * Detect, enable, and patch alternatives for the available system
3766 * cpucaps.
3767 */
3768 update_cpu_capabilities(SCOPE_SYSTEM);
3769 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3770 apply_alternatives_all();
3771
3772 /*
3773 * Log any cpucaps with a cpumask as these aren't logged by
3774 * update_cpu_capabilities().
3775 */
3776 for (int i = 0; i < ARM64_NCAPS; i++) {
3777 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i];
3778
3779 if (caps && caps->cpus && caps->desc &&
3780 cpumask_any(caps->cpus) < nr_cpu_ids)
3781 pr_info("detected: %s on CPU%*pbl\n",
3782 caps->desc, cpumask_pr_args(caps->cpus));
3783 }
3784
3785 /*
3786 * TTBR0 PAN doesn't have its own cpucap, so log it manually.
3787 */
3788 if (system_uses_ttbr0_pan())
3789 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
3790 }
3791
setup_system_features(void)3792 void __init setup_system_features(void)
3793 {
3794 setup_system_capabilities();
3795
3796 kpti_install_ng_mappings();
3797
3798 sve_setup();
3799 sme_setup();
3800
3801 /*
3802 * Check for sane CTR_EL0.CWG value.
3803 */
3804 if (!cache_type_cwg())
3805 pr_warn("No Cache Writeback Granule information, assuming %d\n",
3806 ARCH_DMA_MINALIGN);
3807 }
3808
setup_user_features(void)3809 void __init setup_user_features(void)
3810 {
3811 user_feature_fixup();
3812
3813 setup_elf_hwcaps(arm64_elf_hwcaps);
3814
3815 if (system_supports_32bit_el0()) {
3816 setup_elf_hwcaps(compat_elf_hwcaps);
3817 elf_hwcap_fixup();
3818 }
3819
3820 minsigstksz_setup();
3821 }
3822
enable_mismatched_32bit_el0(unsigned int cpu)3823 static int enable_mismatched_32bit_el0(unsigned int cpu)
3824 {
3825 /*
3826 * The first 32-bit-capable CPU we detected and so can no longer
3827 * be offlined by userspace. -1 indicates we haven't yet onlined
3828 * a 32-bit-capable CPU.
3829 */
3830 static int lucky_winner = -1;
3831
3832 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
3833 bool cpu_32bit = false;
3834
3835 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
3836 if (!housekeeping_cpu(cpu, HK_TYPE_TICK))
3837 pr_info("Treating adaptive-ticks CPU %u as 64-bit only\n", cpu);
3838 else
3839 cpu_32bit = true;
3840 }
3841
3842 if (cpu_32bit) {
3843 cpumask_set_cpu(cpu, cpu_32bit_el0_mask);
3844 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);
3845 }
3846
3847 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit)
3848 return 0;
3849
3850 if (lucky_winner >= 0)
3851 return 0;
3852
3853 /*
3854 * We've detected a mismatch. We need to keep one of our CPUs with
3855 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting
3856 * every CPU in the system for a 32-bit task.
3857 */
3858 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask,
3859 cpu_active_mask);
3860 get_cpu_device(lucky_winner)->offline_disabled = true;
3861 setup_elf_hwcaps(compat_elf_hwcaps);
3862 elf_hwcap_fixup();
3863 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n",
3864 cpu, lucky_winner);
3865 return 0;
3866 }
3867
init_32bit_el0_mask(void)3868 static int __init init_32bit_el0_mask(void)
3869 {
3870 if (!allow_mismatched_32bit_el0)
3871 return 0;
3872
3873 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))
3874 return -ENOMEM;
3875
3876 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
3877 "arm64/mismatched_32bit_el0:online",
3878 enable_mismatched_32bit_el0, NULL);
3879 }
3880 subsys_initcall_sync(init_32bit_el0_mask);
3881
cpu_enable_cnp(struct arm64_cpu_capabilities const * cap)3882 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
3883 {
3884 cpu_enable_swapper_cnp();
3885 }
3886
3887 /*
3888 * We emulate only the following system register space.
3889 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7]
3890 * See Table C5-6 System instruction encodings for System register accesses,
3891 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
3892 */
is_emulated(u32 id)3893 static inline bool __attribute_const__ is_emulated(u32 id)
3894 {
3895 return (sys_reg_Op0(id) == 0x3 &&
3896 sys_reg_CRn(id) == 0x0 &&
3897 sys_reg_Op1(id) == 0x0 &&
3898 (sys_reg_CRm(id) == 0 ||
3899 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7))));
3900 }
3901
3902 /*
3903 * With CRm == 0, reg should be one of :
3904 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
3905 */
emulate_id_reg(u32 id,u64 * valp)3906 static inline int emulate_id_reg(u32 id, u64 *valp)
3907 {
3908 switch (id) {
3909 case SYS_MIDR_EL1:
3910 *valp = read_cpuid_id();
3911 break;
3912 case SYS_MPIDR_EL1:
3913 *valp = SYS_MPIDR_SAFE_VAL;
3914 break;
3915 case SYS_REVIDR_EL1:
3916 /* IMPLEMENTATION DEFINED values are emulated with 0 */
3917 *valp = 0;
3918 break;
3919 default:
3920 return -EINVAL;
3921 }
3922
3923 return 0;
3924 }
3925
emulate_sys_reg(u32 id,u64 * valp)3926 static int emulate_sys_reg(u32 id, u64 *valp)
3927 {
3928 struct arm64_ftr_reg *regp;
3929
3930 if (!is_emulated(id))
3931 return -EINVAL;
3932
3933 if (sys_reg_CRm(id) == 0)
3934 return emulate_id_reg(id, valp);
3935
3936 regp = get_arm64_ftr_reg_nowarn(id);
3937 if (regp)
3938 *valp = arm64_ftr_reg_user_value(regp);
3939 else
3940 /*
3941 * The untracked registers are either IMPLEMENTATION DEFINED
3942 * (e.g, ID_AFR0_EL1) or reserved RAZ.
3943 */
3944 *valp = 0;
3945 return 0;
3946 }
3947
do_emulate_mrs(struct pt_regs * regs,u32 sys_reg,u32 rt)3948 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
3949 {
3950 int rc;
3951 u64 val;
3952
3953 rc = emulate_sys_reg(sys_reg, &val);
3954 if (!rc) {
3955 pt_regs_write_reg(regs, rt, val);
3956 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
3957 }
3958 return rc;
3959 }
3960
try_emulate_mrs(struct pt_regs * regs,u32 insn)3961 bool try_emulate_mrs(struct pt_regs *regs, u32 insn)
3962 {
3963 u32 sys_reg, rt;
3964
3965 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn))
3966 return false;
3967
3968 /*
3969 * sys_reg values are defined as used in mrs/msr instruction.
3970 * shift the imm value to get the encoding.
3971 */
3972 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
3973 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
3974 return do_emulate_mrs(regs, sys_reg, rt) == 0;
3975 }
3976
arm64_get_meltdown_state(void)3977 enum mitigation_state arm64_get_meltdown_state(void)
3978 {
3979 if (__meltdown_safe)
3980 return SPECTRE_UNAFFECTED;
3981
3982 if (arm64_kernel_unmapped_at_el0())
3983 return SPECTRE_MITIGATED;
3984
3985 return SPECTRE_VULNERABLE;
3986 }
3987
cpu_show_meltdown(struct device * dev,struct device_attribute * attr,char * buf)3988 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
3989 char *buf)
3990 {
3991 switch (arm64_get_meltdown_state()) {
3992 case SPECTRE_UNAFFECTED:
3993 return sprintf(buf, "Not affected\n");
3994
3995 case SPECTRE_MITIGATED:
3996 return sprintf(buf, "Mitigation: PTI\n");
3997
3998 default:
3999 return sprintf(buf, "Vulnerable\n");
4000 }
4001 }
4002