1 /*
2 * QEMU AArch64 CPU
3 *
4 * Copyright (c) 2013 Linaro Ltd
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "cpu.h"
24 #include "cpregs.h"
25 #include "qemu/module.h"
26 #include "qemu/units.h"
27 #include "system/kvm.h"
28 #include "system/hvf.h"
29 #include "system/qtest.h"
30 #include "system/tcg.h"
31 #include "kvm_arm.h"
32 #include "hvf_arm.h"
33 #include "qapi/visitor.h"
34 #include "hw/qdev-properties.h"
35 #include "internals.h"
36 #include "cpu-features.h"
37 #include "cpregs.h"
38
arm_cpu_sve_finalize(ARMCPU * cpu,Error ** errp)39 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
40 {
41 /*
42 * If any vector lengths are explicitly enabled with sve<N> properties,
43 * then all other lengths are implicitly disabled. If sve-max-vq is
44 * specified then it is the same as explicitly enabling all lengths
45 * up to and including the specified maximum, which means all larger
46 * lengths will be implicitly disabled. If no sve<N> properties
47 * are enabled and sve-max-vq is not specified, then all lengths not
48 * explicitly disabled will be enabled. Additionally, all power-of-two
49 * vector lengths less than the maximum enabled length will be
50 * automatically enabled and all vector lengths larger than the largest
51 * disabled power-of-two vector length will be automatically disabled.
52 * Errors are generated if the user provided input that interferes with
53 * any of the above. Finally, if SVE is not disabled, then at least one
54 * vector length must be enabled.
55 */
56 uint32_t vq_map = cpu->sve_vq.map;
57 uint32_t vq_init = cpu->sve_vq.init;
58 uint32_t vq_supported;
59 uint32_t vq_mask = 0;
60 uint32_t tmp, vq, max_vq = 0;
61
62 /*
63 * CPU models specify a set of supported vector lengths which are
64 * enabled by default. Attempting to enable any vector length not set
65 * in the supported bitmap results in an error. When KVM is enabled we
66 * fetch the supported bitmap from the host.
67 */
68 if (kvm_enabled()) {
69 if (kvm_arm_sve_supported()) {
70 cpu->sve_vq.supported = kvm_arm_sve_get_vls(cpu);
71 vq_supported = cpu->sve_vq.supported;
72 } else {
73 assert(!cpu_isar_feature(aa64_sve, cpu));
74 vq_supported = 0;
75 }
76 } else {
77 vq_supported = cpu->sve_vq.supported;
78 }
79
80 /*
81 * Process explicit sve<N> properties.
82 * From the properties, sve_vq_map<N> implies sve_vq_init<N>.
83 * Check first for any sve<N> enabled.
84 */
85 if (vq_map != 0) {
86 max_vq = 32 - clz32(vq_map);
87 vq_mask = MAKE_64BIT_MASK(0, max_vq);
88
89 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) {
90 error_setg(errp, "cannot enable sve%d", max_vq * 128);
91 error_append_hint(errp, "sve%d is larger than the maximum vector "
92 "length, sve-max-vq=%d (%d bits)\n",
93 max_vq * 128, cpu->sve_max_vq,
94 cpu->sve_max_vq * 128);
95 return;
96 }
97
98 if (kvm_enabled()) {
99 /*
100 * For KVM we have to automatically enable all supported uninitialized
101 * lengths, even when the smaller lengths are not all powers-of-two.
102 */
103 vq_map |= vq_supported & ~vq_init & vq_mask;
104 } else {
105 /* Propagate enabled bits down through required powers-of-two. */
106 vq_map |= SVE_VQ_POW2_MAP & ~vq_init & vq_mask;
107 }
108 } else if (cpu->sve_max_vq == 0) {
109 /*
110 * No explicit bits enabled, and no implicit bits from sve-max-vq.
111 */
112 if (!cpu_isar_feature(aa64_sve, cpu)) {
113 /*
114 * SVE is disabled and so are all vector lengths. Good.
115 * Disable all SVE extensions as well.
116 */
117 cpu->isar.id_aa64zfr0 = 0;
118 return;
119 }
120
121 if (kvm_enabled()) {
122 /* Disabling a supported length disables all larger lengths. */
123 tmp = vq_init & vq_supported;
124 } else {
125 /* Disabling a power-of-two disables all larger lengths. */
126 tmp = vq_init & SVE_VQ_POW2_MAP;
127 }
128 vq = ctz32(tmp) + 1;
129
130 max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
131 vq_mask = max_vq > 0 ? MAKE_64BIT_MASK(0, max_vq) : 0;
132 vq_map = vq_supported & ~vq_init & vq_mask;
133
134 if (vq_map == 0) {
135 error_setg(errp, "cannot disable sve%d", vq * 128);
136 error_append_hint(errp, "Disabling sve%d results in all "
137 "vector lengths being disabled.\n",
138 vq * 128);
139 error_append_hint(errp, "With SVE enabled, at least one "
140 "vector length must be enabled.\n");
141 return;
142 }
143
144 max_vq = 32 - clz32(vq_map);
145 vq_mask = MAKE_64BIT_MASK(0, max_vq);
146 }
147
148 /*
149 * Process the sve-max-vq property.
150 * Note that we know from the above that no bit above
151 * sve-max-vq is currently set.
152 */
153 if (cpu->sve_max_vq != 0) {
154 max_vq = cpu->sve_max_vq;
155 vq_mask = MAKE_64BIT_MASK(0, max_vq);
156
157 if (vq_init & ~vq_map & (1 << (max_vq - 1))) {
158 error_setg(errp, "cannot disable sve%d", max_vq * 128);
159 error_append_hint(errp, "The maximum vector length must be "
160 "enabled, sve-max-vq=%d (%d bits)\n",
161 max_vq, max_vq * 128);
162 return;
163 }
164
165 /* Set all bits not explicitly set within sve-max-vq. */
166 vq_map |= ~vq_init & vq_mask;
167 }
168
169 /*
170 * We should know what max-vq is now. Also, as we're done
171 * manipulating sve-vq-map, we ensure any bits above max-vq
172 * are clear, just in case anybody looks.
173 */
174 assert(max_vq != 0);
175 assert(vq_mask != 0);
176 vq_map &= vq_mask;
177
178 /* Ensure the set of lengths matches what is supported. */
179 tmp = vq_map ^ (vq_supported & vq_mask);
180 if (tmp) {
181 vq = 32 - clz32(tmp);
182 if (vq_map & (1 << (vq - 1))) {
183 if (cpu->sve_max_vq) {
184 error_setg(errp, "cannot set sve-max-vq=%d", cpu->sve_max_vq);
185 error_append_hint(errp, "This CPU does not support "
186 "the vector length %d-bits.\n", vq * 128);
187 error_append_hint(errp, "It may not be possible to use "
188 "sve-max-vq with this CPU. Try "
189 "using only sve<N> properties.\n");
190 } else {
191 error_setg(errp, "cannot enable sve%d", vq * 128);
192 if (vq_supported) {
193 error_append_hint(errp, "This CPU does not support "
194 "the vector length %d-bits.\n", vq * 128);
195 } else {
196 error_append_hint(errp, "SVE not supported by KVM "
197 "on this host\n");
198 }
199 }
200 return;
201 } else {
202 if (kvm_enabled()) {
203 error_setg(errp, "cannot disable sve%d", vq * 128);
204 error_append_hint(errp, "The KVM host requires all "
205 "supported vector lengths smaller "
206 "than %d bits to also be enabled.\n",
207 max_vq * 128);
208 return;
209 } else {
210 /* Ensure all required powers-of-two are enabled. */
211 tmp = SVE_VQ_POW2_MAP & vq_mask & ~vq_map;
212 if (tmp) {
213 vq = 32 - clz32(tmp);
214 error_setg(errp, "cannot disable sve%d", vq * 128);
215 error_append_hint(errp, "sve%d is required as it "
216 "is a power-of-two length smaller "
217 "than the maximum, sve%d\n",
218 vq * 128, max_vq * 128);
219 return;
220 }
221 }
222 }
223 }
224
225 /*
226 * Now that we validated all our vector lengths, the only question
227 * left to answer is if we even want SVE at all.
228 */
229 if (!cpu_isar_feature(aa64_sve, cpu)) {
230 error_setg(errp, "cannot enable sve%d", max_vq * 128);
231 error_append_hint(errp, "SVE must be enabled to enable vector "
232 "lengths.\n");
233 error_append_hint(errp, "Add sve=on to the CPU property list.\n");
234 return;
235 }
236
237 /* From now on sve_max_vq is the actual maximum supported length. */
238 cpu->sve_max_vq = max_vq;
239 cpu->sve_vq.map = vq_map;
240 }
241
242 /*
243 * Note that cpu_arm_{get,set}_vq cannot use the simpler
244 * object_property_add_bool interface because they make use of the
245 * contents of "name" to determine which bit on which to operate.
246 */
cpu_arm_get_vq(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)247 static void cpu_arm_get_vq(Object *obj, Visitor *v, const char *name,
248 void *opaque, Error **errp)
249 {
250 ARMCPU *cpu = ARM_CPU(obj);
251 ARMVQMap *vq_map = opaque;
252 uint32_t vq = atoi(&name[3]) / 128;
253 bool sve = vq_map == &cpu->sve_vq;
254 bool value;
255
256 /* All vector lengths are disabled when feature is off. */
257 if (sve
258 ? !cpu_isar_feature(aa64_sve, cpu)
259 : !cpu_isar_feature(aa64_sme, cpu)) {
260 value = false;
261 } else {
262 value = extract32(vq_map->map, vq - 1, 1);
263 }
264 visit_type_bool(v, name, &value, errp);
265 }
266
cpu_arm_set_vq(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)267 static void cpu_arm_set_vq(Object *obj, Visitor *v, const char *name,
268 void *opaque, Error **errp)
269 {
270 ARMVQMap *vq_map = opaque;
271 uint32_t vq = atoi(&name[3]) / 128;
272 bool value;
273
274 if (!visit_type_bool(v, name, &value, errp)) {
275 return;
276 }
277
278 vq_map->map = deposit32(vq_map->map, vq - 1, 1, value);
279 vq_map->init |= 1 << (vq - 1);
280 }
281
cpu_arm_get_sve(Object * obj,Error ** errp)282 static bool cpu_arm_get_sve(Object *obj, Error **errp)
283 {
284 ARMCPU *cpu = ARM_CPU(obj);
285 return cpu_isar_feature(aa64_sve, cpu);
286 }
287
cpu_arm_set_sve(Object * obj,bool value,Error ** errp)288 static void cpu_arm_set_sve(Object *obj, bool value, Error **errp)
289 {
290 ARMCPU *cpu = ARM_CPU(obj);
291 uint64_t t;
292
293 if (value && kvm_enabled() && !kvm_arm_sve_supported()) {
294 error_setg(errp, "'sve' feature not supported by KVM on this host");
295 return;
296 }
297
298 t = cpu->isar.id_aa64pfr0;
299 t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
300 cpu->isar.id_aa64pfr0 = t;
301 }
302
arm_cpu_sme_finalize(ARMCPU * cpu,Error ** errp)303 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
304 {
305 uint32_t vq_map = cpu->sme_vq.map;
306 uint32_t vq_init = cpu->sme_vq.init;
307 uint32_t vq_supported = cpu->sme_vq.supported;
308 uint32_t vq;
309
310 if (vq_map == 0) {
311 if (!cpu_isar_feature(aa64_sme, cpu)) {
312 cpu->isar.id_aa64smfr0 = 0;
313 return;
314 }
315
316 /* TODO: KVM will require limitations via SMCR_EL2. */
317 vq_map = vq_supported & ~vq_init;
318
319 if (vq_map == 0) {
320 vq = ctz32(vq_supported) + 1;
321 error_setg(errp, "cannot disable sme%d", vq * 128);
322 error_append_hint(errp, "All SME vector lengths are disabled.\n");
323 error_append_hint(errp, "With SME enabled, at least one "
324 "vector length must be enabled.\n");
325 return;
326 }
327 } else {
328 if (!cpu_isar_feature(aa64_sme, cpu)) {
329 vq = 32 - clz32(vq_map);
330 error_setg(errp, "cannot enable sme%d", vq * 128);
331 error_append_hint(errp, "SME must be enabled to enable "
332 "vector lengths.\n");
333 error_append_hint(errp, "Add sme=on to the CPU property list.\n");
334 return;
335 }
336 /* TODO: KVM will require limitations via SMCR_EL2. */
337 }
338
339 cpu->sme_vq.map = vq_map;
340 }
341
cpu_arm_get_sme(Object * obj,Error ** errp)342 static bool cpu_arm_get_sme(Object *obj, Error **errp)
343 {
344 ARMCPU *cpu = ARM_CPU(obj);
345 return cpu_isar_feature(aa64_sme, cpu);
346 }
347
cpu_arm_set_sme(Object * obj,bool value,Error ** errp)348 static void cpu_arm_set_sme(Object *obj, bool value, Error **errp)
349 {
350 ARMCPU *cpu = ARM_CPU(obj);
351 uint64_t t;
352
353 t = cpu->isar.id_aa64pfr1;
354 t = FIELD_DP64(t, ID_AA64PFR1, SME, value);
355 cpu->isar.id_aa64pfr1 = t;
356 }
357
cpu_arm_get_sme_fa64(Object * obj,Error ** errp)358 static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp)
359 {
360 ARMCPU *cpu = ARM_CPU(obj);
361 return cpu_isar_feature(aa64_sme, cpu) &&
362 cpu_isar_feature(aa64_sme_fa64, cpu);
363 }
364
cpu_arm_set_sme_fa64(Object * obj,bool value,Error ** errp)365 static void cpu_arm_set_sme_fa64(Object *obj, bool value, Error **errp)
366 {
367 ARMCPU *cpu = ARM_CPU(obj);
368 uint64_t t;
369
370 t = cpu->isar.id_aa64smfr0;
371 t = FIELD_DP64(t, ID_AA64SMFR0, FA64, value);
372 cpu->isar.id_aa64smfr0 = t;
373 }
374
375 #ifdef CONFIG_USER_ONLY
376 /* Mirror linux /proc/sys/abi/{sve,sme}_default_vector_length. */
cpu_arm_set_default_vec_len(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)377 static void cpu_arm_set_default_vec_len(Object *obj, Visitor *v,
378 const char *name, void *opaque,
379 Error **errp)
380 {
381 uint32_t *ptr_default_vq = opaque;
382 int32_t default_len, default_vq, remainder;
383
384 if (!visit_type_int32(v, name, &default_len, errp)) {
385 return;
386 }
387
388 /* Undocumented, but the kernel allows -1 to indicate "maximum". */
389 if (default_len == -1) {
390 *ptr_default_vq = ARM_MAX_VQ;
391 return;
392 }
393
394 default_vq = default_len / 16;
395 remainder = default_len % 16;
396
397 /*
398 * Note that the 512 max comes from include/uapi/asm/sve_context.h
399 * and is the maximum architectural width of ZCR_ELx.LEN.
400 */
401 if (remainder || default_vq < 1 || default_vq > 512) {
402 ARMCPU *cpu = ARM_CPU(obj);
403 const char *which =
404 (ptr_default_vq == &cpu->sve_default_vq ? "sve" : "sme");
405
406 error_setg(errp, "cannot set %s-default-vector-length", which);
407 if (remainder) {
408 error_append_hint(errp, "Vector length not a multiple of 16\n");
409 } else if (default_vq < 1) {
410 error_append_hint(errp, "Vector length smaller than 16\n");
411 } else {
412 error_append_hint(errp, "Vector length larger than %d\n",
413 512 * 16);
414 }
415 return;
416 }
417
418 *ptr_default_vq = default_vq;
419 }
420
cpu_arm_get_default_vec_len(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)421 static void cpu_arm_get_default_vec_len(Object *obj, Visitor *v,
422 const char *name, void *opaque,
423 Error **errp)
424 {
425 uint32_t *ptr_default_vq = opaque;
426 int32_t value = *ptr_default_vq * 16;
427
428 visit_type_int32(v, name, &value, errp);
429 }
430 #endif
431
aarch64_add_sve_properties(Object * obj)432 void aarch64_add_sve_properties(Object *obj)
433 {
434 ARMCPU *cpu = ARM_CPU(obj);
435 uint32_t vq;
436
437 object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve);
438
439 for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
440 char name[8];
441 snprintf(name, sizeof(name), "sve%d", vq * 128);
442 object_property_add(obj, name, "bool", cpu_arm_get_vq,
443 cpu_arm_set_vq, NULL, &cpu->sve_vq);
444 }
445
446 #ifdef CONFIG_USER_ONLY
447 /* Mirror linux /proc/sys/abi/sve_default_vector_length. */
448 object_property_add(obj, "sve-default-vector-length", "int32",
449 cpu_arm_get_default_vec_len,
450 cpu_arm_set_default_vec_len, NULL,
451 &cpu->sve_default_vq);
452 #endif
453 }
454
aarch64_add_sme_properties(Object * obj)455 void aarch64_add_sme_properties(Object *obj)
456 {
457 ARMCPU *cpu = ARM_CPU(obj);
458 uint32_t vq;
459
460 object_property_add_bool(obj, "sme", cpu_arm_get_sme, cpu_arm_set_sme);
461 object_property_add_bool(obj, "sme_fa64", cpu_arm_get_sme_fa64,
462 cpu_arm_set_sme_fa64);
463
464 for (vq = 1; vq <= ARM_MAX_VQ; vq <<= 1) {
465 char name[8];
466 snprintf(name, sizeof(name), "sme%d", vq * 128);
467 object_property_add(obj, name, "bool", cpu_arm_get_vq,
468 cpu_arm_set_vq, NULL, &cpu->sme_vq);
469 }
470
471 #ifdef CONFIG_USER_ONLY
472 /* Mirror linux /proc/sys/abi/sme_default_vector_length. */
473 object_property_add(obj, "sme-default-vector-length", "int32",
474 cpu_arm_get_default_vec_len,
475 cpu_arm_set_default_vec_len, NULL,
476 &cpu->sme_default_vq);
477 #endif
478 }
479
arm_cpu_pauth_finalize(ARMCPU * cpu,Error ** errp)480 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
481 {
482 ARMPauthFeature features = cpu_isar_feature(pauth_feature, cpu);
483 uint64_t isar1, isar2;
484
485 /*
486 * These properties enable or disable Pauth as a whole, or change
487 * the pauth algorithm, but do not change the set of features that
488 * are present. We have saved a copy of those features above and
489 * will now place it into the field that chooses the algorithm.
490 *
491 * Begin by disabling all fields.
492 */
493 isar1 = cpu->isar.id_aa64isar1;
494 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, 0);
495 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 0);
496 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, 0);
497 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 0);
498
499 isar2 = cpu->isar.id_aa64isar2;
500 isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0);
501 isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0);
502
503 if (kvm_enabled() || hvf_enabled()) {
504 /*
505 * Exit early if PAuth is enabled and fall through to disable it.
506 * The algorithm selection properties are not present.
507 */
508 if (cpu->prop_pauth) {
509 if (features == 0) {
510 error_setg(errp, "'pauth' feature not supported by "
511 "%s on this host", current_accel_name());
512 }
513 return;
514 }
515 } else {
516 /* Pauth properties are only present when the model supports it. */
517 if (features == 0) {
518 assert(!cpu->prop_pauth);
519 return;
520 }
521
522 if (cpu->prop_pauth) {
523 if ((cpu->prop_pauth_impdef && cpu->prop_pauth_qarma3) ||
524 (cpu->prop_pauth_impdef && cpu->prop_pauth_qarma5) ||
525 (cpu->prop_pauth_qarma3 && cpu->prop_pauth_qarma5)) {
526 error_setg(errp,
527 "cannot enable pauth-impdef, pauth-qarma3 and "
528 "pauth-qarma5 at the same time");
529 return;
530 }
531
532 bool use_default = !cpu->prop_pauth_qarma5 &&
533 !cpu->prop_pauth_qarma3 &&
534 !cpu->prop_pauth_impdef;
535
536 if (cpu->prop_pauth_qarma5 ||
537 (use_default &&
538 cpu->backcompat_pauth_default_use_qarma5)) {
539 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, features);
540 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1);
541 } else if (cpu->prop_pauth_qarma3) {
542 isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, features);
543 isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 1);
544 } else if (cpu->prop_pauth_impdef ||
545 (use_default &&
546 !cpu->backcompat_pauth_default_use_qarma5)) {
547 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, features);
548 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 1);
549 } else {
550 g_assert_not_reached();
551 }
552 } else if (cpu->prop_pauth_impdef ||
553 cpu->prop_pauth_qarma3 ||
554 cpu->prop_pauth_qarma5) {
555 error_setg(errp, "cannot enable pauth-impdef, pauth-qarma3 or "
556 "pauth-qarma5 without pauth");
557 error_append_hint(errp, "Add pauth=on to the CPU property list.\n");
558 }
559 }
560
561 cpu->isar.id_aa64isar1 = isar1;
562 cpu->isar.id_aa64isar2 = isar2;
563 }
564
565 static const Property arm_cpu_pauth_property =
566 DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true);
567 static const Property arm_cpu_pauth_impdef_property =
568 DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false);
569 static const Property arm_cpu_pauth_qarma3_property =
570 DEFINE_PROP_BOOL("pauth-qarma3", ARMCPU, prop_pauth_qarma3, false);
571 static Property arm_cpu_pauth_qarma5_property =
572 DEFINE_PROP_BOOL("pauth-qarma5", ARMCPU, prop_pauth_qarma5, false);
573
aarch64_add_pauth_properties(Object * obj)574 void aarch64_add_pauth_properties(Object *obj)
575 {
576 ARMCPU *cpu = ARM_CPU(obj);
577
578 /* Default to PAUTH on, with the architected algorithm on TCG. */
579 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property);
580 if (kvm_enabled() || hvf_enabled()) {
581 /*
582 * Mirror PAuth support from the probed sysregs back into the
583 * property for KVM or hvf. Is it just a bit backward? Yes it is!
584 * Note that prop_pauth is true whether the host CPU supports the
585 * architected QARMA5 algorithm or the IMPDEF one. We don't
586 * provide the separate pauth-impdef property for KVM or hvf,
587 * only for TCG.
588 */
589 cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu);
590 } else {
591 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property);
592 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_qarma3_property);
593 qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_qarma5_property);
594 }
595 }
596
arm_cpu_lpa2_finalize(ARMCPU * cpu,Error ** errp)597 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
598 {
599 uint64_t t;
600
601 /*
602 * We only install the property for tcg -cpu max; this is the
603 * only situation in which the cpu field can be true.
604 */
605 if (!cpu->prop_lpa2) {
606 return;
607 }
608
609 t = cpu->isar.id_aa64mmfr0;
610 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 */
611 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 */
612 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */
613 t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2 */
614 cpu->isar.id_aa64mmfr0 = t;
615 }
616
aarch64_a57_initfn(Object * obj)617 static void aarch64_a57_initfn(Object *obj)
618 {
619 ARMCPU *cpu = ARM_CPU(obj);
620
621 cpu->dtb_compatible = "arm,cortex-a57";
622 set_feature(&cpu->env, ARM_FEATURE_V8);
623 set_feature(&cpu->env, ARM_FEATURE_NEON);
624 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
625 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
626 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
627 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
628 set_feature(&cpu->env, ARM_FEATURE_EL2);
629 set_feature(&cpu->env, ARM_FEATURE_EL3);
630 set_feature(&cpu->env, ARM_FEATURE_PMU);
631 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
632 cpu->midr = 0x411fd070;
633 cpu->revidr = 0x00000000;
634 cpu->reset_fpsid = 0x41034070;
635 cpu->isar.mvfr0 = 0x10110222;
636 cpu->isar.mvfr1 = 0x12111111;
637 cpu->isar.mvfr2 = 0x00000043;
638 cpu->ctr = 0x8444c004;
639 cpu->reset_sctlr = 0x00c50838;
640 cpu->isar.id_pfr0 = 0x00000131;
641 cpu->isar.id_pfr1 = 0x00011011;
642 cpu->isar.id_dfr0 = 0x03010066;
643 cpu->id_afr0 = 0x00000000;
644 cpu->isar.id_mmfr0 = 0x10101105;
645 cpu->isar.id_mmfr1 = 0x40000000;
646 cpu->isar.id_mmfr2 = 0x01260000;
647 cpu->isar.id_mmfr3 = 0x02102211;
648 cpu->isar.id_isar0 = 0x02101110;
649 cpu->isar.id_isar1 = 0x13112111;
650 cpu->isar.id_isar2 = 0x21232042;
651 cpu->isar.id_isar3 = 0x01112131;
652 cpu->isar.id_isar4 = 0x00011142;
653 cpu->isar.id_isar5 = 0x00011121;
654 cpu->isar.id_isar6 = 0;
655 cpu->isar.id_aa64pfr0 = 0x00002222;
656 cpu->isar.id_aa64dfr0 = 0x10305106;
657 cpu->isar.id_aa64isar0 = 0x00011120;
658 cpu->isar.id_aa64mmfr0 = 0x00001124;
659 cpu->isar.dbgdidr = 0x3516d000;
660 cpu->isar.dbgdevid = 0x01110f13;
661 cpu->isar.dbgdevid1 = 0x2;
662 cpu->isar.reset_pmcr_el0 = 0x41013000;
663 cpu->clidr = 0x0a200023;
664 /* 32KB L1 dcache */
665 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
666 /* 48KB L1 icache */
667 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
668 /* 2048KB L2 cache */
669 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
670 cpu->dcz_blocksize = 4; /* 64 bytes */
671 cpu->gic_num_lrs = 4;
672 cpu->gic_vpribits = 5;
673 cpu->gic_vprebits = 5;
674 cpu->gic_pribits = 5;
675 define_cortex_a72_a57_a53_cp_reginfo(cpu);
676 }
677
aarch64_a53_initfn(Object * obj)678 static void aarch64_a53_initfn(Object *obj)
679 {
680 ARMCPU *cpu = ARM_CPU(obj);
681
682 cpu->dtb_compatible = "arm,cortex-a53";
683 set_feature(&cpu->env, ARM_FEATURE_V8);
684 set_feature(&cpu->env, ARM_FEATURE_NEON);
685 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
686 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
687 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
688 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
689 set_feature(&cpu->env, ARM_FEATURE_EL2);
690 set_feature(&cpu->env, ARM_FEATURE_EL3);
691 set_feature(&cpu->env, ARM_FEATURE_PMU);
692 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
693 cpu->midr = 0x410fd034;
694 cpu->revidr = 0x00000100;
695 cpu->reset_fpsid = 0x41034070;
696 cpu->isar.mvfr0 = 0x10110222;
697 cpu->isar.mvfr1 = 0x12111111;
698 cpu->isar.mvfr2 = 0x00000043;
699 cpu->ctr = 0x84448004; /* L1Ip = VIPT */
700 cpu->reset_sctlr = 0x00c50838;
701 cpu->isar.id_pfr0 = 0x00000131;
702 cpu->isar.id_pfr1 = 0x00011011;
703 cpu->isar.id_dfr0 = 0x03010066;
704 cpu->id_afr0 = 0x00000000;
705 cpu->isar.id_mmfr0 = 0x10101105;
706 cpu->isar.id_mmfr1 = 0x40000000;
707 cpu->isar.id_mmfr2 = 0x01260000;
708 cpu->isar.id_mmfr3 = 0x02102211;
709 cpu->isar.id_isar0 = 0x02101110;
710 cpu->isar.id_isar1 = 0x13112111;
711 cpu->isar.id_isar2 = 0x21232042;
712 cpu->isar.id_isar3 = 0x01112131;
713 cpu->isar.id_isar4 = 0x00011142;
714 cpu->isar.id_isar5 = 0x00011121;
715 cpu->isar.id_isar6 = 0;
716 cpu->isar.id_aa64pfr0 = 0x00002222;
717 cpu->isar.id_aa64dfr0 = 0x10305106;
718 cpu->isar.id_aa64isar0 = 0x00011120;
719 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
720 cpu->isar.dbgdidr = 0x3516d000;
721 cpu->isar.dbgdevid = 0x00110f13;
722 cpu->isar.dbgdevid1 = 0x1;
723 cpu->isar.reset_pmcr_el0 = 0x41033000;
724 cpu->clidr = 0x0a200023;
725 /* 32KB L1 dcache */
726 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
727 /* 32KB L1 icache */
728 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 1, 64, 32 * KiB, 2);
729 /* 1024KB L2 cache */
730 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7);
731 cpu->dcz_blocksize = 4; /* 64 bytes */
732 cpu->gic_num_lrs = 4;
733 cpu->gic_vpribits = 5;
734 cpu->gic_vprebits = 5;
735 cpu->gic_pribits = 5;
736 define_cortex_a72_a57_a53_cp_reginfo(cpu);
737 }
738
aarch64_host_initfn(Object * obj)739 static void aarch64_host_initfn(Object *obj)
740 {
741 #if defined(CONFIG_KVM)
742 ARMCPU *cpu = ARM_CPU(obj);
743 kvm_arm_set_cpu_features_from_host(cpu);
744 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
745 aarch64_add_sve_properties(obj);
746 aarch64_add_pauth_properties(obj);
747 }
748 #elif defined(CONFIG_HVF)
749 ARMCPU *cpu = ARM_CPU(obj);
750 hvf_arm_set_cpu_features_from_host(cpu);
751 aarch64_add_pauth_properties(obj);
752 #else
753 g_assert_not_reached();
754 #endif
755 }
756
aarch64_max_initfn(Object * obj)757 static void aarch64_max_initfn(Object *obj)
758 {
759 if (kvm_enabled() || hvf_enabled()) {
760 /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
761 aarch64_host_initfn(obj);
762 return;
763 }
764
765 if (tcg_enabled() || qtest_enabled()) {
766 aarch64_a57_initfn(obj);
767 }
768
769 /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
770 if (tcg_enabled()) {
771 aarch64_max_tcg_initfn(obj);
772 }
773 }
774
775 static const ARMCPUInfo aarch64_cpus[] = {
776 { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
777 { .name = "cortex-a53", .initfn = aarch64_a53_initfn },
778 { .name = "max", .initfn = aarch64_max_initfn },
779 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
780 { .name = "host", .initfn = aarch64_host_initfn },
781 #endif
782 };
783
aarch64_cpu_register_types(void)784 static void aarch64_cpu_register_types(void)
785 {
786 size_t i;
787
788 for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
789 arm_cpu_register(&aarch64_cpus[i]);
790 }
791 }
792
793 type_init(aarch64_cpu_register_types)
794