1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2018 Alexandru Elisei <alexandru.elisei@gmail.com>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include <sys/types.h>
30 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <sys/lock.h>
33
34 #include <machine/cpu.h>
35 #include <machine/hypervisor.h>
36
37 #include <dev/vmm/vmm_vm.h>
38
39 #include "arm64.h"
40 #include "reset.h"
41
42 /*
43 * Make the architecturally UNKNOWN value 0. As a bonus, we don't have to
44 * manually set all those RES0 fields.
45 */
46 #define ARCH_UNKNOWN 0
47 #define set_arch_unknown(reg) (memset(&(reg), ARCH_UNKNOWN, sizeof(reg)))
48
49 void
reset_vm_el01_regs(void * vcpu)50 reset_vm_el01_regs(void *vcpu)
51 {
52 struct hypctx *el2ctx;
53
54 el2ctx = vcpu;
55
56 set_arch_unknown(el2ctx->tf);
57
58 set_arch_unknown(el2ctx->actlr_el1);
59 set_arch_unknown(el2ctx->afsr0_el1);
60 set_arch_unknown(el2ctx->afsr1_el1);
61 set_arch_unknown(el2ctx->amair_el1);
62 set_arch_unknown(el2ctx->contextidr_el1);
63 set_arch_unknown(el2ctx->cpacr_el1);
64 set_arch_unknown(el2ctx->csselr_el1);
65 set_arch_unknown(el2ctx->elr_el1);
66 set_arch_unknown(el2ctx->esr_el1);
67 set_arch_unknown(el2ctx->far_el1);
68 set_arch_unknown(el2ctx->mair_el1);
69 set_arch_unknown(el2ctx->mdccint_el1);
70 set_arch_unknown(el2ctx->mdscr_el1);
71 set_arch_unknown(el2ctx->par_el1);
72
73 /*
74 * Guest starts with:
75 * ~SCTLR_M: MMU off
76 * ~SCTLR_C: data cache off
77 * SCTLR_CP15BEN: memory barrier instruction enable from EL0; RAO/WI
78 * ~SCTLR_I: instruction cache off
79 */
80 el2ctx->sctlr_el1 = SCTLR_RES1;
81 el2ctx->sctlr_el1 &= ~SCTLR_M & ~SCTLR_C & ~SCTLR_I;
82 el2ctx->sctlr_el1 |= SCTLR_CP15BEN;
83
84 set_arch_unknown(el2ctx->sp_el0);
85 set_arch_unknown(el2ctx->tcr_el1);
86 set_arch_unknown(el2ctx->tpidr_el0);
87 set_arch_unknown(el2ctx->tpidr_el1);
88 set_arch_unknown(el2ctx->tpidrro_el0);
89 set_arch_unknown(el2ctx->ttbr0_el1);
90 set_arch_unknown(el2ctx->ttbr1_el1);
91 set_arch_unknown(el2ctx->vbar_el1);
92 set_arch_unknown(el2ctx->spsr_el1);
93
94 set_arch_unknown(el2ctx->dbgbcr_el1);
95 set_arch_unknown(el2ctx->dbgbvr_el1);
96 set_arch_unknown(el2ctx->dbgwcr_el1);
97 set_arch_unknown(el2ctx->dbgwvr_el1);
98
99 el2ctx->pmcr_el0 = READ_SPECIALREG(pmcr_el0) & PMCR_N_MASK;
100 /* PMCR_LC is unknown when AArch32 is supported or RES1 otherwise */
101 el2ctx->pmcr_el0 |= PMCR_LC;
102 set_arch_unknown(el2ctx->pmccntr_el0);
103 set_arch_unknown(el2ctx->pmccfiltr_el0);
104 set_arch_unknown(el2ctx->pmuserenr_el0);
105 set_arch_unknown(el2ctx->pmselr_el0);
106 set_arch_unknown(el2ctx->pmxevcntr_el0);
107 set_arch_unknown(el2ctx->pmcntenset_el0);
108 set_arch_unknown(el2ctx->pmintenset_el1);
109 set_arch_unknown(el2ctx->pmovsset_el0);
110 memset(el2ctx->pmevcntr_el0, 0, sizeof(el2ctx->pmevcntr_el0));
111 memset(el2ctx->pmevtyper_el0, 0, sizeof(el2ctx->pmevtyper_el0));
112 }
113
114 void
reset_vm_el2_regs(void * vcpu)115 reset_vm_el2_regs(void *vcpu)
116 {
117 struct hypctx *el2ctx;
118 uint64_t cpu_aff, vcpuid;
119
120 el2ctx = vcpu;
121 vcpuid = vcpu_vcpuid(el2ctx->vcpu);
122
123 /*
124 * Set the Hypervisor Configuration Register:
125 *
126 * HCR_RW: use AArch64 for EL1
127 * HCR_TID3: handle ID registers in the vmm to privide a common
128 * set of featers on all vcpus
129 * HCR_TWI: Trap WFI to the hypervisor
130 * HCR_BSU_IS: barrier instructions apply to the inner shareable
131 * domain
132 * HCR_FB: broadcast maintenance operations
133 * HCR_AMO: route physical SError interrupts to EL2
134 * HCR_IMO: route physical IRQ interrupts to EL2
135 * HCR_FMO: route physical FIQ interrupts to EL2
136 * HCR_SWIO: turn set/way invalidate into set/way clean and
137 * invalidate
138 * HCR_VM: use stage 2 translation
139 */
140 el2ctx->hcr_el2 = HCR_RW | HCR_TID3 | HCR_TWI | HCR_BSU_IS | HCR_FB |
141 HCR_AMO | HCR_IMO | HCR_FMO | HCR_SWIO | HCR_VM;
142 if (in_vhe()) {
143 el2ctx->hcr_el2 |= HCR_E2H;
144 }
145
146 /* Set the Extended Hypervisor Configuration Register */
147 el2ctx->hcrx_el2 = 0;
148 /* TODO: Trap all extensions we don't support */
149 el2ctx->mdcr_el2 = MDCR_EL2_TDOSA | MDCR_EL2_TDRA | MDCR_EL2_TPMS |
150 MDCR_EL2_TTRF;
151 /* PMCR_EL0.N is read from MDCR_EL2.HPMN */
152 el2ctx->mdcr_el2 |= (el2ctx->pmcr_el0 & PMCR_N_MASK) >> PMCR_N_SHIFT;
153
154 el2ctx->vmpidr_el2 = VMPIDR_EL2_RES1;
155 /* The guest will detect a multi-core, single-threaded CPU */
156 el2ctx->vmpidr_el2 &= ~VMPIDR_EL2_U & ~VMPIDR_EL2_MT;
157 /*
158 * Generate the guest MPIDR value. We only support 16 CPUs at affinity
159 * level 0 to simplify the vgicv3 driver (see writing sgi1r_el1).
160 */
161 cpu_aff = (vcpuid & 0xf) << MPIDR_AFF0_SHIFT |
162 ((vcpuid >> 4) & 0xff) << MPIDR_AFF1_SHIFT |
163 ((vcpuid >> 12) & 0xff) << MPIDR_AFF2_SHIFT |
164 ((vcpuid >> 20) & 0xff) << MPIDR_AFF3_SHIFT;
165 el2ctx->vmpidr_el2 |= cpu_aff;
166
167 /* Use the same CPU identification information as the host */
168 el2ctx->vpidr_el2 = CPU_IMPL_TO_MIDR(CPU_IMPL_ARM);
169 el2ctx->vpidr_el2 |= CPU_VAR_TO_MIDR(0);
170 el2ctx->vpidr_el2 |= CPU_ARCH_TO_MIDR(0xf);
171 el2ctx->vpidr_el2 |= CPU_PART_TO_MIDR(CPU_PART_FOUNDATION);
172 el2ctx->vpidr_el2 |= CPU_REV_TO_MIDR(0);
173
174 /*
175 * Don't trap accesses to CPACR_EL1, trace, SVE, Advanced SIMD
176 * and floating point functionality to EL2.
177 */
178 if (in_vhe())
179 el2ctx->cptr_el2 = CPTR_E2H_TRAP_ALL | CPTR_E2H_FPEN;
180 else
181 el2ctx->cptr_el2 = CPTR_TRAP_ALL & ~CPTR_TFP;
182 el2ctx->cptr_el2 &= ~CPTR_TCPAC;
183 /*
184 * Disable interrupts in the guest. The guest OS will re-enable
185 * them.
186 */
187 el2ctx->tf.tf_spsr = PSR_D | PSR_A | PSR_I | PSR_F;
188 /* Use the EL1 stack when taking exceptions to EL1 */
189 el2ctx->tf.tf_spsr |= PSR_M_EL1h;
190
191 /* FEAT_FGT traps */
192 if ((el2ctx->hyp->feats & HYP_FEAT_FGT) != 0) {
193 #define HFGT_TRAP_FIELDS(read, write, read_pfx, write_pfx, name, trap) \
194 do { \
195 el2ctx->read |= read_pfx ## _EL2_ ## name ## _ ## trap; \
196 el2ctx->write |= write_pfx ## _EL2_ ## name ## _ ## trap; \
197 } while (0)
198
199
200 /*
201 * Traps for special registers
202 */
203
204 /* Debug registers */
205 el2ctx->hdfgrtr_el2 = 0;
206 el2ctx->hdfgwtr_el2 = 0;
207
208 /* FEAT_BRBE */
209 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
210 nBRBDATA, TRAP);
211 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
212 nBRBCTL, TRAP);
213 el2ctx->hdfgrtr_el2 |= HDFGRTR_EL2_nBRBIDR_TRAP;
214
215 /* FEAT_TRBE */
216 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
217 TRBTRG_EL1, TRAP);
218 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
219 TRBSR_EL1, TRAP);
220 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
221 TRBPTR_EL1, TRAP);
222 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
223 TRBMAR_EL1, TRAP);
224 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
225 TRBLIMITR_EL1, TRAP);
226 el2ctx->hdfgrtr_el2 |= HDFGRTR_EL2_TRBIDR_EL1_TRAP;
227 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
228 TRBBASER_EL1, TRAP);
229
230 /* FEAT_TRF */
231 el2ctx->hdfgwtr_el2 |= HDFGWTR_EL2_TRFCR_EL1_TRAP;
232
233 /* FEAT_ETE */
234 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
235 TRCVICTLR, TRAP);
236 el2ctx->hdfgrtr_el2 |= HDFGRTR_EL2_TRCSTATR_TRAP;
237 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
238 TRCSSCSRn, TRAP);
239 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
240 TRCSEQSTR, TRAP);
241 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
242 TRCPRGCTLR, TRAP);
243 el2ctx->hdfgrtr_el2 |= HDFGRTR_EL2_TRCOSLSR_TRAP;
244 el2ctx->hdfgwtr_el2 |= HDFGWTR_EL2_TRCOSLAR_TRAP;
245 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
246 TRCIMSPECn, TRAP);
247 el2ctx->hdfgrtr_el2 |= HDFGRTR_EL2_TRCID_TRAP;
248 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
249 TRCCNTVRn, TRAP);
250 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
251 TRCCLAIM, TRAP);
252 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
253 TRCAUXCTLR, TRAP);
254 el2ctx->hdfgrtr_el2 |= HDFGRTR_EL2_TRCAUTHSTATUS_TRAP;
255 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
256 TRC, TRAP);
257 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
258 PMSLATFR_EL1, TRAP);
259 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
260 PMSIRR_EL1, TRAP);
261
262 /* FEAT_SPE */
263 el2ctx->hdfgrtr_el2 |= HDFGRTR_EL2_PMBIDR_EL1_TRAP;
264 el2ctx->hdfgrtr_el2 |= HDFGRTR_EL2_PMSIDR_EL1_TRAP;
265 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
266 PMSICR_EL1, TRAP);
267 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
268 PMSFCR_EL1, TRAP);
269 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
270 PMSEVFR_EL1, TRAP);
271 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
272 PMSCR_EL1, TRAP);
273 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
274 PMBSR_EL1, TRAP);
275 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
276 PMBPTR_EL1, TRAP);
277 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
278 PMBLIMITR_EL1, TRAP);
279
280 /* FEAT_SPE_FnE */
281 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
282 nPMSNEVFR_EL1, TRAP);
283
284 /* FEAT_PMUv3 */
285 el2ctx->hdfgrtr_el2 |= HDFGRTR_EL2_PMCEIDn_EL0_NOTRAP;
286 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
287 PMUSERENR_EL0, NOTRAP);
288 el2ctx->hdfgrtr_el2 |= HDFGRTR_EL2_PMMIR_EL1_NOTRAP;
289 el2ctx->hdfgwtr_el2 |= HDFGWTR_EL2_PMCR_EL0_NOTRAP;
290 el2ctx->hdfgwtr_el2 |= HDFGWTR_EL2_PMSWINC_EL0_NOTRAP;
291 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
292 PMSELR_EL0, NOTRAP);
293 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
294 PMOVS, NOTRAP);
295 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
296 PMINTEN, NOTRAP);
297 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
298 PMCNTEN, NOTRAP);
299 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
300 PMCCNTR_EL0, NOTRAP);
301 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
302 PMCCFILTR_EL0, NOTRAP);
303 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
304 PMEVTYPERn_EL0, NOTRAP);
305 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
306 PMEVCNTRn_EL0, NOTRAP);
307
308 /* FEAT_DoubleLock */
309 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
310 OSDLR_EL1, TRAP);
311
312 /* Base architecture */
313 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
314 OSECCR_EL1, NOTRAP);
315 el2ctx->hdfgrtr_el2 |= HDFGRTR_EL2_OSLSR_EL1_NOTRAP;
316 el2ctx->hdfgwtr_el2 |= HDFGWTR_EL2_OSLAR_EL1_NOTRAP;
317 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
318 DBGPRCR_EL1, NOTRAP);
319 el2ctx->hdfgrtr_el2 |= HDFGRTR_EL2_DBGAUTHSTATUS_EL1_NOTRAP;
320 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
321 DBGCLAIM, NOTRAP);
322 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
323 MDSCR_EL1, NOTRAP);
324 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
325 DBGWVRn_EL1, NOTRAP);
326 el2ctx->hdfgwtr_el2 |= HDFGWTR_EL2_DBGWCRn_EL1_NOTRAP;
327 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
328 DBGBVRn_EL1, NOTRAP);
329 HFGT_TRAP_FIELDS(hdfgrtr_el2, hdfgwtr_el2, HDFGRTR, HDFGWTR,
330 DBGBCRn_EL1, NOTRAP);
331
332
333 /* Non-debug special registers */
334 el2ctx->hfgrtr_el2 = 0;
335 el2ctx->hfgwtr_el2 = 0;
336
337 /* FEAT_AIE */
338 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
339 nAMAIR2_EL1, TRAP);
340 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
341 nMAIR2_EL1, TRAP);
342
343 /* FEAT_S2POE */
344 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
345 nS2POR_EL1, TRAP);
346
347 /* FEAT_S1POE */
348 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
349 nPOR_EL1, TRAP);
350 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
351 nPOR_EL0, TRAP);
352
353 /* FEAT_S1PIE */
354 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
355 nPIR_EL1, TRAP);
356 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
357 nPIRE0_EL1, TRAP);
358
359 /* FEAT_THE */
360 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
361 nRCWMASK_EL1, TRAP);
362
363 /* FEAT_SME */
364 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
365 nTPIDR2_EL0, TRAP);
366 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
367 nSMPRI_EL1, TRAP);
368
369 /* FEAT_GCS */
370 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
371 nGCS_EL1, TRAP);
372 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
373 nGCS_EL0, TRAP);
374
375 /* FEAT_LS64_ACCDATA */
376 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
377 nACCDATA_EL1, TRAP);
378
379 /* FEAT_RASv1p1 */
380 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
381 ERXPFGCDN_EL1, TRAP);
382 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
383 ERXPFGCTL_EL1, TRAP);
384 el2ctx->hfgrtr_el2 |= HFGRTR_EL2_ERXPFGF_EL1_TRAP;
385
386 /* FEAT_RAS */
387 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
388 ERXADDR_EL1, TRAP);
389 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
390 ERXMISCn_EL1, TRAP);
391 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
392 ERXSTATUS_EL1, TRAP);
393 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
394 ERXCTLR_EL1, TRAP);
395 el2ctx->hfgrtr_el2 |= HFGRTR_EL2_ERXFR_EL1_TRAP;
396 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
397 ERRSELR_EL1, TRAP);
398 el2ctx->hfgrtr_el2 |= HFGRTR_EL2_ERRIDR_EL1_TRAP;
399
400 /* GICv3 */
401 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
402 ICC_IGRPENn_EL1, NOTRAP);
403
404 /* FEAT_LOR */
405 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
406 LORSA_EL1, TRAP);
407 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
408 LORN_EL1, TRAP);
409 el2ctx->hfgrtr_el2 |= HFGRTR_EL2_LORID_EL1_TRAP;
410 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
411 LOREA_EL1, TRAP);
412 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
413 LORC_EL1, TRAP);
414
415 /* FEAT_PAuth */
416 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
417 APIBKey, TRAP);
418 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
419 APIAKey, TRAP);
420 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
421 APGAKey, TRAP);
422 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
423 APDBKey, TRAP);
424 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
425 APDAKey, TRAP);
426
427 /* Base architecture */
428 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
429 VBAR_EL1, NOTRAP);
430 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
431 TTBR1_EL1, NOTRAP);
432 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
433 TTBR0_EL1, NOTRAP);
434 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
435 TPIDR_EL0, NOTRAP);
436 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
437 TPIDRRO_EL0, NOTRAP);
438 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
439 TPIDR_EL1, NOTRAP);
440 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
441 TCR_EL1, NOTRAP);
442 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
443 SCXTNUM_EL0, TRAP);
444 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
445 SCXTNUM_EL1, TRAP);
446 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
447 SCTLR_EL1, NOTRAP);
448 el2ctx->hfgrtr_el2 |= HFGRTR_EL2_REVIDR_EL1_NOTRAP;
449 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
450 PAR_EL1, NOTRAP);
451 el2ctx->hfgrtr_el2 |= HFGRTR_EL2_MPIDR_EL1_NOTRAP;
452 el2ctx->hfgrtr_el2 |= HFGRTR_EL2_MIDR_EL1_NOTRAP;
453 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
454 MAIR_EL1, NOTRAP);
455 el2ctx->hfgrtr_el2 |= HFGRTR_EL2_ISR_EL1_NOTRAP;
456 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
457 FAR_EL1, NOTRAP);
458 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
459 ESR_EL1, NOTRAP);
460 el2ctx->hfgrtr_el2 |= HFGRTR_EL2_DCZID_EL0_NOTRAP;
461 el2ctx->hfgrtr_el2 |= HFGRTR_EL2_CTR_EL0_NOTRAP;
462 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
463 CSSELR_EL1, NOTRAP);
464 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
465 CPACR_EL1, NOTRAP);
466 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
467 CONTEXTIDR_EL1, NOTRAP);
468 el2ctx->hfgrtr_el2 |= HFGRTR_EL2_CLIDR_EL1_NOTRAP;
469 el2ctx->hfgrtr_el2 |= HFGRTR_EL2_CCSIDR_EL1_NOTRAP;
470 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
471 AMAIR_EL1, NOTRAP);
472 el2ctx->hfgrtr_el2 |= HFGRTR_EL2_AIDR_EL1_NOTRAP;
473 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
474 AFSR1_EL1, NOTRAP);
475 HFGT_TRAP_FIELDS(hfgrtr_el2, hfgwtr_el2, HFGRTR, HFGWTR,
476 AFSR0_EL1, NOTRAP);
477
478 /*
479 * Traps for instructions
480 */
481
482 /* Enable all TLBI, cache and AT variants */
483 el2ctx->hfgitr_el2 = 0;
484
485 /* FEAT_ATS1A */
486 el2ctx->hfgitr_el2 |=
487 HFGITR_EL2_ATS1E1A_TRAP;
488
489 /* FEAT_SPECRES2 */
490 el2ctx->hfgitr_el2 |=
491 HFGITR_EL2_COSPRCTX_TRAP;
492
493 /* FEAT_GCS */
494 el2ctx->hfgitr_el2 |=
495 HFGITR_EL2_nGCSEPP_TRAP |
496 HFGITR_EL2_nGCSSTR_EL1_TRAP |
497 HFGITR_EL2_nGCSPUSHM_EL1_TRAP;
498
499 /* FEAT_BRBE */
500 el2ctx->hfgitr_el2 |=
501 HFGITR_EL2_nBRBIALL_TRAP |
502 HFGITR_EL2_nBRBINJ_TRAP;
503
504 /* FEAT_SPECRES */
505 el2ctx->hfgitr_el2 |=
506 HFGITR_EL2_CPPRCTX_TRAP |
507 HFGITR_EL2_DVPRCTX_TRAP |
508 HFGITR_EL2_CFPRCTX_TRAP;
509
510 /* FEAT_TLBIRANGE */
511 el2ctx->hfgitr_el2 |=
512 HFGITR_EL2_TLBIRVAALE1_TRAP |
513 HFGITR_EL2_TLBIRVALE1_TRAP |
514 HFGITR_EL2_TLBIRVAAE1_TRAP |
515 HFGITR_EL2_TLBIRVAE1_TRAP |
516 HFGITR_EL2_TLBIRVAALE1IS_TRAP |
517 HFGITR_EL2_TLBIRVALE1IS_TRAP |
518 HFGITR_EL2_TLBIRVAAE1IS_TRAP |
519 HFGITR_EL2_TLBIRVAE1IS_TRAP;
520
521 /* FEAT_TLBIRANGE && FEAT_TLBIOS */
522 el2ctx->hfgitr_el2 |=
523 HFGITR_EL2_TLBIRVAALE1OS_TRAP |
524 HFGITR_EL2_TLBIRVALE1OS_TRAP |
525 HFGITR_EL2_TLBIRVAAE1OS_TRAP |
526 HFGITR_EL2_TLBIRVAE1OS_TRAP;
527
528 /* FEAT_TLBIOS */
529 el2ctx->hfgitr_el2 |=
530 HFGITR_EL2_TLBIVAALE1OS_TRAP |
531 HFGITR_EL2_TLBIVALE1OS_TRAP |
532 HFGITR_EL2_TLBIVAAE1OS_TRAP |
533 HFGITR_EL2_TLBIASIDE1OS_TRAP |
534 HFGITR_EL2_TLBIVAE1OS_TRAP |
535 HFGITR_EL2_TLBIVMALLE1OS_TRAP;
536
537 /* FEAT_PAN2 */
538 el2ctx->hfgitr_el2 |=
539 HFGITR_EL2_ATS1E1WP_TRAP |
540 HFGITR_EL2_ATS1E1RP_TRAP;
541
542 /* FEAT_DPB2 */
543 el2ctx->hfgitr_el2 |=
544 HFGITR_EL2_DCCVADP_TRAP;
545
546 /* Base architecture */
547 el2ctx->hfgitr_el2 |=
548 HFGITR_EL2_DCCVAC_NOTRAP |
549 HFGITR_EL2_SVC_EL1_NOTRAP |
550 HFGITR_EL2_SVC_EL0_NOTRAP |
551 HFGITR_EL2_ERET_NOTRAP;
552
553 el2ctx->hfgitr_el2 |=
554 HFGITR_EL2_TLBIVAALE1_NOTRAP |
555 HFGITR_EL2_TLBIVALE1_NOTRAP |
556 HFGITR_EL2_TLBIVAAE1_NOTRAP |
557 HFGITR_EL2_TLBIASIDE1_NOTRAP |
558 HFGITR_EL2_TLBIVAE1_NOTRAP |
559 HFGITR_EL2_TLBIVMALLE1_NOTRAP |
560 HFGITR_EL2_TLBIVAALE1IS_NOTRAP |
561 HFGITR_EL2_TLBIVALE1IS_NOTRAP |
562 HFGITR_EL2_TLBIVAAE1IS_NOTRAP |
563 HFGITR_EL2_TLBIASIDE1IS_NOTRAP |
564 HFGITR_EL2_TLBIVAE1IS_NOTRAP |
565 HFGITR_EL2_TLBIVMALLE1IS_NOTRAP;
566
567 el2ctx->hfgitr_el2 |=
568 HFGITR_EL2_ATS1E0W_NOTRAP |
569 HFGITR_EL2_ATS1E0R_NOTRAP |
570 HFGITR_EL2_ATS1E1W_NOTRAP |
571 HFGITR_EL2_ATS1E1R_NOTRAP |
572 HFGITR_EL2_DCZVA_NOTRAP |
573 HFGITR_EL2_DCCIVAC_NOTRAP |
574 HFGITR_EL2_DCCVAP_NOTRAP |
575 HFGITR_EL2_DCCVAU_NOTRAP |
576 HFGITR_EL2_DCCISW_NOTRAP |
577 HFGITR_EL2_DCCSW_NOTRAP |
578 HFGITR_EL2_DCISW_NOTRAP |
579 HFGITR_EL2_DCIVAC_NOTRAP |
580 HFGITR_EL2_ICIVAU_NOTRAP |
581 HFGITR_EL2_ICIALLU_NOTRAP |
582 HFGITR_EL2_ICIALLUIS_NOTRAP;
583
584 }
585
586 /* FEAT_FGT2 traps */
587 if ((el2ctx->hyp->feats & HYP_FEAT_FGT2) != 0) {
588 /* Trap everything here until we support the feature */
589 el2ctx->hdfgrtr2_el2 = 0;
590 el2ctx->hdfgwtr2_el2 = 0;
591 el2ctx->hfgitr2_el2 = 0;
592 el2ctx->hfgrtr2_el2 = 0;
593 el2ctx->hfgwtr2_el2 = 0;
594 }
595 }
596