1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Texas Instruments N-Port Ethernet Switch Address Lookup Engine
4 *
5 * Copyright (C) 2012 Texas Instruments
6 *
7 */
8 #include <linux/bitmap.h>
9 #include <linux/if_vlan.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/seq_file.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/stat.h>
19 #include <linux/sysfs.h>
20 #include <linux/etherdevice.h>
21
22 #include "cpsw_ale.h"
23
24 #define BITMASK(bits) (BIT(bits) - 1)
25
26 /* ALE Registers */
27 #define ALE_IDVER 0x00
28 #define ALE_STATUS 0x04
29 #define ALE_CONTROL 0x08
30 #define ALE_PRESCALE 0x10
31 #define ALE_AGING_TIMER 0x14
32 #define ALE_UNKNOWNVLAN 0x18
33 #define ALE_TABLE_CONTROL 0x20
34 #define ALE_TABLE 0x34
35 #define ALE_PORTCTL 0x40
36
37 /* ALE NetCP NU switch specific Registers */
38 #define ALE_UNKNOWNVLAN_MEMBER 0x90
39 #define ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD 0x94
40 #define ALE_UNKNOWNVLAN_REG_MCAST_FLOOD 0x98
41 #define ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS 0x9C
42 #define ALE_VLAN_MASK_MUX(reg) (0xc0 + (0x4 * (reg)))
43
44 #define ALE_POLICER_PORT_OUI 0x100
45 #define ALE_POLICER_DA_SA 0x104
46 #define ALE_POLICER_VLAN 0x108
47 #define ALE_POLICER_ETHERTYPE_IPSA 0x10c
48 #define ALE_POLICER_IPDA 0x110
49 #define ALE_POLICER_PIR 0x118
50 #define ALE_POLICER_CIR 0x11c
51 #define ALE_POLICER_TBL_CTL 0x120
52 #define ALE_POLICER_CTL 0x124
53 #define ALE_POLICER_TEST_CTL 0x128
54 #define ALE_POLICER_HIT_STATUS 0x12c
55 #define ALE_THREAD_DEF 0x134
56 #define ALE_THREAD_CTL 0x138
57 #define ALE_THREAD_VAL 0x13c
58
59 #define ALE_POLICER_TBL_WRITE_ENABLE BIT(31)
60 #define ALE_POLICER_TBL_INDEX_MASK GENMASK(4, 0)
61
62 #define AM65_CPSW_ALE_THREAD_DEF_REG 0x134
63
64 /* ALE_AGING_TIMER */
65 #define ALE_AGING_TIMER_MASK GENMASK(23, 0)
66
67 #define ALE_RATE_LIMIT_MIN_PPS 1000
68
69 /**
70 * struct ale_entry_fld - The ALE tbl entry field description
71 * @start_bit: field start bit
72 * @num_bits: field bit length
73 * @flags: field flags
74 */
75 struct ale_entry_fld {
76 u8 start_bit;
77 u8 num_bits;
78 u8 flags;
79 };
80
81 enum {
82 CPSW_ALE_F_STATUS_REG = BIT(0), /* Status register present */
83 CPSW_ALE_F_HW_AUTOAGING = BIT(1), /* HW auto aging */
84
85 CPSW_ALE_F_COUNT
86 };
87
88 /**
89 * struct cpsw_ale_dev_id - The ALE version/SoC specific configuration
90 * @dev_id: ALE version/SoC id
91 * @features: features supported by ALE
92 * @tbl_entries: number of ALE entries
93 * @reg_fields: pointer to array of register field configuration
94 * @num_fields: number of fields in the reg_fields array
95 * @nu_switch_ale: NU Switch ALE
96 * @vlan_entry_tbl: ALE vlan entry fields description tbl
97 */
98 struct cpsw_ale_dev_id {
99 const char *dev_id;
100 u32 features;
101 u32 tbl_entries;
102 const struct reg_field *reg_fields;
103 int num_fields;
104 bool nu_switch_ale;
105 const struct ale_entry_fld *vlan_entry_tbl;
106 };
107
108 #define ALE_TABLE_WRITE BIT(31)
109
110 #define ALE_TYPE_FREE 0
111 #define ALE_TYPE_ADDR 1
112 #define ALE_TYPE_VLAN 2
113 #define ALE_TYPE_VLAN_ADDR 3
114
115 #define ALE_UCAST_PERSISTANT 0
116 #define ALE_UCAST_UNTOUCHED 1
117 #define ALE_UCAST_OUI 2
118 #define ALE_UCAST_TOUCHED 3
119
120 #define ALE_TABLE_SIZE_MULTIPLIER 1024
121 #define ALE_POLICER_SIZE_MULTIPLIER 8
122
cpsw_ale_get_field(u32 * ale_entry,u32 start,u32 bits)123 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
124 {
125 int idx, idx2, index;
126 u32 hi_val = 0;
127
128 idx = start / 32;
129 idx2 = (start + bits - 1) / 32;
130 /* Check if bits to be fetched exceed a word */
131 if (idx != idx2) {
132 index = 2 - idx2; /* flip */
133 hi_val = ale_entry[index] << ((idx2 * 32) - start);
134 }
135 start -= idx * 32;
136 idx = 2 - idx; /* flip */
137 return (hi_val + (ale_entry[idx] >> start)) & BITMASK(bits);
138 }
139
cpsw_ale_set_field(u32 * ale_entry,u32 start,u32 bits,u32 value)140 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
141 u32 value)
142 {
143 int idx, idx2, index;
144
145 value &= BITMASK(bits);
146 idx = start / 32;
147 idx2 = (start + bits - 1) / 32;
148 /* Check if bits to be set exceed a word */
149 if (idx != idx2) {
150 index = 2 - idx2; /* flip */
151 ale_entry[index] &= ~(BITMASK(bits + start - (idx2 * 32)));
152 ale_entry[index] |= (value >> ((idx2 * 32) - start));
153 }
154 start -= idx * 32;
155 idx = 2 - idx; /* flip */
156 ale_entry[idx] &= ~(BITMASK(bits) << start);
157 ale_entry[idx] |= (value << start);
158 }
159
160 #define DEFINE_ALE_FIELD_GET(name, start, bits) \
161 static inline int cpsw_ale_get_##name(u32 *ale_entry) \
162 { \
163 return cpsw_ale_get_field(ale_entry, start, bits); \
164 }
165
166 #define DEFINE_ALE_FIELD_SET(name, start, bits) \
167 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
168 { \
169 cpsw_ale_set_field(ale_entry, start, bits, value); \
170 }
171
172 #define DEFINE_ALE_FIELD(name, start, bits) \
173 DEFINE_ALE_FIELD_GET(name, start, bits) \
174 DEFINE_ALE_FIELD_SET(name, start, bits)
175
176 #define DEFINE_ALE_FIELD1_GET(name, start) \
177 static inline int cpsw_ale_get_##name(u32 *ale_entry, u32 bits) \
178 { \
179 return cpsw_ale_get_field(ale_entry, start, bits); \
180 }
181
182 #define DEFINE_ALE_FIELD1_SET(name, start) \
183 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value, \
184 u32 bits) \
185 { \
186 cpsw_ale_set_field(ale_entry, start, bits, value); \
187 }
188
189 #define DEFINE_ALE_FIELD1(name, start) \
190 DEFINE_ALE_FIELD1_GET(name, start) \
191 DEFINE_ALE_FIELD1_SET(name, start)
192
193 enum {
194 ALE_ENT_VID_MEMBER_LIST = 0,
195 ALE_ENT_VID_UNREG_MCAST_MSK,
196 ALE_ENT_VID_REG_MCAST_MSK,
197 ALE_ENT_VID_FORCE_UNTAGGED_MSK,
198 ALE_ENT_VID_UNREG_MCAST_IDX,
199 ALE_ENT_VID_REG_MCAST_IDX,
200 ALE_ENT_VID_LAST,
201 };
202
203 #define ALE_FLD_ALLOWED BIT(0)
204 #define ALE_FLD_SIZE_PORT_MASK_BITS BIT(1)
205 #define ALE_FLD_SIZE_PORT_NUM_BITS BIT(2)
206
207 #define ALE_ENTRY_FLD(id, start, bits) \
208 [id] = { \
209 .start_bit = start, \
210 .num_bits = bits, \
211 .flags = ALE_FLD_ALLOWED, \
212 }
213
214 #define ALE_ENTRY_FLD_DYN_MSK_SIZE(id, start) \
215 [id] = { \
216 .start_bit = start, \
217 .num_bits = 0, \
218 .flags = ALE_FLD_ALLOWED | \
219 ALE_FLD_SIZE_PORT_MASK_BITS, \
220 }
221
222 /* dm814x, am3/am4/am5, k2hk */
223 static const struct ale_entry_fld vlan_entry_cpsw[ALE_ENT_VID_LAST] = {
224 ALE_ENTRY_FLD(ALE_ENT_VID_MEMBER_LIST, 0, 3),
225 ALE_ENTRY_FLD(ALE_ENT_VID_UNREG_MCAST_MSK, 8, 3),
226 ALE_ENTRY_FLD(ALE_ENT_VID_REG_MCAST_MSK, 16, 3),
227 ALE_ENTRY_FLD(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24, 3),
228 };
229
230 /* k2e/k2l, k3 am65/j721e cpsw2g */
231 static const struct ale_entry_fld vlan_entry_nu[ALE_ENT_VID_LAST] = {
232 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_MEMBER_LIST, 0),
233 ALE_ENTRY_FLD(ALE_ENT_VID_UNREG_MCAST_IDX, 20, 3),
234 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24),
235 ALE_ENTRY_FLD(ALE_ENT_VID_REG_MCAST_IDX, 44, 3),
236 };
237
238 /* K3 j721e/j7200 cpsw9g/5g, am64x cpsw3g */
239 static const struct ale_entry_fld vlan_entry_k3_cpswxg[] = {
240 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_MEMBER_LIST, 0),
241 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_UNREG_MCAST_MSK, 12),
242 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_FORCE_UNTAGGED_MSK, 24),
243 ALE_ENTRY_FLD_DYN_MSK_SIZE(ALE_ENT_VID_REG_MCAST_MSK, 36),
244 };
245
246 DEFINE_ALE_FIELD(entry_type, 60, 2)
247 DEFINE_ALE_FIELD(vlan_id, 48, 12)
248 DEFINE_ALE_FIELD_SET(mcast_state, 62, 2)
249 DEFINE_ALE_FIELD1(port_mask, 66)
250 DEFINE_ALE_FIELD(super, 65, 1)
251 DEFINE_ALE_FIELD(ucast_type, 62, 2)
252 DEFINE_ALE_FIELD1_SET(port_num, 66)
253 DEFINE_ALE_FIELD_SET(blocked, 65, 1)
254 DEFINE_ALE_FIELD_SET(secure, 64, 1)
255 DEFINE_ALE_FIELD_GET(mcast, 40, 1)
256
257 #define NU_VLAN_UNREG_MCAST_IDX 1
258
cpsw_ale_entry_get_fld(struct cpsw_ale * ale,u32 * ale_entry,const struct ale_entry_fld * entry_tbl,int fld_id)259 static int cpsw_ale_entry_get_fld(struct cpsw_ale *ale,
260 u32 *ale_entry,
261 const struct ale_entry_fld *entry_tbl,
262 int fld_id)
263 {
264 const struct ale_entry_fld *entry_fld;
265 u32 bits;
266
267 if (!ale || !ale_entry)
268 return -EINVAL;
269
270 entry_fld = &entry_tbl[fld_id];
271 if (!(entry_fld->flags & ALE_FLD_ALLOWED)) {
272 dev_err(ale->params.dev, "get: wrong ale fld id %d\n", fld_id);
273 return -ENOENT;
274 }
275
276 bits = entry_fld->num_bits;
277 if (entry_fld->flags & ALE_FLD_SIZE_PORT_MASK_BITS)
278 bits = ale->port_mask_bits;
279
280 return cpsw_ale_get_field(ale_entry, entry_fld->start_bit, bits);
281 }
282
cpsw_ale_entry_set_fld(struct cpsw_ale * ale,u32 * ale_entry,const struct ale_entry_fld * entry_tbl,int fld_id,u32 value)283 static void cpsw_ale_entry_set_fld(struct cpsw_ale *ale,
284 u32 *ale_entry,
285 const struct ale_entry_fld *entry_tbl,
286 int fld_id,
287 u32 value)
288 {
289 const struct ale_entry_fld *entry_fld;
290 u32 bits;
291
292 if (!ale || !ale_entry)
293 return;
294
295 entry_fld = &entry_tbl[fld_id];
296 if (!(entry_fld->flags & ALE_FLD_ALLOWED)) {
297 dev_err(ale->params.dev, "set: wrong ale fld id %d\n", fld_id);
298 return;
299 }
300
301 bits = entry_fld->num_bits;
302 if (entry_fld->flags & ALE_FLD_SIZE_PORT_MASK_BITS)
303 bits = ale->port_mask_bits;
304
305 cpsw_ale_set_field(ale_entry, entry_fld->start_bit, bits, value);
306 }
307
cpsw_ale_vlan_get_fld(struct cpsw_ale * ale,u32 * ale_entry,int fld_id)308 static int cpsw_ale_vlan_get_fld(struct cpsw_ale *ale,
309 u32 *ale_entry,
310 int fld_id)
311 {
312 return cpsw_ale_entry_get_fld(ale, ale_entry,
313 ale->vlan_entry_tbl, fld_id);
314 }
315
cpsw_ale_vlan_set_fld(struct cpsw_ale * ale,u32 * ale_entry,int fld_id,u32 value)316 static void cpsw_ale_vlan_set_fld(struct cpsw_ale *ale,
317 u32 *ale_entry,
318 int fld_id,
319 u32 value)
320 {
321 cpsw_ale_entry_set_fld(ale, ale_entry,
322 ale->vlan_entry_tbl, fld_id, value);
323 }
324
325 /* The MAC address field in the ALE entry cannot be macroized as above */
cpsw_ale_get_addr(u32 * ale_entry,u8 * addr)326 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
327 {
328 int i;
329
330 for (i = 0; i < 6; i++)
331 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
332 }
333
cpsw_ale_set_addr(u32 * ale_entry,const u8 * addr)334 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
335 {
336 int i;
337
338 for (i = 0; i < 6; i++)
339 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
340 }
341
cpsw_ale_read(struct cpsw_ale * ale,int idx,u32 * ale_entry)342 static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry)
343 {
344 int i;
345
346 WARN_ON(idx > ale->params.ale_entries);
347
348 writel_relaxed(idx, ale->params.ale_regs + ALE_TABLE_CONTROL);
349
350 for (i = 0; i < ALE_ENTRY_WORDS; i++)
351 ale_entry[i] = readl_relaxed(ale->params.ale_regs +
352 ALE_TABLE + 4 * i);
353
354 return idx;
355 }
356
cpsw_ale_write(struct cpsw_ale * ale,int idx,u32 * ale_entry)357 static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry)
358 {
359 int i;
360
361 WARN_ON(idx > ale->params.ale_entries);
362
363 for (i = 0; i < ALE_ENTRY_WORDS; i++)
364 writel_relaxed(ale_entry[i], ale->params.ale_regs +
365 ALE_TABLE + 4 * i);
366
367 writel_relaxed(idx | ALE_TABLE_WRITE, ale->params.ale_regs +
368 ALE_TABLE_CONTROL);
369
370 return idx;
371 }
372
cpsw_ale_match_addr(struct cpsw_ale * ale,const u8 * addr,u16 vid)373 static int cpsw_ale_match_addr(struct cpsw_ale *ale, const u8 *addr, u16 vid)
374 {
375 u32 ale_entry[ALE_ENTRY_WORDS];
376 int type, idx;
377
378 for (idx = 0; idx < ale->params.ale_entries; idx++) {
379 u8 entry_addr[6];
380
381 cpsw_ale_read(ale, idx, ale_entry);
382 type = cpsw_ale_get_entry_type(ale_entry);
383 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
384 continue;
385 if (cpsw_ale_get_vlan_id(ale_entry) != vid)
386 continue;
387 cpsw_ale_get_addr(ale_entry, entry_addr);
388 if (ether_addr_equal(entry_addr, addr))
389 return idx;
390 }
391 return -ENOENT;
392 }
393
cpsw_ale_match_vlan(struct cpsw_ale * ale,u16 vid)394 static int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid)
395 {
396 u32 ale_entry[ALE_ENTRY_WORDS];
397 int type, idx;
398
399 for (idx = 0; idx < ale->params.ale_entries; idx++) {
400 cpsw_ale_read(ale, idx, ale_entry);
401 type = cpsw_ale_get_entry_type(ale_entry);
402 if (type != ALE_TYPE_VLAN)
403 continue;
404 if (cpsw_ale_get_vlan_id(ale_entry) == vid)
405 return idx;
406 }
407 return -ENOENT;
408 }
409
cpsw_ale_match_free(struct cpsw_ale * ale)410 static int cpsw_ale_match_free(struct cpsw_ale *ale)
411 {
412 u32 ale_entry[ALE_ENTRY_WORDS];
413 int type, idx;
414
415 for (idx = 0; idx < ale->params.ale_entries; idx++) {
416 cpsw_ale_read(ale, idx, ale_entry);
417 type = cpsw_ale_get_entry_type(ale_entry);
418 if (type == ALE_TYPE_FREE)
419 return idx;
420 }
421 return -ENOENT;
422 }
423
cpsw_ale_find_ageable(struct cpsw_ale * ale)424 static int cpsw_ale_find_ageable(struct cpsw_ale *ale)
425 {
426 u32 ale_entry[ALE_ENTRY_WORDS];
427 int type, idx;
428
429 for (idx = 0; idx < ale->params.ale_entries; idx++) {
430 cpsw_ale_read(ale, idx, ale_entry);
431 type = cpsw_ale_get_entry_type(ale_entry);
432 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
433 continue;
434 if (cpsw_ale_get_mcast(ale_entry))
435 continue;
436 type = cpsw_ale_get_ucast_type(ale_entry);
437 if (type != ALE_UCAST_PERSISTANT &&
438 type != ALE_UCAST_OUI)
439 return idx;
440 }
441 return -ENOENT;
442 }
443
cpsw_ale_flush_mcast(struct cpsw_ale * ale,u32 * ale_entry,int port_mask)444 static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry,
445 int port_mask)
446 {
447 int mask;
448
449 mask = cpsw_ale_get_port_mask(ale_entry,
450 ale->port_mask_bits);
451 if ((mask & port_mask) == 0)
452 return; /* ports dont intersect, not interested */
453 mask &= (~port_mask | ALE_PORT_HOST);
454
455 if (mask == 0x0 || mask == ALE_PORT_HOST)
456 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
457 else
458 cpsw_ale_set_port_mask(ale_entry, mask,
459 ale->port_mask_bits);
460 }
461
cpsw_ale_flush_multicast(struct cpsw_ale * ale,int port_mask,int vid)462 int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid)
463 {
464 u32 ale_entry[ALE_ENTRY_WORDS];
465 int ret, idx;
466
467 for (idx = 0; idx < ale->params.ale_entries; idx++) {
468 cpsw_ale_read(ale, idx, ale_entry);
469 ret = cpsw_ale_get_entry_type(ale_entry);
470 if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR)
471 continue;
472
473 /* if vid passed is -1 then remove all multicast entry from
474 * the table irrespective of vlan id, if a valid vlan id is
475 * passed then remove only multicast added to that vlan id.
476 * if vlan id doesn't match then move on to next entry.
477 */
478 if (vid != -1 && cpsw_ale_get_vlan_id(ale_entry) != vid)
479 continue;
480
481 if (cpsw_ale_get_mcast(ale_entry)) {
482 u8 addr[6];
483
484 if (cpsw_ale_get_super(ale_entry))
485 continue;
486
487 cpsw_ale_get_addr(ale_entry, addr);
488 if (!is_broadcast_ether_addr(addr))
489 cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
490 }
491
492 cpsw_ale_write(ale, idx, ale_entry);
493 }
494 return 0;
495 }
496 EXPORT_SYMBOL_GPL(cpsw_ale_flush_multicast);
497
cpsw_ale_set_vlan_entry_type(u32 * ale_entry,int flags,u16 vid)498 static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry,
499 int flags, u16 vid)
500 {
501 if (flags & ALE_VLAN) {
502 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR);
503 cpsw_ale_set_vlan_id(ale_entry, vid);
504 } else {
505 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
506 }
507 }
508
cpsw_ale_add_ucast(struct cpsw_ale * ale,const u8 * addr,int port,int flags,u16 vid)509 int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
510 int flags, u16 vid)
511 {
512 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
513 int idx;
514
515 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid);
516
517 cpsw_ale_set_addr(ale_entry, addr);
518 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
519 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
520 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
521 cpsw_ale_set_port_num(ale_entry, port, ale->port_num_bits);
522
523 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
524 if (idx < 0)
525 idx = cpsw_ale_match_free(ale);
526 if (idx < 0)
527 idx = cpsw_ale_find_ageable(ale);
528 if (idx < 0)
529 return -ENOMEM;
530
531 cpsw_ale_write(ale, idx, ale_entry);
532 return 0;
533 }
534 EXPORT_SYMBOL_GPL(cpsw_ale_add_ucast);
535
cpsw_ale_del_ucast(struct cpsw_ale * ale,const u8 * addr,int port,int flags,u16 vid)536 int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
537 int flags, u16 vid)
538 {
539 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
540 int idx;
541
542 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
543 if (idx < 0)
544 return -ENOENT;
545
546 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
547 cpsw_ale_write(ale, idx, ale_entry);
548 return 0;
549 }
550 EXPORT_SYMBOL_GPL(cpsw_ale_del_ucast);
551
cpsw_ale_add_mcast(struct cpsw_ale * ale,const u8 * addr,int port_mask,int flags,u16 vid,int mcast_state)552 int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
553 int flags, u16 vid, int mcast_state)
554 {
555 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
556 int idx, mask;
557
558 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
559 if (idx >= 0)
560 cpsw_ale_read(ale, idx, ale_entry);
561
562 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid);
563
564 cpsw_ale_set_addr(ale_entry, addr);
565 cpsw_ale_set_super(ale_entry, (flags & ALE_SUPER) ? 1 : 0);
566 cpsw_ale_set_mcast_state(ale_entry, mcast_state);
567
568 mask = cpsw_ale_get_port_mask(ale_entry,
569 ale->port_mask_bits);
570 port_mask |= mask;
571 cpsw_ale_set_port_mask(ale_entry, port_mask,
572 ale->port_mask_bits);
573
574 if (idx < 0)
575 idx = cpsw_ale_match_free(ale);
576 if (idx < 0)
577 idx = cpsw_ale_find_ageable(ale);
578 if (idx < 0)
579 return -ENOMEM;
580
581 cpsw_ale_write(ale, idx, ale_entry);
582 return 0;
583 }
584 EXPORT_SYMBOL_GPL(cpsw_ale_add_mcast);
585
cpsw_ale_del_mcast(struct cpsw_ale * ale,const u8 * addr,int port_mask,int flags,u16 vid)586 int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
587 int flags, u16 vid)
588 {
589 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
590 int mcast_members = 0;
591 int idx;
592
593 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
594 if (idx < 0)
595 return -ENOENT;
596
597 cpsw_ale_read(ale, idx, ale_entry);
598
599 if (port_mask) {
600 mcast_members = cpsw_ale_get_port_mask(ale_entry,
601 ale->port_mask_bits);
602 mcast_members &= ~port_mask;
603 }
604
605 if (mcast_members)
606 cpsw_ale_set_port_mask(ale_entry, mcast_members,
607 ale->port_mask_bits);
608 else
609 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
610
611 cpsw_ale_write(ale, idx, ale_entry);
612 return 0;
613 }
614 EXPORT_SYMBOL_GPL(cpsw_ale_del_mcast);
615
616 /* ALE NetCP NU switch specific vlan functions */
cpsw_ale_set_vlan_mcast(struct cpsw_ale * ale,u32 * ale_entry,int reg_mcast,int unreg_mcast)617 static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry,
618 int reg_mcast, int unreg_mcast)
619 {
620 int idx;
621
622 /* Set VLAN registered multicast flood mask */
623 idx = cpsw_ale_vlan_get_fld(ale, ale_entry,
624 ALE_ENT_VID_REG_MCAST_IDX);
625 writel(reg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
626
627 /* Set VLAN unregistered multicast flood mask */
628 idx = cpsw_ale_vlan_get_fld(ale, ale_entry,
629 ALE_ENT_VID_UNREG_MCAST_IDX);
630 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
631 }
632
cpsw_ale_set_vlan_untag(struct cpsw_ale * ale,u32 * ale_entry,u16 vid,int untag_mask)633 static void cpsw_ale_set_vlan_untag(struct cpsw_ale *ale, u32 *ale_entry,
634 u16 vid, int untag_mask)
635 {
636 cpsw_ale_vlan_set_fld(ale, ale_entry,
637 ALE_ENT_VID_FORCE_UNTAGGED_MSK,
638 untag_mask);
639 if (untag_mask & ALE_PORT_HOST)
640 bitmap_set(ale->p0_untag_vid_mask, vid, 1);
641 else
642 bitmap_clear(ale->p0_untag_vid_mask, vid, 1);
643 }
644
cpsw_ale_add_vlan(struct cpsw_ale * ale,u16 vid,int port_mask,int untag,int reg_mcast,int unreg_mcast)645 int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag,
646 int reg_mcast, int unreg_mcast)
647 {
648 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
649 int idx;
650
651 idx = cpsw_ale_match_vlan(ale, vid);
652 if (idx >= 0)
653 cpsw_ale_read(ale, idx, ale_entry);
654
655 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN);
656 cpsw_ale_set_vlan_id(ale_entry, vid);
657 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag);
658
659 if (!ale->params.nu_switch_ale) {
660 cpsw_ale_vlan_set_fld(ale, ale_entry,
661 ALE_ENT_VID_REG_MCAST_MSK, reg_mcast);
662 cpsw_ale_vlan_set_fld(ale, ale_entry,
663 ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast);
664 } else {
665 cpsw_ale_vlan_set_fld(ale, ale_entry,
666 ALE_ENT_VID_UNREG_MCAST_IDX,
667 NU_VLAN_UNREG_MCAST_IDX);
668 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, unreg_mcast);
669 }
670
671 cpsw_ale_vlan_set_fld(ale, ale_entry,
672 ALE_ENT_VID_MEMBER_LIST, port_mask);
673
674 if (idx < 0)
675 idx = cpsw_ale_match_free(ale);
676 if (idx < 0)
677 idx = cpsw_ale_find_ageable(ale);
678 if (idx < 0)
679 return -ENOMEM;
680
681 cpsw_ale_write(ale, idx, ale_entry);
682 return 0;
683 }
684 EXPORT_SYMBOL_GPL(cpsw_ale_add_vlan);
685
cpsw_ale_vlan_del_modify_int(struct cpsw_ale * ale,u32 * ale_entry,u16 vid,int port_mask)686 static void cpsw_ale_vlan_del_modify_int(struct cpsw_ale *ale, u32 *ale_entry,
687 u16 vid, int port_mask)
688 {
689 int reg_mcast, unreg_mcast;
690 int members, untag;
691
692 members = cpsw_ale_vlan_get_fld(ale, ale_entry,
693 ALE_ENT_VID_MEMBER_LIST);
694 members &= ~port_mask;
695 if (!members) {
696 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0);
697 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
698 return;
699 }
700
701 untag = cpsw_ale_vlan_get_fld(ale, ale_entry,
702 ALE_ENT_VID_FORCE_UNTAGGED_MSK);
703 reg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry,
704 ALE_ENT_VID_REG_MCAST_MSK);
705 unreg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry,
706 ALE_ENT_VID_UNREG_MCAST_MSK);
707 untag &= members;
708 reg_mcast &= members;
709 unreg_mcast &= members;
710
711 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag);
712
713 if (!ale->params.nu_switch_ale) {
714 cpsw_ale_vlan_set_fld(ale, ale_entry,
715 ALE_ENT_VID_REG_MCAST_MSK, reg_mcast);
716 cpsw_ale_vlan_set_fld(ale, ale_entry,
717 ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast);
718 } else {
719 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast,
720 unreg_mcast);
721 }
722 cpsw_ale_vlan_set_fld(ale, ale_entry,
723 ALE_ENT_VID_MEMBER_LIST, members);
724 }
725
cpsw_ale_vlan_del_modify(struct cpsw_ale * ale,u16 vid,int port_mask)726 int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask)
727 {
728 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
729 int idx;
730
731 idx = cpsw_ale_match_vlan(ale, vid);
732 if (idx < 0)
733 return -ENOENT;
734
735 cpsw_ale_read(ale, idx, ale_entry);
736
737 cpsw_ale_vlan_del_modify_int(ale, ale_entry, vid, port_mask);
738 cpsw_ale_write(ale, idx, ale_entry);
739
740 return 0;
741 }
742 EXPORT_SYMBOL_GPL(cpsw_ale_vlan_del_modify);
743
cpsw_ale_del_vlan(struct cpsw_ale * ale,u16 vid,int port_mask)744 int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask)
745 {
746 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
747 int members, idx;
748
749 idx = cpsw_ale_match_vlan(ale, vid);
750 if (idx < 0)
751 return -ENOENT;
752
753 cpsw_ale_read(ale, idx, ale_entry);
754
755 /* if !port_mask - force remove VLAN (legacy).
756 * Check if there are other VLAN members ports
757 * if no - remove VLAN.
758 * if yes it means same VLAN was added to >1 port in multi port mode, so
759 * remove port_mask ports from VLAN ALE entry excluding Host port.
760 */
761 members = cpsw_ale_vlan_get_fld(ale, ale_entry, ALE_ENT_VID_MEMBER_LIST);
762 members &= ~port_mask;
763
764 if (!port_mask || !members) {
765 /* last port or force remove - remove VLAN */
766 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0);
767 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
768 } else {
769 port_mask &= ~ALE_PORT_HOST;
770 cpsw_ale_vlan_del_modify_int(ale, ale_entry, vid, port_mask);
771 }
772
773 cpsw_ale_write(ale, idx, ale_entry);
774
775 return 0;
776 }
777 EXPORT_SYMBOL_GPL(cpsw_ale_del_vlan);
778
cpsw_ale_vlan_add_modify(struct cpsw_ale * ale,u16 vid,int port_mask,int untag_mask,int reg_mask,int unreg_mask)779 int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask,
780 int untag_mask, int reg_mask, int unreg_mask)
781 {
782 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
783 int reg_mcast_members, unreg_mcast_members;
784 int vlan_members, untag_members;
785 int idx, ret = 0;
786
787 idx = cpsw_ale_match_vlan(ale, vid);
788 if (idx >= 0)
789 cpsw_ale_read(ale, idx, ale_entry);
790
791 vlan_members = cpsw_ale_vlan_get_fld(ale, ale_entry,
792 ALE_ENT_VID_MEMBER_LIST);
793 reg_mcast_members = cpsw_ale_vlan_get_fld(ale, ale_entry,
794 ALE_ENT_VID_REG_MCAST_MSK);
795 unreg_mcast_members =
796 cpsw_ale_vlan_get_fld(ale, ale_entry,
797 ALE_ENT_VID_UNREG_MCAST_MSK);
798 untag_members = cpsw_ale_vlan_get_fld(ale, ale_entry,
799 ALE_ENT_VID_FORCE_UNTAGGED_MSK);
800
801 vlan_members |= port_mask;
802 untag_members = (untag_members & ~port_mask) | untag_mask;
803 reg_mcast_members = (reg_mcast_members & ~port_mask) | reg_mask;
804 unreg_mcast_members = (unreg_mcast_members & ~port_mask) | unreg_mask;
805
806 ret = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members,
807 reg_mcast_members, unreg_mcast_members);
808 if (ret) {
809 dev_err(ale->params.dev, "Unable to add vlan\n");
810 return ret;
811 }
812 dev_dbg(ale->params.dev, "port mask 0x%x untag 0x%x\n", vlan_members,
813 untag_mask);
814
815 return ret;
816 }
817 EXPORT_SYMBOL_GPL(cpsw_ale_vlan_add_modify);
818
cpsw_ale_set_unreg_mcast(struct cpsw_ale * ale,int unreg_mcast_mask,bool add)819 void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask,
820 bool add)
821 {
822 u32 ale_entry[ALE_ENTRY_WORDS];
823 int unreg_members = 0;
824 int type, idx;
825
826 for (idx = 0; idx < ale->params.ale_entries; idx++) {
827 cpsw_ale_read(ale, idx, ale_entry);
828 type = cpsw_ale_get_entry_type(ale_entry);
829 if (type != ALE_TYPE_VLAN)
830 continue;
831
832 unreg_members =
833 cpsw_ale_vlan_get_fld(ale, ale_entry,
834 ALE_ENT_VID_UNREG_MCAST_MSK);
835 if (add)
836 unreg_members |= unreg_mcast_mask;
837 else
838 unreg_members &= ~unreg_mcast_mask;
839 cpsw_ale_vlan_set_fld(ale, ale_entry,
840 ALE_ENT_VID_UNREG_MCAST_MSK,
841 unreg_members);
842 cpsw_ale_write(ale, idx, ale_entry);
843 }
844 }
845 EXPORT_SYMBOL_GPL(cpsw_ale_set_unreg_mcast);
846
cpsw_ale_vlan_set_unreg_mcast(struct cpsw_ale * ale,u32 * ale_entry,int allmulti)847 static void cpsw_ale_vlan_set_unreg_mcast(struct cpsw_ale *ale, u32 *ale_entry,
848 int allmulti)
849 {
850 int unreg_mcast;
851
852 unreg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry,
853 ALE_ENT_VID_UNREG_MCAST_MSK);
854 if (allmulti)
855 unreg_mcast |= ALE_PORT_HOST;
856 else
857 unreg_mcast &= ~ALE_PORT_HOST;
858
859 cpsw_ale_vlan_set_fld(ale, ale_entry,
860 ALE_ENT_VID_UNREG_MCAST_MSK, unreg_mcast);
861 }
862
863 static void
cpsw_ale_vlan_set_unreg_mcast_idx(struct cpsw_ale * ale,u32 * ale_entry,int allmulti)864 cpsw_ale_vlan_set_unreg_mcast_idx(struct cpsw_ale *ale, u32 *ale_entry,
865 int allmulti)
866 {
867 int unreg_mcast;
868 int idx;
869
870 idx = cpsw_ale_vlan_get_fld(ale, ale_entry,
871 ALE_ENT_VID_UNREG_MCAST_IDX);
872
873 unreg_mcast = readl(ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
874
875 if (allmulti)
876 unreg_mcast |= ALE_PORT_HOST;
877 else
878 unreg_mcast &= ~ALE_PORT_HOST;
879
880 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
881 }
882
cpsw_ale_set_allmulti(struct cpsw_ale * ale,int allmulti,int port)883 void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port)
884 {
885 u32 ale_entry[ALE_ENTRY_WORDS];
886 int type, idx;
887
888 for (idx = 0; idx < ale->params.ale_entries; idx++) {
889 int vlan_members;
890
891 cpsw_ale_read(ale, idx, ale_entry);
892 type = cpsw_ale_get_entry_type(ale_entry);
893 if (type != ALE_TYPE_VLAN)
894 continue;
895
896 vlan_members = cpsw_ale_vlan_get_fld(ale, ale_entry,
897 ALE_ENT_VID_MEMBER_LIST);
898
899 if (port != -1 && !(vlan_members & BIT(port)))
900 continue;
901
902 if (!ale->params.nu_switch_ale)
903 cpsw_ale_vlan_set_unreg_mcast(ale, ale_entry, allmulti);
904 else
905 cpsw_ale_vlan_set_unreg_mcast_idx(ale, ale_entry,
906 allmulti);
907
908 cpsw_ale_write(ale, idx, ale_entry);
909 }
910 }
911 EXPORT_SYMBOL_GPL(cpsw_ale_set_allmulti);
912
913 struct ale_control_info {
914 const char *name;
915 int offset, port_offset;
916 int shift, port_shift;
917 int bits;
918 };
919
920 static struct ale_control_info ale_controls[ALE_NUM_CONTROLS] = {
921 [ALE_ENABLE] = {
922 .name = "enable",
923 .offset = ALE_CONTROL,
924 .port_offset = 0,
925 .shift = 31,
926 .port_shift = 0,
927 .bits = 1,
928 },
929 [ALE_CLEAR] = {
930 .name = "clear",
931 .offset = ALE_CONTROL,
932 .port_offset = 0,
933 .shift = 30,
934 .port_shift = 0,
935 .bits = 1,
936 },
937 [ALE_AGEOUT] = {
938 .name = "ageout",
939 .offset = ALE_CONTROL,
940 .port_offset = 0,
941 .shift = 29,
942 .port_shift = 0,
943 .bits = 1,
944 },
945 [ALE_P0_UNI_FLOOD] = {
946 .name = "port0_unicast_flood",
947 .offset = ALE_CONTROL,
948 .port_offset = 0,
949 .shift = 8,
950 .port_shift = 0,
951 .bits = 1,
952 },
953 [ALE_VLAN_NOLEARN] = {
954 .name = "vlan_nolearn",
955 .offset = ALE_CONTROL,
956 .port_offset = 0,
957 .shift = 7,
958 .port_shift = 0,
959 .bits = 1,
960 },
961 [ALE_NO_PORT_VLAN] = {
962 .name = "no_port_vlan",
963 .offset = ALE_CONTROL,
964 .port_offset = 0,
965 .shift = 6,
966 .port_shift = 0,
967 .bits = 1,
968 },
969 [ALE_OUI_DENY] = {
970 .name = "oui_deny",
971 .offset = ALE_CONTROL,
972 .port_offset = 0,
973 .shift = 5,
974 .port_shift = 0,
975 .bits = 1,
976 },
977 [ALE_BYPASS] = {
978 .name = "bypass",
979 .offset = ALE_CONTROL,
980 .port_offset = 0,
981 .shift = 4,
982 .port_shift = 0,
983 .bits = 1,
984 },
985 [ALE_RATE_LIMIT_TX] = {
986 .name = "rate_limit_tx",
987 .offset = ALE_CONTROL,
988 .port_offset = 0,
989 .shift = 3,
990 .port_shift = 0,
991 .bits = 1,
992 },
993 [ALE_VLAN_AWARE] = {
994 .name = "vlan_aware",
995 .offset = ALE_CONTROL,
996 .port_offset = 0,
997 .shift = 2,
998 .port_shift = 0,
999 .bits = 1,
1000 },
1001 [ALE_AUTH_ENABLE] = {
1002 .name = "auth_enable",
1003 .offset = ALE_CONTROL,
1004 .port_offset = 0,
1005 .shift = 1,
1006 .port_shift = 0,
1007 .bits = 1,
1008 },
1009 [ALE_RATE_LIMIT] = {
1010 .name = "rate_limit",
1011 .offset = ALE_CONTROL,
1012 .port_offset = 0,
1013 .shift = 0,
1014 .port_shift = 0,
1015 .bits = 1,
1016 },
1017 [ALE_PORT_STATE] = {
1018 .name = "port_state",
1019 .offset = ALE_PORTCTL,
1020 .port_offset = 4,
1021 .shift = 0,
1022 .port_shift = 0,
1023 .bits = 2,
1024 },
1025 [ALE_PORT_DROP_UNTAGGED] = {
1026 .name = "drop_untagged",
1027 .offset = ALE_PORTCTL,
1028 .port_offset = 4,
1029 .shift = 2,
1030 .port_shift = 0,
1031 .bits = 1,
1032 },
1033 [ALE_PORT_DROP_UNKNOWN_VLAN] = {
1034 .name = "drop_unknown",
1035 .offset = ALE_PORTCTL,
1036 .port_offset = 4,
1037 .shift = 3,
1038 .port_shift = 0,
1039 .bits = 1,
1040 },
1041 [ALE_PORT_NOLEARN] = {
1042 .name = "nolearn",
1043 .offset = ALE_PORTCTL,
1044 .port_offset = 4,
1045 .shift = 4,
1046 .port_shift = 0,
1047 .bits = 1,
1048 },
1049 [ALE_PORT_NO_SA_UPDATE] = {
1050 .name = "no_source_update",
1051 .offset = ALE_PORTCTL,
1052 .port_offset = 4,
1053 .shift = 5,
1054 .port_shift = 0,
1055 .bits = 1,
1056 },
1057 [ALE_PORT_MACONLY] = {
1058 .name = "mac_only_port_mode",
1059 .offset = ALE_PORTCTL,
1060 .port_offset = 4,
1061 .shift = 11,
1062 .port_shift = 0,
1063 .bits = 1,
1064 },
1065 [ALE_PORT_MACONLY_CAF] = {
1066 .name = "mac_only_port_caf",
1067 .offset = ALE_PORTCTL,
1068 .port_offset = 4,
1069 .shift = 13,
1070 .port_shift = 0,
1071 .bits = 1,
1072 },
1073 [ALE_PORT_MCAST_LIMIT] = {
1074 .name = "mcast_limit",
1075 .offset = ALE_PORTCTL,
1076 .port_offset = 4,
1077 .shift = 16,
1078 .port_shift = 0,
1079 .bits = 8,
1080 },
1081 [ALE_PORT_BCAST_LIMIT] = {
1082 .name = "bcast_limit",
1083 .offset = ALE_PORTCTL,
1084 .port_offset = 4,
1085 .shift = 24,
1086 .port_shift = 0,
1087 .bits = 8,
1088 },
1089 [ALE_PORT_UNKNOWN_VLAN_MEMBER] = {
1090 .name = "unknown_vlan_member",
1091 .offset = ALE_UNKNOWNVLAN,
1092 .port_offset = 0,
1093 .shift = 0,
1094 .port_shift = 0,
1095 .bits = 6,
1096 },
1097 [ALE_PORT_UNKNOWN_MCAST_FLOOD] = {
1098 .name = "unknown_mcast_flood",
1099 .offset = ALE_UNKNOWNVLAN,
1100 .port_offset = 0,
1101 .shift = 8,
1102 .port_shift = 0,
1103 .bits = 6,
1104 },
1105 [ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = {
1106 .name = "unknown_reg_flood",
1107 .offset = ALE_UNKNOWNVLAN,
1108 .port_offset = 0,
1109 .shift = 16,
1110 .port_shift = 0,
1111 .bits = 6,
1112 },
1113 [ALE_PORT_UNTAGGED_EGRESS] = {
1114 .name = "untagged_egress",
1115 .offset = ALE_UNKNOWNVLAN,
1116 .port_offset = 0,
1117 .shift = 24,
1118 .port_shift = 0,
1119 .bits = 6,
1120 },
1121 [ALE_DEFAULT_THREAD_ID] = {
1122 .name = "default_thread_id",
1123 .offset = AM65_CPSW_ALE_THREAD_DEF_REG,
1124 .port_offset = 0,
1125 .shift = 0,
1126 .port_shift = 0,
1127 .bits = 6,
1128 },
1129 [ALE_DEFAULT_THREAD_ENABLE] = {
1130 .name = "default_thread_id_enable",
1131 .offset = AM65_CPSW_ALE_THREAD_DEF_REG,
1132 .port_offset = 0,
1133 .shift = 15,
1134 .port_shift = 0,
1135 .bits = 1,
1136 },
1137 };
1138
cpsw_ale_control_set(struct cpsw_ale * ale,int port,int control,int value)1139 int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control,
1140 int value)
1141 {
1142 const struct ale_control_info *info;
1143 int offset, shift;
1144 u32 tmp, mask;
1145
1146 if (control < 0 || control >= ARRAY_SIZE(ale_controls))
1147 return -EINVAL;
1148
1149 info = &ale_controls[control];
1150 if (info->port_offset == 0 && info->port_shift == 0)
1151 port = 0; /* global, port is a dont care */
1152
1153 if (port < 0 || port >= ale->params.ale_ports)
1154 return -EINVAL;
1155
1156 mask = BITMASK(info->bits);
1157 if (value & ~mask)
1158 return -EINVAL;
1159
1160 offset = info->offset + (port * info->port_offset);
1161 shift = info->shift + (port * info->port_shift);
1162
1163 tmp = readl_relaxed(ale->params.ale_regs + offset);
1164 tmp = (tmp & ~(mask << shift)) | (value << shift);
1165 writel_relaxed(tmp, ale->params.ale_regs + offset);
1166
1167 return 0;
1168 }
1169 EXPORT_SYMBOL_GPL(cpsw_ale_control_set);
1170
cpsw_ale_control_get(struct cpsw_ale * ale,int port,int control)1171 int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control)
1172 {
1173 const struct ale_control_info *info;
1174 int offset, shift;
1175 u32 tmp;
1176
1177 if (control < 0 || control >= ARRAY_SIZE(ale_controls))
1178 return -EINVAL;
1179
1180 info = &ale_controls[control];
1181 if (info->port_offset == 0 && info->port_shift == 0)
1182 port = 0; /* global, port is a dont care */
1183
1184 if (port < 0 || port >= ale->params.ale_ports)
1185 return -EINVAL;
1186
1187 offset = info->offset + (port * info->port_offset);
1188 shift = info->shift + (port * info->port_shift);
1189
1190 tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift;
1191 return tmp & BITMASK(info->bits);
1192 }
1193 EXPORT_SYMBOL_GPL(cpsw_ale_control_get);
1194
cpsw_ale_rx_ratelimit_mc(struct cpsw_ale * ale,int port,unsigned int ratelimit_pps)1195 int cpsw_ale_rx_ratelimit_mc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps)
1196
1197 {
1198 int val = ratelimit_pps / ALE_RATE_LIMIT_MIN_PPS;
1199 u32 remainder = ratelimit_pps % ALE_RATE_LIMIT_MIN_PPS;
1200
1201 if (ratelimit_pps && !val) {
1202 dev_err(ale->params.dev, "ALE MC port:%d ratelimit min value 1000pps\n", port);
1203 return -EINVAL;
1204 }
1205
1206 if (remainder)
1207 dev_info(ale->params.dev, "ALE port:%d MC ratelimit set to %dpps (requested %d)\n",
1208 port, ratelimit_pps - remainder, ratelimit_pps);
1209
1210 cpsw_ale_control_set(ale, port, ALE_PORT_MCAST_LIMIT, val);
1211
1212 dev_dbg(ale->params.dev, "ALE port:%d MC ratelimit set %d\n",
1213 port, val * ALE_RATE_LIMIT_MIN_PPS);
1214 return 0;
1215 }
1216 EXPORT_SYMBOL_GPL(cpsw_ale_rx_ratelimit_mc);
1217
cpsw_ale_rx_ratelimit_bc(struct cpsw_ale * ale,int port,unsigned int ratelimit_pps)1218 int cpsw_ale_rx_ratelimit_bc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps)
1219
1220 {
1221 int val = ratelimit_pps / ALE_RATE_LIMIT_MIN_PPS;
1222 u32 remainder = ratelimit_pps % ALE_RATE_LIMIT_MIN_PPS;
1223
1224 if (ratelimit_pps && !val) {
1225 dev_err(ale->params.dev, "ALE port:%d BC ratelimit min value 1000pps\n", port);
1226 return -EINVAL;
1227 }
1228
1229 if (remainder)
1230 dev_info(ale->params.dev, "ALE port:%d BC ratelimit set to %dpps (requested %d)\n",
1231 port, ratelimit_pps - remainder, ratelimit_pps);
1232
1233 cpsw_ale_control_set(ale, port, ALE_PORT_BCAST_LIMIT, val);
1234
1235 dev_dbg(ale->params.dev, "ALE port:%d BC ratelimit set %d\n",
1236 port, val * ALE_RATE_LIMIT_MIN_PPS);
1237 return 0;
1238 }
1239 EXPORT_SYMBOL_GPL(cpsw_ale_rx_ratelimit_bc);
1240
cpsw_ale_timer(struct timer_list * t)1241 static void cpsw_ale_timer(struct timer_list *t)
1242 {
1243 struct cpsw_ale *ale = timer_container_of(ale, t, timer);
1244
1245 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
1246
1247 if (ale->ageout) {
1248 ale->timer.expires = jiffies + ale->ageout;
1249 add_timer(&ale->timer);
1250 }
1251 }
1252
cpsw_ale_hw_aging_timer_start(struct cpsw_ale * ale)1253 static void cpsw_ale_hw_aging_timer_start(struct cpsw_ale *ale)
1254 {
1255 u32 aging_timer;
1256
1257 aging_timer = ale->params.bus_freq / 1000000;
1258 aging_timer *= ale->params.ale_ageout;
1259
1260 if (aging_timer & ~ALE_AGING_TIMER_MASK) {
1261 aging_timer = ALE_AGING_TIMER_MASK;
1262 dev_warn(ale->params.dev,
1263 "ALE aging timer overflow, set to max\n");
1264 }
1265
1266 writel(aging_timer, ale->params.ale_regs + ALE_AGING_TIMER);
1267 }
1268
cpsw_ale_hw_aging_timer_stop(struct cpsw_ale * ale)1269 static void cpsw_ale_hw_aging_timer_stop(struct cpsw_ale *ale)
1270 {
1271 writel(0, ale->params.ale_regs + ALE_AGING_TIMER);
1272 }
1273
cpsw_ale_aging_start(struct cpsw_ale * ale)1274 static void cpsw_ale_aging_start(struct cpsw_ale *ale)
1275 {
1276 if (!ale->params.ale_ageout)
1277 return;
1278
1279 if (ale->features & CPSW_ALE_F_HW_AUTOAGING) {
1280 cpsw_ale_hw_aging_timer_start(ale);
1281 return;
1282 }
1283
1284 timer_setup(&ale->timer, cpsw_ale_timer, 0);
1285 ale->timer.expires = jiffies + ale->ageout;
1286 add_timer(&ale->timer);
1287 }
1288
cpsw_ale_aging_stop(struct cpsw_ale * ale)1289 static void cpsw_ale_aging_stop(struct cpsw_ale *ale)
1290 {
1291 if (!ale->params.ale_ageout)
1292 return;
1293
1294 if (ale->features & CPSW_ALE_F_HW_AUTOAGING) {
1295 cpsw_ale_hw_aging_timer_stop(ale);
1296 return;
1297 }
1298
1299 timer_delete_sync(&ale->timer);
1300 }
1301
cpsw_ale_start(struct cpsw_ale * ale)1302 void cpsw_ale_start(struct cpsw_ale *ale)
1303 {
1304 unsigned long ale_prescale;
1305
1306 /* configure Broadcast and Multicast Rate Limit
1307 * number_of_packets = (Fclk / ALE_PRESCALE) * port.BCAST/MCAST_LIMIT
1308 * ALE_PRESCALE width is 19bit and min value 0x10
1309 * port.BCAST/MCAST_LIMIT is 8bit
1310 *
1311 * For multi port configuration support the ALE_PRESCALE is configured to 1ms interval,
1312 * which allows to configure port.BCAST/MCAST_LIMIT per port and achieve:
1313 * min number_of_packets = 1000 when port.BCAST/MCAST_LIMIT = 1
1314 * max number_of_packets = 1000 * 255 = 255000 when port.BCAST/MCAST_LIMIT = 0xFF
1315 */
1316 ale_prescale = ale->params.bus_freq / ALE_RATE_LIMIT_MIN_PPS;
1317 writel((u32)ale_prescale, ale->params.ale_regs + ALE_PRESCALE);
1318
1319 /* Allow MC/BC rate limiting globally.
1320 * The actual Rate Limit cfg enabled per-port by port.BCAST/MCAST_LIMIT
1321 */
1322 cpsw_ale_control_set(ale, 0, ALE_RATE_LIMIT, 1);
1323
1324 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1);
1325 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
1326
1327 cpsw_ale_aging_start(ale);
1328 }
1329 EXPORT_SYMBOL_GPL(cpsw_ale_start);
1330
cpsw_ale_stop(struct cpsw_ale * ale)1331 void cpsw_ale_stop(struct cpsw_ale *ale)
1332 {
1333 cpsw_ale_aging_stop(ale);
1334 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
1335 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);
1336 }
1337 EXPORT_SYMBOL_GPL(cpsw_ale_stop);
1338
1339 static const struct reg_field ale_fields_cpsw[] = {
1340 /* CPSW_ALE_IDVER_REG */
1341 [MINOR_VER] = REG_FIELD(ALE_IDVER, 0, 7),
1342 [MAJOR_VER] = REG_FIELD(ALE_IDVER, 8, 15),
1343 };
1344
1345 static const struct reg_field ale_fields_cpsw_nu[] = {
1346 /* CPSW_ALE_IDVER_REG */
1347 [MINOR_VER] = REG_FIELD(ALE_IDVER, 0, 7),
1348 [MAJOR_VER] = REG_FIELD(ALE_IDVER, 8, 10),
1349 /* CPSW_ALE_STATUS_REG */
1350 [ALE_ENTRIES] = REG_FIELD(ALE_STATUS, 0, 7),
1351 [ALE_POLICERS] = REG_FIELD(ALE_STATUS, 8, 15),
1352 /* CPSW_ALE_POLICER_PORT_OUI_REG */
1353 [POL_PORT_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 31, 31),
1354 [POL_TRUNK_ID] = REG_FIELD(ALE_POLICER_PORT_OUI, 30, 30),
1355 [POL_PORT_NUM] = REG_FIELD(ALE_POLICER_PORT_OUI, 25, 25),
1356 [POL_PRI_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 19, 19),
1357 [POL_PRI_VAL] = REG_FIELD(ALE_POLICER_PORT_OUI, 16, 18),
1358 [POL_OUI_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 15, 15),
1359 [POL_OUI_INDEX] = REG_FIELD(ALE_POLICER_PORT_OUI, 0, 5),
1360
1361 /* CPSW_ALE_POLICER_DA_SA_REG */
1362 [POL_DST_MEN] = REG_FIELD(ALE_POLICER_DA_SA, 31, 31),
1363 [POL_DST_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 16, 21),
1364 [POL_SRC_MEN] = REG_FIELD(ALE_POLICER_DA_SA, 15, 15),
1365 [POL_SRC_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 0, 5),
1366
1367 /* CPSW_ALE_POLICER_VLAN_REG */
1368 [POL_OVLAN_MEN] = REG_FIELD(ALE_POLICER_VLAN, 31, 31),
1369 [POL_OVLAN_INDEX] = REG_FIELD(ALE_POLICER_VLAN, 16, 21),
1370 [POL_IVLAN_MEN] = REG_FIELD(ALE_POLICER_VLAN, 15, 15),
1371 [POL_IVLAN_INDEX] = REG_FIELD(ALE_POLICER_VLAN, 0, 5),
1372
1373 /* CPSW_ALE_POLICER_ETHERTYPE_IPSA_REG */
1374 [POL_ETHERTYPE_MEN] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 31, 31),
1375 [POL_ETHERTYPE_INDEX] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 16, 21),
1376 [POL_IPSRC_MEN] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 15, 15),
1377 [POL_IPSRC_INDEX] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 0, 5),
1378
1379 /* CPSW_ALE_POLICER_IPDA_REG */
1380 [POL_IPDST_MEN] = REG_FIELD(ALE_POLICER_IPDA, 31, 31),
1381 [POL_IPDST_INDEX] = REG_FIELD(ALE_POLICER_IPDA, 16, 21),
1382
1383 /* CPSW_ALE_POLICER_TBL_CTL_REG */
1384 /**
1385 * REG_FIELDS not defined for this as fields cannot be correctly
1386 * used independently
1387 */
1388
1389 /* CPSW_ALE_POLICER_CTL_REG */
1390 [POL_EN] = REG_FIELD(ALE_POLICER_CTL, 31, 31),
1391 [POL_RED_DROP_EN] = REG_FIELD(ALE_POLICER_CTL, 29, 29),
1392 [POL_YELLOW_DROP_EN] = REG_FIELD(ALE_POLICER_CTL, 28, 28),
1393 [POL_YELLOW_THRESH] = REG_FIELD(ALE_POLICER_CTL, 24, 26),
1394 [POL_POL_MATCH_MODE] = REG_FIELD(ALE_POLICER_CTL, 22, 23),
1395 [POL_PRIORITY_THREAD_EN] = REG_FIELD(ALE_POLICER_CTL, 21, 21),
1396 [POL_MAC_ONLY_DEF_DIS] = REG_FIELD(ALE_POLICER_CTL, 20, 20),
1397
1398 /* CPSW_ALE_POLICER_TEST_CTL_REG */
1399 [POL_TEST_CLR] = REG_FIELD(ALE_POLICER_TEST_CTL, 31, 31),
1400 [POL_TEST_CLR_RED] = REG_FIELD(ALE_POLICER_TEST_CTL, 30, 30),
1401 [POL_TEST_CLR_YELLOW] = REG_FIELD(ALE_POLICER_TEST_CTL, 29, 29),
1402 [POL_TEST_CLR_SELECTED] = REG_FIELD(ALE_POLICER_TEST_CTL, 28, 28),
1403 [POL_TEST_ENTRY] = REG_FIELD(ALE_POLICER_TEST_CTL, 0, 4),
1404
1405 /* CPSW_ALE_POLICER_HIT_STATUS_REG */
1406 [POL_STATUS_HIT] = REG_FIELD(ALE_POLICER_HIT_STATUS, 31, 31),
1407 [POL_STATUS_HIT_RED] = REG_FIELD(ALE_POLICER_HIT_STATUS, 30, 30),
1408 [POL_STATUS_HIT_YELLOW] = REG_FIELD(ALE_POLICER_HIT_STATUS, 29, 29),
1409
1410 /* CPSW_ALE_THREAD_DEF_REG */
1411 [ALE_DEFAULT_THREAD_EN] = REG_FIELD(ALE_THREAD_DEF, 15, 15),
1412 [ALE_DEFAULT_THREAD_VAL] = REG_FIELD(ALE_THREAD_DEF, 0, 5),
1413
1414 /* CPSW_ALE_THREAD_CTL_REG */
1415 [ALE_THREAD_CLASS_INDEX] = REG_FIELD(ALE_THREAD_CTL, 0, 4),
1416
1417 /* CPSW_ALE_THREAD_VAL_REG */
1418 [ALE_THREAD_ENABLE] = REG_FIELD(ALE_THREAD_VAL, 15, 15),
1419 [ALE_THREAD_VALUE] = REG_FIELD(ALE_THREAD_VAL, 0, 5),
1420 };
1421
1422 static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = {
1423 {
1424 /* am3/4/5, dra7. dm814x, 66ak2hk-gbe */
1425 .dev_id = "cpsw",
1426 .tbl_entries = 1024,
1427 .reg_fields = ale_fields_cpsw,
1428 .num_fields = ARRAY_SIZE(ale_fields_cpsw),
1429 .vlan_entry_tbl = vlan_entry_cpsw,
1430 },
1431 {
1432 /* 66ak2h_xgbe */
1433 .dev_id = "66ak2h-xgbe",
1434 .tbl_entries = 2048,
1435 .reg_fields = ale_fields_cpsw,
1436 .num_fields = ARRAY_SIZE(ale_fields_cpsw),
1437 .vlan_entry_tbl = vlan_entry_cpsw,
1438 },
1439 {
1440 .dev_id = "66ak2el",
1441 .features = CPSW_ALE_F_STATUS_REG,
1442 .reg_fields = ale_fields_cpsw_nu,
1443 .num_fields = ARRAY_SIZE(ale_fields_cpsw_nu),
1444 .nu_switch_ale = true,
1445 .vlan_entry_tbl = vlan_entry_nu,
1446 },
1447 {
1448 .dev_id = "66ak2g",
1449 .features = CPSW_ALE_F_STATUS_REG,
1450 .tbl_entries = 64,
1451 .reg_fields = ale_fields_cpsw_nu,
1452 .num_fields = ARRAY_SIZE(ale_fields_cpsw_nu),
1453 .nu_switch_ale = true,
1454 .vlan_entry_tbl = vlan_entry_nu,
1455 },
1456 {
1457 .dev_id = "am65x-cpsw2g",
1458 .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING,
1459 .tbl_entries = 64,
1460 .reg_fields = ale_fields_cpsw_nu,
1461 .num_fields = ARRAY_SIZE(ale_fields_cpsw_nu),
1462 .nu_switch_ale = true,
1463 .vlan_entry_tbl = vlan_entry_nu,
1464 },
1465 {
1466 .dev_id = "j721e-cpswxg",
1467 .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING,
1468 .reg_fields = ale_fields_cpsw_nu,
1469 .num_fields = ARRAY_SIZE(ale_fields_cpsw_nu),
1470 .vlan_entry_tbl = vlan_entry_k3_cpswxg,
1471 },
1472 {
1473 .dev_id = "am64-cpswxg",
1474 .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING,
1475 .reg_fields = ale_fields_cpsw_nu,
1476 .num_fields = ARRAY_SIZE(ale_fields_cpsw_nu),
1477 .vlan_entry_tbl = vlan_entry_k3_cpswxg,
1478 .tbl_entries = 512,
1479 },
1480 { },
1481 };
1482
1483 static const struct
cpsw_ale_match_id(const struct cpsw_ale_dev_id * id,const char * dev_id)1484 cpsw_ale_dev_id *cpsw_ale_match_id(const struct cpsw_ale_dev_id *id,
1485 const char *dev_id)
1486 {
1487 if (!dev_id)
1488 return NULL;
1489
1490 while (id->dev_id) {
1491 if (strcmp(dev_id, id->dev_id) == 0)
1492 return id;
1493 id++;
1494 }
1495 return NULL;
1496 }
1497
1498 static const struct regmap_config ale_regmap_cfg = {
1499 .reg_bits = 32,
1500 .val_bits = 32,
1501 .reg_stride = 4,
1502 .name = "cpsw-ale",
1503 };
1504
cpsw_ale_regfield_init(struct cpsw_ale * ale)1505 static int cpsw_ale_regfield_init(struct cpsw_ale *ale)
1506 {
1507 const struct reg_field *reg_fields = ale->params.reg_fields;
1508 struct device *dev = ale->params.dev;
1509 struct regmap *regmap = ale->regmap;
1510 int i;
1511
1512 for (i = 0; i < ale->params.num_fields; i++) {
1513 ale->fields[i] = devm_regmap_field_alloc(dev, regmap,
1514 reg_fields[i]);
1515 if (IS_ERR(ale->fields[i])) {
1516 dev_err(dev, "Unable to allocate regmap field %d\n", i);
1517 return PTR_ERR(ale->fields[i]);
1518 }
1519 }
1520
1521 return 0;
1522 }
1523
cpsw_ale_create(struct cpsw_ale_params * params)1524 struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params)
1525 {
1526 u32 ale_entries, rev_major, rev_minor, policers;
1527 const struct cpsw_ale_dev_id *ale_dev_id;
1528 struct cpsw_ale *ale;
1529 int ret;
1530
1531 ale_dev_id = cpsw_ale_match_id(cpsw_ale_id_match, params->dev_id);
1532 if (!ale_dev_id)
1533 return ERR_PTR(-EINVAL);
1534
1535 params->ale_entries = ale_dev_id->tbl_entries;
1536 params->nu_switch_ale = ale_dev_id->nu_switch_ale;
1537 params->reg_fields = ale_dev_id->reg_fields;
1538 params->num_fields = ale_dev_id->num_fields;
1539
1540 ale = devm_kzalloc(params->dev, sizeof(*ale), GFP_KERNEL);
1541 if (!ale)
1542 return ERR_PTR(-ENOMEM);
1543 ale->regmap = devm_regmap_init_mmio(params->dev, params->ale_regs,
1544 &ale_regmap_cfg);
1545 if (IS_ERR(ale->regmap)) {
1546 dev_err(params->dev, "Couldn't create CPSW ALE regmap\n");
1547 return ERR_PTR(-ENOMEM);
1548 }
1549
1550 ale->params = *params;
1551 ret = cpsw_ale_regfield_init(ale);
1552 if (ret)
1553 return ERR_PTR(ret);
1554
1555 ale->p0_untag_vid_mask = devm_bitmap_zalloc(params->dev, VLAN_N_VID,
1556 GFP_KERNEL);
1557 if (!ale->p0_untag_vid_mask)
1558 return ERR_PTR(-ENOMEM);
1559
1560 ale->ageout = ale->params.ale_ageout * HZ;
1561 ale->features = ale_dev_id->features;
1562 ale->vlan_entry_tbl = ale_dev_id->vlan_entry_tbl;
1563
1564 regmap_field_read(ale->fields[MINOR_VER], &rev_minor);
1565 regmap_field_read(ale->fields[MAJOR_VER], &rev_major);
1566 ale->version = rev_major << 8 | rev_minor;
1567 dev_info(ale->params.dev, "initialized cpsw ale version %d.%d\n",
1568 rev_major, rev_minor);
1569
1570 if (ale->features & CPSW_ALE_F_STATUS_REG &&
1571 !ale->params.ale_entries) {
1572 regmap_field_read(ale->fields[ALE_ENTRIES], &ale_entries);
1573 /* ALE available on newer NetCP switches has introduced
1574 * a register, ALE_STATUS, to indicate the size of ALE
1575 * table which shows the size as a multiple of 1024 entries.
1576 * For these, params.ale_entries will be set to zero. So
1577 * read the register and update the value of ale_entries.
1578 * return error if ale_entries is zero in ALE_STATUS.
1579 */
1580 if (!ale_entries)
1581 return ERR_PTR(-EINVAL);
1582
1583 ale_entries *= ALE_TABLE_SIZE_MULTIPLIER;
1584 ale->params.ale_entries = ale_entries;
1585 }
1586
1587 if (ale->features & CPSW_ALE_F_STATUS_REG &&
1588 !ale->params.num_policers) {
1589 regmap_field_read(ale->fields[ALE_POLICERS], &policers);
1590 if (!policers)
1591 return ERR_PTR(-EINVAL);
1592
1593 policers *= ALE_POLICER_SIZE_MULTIPLIER;
1594 ale->params.num_policers = policers;
1595 }
1596
1597 dev_info(ale->params.dev,
1598 "ALE Table size %ld, Policers %ld\n", ale->params.ale_entries,
1599 ale->params.num_policers);
1600
1601 /* set default bits for existing h/w */
1602 ale->port_mask_bits = ale->params.ale_ports;
1603 ale->port_num_bits = order_base_2(ale->params.ale_ports);
1604 ale->vlan_field_bits = ale->params.ale_ports;
1605
1606 /* Set defaults override for ALE on NetCP NU switch and for version
1607 * 1R3
1608 */
1609 if (ale->params.nu_switch_ale) {
1610 /* Separate registers for unknown vlan configuration.
1611 * Also there are N bits, where N is number of ale
1612 * ports and shift value should be 0
1613 */
1614 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].bits =
1615 ale->params.ale_ports;
1616 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].offset =
1617 ALE_UNKNOWNVLAN_MEMBER;
1618 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].bits =
1619 ale->params.ale_ports;
1620 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].shift = 0;
1621 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].offset =
1622 ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD;
1623 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].bits =
1624 ale->params.ale_ports;
1625 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].shift = 0;
1626 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].offset =
1627 ALE_UNKNOWNVLAN_REG_MCAST_FLOOD;
1628 ale_controls[ALE_PORT_UNTAGGED_EGRESS].bits =
1629 ale->params.ale_ports;
1630 ale_controls[ALE_PORT_UNTAGGED_EGRESS].shift = 0;
1631 ale_controls[ALE_PORT_UNTAGGED_EGRESS].offset =
1632 ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS;
1633 }
1634
1635 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
1636 return ale;
1637 }
1638 EXPORT_SYMBOL_GPL(cpsw_ale_create);
1639
cpsw_ale_dump(struct cpsw_ale * ale,u32 * data)1640 void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data)
1641 {
1642 int i;
1643
1644 for (i = 0; i < ale->params.ale_entries; i++) {
1645 cpsw_ale_read(ale, i, data);
1646 data += ALE_ENTRY_WORDS;
1647 }
1648 }
1649 EXPORT_SYMBOL_GPL(cpsw_ale_dump);
1650
cpsw_ale_restore(struct cpsw_ale * ale,u32 * data)1651 void cpsw_ale_restore(struct cpsw_ale *ale, u32 *data)
1652 {
1653 int i;
1654
1655 for (i = 0; i < ale->params.ale_entries; i++) {
1656 cpsw_ale_write(ale, i, data);
1657 data += ALE_ENTRY_WORDS;
1658 }
1659 }
1660 EXPORT_SYMBOL_GPL(cpsw_ale_restore);
1661
cpsw_ale_get_num_entries(struct cpsw_ale * ale)1662 u32 cpsw_ale_get_num_entries(struct cpsw_ale *ale)
1663 {
1664 return ale ? ale->params.ale_entries : 0;
1665 }
1666 EXPORT_SYMBOL_GPL(cpsw_ale_get_num_entries);
1667
1668 /* Reads the specified policer index into ALE POLICER registers */
cpsw_ale_policer_read_idx(struct cpsw_ale * ale,u32 idx)1669 static void cpsw_ale_policer_read_idx(struct cpsw_ale *ale, u32 idx)
1670 {
1671 idx &= ALE_POLICER_TBL_INDEX_MASK;
1672 writel_relaxed(idx, ale->params.ale_regs + ALE_POLICER_TBL_CTL);
1673 }
1674
1675 /* Writes the ALE POLICER registers into the specified policer index */
cpsw_ale_policer_write_idx(struct cpsw_ale * ale,u32 idx)1676 static void cpsw_ale_policer_write_idx(struct cpsw_ale *ale, u32 idx)
1677 {
1678 idx &= ALE_POLICER_TBL_INDEX_MASK;
1679 idx |= ALE_POLICER_TBL_WRITE_ENABLE;
1680 writel_relaxed(idx, ale->params.ale_regs + ALE_POLICER_TBL_CTL);
1681 }
1682
1683 /* enables/disables the custom thread value for the specified policer index */
cpsw_ale_policer_thread_idx_enable(struct cpsw_ale * ale,u32 idx,u32 thread_id,bool enable)1684 static void cpsw_ale_policer_thread_idx_enable(struct cpsw_ale *ale, u32 idx,
1685 u32 thread_id, bool enable)
1686 {
1687 regmap_field_write(ale->fields[ALE_THREAD_CLASS_INDEX], idx);
1688 regmap_field_write(ale->fields[ALE_THREAD_VALUE], thread_id);
1689 regmap_field_write(ale->fields[ALE_THREAD_ENABLE], enable ? 1 : 0);
1690 }
1691
1692 /* Disable all policer entries and thread mappings */
cpsw_ale_policer_reset(struct cpsw_ale * ale)1693 static void cpsw_ale_policer_reset(struct cpsw_ale *ale)
1694 {
1695 int i;
1696
1697 for (i = 0; i < ale->params.num_policers ; i++) {
1698 cpsw_ale_policer_read_idx(ale, i);
1699 regmap_field_write(ale->fields[POL_PORT_MEN], 0);
1700 regmap_field_write(ale->fields[POL_PRI_MEN], 0);
1701 regmap_field_write(ale->fields[POL_OUI_MEN], 0);
1702 regmap_field_write(ale->fields[POL_DST_MEN], 0);
1703 regmap_field_write(ale->fields[POL_SRC_MEN], 0);
1704 regmap_field_write(ale->fields[POL_OVLAN_MEN], 0);
1705 regmap_field_write(ale->fields[POL_IVLAN_MEN], 0);
1706 regmap_field_write(ale->fields[POL_ETHERTYPE_MEN], 0);
1707 regmap_field_write(ale->fields[POL_IPSRC_MEN], 0);
1708 regmap_field_write(ale->fields[POL_IPDST_MEN], 0);
1709 regmap_field_write(ale->fields[POL_EN], 0);
1710 regmap_field_write(ale->fields[POL_RED_DROP_EN], 0);
1711 regmap_field_write(ale->fields[POL_YELLOW_DROP_EN], 0);
1712 regmap_field_write(ale->fields[POL_PRIORITY_THREAD_EN], 0);
1713
1714 cpsw_ale_policer_thread_idx_enable(ale, i, 0, 0);
1715 }
1716 }
1717
1718 /* Default classifier is to map 8 user priorities to N receive channels */
cpsw_ale_classifier_setup_default(struct cpsw_ale * ale,int num_rx_ch)1719 void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch)
1720 {
1721 int pri, idx;
1722
1723 /* Reference:
1724 * IEEE802.1Q-2014, Standard for Local and metropolitan area networks
1725 * Table I-2 - Traffic type acronyms
1726 * Table I-3 - Defining traffic types
1727 * Section I.4 Traffic types and priority values, states:
1728 * "0 is thus used both for default priority and for Best Effort, and
1729 * Background is associated with a priority value of 1. This means
1730 * that the value 1 effectively communicates a lower priority than 0."
1731 *
1732 * In the table below, Priority Code Point (PCP) 0 is assigned
1733 * to a higher priority thread than PCP 1 wherever possible.
1734 * The table maps which thread the PCP traffic needs to be
1735 * sent to for a given number of threads (RX channels). Upper threads
1736 * have higher priority.
1737 * e.g. if number of threads is 8 then user priority 0 will map to
1738 * pri_thread_map[8-1][0] i.e. thread 1
1739 */
1740
1741 int pri_thread_map[8][8] = { /* BK,BE,EE,CA,VI,VO,IC,NC */
1742 { 0, 0, 0, 0, 0, 0, 0, 0, },
1743 { 0, 0, 0, 0, 1, 1, 1, 1, },
1744 { 0, 0, 0, 0, 1, 1, 2, 2, },
1745 { 0, 0, 1, 1, 2, 2, 3, 3, },
1746 { 0, 0, 1, 1, 2, 2, 3, 4, },
1747 { 1, 0, 2, 2, 3, 3, 4, 5, },
1748 { 1, 0, 2, 3, 4, 4, 5, 6, },
1749 { 1, 0, 2, 3, 4, 5, 6, 7 } };
1750
1751 cpsw_ale_policer_reset(ale);
1752
1753 /* use first 8 classifiers to map 8 (DSCP/PCP) priorities to channels */
1754 for (pri = 0; pri < 8; pri++) {
1755 idx = pri;
1756
1757 /* Classifier 'idx' match on priority 'pri' */
1758 cpsw_ale_policer_read_idx(ale, idx);
1759 regmap_field_write(ale->fields[POL_PRI_VAL], pri);
1760 regmap_field_write(ale->fields[POL_PRI_MEN], 1);
1761 cpsw_ale_policer_write_idx(ale, idx);
1762
1763 /* Map Classifier 'idx' to thread provided by the map */
1764 cpsw_ale_policer_thread_idx_enable(ale, idx,
1765 pri_thread_map[num_rx_ch - 1][pri],
1766 1);
1767 }
1768 }
1769 EXPORT_SYMBOL_GPL(cpsw_ale_classifier_setup_default);
1770
1771 MODULE_LICENSE("GPL");
1772 MODULE_DESCRIPTION("TI N-Port Ethernet Switch Address Lookup Engine");
1773