1 /*
2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 *
25 * PCI bus layout on a real G5 (U3 based):
26 *
27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
47 */
48
49 #include "qemu/osdep.h"
50 #include "qemu/datadir.h"
51 #include "qemu/units.h"
52 #include "qapi/error.h"
53 #include "exec/target_page.h"
54 #include "hw/ppc/ppc.h"
55 #include "hw/qdev-properties.h"
56 #include "hw/nvram/mac_nvram.h"
57 #include "hw/boards.h"
58 #include "hw/pci-host/uninorth.h"
59 #include "hw/input/adb.h"
60 #include "hw/ppc/mac_dbdma.h"
61 #include "hw/pci/pci.h"
62 #include "net/net.h"
63 #include "system/system.h"
64 #include "hw/nvram/fw_cfg.h"
65 #include "hw/char/escc.h"
66 #include "hw/misc/macio/macio.h"
67 #include "hw/ppc/openpic.h"
68 #include "hw/loader.h"
69 #include "hw/fw-path-provider.h"
70 #include "elf.h"
71 #include "qemu/error-report.h"
72 #include "system/kvm.h"
73 #include "system/reset.h"
74 #include "kvm_ppc.h"
75 #include "hw/usb.h"
76 #include "hw/sysbus.h"
77 #include "trace.h"
78
79 #define MAX_IDE_BUS 2
80 #define CFG_ADDR 0xf0000510
81 #define TBFREQ (25UL * 1000UL * 1000UL)
82 #define CLOCKFREQ (900UL * 1000UL * 1000UL)
83 #define BUSFREQ (100UL * 1000UL * 1000UL)
84
85 #define NDRV_VGA_FILENAME "qemu_vga.ndrv"
86
87 #define PROM_FILENAME "openbios-ppc"
88 #define PROM_BASE 0xfff00000
89 #define PROM_SIZE (1 * MiB)
90
91 #define KERNEL_LOAD_ADDR 0x01000000
92 #define KERNEL_GAP 0x00100000
93
94 #define TYPE_CORE99_MACHINE MACHINE_TYPE_NAME("mac99")
95 typedef struct Core99MachineState Core99MachineState;
96 DECLARE_INSTANCE_CHECKER(Core99MachineState, CORE99_MACHINE,
97 TYPE_CORE99_MACHINE)
98
99 typedef enum {
100 CORE99_VIA_CONFIG_CUDA = 0,
101 CORE99_VIA_CONFIG_PMU,
102 CORE99_VIA_CONFIG_PMU_ADB
103 } Core99ViaConfig;
104
105 struct Core99MachineState {
106 /*< private >*/
107 MachineState parent;
108
109 Core99ViaConfig via_config;
110 };
111
fw_cfg_boot_set(void * opaque,const char * boot_device,Error ** errp)112 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
113 Error **errp)
114 {
115 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
116 }
117
translate_kernel_address(void * opaque,uint64_t addr)118 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
119 {
120 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
121 }
122
ppc_core99_reset(void * opaque)123 static void ppc_core99_reset(void *opaque)
124 {
125 PowerPCCPU *cpu = opaque;
126
127 cpu_reset(CPU(cpu));
128 /* 970 CPUs want to get their initial IP as part of their boot protocol */
129 cpu->env.nip = PROM_BASE + 0x100;
130 }
131
132 /* PowerPC Mac99 hardware initialisation */
ppc_core99_init(MachineState * machine)133 static void ppc_core99_init(MachineState *machine)
134 {
135 Core99MachineState *core99_machine = CORE99_MACHINE(machine);
136 MachineClass *mc = MACHINE_GET_CLASS(machine);
137 PowerPCCPU *cpu = NULL;
138 CPUPPCState *env = NULL;
139 char *filename;
140 IrqLines *openpic_irqs;
141 int i, j, k, ppc_boot_device, machine_arch, bios_size = -1;
142 const char *bios_name = machine->firmware ?: PROM_FILENAME;
143 MemoryRegion *bios = g_new(MemoryRegion, 1);
144 hwaddr kernel_base = 0, initrd_base = 0, cmdline_base = 0;
145 long kernel_size = 0, initrd_size = 0;
146 PCIBus *pci_bus;
147 bool has_pmu, has_adb;
148 Object *macio;
149 MACIOIDEState *macio_ide;
150 BusState *adb_bus;
151 MacIONVRAMState *nvr;
152 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
153 void *fw_cfg;
154 SysBusDevice *s;
155 DeviceState *dev, *pic_dev, *uninorth_pci_dev;
156 DeviceState *uninorth_internal_dev = NULL, *uninorth_agp_dev = NULL;
157 hwaddr nvram_addr = 0xFFF04000;
158 uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ;
159
160 /* init CPUs */
161 for (i = 0; i < machine->smp.cpus; i++) {
162 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
163 env = &cpu->env;
164
165 /* Set time-base frequency to 100 Mhz */
166 cpu_ppc_tb_init(env, TBFREQ);
167 qemu_register_reset(ppc_core99_reset, cpu);
168 }
169
170 /* allocate RAM */
171 if (machine->ram_size > 2 * GiB) {
172 error_report("RAM size more than 2 GiB is not supported");
173 exit(1);
174 }
175 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
176
177 /* allocate and load firmware ROM */
178 memory_region_init_rom(bios, NULL, "ppc_core99.bios", PROM_SIZE,
179 &error_fatal);
180 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios);
181
182 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
183 if (filename) {
184 /* Load OpenBIOS (ELF) */
185 bios_size = load_elf(filename, NULL, NULL, NULL, NULL,
186 NULL, NULL, NULL,
187 ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0);
188
189 if (bios_size <= 0) {
190 /* or load binary ROM image */
191 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE);
192 }
193 g_free(filename);
194 }
195 if (bios_size < 0 || bios_size > PROM_SIZE) {
196 error_report("could not load PowerPC bios '%s'", bios_name);
197 exit(1);
198 }
199
200 if (machine->kernel_filename) {
201 kernel_base = KERNEL_LOAD_ADDR;
202 kernel_size = load_elf(machine->kernel_filename, NULL,
203 translate_kernel_address, NULL, NULL, NULL,
204 NULL, NULL, ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0);
205 if (kernel_size < 0) {
206 kernel_size = load_aout(machine->kernel_filename, kernel_base,
207 machine->ram_size - kernel_base,
208 true, TARGET_PAGE_SIZE);
209 }
210 if (kernel_size < 0) {
211 kernel_size = load_image_targphys(machine->kernel_filename,
212 kernel_base,
213 machine->ram_size - kernel_base);
214 }
215 if (kernel_size < 0) {
216 error_report("could not load kernel '%s'",
217 machine->kernel_filename);
218 exit(1);
219 }
220 /* load initrd */
221 if (machine->initrd_filename) {
222 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
223 initrd_size = load_image_targphys(machine->initrd_filename,
224 initrd_base,
225 machine->ram_size - initrd_base);
226 if (initrd_size < 0) {
227 error_report("could not load initial ram disk '%s'",
228 machine->initrd_filename);
229 exit(1);
230 }
231 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
232 } else {
233 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
234 }
235 ppc_boot_device = 'm';
236 } else {
237 ppc_boot_device = '\0';
238 /* We consider that NewWorld PowerMac never have any floppy drive
239 * For now, OHW cannot boot from the network.
240 */
241 for (i = 0; machine->boot_config.order[i] != '\0'; i++) {
242 if (machine->boot_config.order[i] >= 'c' &&
243 machine->boot_config.order[i] <= 'f') {
244 ppc_boot_device = machine->boot_config.order[i];
245 break;
246 }
247 }
248 if (ppc_boot_device == '\0') {
249 error_report("No valid boot device for Mac99 machine");
250 exit(1);
251 }
252 }
253
254 openpic_irqs = g_new0(IrqLines, machine->smp.cpus);
255 dev = DEVICE(cpu);
256 for (i = 0; i < machine->smp.cpus; i++) {
257 /* Mac99 IRQ connection between OpenPIC outputs pins
258 * and PowerPC input pins
259 */
260 switch (PPC_INPUT(env)) {
261 case PPC_FLAGS_INPUT_6xx:
262 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] =
263 qdev_get_gpio_in(dev, PPC6xx_INPUT_INT);
264 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] =
265 qdev_get_gpio_in(dev, PPC6xx_INPUT_INT);
266 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] =
267 qdev_get_gpio_in(dev, PPC6xx_INPUT_MCP);
268 /* Not connected ? */
269 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL;
270 /* Check this */
271 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] =
272 qdev_get_gpio_in(dev, PPC6xx_INPUT_HRESET);
273 break;
274 #if defined(TARGET_PPC64)
275 case PPC_FLAGS_INPUT_970:
276 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] =
277 qdev_get_gpio_in(dev, PPC970_INPUT_INT);
278 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] =
279 qdev_get_gpio_in(dev, PPC970_INPUT_INT);
280 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] =
281 qdev_get_gpio_in(dev, PPC970_INPUT_MCP);
282 /* Not connected ? */
283 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL;
284 /* Check this */
285 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] =
286 qdev_get_gpio_in(dev, PPC970_INPUT_HRESET);
287 break;
288 #endif /* defined(TARGET_PPC64) */
289 default:
290 error_report("Bus model not supported on mac99 machine");
291 exit(1);
292 }
293 }
294
295 /* UniN init */
296 s = SYS_BUS_DEVICE(qdev_new(TYPE_UNI_NORTH));
297 sysbus_realize_and_unref(s, &error_fatal);
298 memory_region_add_subregion(get_system_memory(), 0xf8000000,
299 sysbus_mmio_get_region(s, 0));
300
301 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
302 machine_arch = ARCH_MAC99_U3;
303 /* 970 gets a U3 bus */
304 /* Uninorth AGP bus */
305 uninorth_pci_dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE);
306 s = SYS_BUS_DEVICE(uninorth_pci_dev);
307 sysbus_realize_and_unref(s, &error_fatal);
308 sysbus_mmio_map(s, 0, 0xf0800000);
309 sysbus_mmio_map(s, 1, 0xf0c00000);
310 /* PCI hole */
311 memory_region_add_subregion(get_system_memory(), 0x80000000,
312 sysbus_mmio_get_region(s, 2));
313 /* Register 8 MB of ISA IO space */
314 memory_region_add_subregion(get_system_memory(), 0xf2000000,
315 sysbus_mmio_get_region(s, 3));
316 } else {
317 machine_arch = ARCH_MAC99;
318 /* Use values found on a real PowerMac */
319 /* Uninorth AGP bus */
320 uninorth_agp_dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
321 s = SYS_BUS_DEVICE(uninorth_agp_dev);
322 sysbus_realize_and_unref(s, &error_fatal);
323 sysbus_mmio_map(s, 0, 0xf0800000);
324 sysbus_mmio_map(s, 1, 0xf0c00000);
325
326 /* Uninorth internal bus */
327 uninorth_internal_dev = qdev_new(
328 TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
329 s = SYS_BUS_DEVICE(uninorth_internal_dev);
330 sysbus_realize_and_unref(s, &error_fatal);
331 sysbus_mmio_map(s, 0, 0xf4800000);
332 sysbus_mmio_map(s, 1, 0xf4c00000);
333
334 /* Uninorth main bus - this must be last to make it the default */
335 uninorth_pci_dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
336 qdev_prop_set_uint32(uninorth_pci_dev, "ofw-addr", 0xf2000000);
337 s = SYS_BUS_DEVICE(uninorth_pci_dev);
338 sysbus_realize_and_unref(s, &error_fatal);
339 sysbus_mmio_map(s, 0, 0xf2800000);
340 sysbus_mmio_map(s, 1, 0xf2c00000);
341 /* PCI hole */
342 memory_region_add_subregion(get_system_memory(), 0x80000000,
343 sysbus_mmio_get_region(s, 2));
344 /* Register 8 MB of ISA IO space */
345 memory_region_add_subregion(get_system_memory(), 0xf2000000,
346 sysbus_mmio_get_region(s, 3));
347 }
348
349 machine->usb |= defaults_enabled() && !machine->usb_disabled;
350 has_pmu = (core99_machine->via_config != CORE99_VIA_CONFIG_CUDA);
351 has_adb = (core99_machine->via_config == CORE99_VIA_CONFIG_CUDA ||
352 core99_machine->via_config == CORE99_VIA_CONFIG_PMU_ADB);
353
354 /* init basic PC hardware */
355 pci_bus = PCI_HOST_BRIDGE(uninorth_pci_dev)->bus;
356
357 /* MacIO */
358 macio = OBJECT(pci_new(-1, TYPE_NEWWORLD_MACIO));
359 dev = DEVICE(macio);
360 qdev_prop_set_uint64(dev, "frequency", tbfreq);
361 qdev_prop_set_bit(dev, "has-pmu", has_pmu);
362 qdev_prop_set_bit(dev, "has-adb", has_adb);
363
364 dev = DEVICE(object_resolve_path_component(macio, "escc"));
365 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
366 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
367
368 pci_realize_and_unref(PCI_DEVICE(macio), pci_bus, &error_fatal);
369
370 pic_dev = DEVICE(object_resolve_path_component(macio, "pic"));
371 for (i = 0; i < 4; i++) {
372 qdev_connect_gpio_out(uninorth_pci_dev, i,
373 qdev_get_gpio_in(pic_dev, 0x1b + i));
374 }
375
376 /* TODO: additional PCI buses only wired up for 32-bit machines */
377 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_970) {
378 /* Uninorth AGP bus */
379 for (i = 0; i < 4; i++) {
380 qdev_connect_gpio_out(uninorth_agp_dev, i,
381 qdev_get_gpio_in(pic_dev, 0x1b + i));
382 }
383
384 /* Uninorth internal bus */
385 for (i = 0; i < 4; i++) {
386 qdev_connect_gpio_out(uninorth_internal_dev, i,
387 qdev_get_gpio_in(pic_dev, 0x1b + i));
388 }
389 }
390
391 /* OpenPIC */
392 s = SYS_BUS_DEVICE(pic_dev);
393 k = 0;
394 for (i = 0; i < machine->smp.cpus; i++) {
395 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
396 sysbus_connect_irq(s, k++, openpic_irqs[i].irq[j]);
397 }
398 }
399 g_free(openpic_irqs);
400
401 /* We only emulate 2 out of 3 IDE controllers for now */
402 ide_drive_get(hd, ARRAY_SIZE(hd));
403
404 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[0]"));
405 macio_ide_init_drives(macio_ide, hd);
406
407 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[1]"));
408 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
409
410 if (has_adb) {
411 if (has_pmu) {
412 dev = DEVICE(object_resolve_path_component(macio, "pmu"));
413 } else {
414 dev = DEVICE(object_resolve_path_component(macio, "cuda"));
415 }
416
417 adb_bus = qdev_get_child_bus(dev, "adb.0");
418 dev = qdev_new(TYPE_ADB_KEYBOARD);
419 qdev_realize_and_unref(dev, adb_bus, &error_fatal);
420
421 dev = qdev_new(TYPE_ADB_MOUSE);
422 qdev_realize_and_unref(dev, adb_bus, &error_fatal);
423 }
424
425 if (machine->usb) {
426 pci_create_simple(pci_bus, -1, "pci-ohci");
427
428 /* U3 needs to use USB for input because Linux doesn't support via-cuda
429 on PPC64 */
430 if (!has_adb || machine_arch == ARCH_MAC99_U3) {
431 USBBus *usb_bus;
432
433 usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS,
434 &error_abort));
435 usb_create_simple(usb_bus, "usb-kbd");
436 usb_create_simple(usb_bus, "usb-mouse");
437 }
438 }
439
440 pci_vga_init(pci_bus);
441
442 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) {
443 graphic_depth = 15;
444 }
445
446 pci_init_nic_devices(pci_bus, mc->default_nic);
447
448 /* The NewWorld NVRAM is not located in the MacIO device */
449 if (kvm_enabled() && qemu_real_host_page_size() > 4096) {
450 /* We can't combine read-write and read-only in a single page, so
451 move the NVRAM out of ROM again for KVM */
452 nvram_addr = 0xFFE00000;
453 }
454 dev = qdev_new(TYPE_MACIO_NVRAM);
455 qdev_prop_set_uint32(dev, "size", MACIO_NVRAM_SIZE);
456 qdev_prop_set_uint32(dev, "it_shift", 1);
457 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
458 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr);
459 nvr = MACIO_NVRAM(dev);
460 pmac_format_nvram_partition(nvr, MACIO_NVRAM_SIZE);
461 /* No PCI init: the BIOS will do it */
462
463 dev = qdev_new(TYPE_FW_CFG_MEM);
464 fw_cfg = FW_CFG(dev);
465 qdev_prop_set_uint32(dev, "data_width", 1);
466 qdev_prop_set_bit(dev, "dma_enabled", false);
467 object_property_add_child(OBJECT(machine), TYPE_FW_CFG, OBJECT(fw_cfg));
468 s = SYS_BUS_DEVICE(dev);
469 sysbus_realize_and_unref(s, &error_fatal);
470 sysbus_mmio_map(s, 0, CFG_ADDR);
471 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
472
473 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
474 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
475 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
476 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
477 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
478 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
479 if (machine->kernel_cmdline) {
480 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
481 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
482 machine->kernel_cmdline);
483 } else {
484 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
485 }
486 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
487 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
488 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
489
490 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
491 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
492 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
493
494 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_VIACONFIG, core99_machine->via_config);
495
496 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
497 if (kvm_enabled()) {
498 uint8_t *hypercall;
499
500 hypercall = g_malloc(16);
501 kvmppc_get_hypercall(env, hypercall, 16);
502 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
503 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
504 }
505 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
506 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
507 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
508 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
509 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr);
510
511 /* MacOS NDRV VGA driver */
512 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
513 if (filename) {
514 gchar *ndrv_file;
515 gsize ndrv_size;
516
517 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) {
518 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
519 }
520 g_free(filename);
521 }
522
523 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
524 }
525
526 /*
527 * Implementation of an interface to adjust firmware path
528 * for the bootindex property handling.
529 */
core99_fw_dev_path(FWPathProvider * p,BusState * bus,DeviceState * dev)530 static char *core99_fw_dev_path(FWPathProvider *p, BusState *bus,
531 DeviceState *dev)
532 {
533 PCIDevice *pci;
534 MACIOIDEState *macio_ide;
535
536 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-newworld")) {
537 pci = PCI_DEVICE(dev);
538 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn));
539 }
540
541 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) {
542 macio_ide = MACIO_IDE(dev);
543 return g_strdup_printf("ata-3@%x", macio_ide->addr);
544 }
545
546 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
547 return g_strdup("disk");
548 }
549
550 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
551 return g_strdup("cdrom");
552 }
553
554 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
555 return g_strdup("disk");
556 }
557
558 return NULL;
559 }
core99_kvm_type(MachineState * machine,const char * arg)560 static int core99_kvm_type(MachineState *machine, const char *arg)
561 {
562 /* Always force PR KVM */
563 return 2;
564 }
565
core99_machine_class_init(ObjectClass * oc,const void * data)566 static void core99_machine_class_init(ObjectClass *oc, const void *data)
567 {
568 MachineClass *mc = MACHINE_CLASS(oc);
569 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
570
571 mc->desc = "Mac99 based PowerMac";
572 mc->init = ppc_core99_init;
573 mc->block_default_type = IF_IDE;
574 /* SMP is not supported currently */
575 mc->max_cpus = 1;
576 mc->default_boot_order = "cd";
577 mc->default_display = "std";
578 mc->default_nic = "sungem";
579 mc->kvm_type = core99_kvm_type;
580 #ifdef TARGET_PPC64
581 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("970fx_v3.1");
582 #else
583 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9");
584 #endif
585 mc->default_ram_id = "ppc_core99.ram";
586 mc->ignore_boot_device_suffixes = true;
587 fwc->get_dev_path = core99_fw_dev_path;
588 }
589
core99_get_via_config(Object * obj,Error ** errp)590 static char *core99_get_via_config(Object *obj, Error **errp)
591 {
592 Core99MachineState *cms = CORE99_MACHINE(obj);
593
594 switch (cms->via_config) {
595 default:
596 case CORE99_VIA_CONFIG_CUDA:
597 return g_strdup("cuda");
598
599 case CORE99_VIA_CONFIG_PMU:
600 return g_strdup("pmu");
601
602 case CORE99_VIA_CONFIG_PMU_ADB:
603 return g_strdup("pmu-adb");
604 }
605 }
606
core99_set_via_config(Object * obj,const char * value,Error ** errp)607 static void core99_set_via_config(Object *obj, const char *value, Error **errp)
608 {
609 Core99MachineState *cms = CORE99_MACHINE(obj);
610
611 if (!strcmp(value, "cuda")) {
612 cms->via_config = CORE99_VIA_CONFIG_CUDA;
613 } else if (!strcmp(value, "pmu")) {
614 cms->via_config = CORE99_VIA_CONFIG_PMU;
615 } else if (!strcmp(value, "pmu-adb")) {
616 cms->via_config = CORE99_VIA_CONFIG_PMU_ADB;
617 } else {
618 error_setg(errp, "Invalid via value");
619 error_append_hint(errp, "Valid values are cuda, pmu, pmu-adb.\n");
620 }
621 }
622
core99_instance_init(Object * obj)623 static void core99_instance_init(Object *obj)
624 {
625 Core99MachineState *cms = CORE99_MACHINE(obj);
626
627 /* Default via_config is CORE99_VIA_CONFIG_CUDA */
628 cms->via_config = CORE99_VIA_CONFIG_CUDA;
629 object_property_add_str(obj, "via", core99_get_via_config,
630 core99_set_via_config);
631 object_property_set_description(obj, "via",
632 "Set VIA configuration. "
633 "Valid values are cuda, pmu and pmu-adb");
634 }
635
636 static const TypeInfo core99_machine_info = {
637 .name = MACHINE_TYPE_NAME("mac99"),
638 .parent = TYPE_MACHINE,
639 .class_init = core99_machine_class_init,
640 .instance_init = core99_instance_init,
641 .instance_size = sizeof(Core99MachineState),
642 .interfaces = (const InterfaceInfo[]) {
643 { TYPE_FW_PATH_PROVIDER },
644 { }
645 },
646 };
647
mac_machine_register_types(void)648 static void mac_machine_register_types(void)
649 {
650 type_register_static(&core99_machine_info);
651 }
652
653 type_init(mac_machine_register_types)
654