1 /*
2 * All test cases of nested virtualization should be in this file
3 *
4 * Author : Arthur Chunqi Li <yzt356@gmail.com>
5 */
6
7 #include <asm/debugreg.h>
8
9 #include "vmx.h"
10 #include "msr.h"
11 #include "processor.h"
12 #include "pmu.h"
13 #include "vm.h"
14 #include "pci.h"
15 #include "fwcfg.h"
16 #include "isr.h"
17 #include "desc.h"
18 #include "apic.h"
19 #include "vmalloc.h"
20 #include "alloc_page.h"
21 #include "smp.h"
22 #include "delay.h"
23 #include "access.h"
24 #include "x86/usermode.h"
25
26 /*
27 * vmcs.GUEST_PENDING_DEBUG has the same format as DR6, although some bits that
28 * are legal in DR6 are reserved in vmcs.GUEST_PENDING_DEBUG. And if any data
29 * or I/O breakpoint matches *and* was enabled, bit 12 is also set.
30 */
31 #define PENDING_DBG_TRAP BIT(12)
32
33 #define VPID_CAP_INVVPID_TYPES_SHIFT 40
34
35 u64 ia32_pat;
36 u64 ia32_efer;
37 void *io_bitmap_a, *io_bitmap_b;
38 u16 ioport;
39
40 unsigned long *pml4;
41 u64 eptp;
42 void *data_page1, *data_page2;
43
44 phys_addr_t pci_physaddr;
45
46 void *pml_log;
47 #define PML_INDEX 512
48
ffs(unsigned x)49 static inline unsigned ffs(unsigned x)
50 {
51 int pos = -1;
52
53 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0"
54 : "+r"(pos) : "rm"(x) : "eax");
55 return pos + 1;
56 }
57
vmcall(void)58 static inline void vmcall(void)
59 {
60 asm volatile("vmcall");
61 }
62
get_vapic_page(void)63 static u32 *get_vapic_page(void)
64 {
65 return (u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR));
66 }
67
get_pi_desc(void)68 static u64 *get_pi_desc(void)
69 {
70 return (u64 *)phys_to_virt(vmcs_read(POSTED_INTR_DESC_ADDR));
71 }
72
basic_guest_main(void)73 static void basic_guest_main(void)
74 {
75 report_pass("Basic VMX test");
76 }
77
basic_exit_handler(union exit_reason exit_reason)78 static int basic_exit_handler(union exit_reason exit_reason)
79 {
80 report_fail("Basic VMX test");
81 print_vmexit_info(exit_reason);
82 return VMX_TEST_EXIT;
83 }
84
vmenter_main(void)85 static void vmenter_main(void)
86 {
87 u64 rax;
88 u64 rsp, resume_rsp;
89
90 report_pass("test vmlaunch");
91
92 asm volatile(
93 "mov %%rsp, %0\n\t"
94 "mov %3, %%rax\n\t"
95 "vmcall\n\t"
96 "mov %%rax, %1\n\t"
97 "mov %%rsp, %2\n\t"
98 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp)
99 : "g"(0xABCD));
100 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume");
101 }
102
vmenter_exit_handler(union exit_reason exit_reason)103 static int vmenter_exit_handler(union exit_reason exit_reason)
104 {
105 u64 guest_rip = vmcs_read(GUEST_RIP);
106
107 switch (exit_reason.basic) {
108 case VMX_VMCALL:
109 if (regs.rax != 0xABCD) {
110 report_fail("test vmresume");
111 return VMX_TEST_VMEXIT;
112 }
113 regs.rax = 0xFFFF;
114 vmcs_write(GUEST_RIP, guest_rip + 3);
115 return VMX_TEST_RESUME;
116 default:
117 report_fail("test vmresume");
118 print_vmexit_info(exit_reason);
119 }
120 return VMX_TEST_VMEXIT;
121 }
122
123 u32 preempt_scale;
124 volatile unsigned long long tsc_val;
125 volatile u32 preempt_val;
126 u64 saved_rip;
127
preemption_timer_init(struct vmcs * vmcs)128 static int preemption_timer_init(struct vmcs *vmcs)
129 {
130 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) {
131 printf("\tPreemption timer is not supported\n");
132 return VMX_TEST_EXIT;
133 }
134 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT);
135 preempt_val = 10000000;
136 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val);
137 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F;
138
139 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT))
140 printf("\tSave preemption value is not supported\n");
141
142 return VMX_TEST_START;
143 }
144
preemption_timer_main(void)145 static void preemption_timer_main(void)
146 {
147 tsc_val = rdtsc();
148 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) {
149 vmx_set_test_stage(0);
150 vmcall();
151 if (vmx_get_test_stage() == 1)
152 vmcall();
153 }
154 vmx_set_test_stage(1);
155 while (vmx_get_test_stage() == 1) {
156 if (((rdtsc() - tsc_val) >> preempt_scale)
157 > 10 * preempt_val) {
158 vmx_set_test_stage(2);
159 vmcall();
160 }
161 }
162 tsc_val = rdtsc();
163 asm volatile ("hlt");
164 vmcall();
165 vmx_set_test_stage(5);
166 vmcall();
167 }
168
preemption_timer_exit_handler(union exit_reason exit_reason)169 static int preemption_timer_exit_handler(union exit_reason exit_reason)
170 {
171 bool guest_halted;
172 u64 guest_rip;
173 u32 insn_len;
174 u32 ctrl_exit;
175
176 guest_rip = vmcs_read(GUEST_RIP);
177 insn_len = vmcs_read(EXI_INST_LEN);
178 switch (exit_reason.basic) {
179 case VMX_PREEMPT:
180 switch (vmx_get_test_stage()) {
181 case 1:
182 case 2:
183 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val,
184 "busy-wait for preemption timer");
185 vmx_set_test_stage(3);
186 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val);
187 return VMX_TEST_RESUME;
188 case 3:
189 guest_halted =
190 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT);
191 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val
192 && guest_halted,
193 "preemption timer during hlt");
194 vmx_set_test_stage(4);
195 vmcs_write(PIN_CONTROLS,
196 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT);
197 vmcs_write(EXI_CONTROLS,
198 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT);
199 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE);
200 return VMX_TEST_RESUME;
201 case 4:
202 report(saved_rip == guest_rip,
203 "preemption timer with 0 value");
204 break;
205 default:
206 report_fail("Invalid stage.");
207 print_vmexit_info(exit_reason);
208 break;
209 }
210 break;
211 case VMX_VMCALL:
212 vmcs_write(GUEST_RIP, guest_rip + insn_len);
213 switch (vmx_get_test_stage()) {
214 case 0:
215 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val,
216 "Keep preemption value");
217 vmx_set_test_stage(1);
218 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val);
219 ctrl_exit = (vmcs_read(EXI_CONTROLS) |
220 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr;
221 vmcs_write(EXI_CONTROLS, ctrl_exit);
222 return VMX_TEST_RESUME;
223 case 1:
224 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val,
225 "Save preemption value");
226 return VMX_TEST_RESUME;
227 case 2:
228 report_fail("busy-wait for preemption timer");
229 vmx_set_test_stage(3);
230 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val);
231 return VMX_TEST_RESUME;
232 case 3:
233 report_fail("preemption timer during hlt");
234 vmx_set_test_stage(4);
235 /* fall through */
236 case 4:
237 vmcs_write(PIN_CONTROLS,
238 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT);
239 vmcs_write(PREEMPT_TIMER_VALUE, 0);
240 saved_rip = guest_rip + insn_len;
241 return VMX_TEST_RESUME;
242 case 5:
243 report_fail("preemption timer with 0 value (vmcall stage 5)");
244 break;
245 default:
246 // Should not reach here
247 report_fail("unexpected stage, %d",
248 vmx_get_test_stage());
249 print_vmexit_info(exit_reason);
250 return VMX_TEST_VMEXIT;
251 }
252 break;
253 default:
254 report_fail("Unknown exit reason, 0x%x", exit_reason.full);
255 print_vmexit_info(exit_reason);
256 }
257 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT);
258 return VMX_TEST_VMEXIT;
259 }
260
msr_bmp_init(void)261 static void msr_bmp_init(void)
262 {
263 void *msr_bitmap;
264 u32 ctrl_cpu0;
265
266 msr_bitmap = alloc_page();
267 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0);
268 ctrl_cpu0 |= CPU_MSR_BITMAP;
269 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0);
270 vmcs_write(MSR_BITMAP, (u64)msr_bitmap);
271 }
272
get_msr_bitmap(void)273 static void *get_msr_bitmap(void)
274 {
275 void *msr_bitmap;
276
277 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) {
278 msr_bitmap = (void *)vmcs_read(MSR_BITMAP);
279 } else {
280 msr_bitmap = alloc_page();
281 memset(msr_bitmap, 0xff, PAGE_SIZE);
282 vmcs_write(MSR_BITMAP, (u64)msr_bitmap);
283 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP);
284 }
285
286 return msr_bitmap;
287 }
288
disable_intercept_for_x2apic_msrs(void)289 static void disable_intercept_for_x2apic_msrs(void)
290 {
291 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap();
292 u32 msr;
293
294 for (msr = APIC_BASE_MSR;
295 msr < (APIC_BASE_MSR+0xff);
296 msr += BITS_PER_LONG) {
297 unsigned int word = msr / BITS_PER_LONG;
298
299 msr_bitmap[word] = 0;
300 msr_bitmap[word + (0x800 / sizeof(long))] = 0;
301 }
302 }
303
test_ctrl_pat_init(struct vmcs * vmcs)304 static int test_ctrl_pat_init(struct vmcs *vmcs)
305 {
306 u64 ctrl_ent;
307 u64 ctrl_exi;
308
309 msr_bmp_init();
310 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) &&
311 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) &&
312 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) {
313 printf("\tSave/load PAT is not supported\n");
314 return 1;
315 }
316
317 ctrl_ent = vmcs_read(ENT_CONTROLS);
318 ctrl_exi = vmcs_read(EXI_CONTROLS);
319 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT;
320 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT);
321 vmcs_write(ENT_CONTROLS, ctrl_ent);
322 vmcs_write(EXI_CONTROLS, ctrl_exi);
323 ia32_pat = rdmsr(MSR_IA32_CR_PAT);
324 vmcs_write(GUEST_PAT, 0x0);
325 vmcs_write(HOST_PAT, ia32_pat);
326 return VMX_TEST_START;
327 }
328
test_ctrl_pat_main(void)329 static void test_ctrl_pat_main(void)
330 {
331 u64 guest_ia32_pat;
332
333 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT);
334 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT))
335 printf("\tENT_LOAD_PAT is not supported.\n");
336 else {
337 if (guest_ia32_pat != 0) {
338 report_fail("Entry load PAT");
339 return;
340 }
341 }
342 wrmsr(MSR_IA32_CR_PAT, 0x6);
343 vmcall();
344 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT);
345 if (ctrl_enter_rev.clr & ENT_LOAD_PAT)
346 report(guest_ia32_pat == ia32_pat, "Entry load PAT");
347 }
348
test_ctrl_pat_exit_handler(union exit_reason exit_reason)349 static int test_ctrl_pat_exit_handler(union exit_reason exit_reason)
350 {
351 u64 guest_rip;
352 u64 guest_pat;
353
354 guest_rip = vmcs_read(GUEST_RIP);
355 switch (exit_reason.basic) {
356 case VMX_VMCALL:
357 guest_pat = vmcs_read(GUEST_PAT);
358 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) {
359 printf("\tEXI_SAVE_PAT is not supported\n");
360 vmcs_write(GUEST_PAT, 0x6);
361 } else {
362 report(guest_pat == 0x6, "Exit save PAT");
363 }
364 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT))
365 printf("\tEXI_LOAD_PAT is not supported\n");
366 else
367 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat,
368 "Exit load PAT");
369 vmcs_write(GUEST_PAT, ia32_pat);
370 vmcs_write(GUEST_RIP, guest_rip + 3);
371 return VMX_TEST_RESUME;
372 default:
373 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full);
374 break;
375 }
376 return VMX_TEST_VMEXIT;
377 }
378
test_ctrl_efer_init(struct vmcs * vmcs)379 static int test_ctrl_efer_init(struct vmcs *vmcs)
380 {
381 u64 ctrl_ent;
382 u64 ctrl_exi;
383
384 msr_bmp_init();
385 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER;
386 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER;
387 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr);
388 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr);
389 ia32_efer = rdmsr(MSR_EFER);
390 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX);
391 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX);
392 return VMX_TEST_START;
393 }
394
test_ctrl_efer_main(void)395 static void test_ctrl_efer_main(void)
396 {
397 u64 guest_ia32_efer;
398
399 guest_ia32_efer = rdmsr(MSR_EFER);
400 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER))
401 printf("\tENT_LOAD_EFER is not supported.\n");
402 else {
403 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) {
404 report_fail("Entry load EFER");
405 return;
406 }
407 }
408 wrmsr(MSR_EFER, ia32_efer);
409 vmcall();
410 guest_ia32_efer = rdmsr(MSR_EFER);
411 if (ctrl_enter_rev.clr & ENT_LOAD_EFER)
412 report(guest_ia32_efer == ia32_efer, "Entry load EFER");
413 }
414
test_ctrl_efer_exit_handler(union exit_reason exit_reason)415 static int test_ctrl_efer_exit_handler(union exit_reason exit_reason)
416 {
417 u64 guest_rip;
418 u64 guest_efer;
419
420 guest_rip = vmcs_read(GUEST_RIP);
421 switch (exit_reason.basic) {
422 case VMX_VMCALL:
423 guest_efer = vmcs_read(GUEST_EFER);
424 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) {
425 printf("\tEXI_SAVE_EFER is not supported\n");
426 vmcs_write(GUEST_EFER, ia32_efer);
427 } else {
428 report(guest_efer == ia32_efer, "Exit save EFER");
429 }
430 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) {
431 printf("\tEXI_LOAD_EFER is not supported\n");
432 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX);
433 } else {
434 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX),
435 "Exit load EFER");
436 }
437 vmcs_write(GUEST_PAT, ia32_efer);
438 vmcs_write(GUEST_RIP, guest_rip + 3);
439 return VMX_TEST_RESUME;
440 default:
441 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full);
442 break;
443 }
444 return VMX_TEST_VMEXIT;
445 }
446
447 u32 guest_cr0, guest_cr4;
448
cr_shadowing_main(void)449 static void cr_shadowing_main(void)
450 {
451 u32 cr0, cr4, tmp;
452
453 // Test read through
454 vmx_set_test_stage(0);
455 guest_cr0 = read_cr0();
456 if (vmx_get_test_stage() == 1)
457 report_fail("Read through CR0");
458 else
459 vmcall();
460 vmx_set_test_stage(1);
461 guest_cr4 = read_cr4();
462 if (vmx_get_test_stage() == 2)
463 report_fail("Read through CR4");
464 else
465 vmcall();
466 // Test write through
467 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP);
468 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE);
469 vmx_set_test_stage(2);
470 write_cr0(guest_cr0);
471 if (vmx_get_test_stage() == 3)
472 report_fail("Write through CR0");
473 else
474 vmcall();
475 vmx_set_test_stage(3);
476 write_cr4(guest_cr4);
477 if (vmx_get_test_stage() == 4)
478 report_fail("Write through CR4");
479 else
480 vmcall();
481 // Test read shadow
482 vmx_set_test_stage(4);
483 vmcall();
484 cr0 = read_cr0();
485 if (vmx_get_test_stage() != 5)
486 report(cr0 == guest_cr0, "Read shadowing CR0");
487 vmx_set_test_stage(5);
488 cr4 = read_cr4();
489 if (vmx_get_test_stage() != 6)
490 report(cr4 == guest_cr4, "Read shadowing CR4");
491 // Test write shadow (same value with shadow)
492 vmx_set_test_stage(6);
493 write_cr0(guest_cr0);
494 if (vmx_get_test_stage() == 7)
495 report_fail("Write shadowing CR0 (same value with shadow)");
496 else
497 vmcall();
498 vmx_set_test_stage(7);
499 write_cr4(guest_cr4);
500 if (vmx_get_test_stage() == 8)
501 report_fail("Write shadowing CR4 (same value with shadow)");
502 else
503 vmcall();
504 // Test write shadow (different value)
505 vmx_set_test_stage(8);
506 tmp = guest_cr0 ^ X86_CR0_TS;
507 asm volatile("mov %0, %%rsi\n\t"
508 "mov %%rsi, %%cr0\n\t"
509 ::"m"(tmp)
510 :"rsi", "memory", "cc");
511 report(vmx_get_test_stage() == 9,
512 "Write shadowing different X86_CR0_TS");
513 vmx_set_test_stage(9);
514 tmp = guest_cr0 ^ X86_CR0_MP;
515 asm volatile("mov %0, %%rsi\n\t"
516 "mov %%rsi, %%cr0\n\t"
517 ::"m"(tmp)
518 :"rsi", "memory", "cc");
519 report(vmx_get_test_stage() == 10,
520 "Write shadowing different X86_CR0_MP");
521 vmx_set_test_stage(10);
522 tmp = guest_cr4 ^ X86_CR4_TSD;
523 asm volatile("mov %0, %%rsi\n\t"
524 "mov %%rsi, %%cr4\n\t"
525 ::"m"(tmp)
526 :"rsi", "memory", "cc");
527 report(vmx_get_test_stage() == 11,
528 "Write shadowing different X86_CR4_TSD");
529 vmx_set_test_stage(11);
530 tmp = guest_cr4 ^ X86_CR4_DE;
531 asm volatile("mov %0, %%rsi\n\t"
532 "mov %%rsi, %%cr4\n\t"
533 ::"m"(tmp)
534 :"rsi", "memory", "cc");
535 report(vmx_get_test_stage() == 12,
536 "Write shadowing different X86_CR4_DE");
537 }
538
cr_shadowing_exit_handler(union exit_reason exit_reason)539 static int cr_shadowing_exit_handler(union exit_reason exit_reason)
540 {
541 u64 guest_rip;
542 u32 insn_len;
543 u32 exit_qual;
544
545 guest_rip = vmcs_read(GUEST_RIP);
546 insn_len = vmcs_read(EXI_INST_LEN);
547 exit_qual = vmcs_read(EXI_QUALIFICATION);
548 switch (exit_reason.basic) {
549 case VMX_VMCALL:
550 switch (vmx_get_test_stage()) {
551 case 0:
552 report(guest_cr0 == vmcs_read(GUEST_CR0),
553 "Read through CR0");
554 break;
555 case 1:
556 report(guest_cr4 == vmcs_read(GUEST_CR4),
557 "Read through CR4");
558 break;
559 case 2:
560 report(guest_cr0 == vmcs_read(GUEST_CR0),
561 "Write through CR0");
562 break;
563 case 3:
564 report(guest_cr4 == vmcs_read(GUEST_CR4),
565 "Write through CR4");
566 break;
567 case 4:
568 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP);
569 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE);
570 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP);
571 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP));
572 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE);
573 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE));
574 break;
575 case 6:
576 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)),
577 "Write shadowing CR0 (same value)");
578 break;
579 case 7:
580 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)),
581 "Write shadowing CR4 (same value)");
582 break;
583 default:
584 // Should not reach here
585 report_fail("unexpected stage, %d",
586 vmx_get_test_stage());
587 print_vmexit_info(exit_reason);
588 return VMX_TEST_VMEXIT;
589 }
590 vmcs_write(GUEST_RIP, guest_rip + insn_len);
591 return VMX_TEST_RESUME;
592 case VMX_CR:
593 switch (vmx_get_test_stage()) {
594 case 4:
595 report_fail("Read shadowing CR0");
596 vmx_inc_test_stage();
597 break;
598 case 5:
599 report_fail("Read shadowing CR4");
600 vmx_inc_test_stage();
601 break;
602 case 6:
603 report_fail("Write shadowing CR0 (same value)");
604 vmx_inc_test_stage();
605 break;
606 case 7:
607 report_fail("Write shadowing CR4 (same value)");
608 vmx_inc_test_stage();
609 break;
610 case 8:
611 case 9:
612 // 0x600 encodes "mov %esi, %cr0"
613 if (exit_qual == 0x600)
614 vmx_inc_test_stage();
615 break;
616 case 10:
617 case 11:
618 // 0x604 encodes "mov %esi, %cr4"
619 if (exit_qual == 0x604)
620 vmx_inc_test_stage();
621 break;
622 default:
623 // Should not reach here
624 report_fail("unexpected stage, %d",
625 vmx_get_test_stage());
626 print_vmexit_info(exit_reason);
627 return VMX_TEST_VMEXIT;
628 }
629 vmcs_write(GUEST_RIP, guest_rip + insn_len);
630 return VMX_TEST_RESUME;
631 default:
632 report_fail("Unknown exit reason, 0x%x", exit_reason.full);
633 print_vmexit_info(exit_reason);
634 }
635 return VMX_TEST_VMEXIT;
636 }
637
iobmp_init(struct vmcs * vmcs)638 static int iobmp_init(struct vmcs *vmcs)
639 {
640 u32 ctrl_cpu0;
641
642 io_bitmap_a = alloc_page();
643 io_bitmap_b = alloc_page();
644 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0);
645 ctrl_cpu0 |= CPU_IO_BITMAP;
646 ctrl_cpu0 &= (~CPU_IO);
647 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0);
648 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a);
649 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b);
650 return VMX_TEST_START;
651 }
652
iobmp_main(void)653 static void iobmp_main(void)
654 {
655 // stage 0, test IO pass
656 vmx_set_test_stage(0);
657 inb(0x5000);
658 outb(0x0, 0x5000);
659 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass");
660 // test IO width, in/out
661 ((u8 *)io_bitmap_a)[0] = 0xFF;
662 vmx_set_test_stage(2);
663 inb(0x0);
664 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in");
665 vmx_set_test_stage(3);
666 outw(0x0, 0x0);
667 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out");
668 vmx_set_test_stage(4);
669 inl(0x0);
670 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long");
671 // test low/high IO port
672 vmx_set_test_stage(5);
673 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8));
674 inb(0x5000);
675 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part");
676 vmx_set_test_stage(6);
677 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8));
678 inb(0x9000);
679 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part");
680 // test partial pass
681 vmx_set_test_stage(7);
682 inl(0x4FFF);
683 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass");
684 // test overrun
685 vmx_set_test_stage(8);
686 memset(io_bitmap_a, 0x0, PAGE_SIZE);
687 memset(io_bitmap_b, 0x0, PAGE_SIZE);
688 inl(0xFFFF);
689 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun");
690 vmx_set_test_stage(9);
691 vmcall();
692 outb(0x0, 0x0);
693 report(vmx_get_test_stage() == 9,
694 "I/O bitmap - ignore unconditional exiting");
695 vmx_set_test_stage(10);
696 vmcall();
697 outb(0x0, 0x0);
698 report(vmx_get_test_stage() == 11,
699 "I/O bitmap - unconditional exiting");
700 }
701
iobmp_exit_handler(union exit_reason exit_reason)702 static int iobmp_exit_handler(union exit_reason exit_reason)
703 {
704 u64 guest_rip;
705 ulong exit_qual;
706 u32 insn_len, ctrl_cpu0;
707
708 guest_rip = vmcs_read(GUEST_RIP);
709 exit_qual = vmcs_read(EXI_QUALIFICATION);
710 insn_len = vmcs_read(EXI_INST_LEN);
711 switch (exit_reason.basic) {
712 case VMX_IO:
713 switch (vmx_get_test_stage()) {
714 case 0:
715 case 1:
716 vmx_inc_test_stage();
717 break;
718 case 2:
719 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE,
720 "I/O bitmap - I/O width, byte");
721 report(exit_qual & VMX_IO_IN,
722 "I/O bitmap - I/O direction, in");
723 vmx_inc_test_stage();
724 break;
725 case 3:
726 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD,
727 "I/O bitmap - I/O width, word");
728 report(!(exit_qual & VMX_IO_IN),
729 "I/O bitmap - I/O direction, out");
730 vmx_inc_test_stage();
731 break;
732 case 4:
733 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG,
734 "I/O bitmap - I/O width, long");
735 vmx_inc_test_stage();
736 break;
737 case 5:
738 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000)
739 vmx_inc_test_stage();
740 break;
741 case 6:
742 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000)
743 vmx_inc_test_stage();
744 break;
745 case 7:
746 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF)
747 vmx_inc_test_stage();
748 break;
749 case 8:
750 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF)
751 vmx_inc_test_stage();
752 break;
753 case 9:
754 case 10:
755 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0);
756 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO);
757 vmx_inc_test_stage();
758 break;
759 default:
760 // Should not reach here
761 report_fail("unexpected stage, %d",
762 vmx_get_test_stage());
763 print_vmexit_info(exit_reason);
764 return VMX_TEST_VMEXIT;
765 }
766 vmcs_write(GUEST_RIP, guest_rip + insn_len);
767 return VMX_TEST_RESUME;
768 case VMX_VMCALL:
769 switch (vmx_get_test_stage()) {
770 case 9:
771 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0);
772 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP;
773 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0);
774 break;
775 case 10:
776 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0);
777 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO;
778 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0);
779 break;
780 default:
781 // Should not reach here
782 report_fail("unexpected stage, %d",
783 vmx_get_test_stage());
784 print_vmexit_info(exit_reason);
785 return VMX_TEST_VMEXIT;
786 }
787 vmcs_write(GUEST_RIP, guest_rip + insn_len);
788 return VMX_TEST_RESUME;
789 default:
790 printf("guest_rip = %#lx\n", guest_rip);
791 printf("\tERROR : Unknown exit reason, 0x%x\n", exit_reason.full);
792 break;
793 }
794 return VMX_TEST_VMEXIT;
795 }
796
797 #define INSN_CPU0 0
798 #define INSN_CPU1 1
799 #define INSN_ALWAYS_TRAP 2
800
801 #define FIELD_EXIT_QUAL (1 << 0)
802 #define FIELD_INSN_INFO (1 << 1)
803
804 asm(
805 "insn_hlt: hlt;ret\n\t"
806 "insn_invlpg: invlpg 0x12345678;ret\n\t"
807 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t"
808 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t"
809 "insn_rdtsc: rdtsc;ret\n\t"
810 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t"
811 "insn_cr3_store: mov %cr3,%rax;ret\n\t"
812 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t"
813 "insn_cr8_store: mov %cr8,%rax;ret\n\t"
814 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t"
815 "insn_pause: pause;ret\n\t"
816 "insn_wbinvd: wbinvd;ret\n\t"
817 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t"
818 "insn_invd: invd;ret\n\t"
819 "insn_sgdt: sgdt gdt_descr;ret\n\t"
820 "insn_lgdt: lgdt gdt_descr;ret\n\t"
821 "insn_sidt: sidt idt_descr;ret\n\t"
822 "insn_lidt: lidt idt_descr;ret\n\t"
823 "insn_sldt: sldt %ax;ret\n\t"
824 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t"
825 "insn_str: str %ax;ret\n\t"
826 "insn_rdrand: rdrand %rax;ret\n\t"
827 "insn_rdseed: rdseed %rax;ret\n\t"
828 );
829 extern void insn_hlt(void);
830 extern void insn_invlpg(void);
831 extern void insn_mwait(void);
832 extern void insn_rdpmc(void);
833 extern void insn_rdtsc(void);
834 extern void insn_cr3_load(void);
835 extern void insn_cr3_store(void);
836 extern void insn_cr8_load(void);
837 extern void insn_cr8_store(void);
838 extern void insn_monitor(void);
839 extern void insn_pause(void);
840 extern void insn_wbinvd(void);
841 extern void insn_sgdt(void);
842 extern void insn_lgdt(void);
843 extern void insn_sidt(void);
844 extern void insn_lidt(void);
845 extern void insn_sldt(void);
846 extern void insn_lldt(void);
847 extern void insn_str(void);
848 extern void insn_cpuid(void);
849 extern void insn_invd(void);
850 extern void insn_rdrand(void);
851 extern void insn_rdseed(void);
852
853 u32 cur_insn;
854 u64 cr3;
855
856 typedef bool (*supported_fn)(void);
857
this_cpu_has_mwait(void)858 static bool this_cpu_has_mwait(void)
859 {
860 return this_cpu_has(X86_FEATURE_MWAIT);
861 }
862
863 struct insn_table {
864 const char *name;
865 u32 flag;
866 void (*insn_func)(void);
867 u32 type;
868 u32 reason;
869 ulong exit_qual;
870 u32 insn_info;
871 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define
872 // which field need to be tested, reason is always tested
873 u32 test_field;
874 const supported_fn supported_fn;
875 u8 disabled;
876 };
877
878 /*
879 * Add more test cases of instruction intercept here. Elements in this
880 * table is:
881 * name/control flag/insn function/type/exit reason/exit qulification/
882 * instruction info/field to test
883 * The last field defines which fields (exit_qual and insn_info) need to be
884 * tested in exit handler. If set to 0, only "reason" is checked.
885 */
886 static struct insn_table insn_table[] = {
887 // Flags for Primary Processor-Based VM-Execution Controls
888 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0},
889 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14,
890 0x12345678, 0, FIELD_EXIT_QUAL},
891 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, this_cpu_has_mwait},
892 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0, this_cpu_has_pmu},
893 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0},
894 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0,
895 FIELD_EXIT_QUAL},
896 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0,
897 FIELD_EXIT_QUAL},
898 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0,
899 FIELD_EXIT_QUAL},
900 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0,
901 FIELD_EXIT_QUAL},
902 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, this_cpu_has_mwait},
903 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0},
904 // Flags for Secondary Processor-Based VM-Execution Controls
905 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0},
906 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0},
907 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0},
908 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0},
909 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0},
910 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0},
911 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0},
912 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0},
913 /* LTR causes a #GP if done with a busy selector, so it is not tested. */
914 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0},
915 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0},
916 // Instructions always trap
917 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0},
918 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0},
919 // Instructions never trap
920 {NULL},
921 };
922
insn_intercept_init(struct vmcs * vmcs)923 static int insn_intercept_init(struct vmcs *vmcs)
924 {
925 u32 ctrl_cpu, cur_insn;
926
927 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY;
928 ctrl_cpu &= ctrl_cpu_rev[0].clr;
929 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu);
930 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set);
931 cr3 = read_cr3();
932
933 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) {
934 if (insn_table[cur_insn].supported_fn == NULL)
935 continue;
936 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn();
937 }
938 return VMX_TEST_START;
939 }
940
insn_intercept_main(void)941 static void insn_intercept_main(void)
942 {
943 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) {
944 vmx_set_test_stage(cur_insn * 2);
945 if ((insn_table[cur_insn].type == INSN_CPU0 &&
946 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) ||
947 (insn_table[cur_insn].type == INSN_CPU1 &&
948 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) {
949 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n",
950 insn_table[cur_insn].type - INSN_CPU0,
951 insn_table[cur_insn].name);
952 continue;
953 }
954
955 if (insn_table[cur_insn].disabled) {
956 printf("\tFeature required for %s is not supported.\n",
957 insn_table[cur_insn].name);
958 continue;
959 }
960
961 if ((insn_table[cur_insn].type == INSN_CPU0 &&
962 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) ||
963 (insn_table[cur_insn].type == INSN_CPU1 &&
964 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) {
965 /* skip hlt, it stalls the guest and is tested below */
966 if (insn_table[cur_insn].insn_func != insn_hlt)
967 insn_table[cur_insn].insn_func();
968 report(vmx_get_test_stage() == cur_insn * 2,
969 "execute %s",
970 insn_table[cur_insn].name);
971 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP)
972 printf("\tCPU_CTRL%d.CPU_%s always traps.\n",
973 insn_table[cur_insn].type - INSN_CPU0,
974 insn_table[cur_insn].name);
975
976 vmcall();
977
978 insn_table[cur_insn].insn_func();
979 report(vmx_get_test_stage() == cur_insn * 2 + 1,
980 "intercept %s",
981 insn_table[cur_insn].name);
982
983 vmx_set_test_stage(cur_insn * 2 + 1);
984 vmcall();
985 }
986 }
987
insn_intercept_exit_handler(union exit_reason exit_reason)988 static int insn_intercept_exit_handler(union exit_reason exit_reason)
989 {
990 u64 guest_rip;
991 ulong exit_qual;
992 u32 insn_len;
993 u32 insn_info;
994 bool pass;
995
996 guest_rip = vmcs_read(GUEST_RIP);
997 exit_qual = vmcs_read(EXI_QUALIFICATION);
998 insn_len = vmcs_read(EXI_INST_LEN);
999 insn_info = vmcs_read(EXI_INST_INFO);
1000
1001 if (exit_reason.basic == VMX_VMCALL) {
1002 u32 val = 0;
1003
1004 if (insn_table[cur_insn].type == INSN_CPU0)
1005 val = vmcs_read(CPU_EXEC_CTRL0);
1006 else if (insn_table[cur_insn].type == INSN_CPU1)
1007 val = vmcs_read(CPU_EXEC_CTRL1);
1008
1009 if (vmx_get_test_stage() & 1)
1010 val &= ~insn_table[cur_insn].flag;
1011 else
1012 val |= insn_table[cur_insn].flag;
1013
1014 if (insn_table[cur_insn].type == INSN_CPU0)
1015 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set);
1016 else if (insn_table[cur_insn].type == INSN_CPU1)
1017 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set);
1018 } else {
1019 pass = (cur_insn * 2 == vmx_get_test_stage()) &&
1020 insn_table[cur_insn].reason == exit_reason.full;
1021 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL &&
1022 insn_table[cur_insn].exit_qual != exit_qual)
1023 pass = false;
1024 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO &&
1025 insn_table[cur_insn].insn_info != insn_info)
1026 pass = false;
1027 if (pass)
1028 vmx_inc_test_stage();
1029 }
1030 vmcs_write(GUEST_RIP, guest_rip + insn_len);
1031 return VMX_TEST_RESUME;
1032 }
1033
1034 /**
1035 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT)
1036 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table
1037 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries
1038 *
1039 * Returns 0 on success, 1 on failure.
1040 *
1041 * Note that @hpa doesn't need to point at actual memory if VM-Launch is
1042 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy
1043 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'.
1044 */
__setup_ept(u64 hpa,bool enable_ad)1045 static int __setup_ept(u64 hpa, bool enable_ad)
1046 {
1047 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) ||
1048 !(ctrl_cpu_rev[1].clr & CPU_EPT)) {
1049 printf("\tEPT is not supported\n");
1050 return 1;
1051 }
1052 if (!is_ept_memtype_supported(EPT_MEM_TYPE_WB)) {
1053 printf("\tWB memtype for EPT walks not supported\n");
1054 return 1;
1055 }
1056
1057 if (!is_4_level_ept_supported()) {
1058 /* Support for 4-level EPT is mandatory. */
1059 report(false, "4-level EPT support check");
1060 printf("\tPWL4 is not supported\n");
1061 return 1;
1062 }
1063
1064 eptp = EPT_MEM_TYPE_WB;
1065 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT);
1066 eptp |= hpa;
1067 if (enable_ad)
1068 eptp |= EPTP_AD_FLAG;
1069
1070 vmcs_write(EPTP, eptp);
1071 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY);
1072 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT);
1073
1074 return 0;
1075 }
1076
1077 /**
1078 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map
1079 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries
1080 *
1081 * Returns 0 on success, 1 on failure.
1082 *
1083 * This is the "real" function for setting up EPT tables, i.e. use this for
1084 * tests that need to run code in the guest with EPT enabled.
1085 */
setup_ept(bool enable_ad)1086 static int setup_ept(bool enable_ad)
1087 {
1088 unsigned long end_of_memory;
1089
1090 pml4 = alloc_page();
1091
1092 if (__setup_ept(virt_to_phys(pml4), enable_ad))
1093 return 1;
1094
1095 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE);
1096 if (end_of_memory < (1ul << 32))
1097 end_of_memory = (1ul << 32);
1098 /* Cannot use large EPT pages if we need to track EPT
1099 * accessed/dirty bits at 4K granularity.
1100 */
1101 setup_ept_range(pml4, 0, end_of_memory, 0,
1102 !enable_ad && ept_2m_supported(),
1103 EPT_WA | EPT_RA | EPT_EA);
1104 return 0;
1105 }
1106
1107 /**
1108 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA
1109 *
1110 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended
1111 * for use by tests that need EPT enabled to verify dependent VMCS controls
1112 * but never expect to fully enter the guest, i.e. don't need setup the actual
1113 * EPT tables.
1114 */
setup_dummy_ept(void)1115 static void setup_dummy_ept(void)
1116 {
1117 if (__setup_ept(0, false))
1118 report_abort("EPT setup unexpectedly failed");
1119 }
1120
enable_unrestricted_guest(bool need_valid_ept)1121 static int enable_unrestricted_guest(bool need_valid_ept)
1122 {
1123 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) ||
1124 !(ctrl_cpu_rev[1].clr & CPU_URG) ||
1125 !(ctrl_cpu_rev[1].clr & CPU_EPT))
1126 return 1;
1127
1128 if (need_valid_ept)
1129 setup_ept(false);
1130 else
1131 setup_dummy_ept();
1132
1133 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY);
1134 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG);
1135
1136 return 0;
1137 }
1138
ept_enable_ad_bits(void)1139 static void ept_enable_ad_bits(void)
1140 {
1141 eptp |= EPTP_AD_FLAG;
1142 vmcs_write(EPTP, eptp);
1143 }
1144
ept_disable_ad_bits(void)1145 static void ept_disable_ad_bits(void)
1146 {
1147 eptp &= ~EPTP_AD_FLAG;
1148 vmcs_write(EPTP, eptp);
1149 }
1150
ept_ad_enabled(void)1151 static int ept_ad_enabled(void)
1152 {
1153 return eptp & EPTP_AD_FLAG;
1154 }
1155
ept_enable_ad_bits_or_skip_test(void)1156 static void ept_enable_ad_bits_or_skip_test(void)
1157 {
1158 if (!ept_ad_bits_supported())
1159 test_skip("EPT AD bits not supported.");
1160 ept_enable_ad_bits();
1161 }
1162
1163 static int apic_version;
1164
ept_init_common(bool have_ad)1165 static int ept_init_common(bool have_ad)
1166 {
1167 int ret;
1168 struct pci_dev pcidev;
1169
1170 /* INVEPT is required by the EPT violation handler. */
1171 if (!is_invept_type_supported(INVEPT_SINGLE))
1172 return VMX_TEST_EXIT;
1173
1174 if (setup_ept(have_ad))
1175 return VMX_TEST_EXIT;
1176
1177 data_page1 = alloc_page();
1178 data_page2 = alloc_page();
1179 *((u32 *)data_page1) = MAGIC_VAL_1;
1180 *((u32 *)data_page2) = MAGIC_VAL_2;
1181 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2,
1182 EPT_RA | EPT_WA | EPT_EA);
1183
1184 apic_version = apic_read(APIC_LVR);
1185
1186 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST);
1187 if (ret != PCIDEVADDR_INVALID) {
1188 pci_dev_init(&pcidev, ret);
1189 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM];
1190 }
1191
1192 return VMX_TEST_START;
1193 }
1194
ept_init(struct vmcs * vmcs)1195 static int ept_init(struct vmcs *vmcs)
1196 {
1197 return ept_init_common(false);
1198 }
1199
ept_common(void)1200 static void ept_common(void)
1201 {
1202 vmx_set_test_stage(0);
1203 if (*((u32 *)data_page2) != MAGIC_VAL_1 ||
1204 *((u32 *)data_page1) != MAGIC_VAL_1)
1205 report_fail("EPT basic framework - read");
1206 else {
1207 *((u32 *)data_page2) = MAGIC_VAL_3;
1208 vmcall();
1209 if (vmx_get_test_stage() == 1) {
1210 if (*((u32 *)data_page1) == MAGIC_VAL_3 &&
1211 *((u32 *)data_page2) == MAGIC_VAL_2)
1212 report_pass("EPT basic framework");
1213 else
1214 report_pass("EPT basic framework - remap");
1215 }
1216 }
1217 // Test EPT Misconfigurations
1218 vmx_set_test_stage(1);
1219 vmcall();
1220 *((u32 *)data_page1) = MAGIC_VAL_1;
1221 if (vmx_get_test_stage() != 2) {
1222 report_fail("EPT misconfigurations");
1223 goto t1;
1224 }
1225 vmx_set_test_stage(2);
1226 vmcall();
1227 *((u32 *)data_page1) = MAGIC_VAL_1;
1228 report(vmx_get_test_stage() == 3, "EPT misconfigurations");
1229 t1:
1230 // Test EPT violation
1231 vmx_set_test_stage(3);
1232 vmcall();
1233 *((u32 *)data_page1) = MAGIC_VAL_1;
1234 report(vmx_get_test_stage() == 4, "EPT violation - page permission");
1235 // Violation caused by EPT paging structure
1236 vmx_set_test_stage(4);
1237 vmcall();
1238 *((u32 *)data_page1) = MAGIC_VAL_2;
1239 report(vmx_get_test_stage() == 5, "EPT violation - paging structure");
1240
1241 // MMIO Read/Write
1242 vmx_set_test_stage(5);
1243 vmcall();
1244
1245 *(u32 volatile *)pci_physaddr;
1246 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read");
1247
1248 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1;
1249 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write");
1250 }
1251
ept_main(void)1252 static void ept_main(void)
1253 {
1254 ept_common();
1255
1256 // Test EPT access to L1 MMIO
1257 vmx_set_test_stage(7);
1258 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access");
1259
1260 // Test invalid operand for INVEPT
1261 vmcall();
1262 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT");
1263 }
1264
invept_test(int type,u64 eptp)1265 static bool invept_test(int type, u64 eptp)
1266 {
1267 bool ret, supported;
1268
1269 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type);
1270 ret = __invept(type, eptp);
1271
1272 if (ret == !supported)
1273 return false;
1274
1275 if (!supported)
1276 printf("WARNING: unsupported invept passed!\n");
1277 else
1278 printf("WARNING: invept failed!\n");
1279
1280 return true;
1281 }
1282
pml_exit_handler(union exit_reason exit_reason)1283 static int pml_exit_handler(union exit_reason exit_reason)
1284 {
1285 u16 index, count;
1286 u64 *pmlbuf = pml_log;
1287 u64 guest_rip = vmcs_read(GUEST_RIP);;
1288 u64 guest_cr3 = vmcs_read(GUEST_CR3);
1289 u32 insn_len = vmcs_read(EXI_INST_LEN);
1290
1291 switch (exit_reason.basic) {
1292 case VMX_VMCALL:
1293 switch (vmx_get_test_stage()) {
1294 case 0:
1295 index = vmcs_read(GUEST_PML_INDEX);
1296 for (count = index + 1; count < PML_INDEX; count++) {
1297 if (pmlbuf[count] == (u64)data_page2) {
1298 vmx_inc_test_stage();
1299 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2);
1300 break;
1301 }
1302 }
1303 break;
1304 case 1:
1305 index = vmcs_read(GUEST_PML_INDEX);
1306 /* Keep clearing the dirty bit till a overflow */
1307 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2);
1308 break;
1309 default:
1310 report_fail("unexpected stage, %d.",
1311 vmx_get_test_stage());
1312 print_vmexit_info(exit_reason);
1313 return VMX_TEST_VMEXIT;
1314 }
1315 vmcs_write(GUEST_RIP, guest_rip + insn_len);
1316 return VMX_TEST_RESUME;
1317 case VMX_PML_FULL:
1318 vmx_inc_test_stage();
1319 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1);
1320 return VMX_TEST_RESUME;
1321 default:
1322 report_fail("Unknown exit reason, 0x%x", exit_reason.full);
1323 print_vmexit_info(exit_reason);
1324 }
1325 return VMX_TEST_VMEXIT;
1326 }
1327
ept_exit_handler_common(union exit_reason exit_reason,bool have_ad)1328 static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad)
1329 {
1330 u64 guest_rip;
1331 u64 guest_cr3;
1332 u32 insn_len;
1333 u32 exit_qual;
1334 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte,
1335 guest_pte_addr;
1336
1337 guest_rip = vmcs_read(GUEST_RIP);
1338 guest_cr3 = vmcs_read(GUEST_CR3);
1339 insn_len = vmcs_read(EXI_INST_LEN);
1340 exit_qual = vmcs_read(EXI_QUALIFICATION);
1341 pteval_t *ptep;
1342 switch (exit_reason.basic) {
1343 case VMX_VMCALL:
1344 switch (vmx_get_test_stage()) {
1345 case 0:
1346 check_ept_ad(pml4, guest_cr3,
1347 (unsigned long)data_page1,
1348 have_ad ? EPT_ACCESS_FLAG : 0,
1349 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0);
1350 check_ept_ad(pml4, guest_cr3,
1351 (unsigned long)data_page2,
1352 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0,
1353 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0);
1354 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1);
1355 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2);
1356 if (have_ad)
1357 invept(INVEPT_SINGLE, eptp);
1358 if (*((u32 *)data_page1) == MAGIC_VAL_3 &&
1359 *((u32 *)data_page2) == MAGIC_VAL_2) {
1360 vmx_inc_test_stage();
1361 install_ept(pml4, (unsigned long)data_page2,
1362 (unsigned long)data_page2,
1363 EPT_RA | EPT_WA | EPT_EA);
1364 } else
1365 report_fail("EPT basic framework - write");
1366 break;
1367 case 1:
1368 install_ept(pml4, (unsigned long)data_page1,
1369 (unsigned long)data_page1, EPT_WA);
1370 invept(INVEPT_SINGLE, eptp);
1371 break;
1372 case 2:
1373 install_ept(pml4, (unsigned long)data_page1,
1374 (unsigned long)data_page1,
1375 EPT_RA | EPT_WA | EPT_EA |
1376 (2 << EPT_MEM_TYPE_SHIFT));
1377 invept(INVEPT_SINGLE, eptp);
1378 break;
1379 case 3:
1380 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1);
1381 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1,
1382 1, &data_page1_pte));
1383 set_ept_pte(pml4, (unsigned long)data_page1,
1384 1, data_page1_pte & ~EPT_PRESENT);
1385 invept(INVEPT_SINGLE, eptp);
1386 break;
1387 case 4:
1388 ptep = get_pte_level((pgd_t *)guest_cr3, data_page1, /*level=*/2);
1389 guest_pte_addr = virt_to_phys(ptep) & PAGE_MASK;
1390
1391 TEST_ASSERT(get_ept_pte(pml4, guest_pte_addr, 2, &data_page1_pte_pte));
1392 set_ept_pte(pml4, guest_pte_addr, 2,
1393 data_page1_pte_pte & ~EPT_PRESENT);
1394 invept(INVEPT_SINGLE, eptp);
1395 break;
1396 case 5:
1397 install_ept(pml4, (unsigned long)pci_physaddr,
1398 (unsigned long)pci_physaddr, 0);
1399 invept(INVEPT_SINGLE, eptp);
1400 break;
1401 case 7:
1402 if (!invept_test(0, eptp))
1403 vmx_inc_test_stage();
1404 break;
1405 // Should not reach here
1406 default:
1407 report_fail("ERROR - unexpected stage, %d.",
1408 vmx_get_test_stage());
1409 print_vmexit_info(exit_reason);
1410 return VMX_TEST_VMEXIT;
1411 }
1412 vmcs_write(GUEST_RIP, guest_rip + insn_len);
1413 return VMX_TEST_RESUME;
1414 case VMX_EPT_MISCONFIG:
1415 switch (vmx_get_test_stage()) {
1416 case 1:
1417 case 2:
1418 vmx_inc_test_stage();
1419 install_ept(pml4, (unsigned long)data_page1,
1420 (unsigned long)data_page1,
1421 EPT_RA | EPT_WA | EPT_EA);
1422 invept(INVEPT_SINGLE, eptp);
1423 break;
1424 // Should not reach here
1425 default:
1426 report_fail("ERROR - unexpected stage, %d.",
1427 vmx_get_test_stage());
1428 print_vmexit_info(exit_reason);
1429 return VMX_TEST_VMEXIT;
1430 }
1431 return VMX_TEST_RESUME;
1432 case VMX_EPT_VIOLATION:
1433 /*
1434 * Exit-qualifications are masked not to account for advanced
1435 * VM-exit information. Once KVM supports this feature, this
1436 * masking should be removed.
1437 */
1438 exit_qual &= ~EPT_VLT_GUEST_MASK;
1439
1440 switch(vmx_get_test_stage()) {
1441 case 3:
1442 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0,
1443 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0);
1444 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1);
1445 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD |
1446 EPT_VLT_PADDR))
1447 vmx_inc_test_stage();
1448 set_ept_pte(pml4, (unsigned long)data_page1,
1449 1, data_page1_pte | (EPT_PRESENT));
1450 invept(INVEPT_SINGLE, eptp);
1451 break;
1452 case 4:
1453 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0,
1454 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0);
1455 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1);
1456 if (exit_qual == (EPT_VLT_RD |
1457 (have_ad ? EPT_VLT_WR : 0) |
1458 EPT_VLT_LADDR_VLD))
1459 vmx_inc_test_stage();
1460 set_ept_pte(pml4, guest_pte_addr, 2,
1461 data_page1_pte_pte | (EPT_PRESENT));
1462 invept(INVEPT_SINGLE, eptp);
1463 break;
1464 case 5:
1465 if (exit_qual & EPT_VLT_RD)
1466 vmx_inc_test_stage();
1467 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr,
1468 1, &memaddr_pte));
1469 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA);
1470 invept(INVEPT_SINGLE, eptp);
1471 break;
1472 case 6:
1473 if (exit_qual & EPT_VLT_WR)
1474 vmx_inc_test_stage();
1475 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr,
1476 1, &memaddr_pte));
1477 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA);
1478 invept(INVEPT_SINGLE, eptp);
1479 break;
1480 default:
1481 // Should not reach here
1482 report_fail("ERROR : unexpected stage, %d",
1483 vmx_get_test_stage());
1484 print_vmexit_info(exit_reason);
1485 return VMX_TEST_VMEXIT;
1486 }
1487 return VMX_TEST_RESUME;
1488 default:
1489 report_fail("Unknown exit reason, 0x%x", exit_reason.full);
1490 print_vmexit_info(exit_reason);
1491 }
1492 return VMX_TEST_VMEXIT;
1493 }
1494
ept_exit_handler(union exit_reason exit_reason)1495 static int ept_exit_handler(union exit_reason exit_reason)
1496 {
1497 return ept_exit_handler_common(exit_reason, false);
1498 }
1499
eptad_init(struct vmcs * vmcs)1500 static int eptad_init(struct vmcs *vmcs)
1501 {
1502 int r = ept_init_common(true);
1503
1504 if (r == VMX_TEST_EXIT)
1505 return r;
1506
1507 if (!ept_ad_bits_supported()) {
1508 printf("\tEPT A/D bits are not supported");
1509 return VMX_TEST_EXIT;
1510 }
1511
1512 return r;
1513 }
1514
pml_init(struct vmcs * vmcs)1515 static int pml_init(struct vmcs *vmcs)
1516 {
1517 u32 ctrl_cpu;
1518 int r = eptad_init(vmcs);
1519
1520 if (r == VMX_TEST_EXIT)
1521 return r;
1522
1523 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) ||
1524 !(ctrl_cpu_rev[1].clr & CPU_PML)) {
1525 printf("\tPML is not supported");
1526 return VMX_TEST_EXIT;
1527 }
1528
1529 pml_log = alloc_page();
1530 vmcs_write(PMLADDR, (u64)pml_log);
1531 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1);
1532
1533 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML;
1534 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu);
1535
1536 return VMX_TEST_START;
1537 }
1538
pml_main(void)1539 static void pml_main(void)
1540 {
1541 int count = 0;
1542
1543 vmx_set_test_stage(0);
1544 *((u32 *)data_page2) = 0x1;
1545 vmcall();
1546 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging");
1547
1548 while (vmx_get_test_stage() == 1) {
1549 vmcall();
1550 *((u32 *)data_page2) = 0x1;
1551 if (count++ > PML_INDEX)
1552 break;
1553 }
1554 report(vmx_get_test_stage() == 2, "PML Full Event");
1555 }
1556
eptad_main(void)1557 static void eptad_main(void)
1558 {
1559 ept_common();
1560 }
1561
eptad_exit_handler(union exit_reason exit_reason)1562 static int eptad_exit_handler(union exit_reason exit_reason)
1563 {
1564 return ept_exit_handler_common(exit_reason, true);
1565 }
1566
1567 #define TIMER_VECTOR 222
1568
1569 static volatile bool timer_fired;
1570
timer_isr(isr_regs_t * regs)1571 static void timer_isr(isr_regs_t *regs)
1572 {
1573 timer_fired = true;
1574 apic_write(APIC_EOI, 0);
1575 }
1576
interrupt_init(struct vmcs * vmcs)1577 static int interrupt_init(struct vmcs *vmcs)
1578 {
1579 msr_bmp_init();
1580 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT);
1581 handle_irq(TIMER_VECTOR, timer_isr);
1582 return VMX_TEST_START;
1583 }
1584
interrupt_main(void)1585 static void interrupt_main(void)
1586 {
1587 long long start, loops;
1588
1589 vmx_set_test_stage(0);
1590
1591 apic_write(APIC_LVTT, TIMER_VECTOR);
1592 sti();
1593
1594 apic_write(APIC_TMICT, 1);
1595 for (loops = 0; loops < 10000000 && !timer_fired; loops++)
1596 asm volatile ("nop");
1597 report(timer_fired, "direct interrupt while running guest");
1598
1599 apic_write(APIC_TMICT, 0);
1600 cli();
1601 vmcall();
1602 timer_fired = false;
1603 apic_write(APIC_TMICT, 1);
1604 for (loops = 0; loops < 10000000 && !timer_fired; loops++)
1605 asm volatile ("nop");
1606 report(timer_fired, "intercepted interrupt while running guest");
1607
1608 sti();
1609 apic_write(APIC_TMICT, 0);
1610 cli();
1611 vmcall();
1612 timer_fired = false;
1613 start = rdtsc();
1614 apic_write(APIC_TMICT, 1000000);
1615
1616 safe_halt();
1617
1618 report(rdtsc() - start > 1000000 && timer_fired,
1619 "direct interrupt + hlt");
1620
1621 apic_write(APIC_TMICT, 0);
1622 cli();
1623 vmcall();
1624 timer_fired = false;
1625 start = rdtsc();
1626 apic_write(APIC_TMICT, 1000000);
1627
1628 safe_halt();
1629
1630 report(rdtsc() - start > 10000 && timer_fired,
1631 "intercepted interrupt + hlt");
1632
1633 apic_write(APIC_TMICT, 0);
1634 cli();
1635 vmcall();
1636 timer_fired = false;
1637 start = rdtsc();
1638 apic_write(APIC_TMICT, 1000000);
1639
1640 sti_nop();
1641 vmcall();
1642
1643 report(rdtsc() - start > 10000 && timer_fired,
1644 "direct interrupt + activity state hlt");
1645
1646 apic_write(APIC_TMICT, 0);
1647 cli();
1648 vmcall();
1649 timer_fired = false;
1650 start = rdtsc();
1651 apic_write(APIC_TMICT, 1000000);
1652
1653 sti_nop();
1654 vmcall();
1655
1656 report(rdtsc() - start > 10000 && timer_fired,
1657 "intercepted interrupt + activity state hlt");
1658
1659 apic_write(APIC_TMICT, 0);
1660 cli();
1661 vmx_set_test_stage(7);
1662 vmcall();
1663 timer_fired = false;
1664 apic_write(APIC_TMICT, 1);
1665 for (loops = 0; loops < 10000000 && !timer_fired; loops++)
1666 asm volatile ("nop");
1667 report(timer_fired,
1668 "running a guest with interrupt acknowledgement set");
1669
1670 apic_write(APIC_TMICT, 0);
1671 sti();
1672 timer_fired = false;
1673 vmcall();
1674 report(timer_fired, "Inject an event to a halted guest");
1675 }
1676
interrupt_exit_handler(union exit_reason exit_reason)1677 static int interrupt_exit_handler(union exit_reason exit_reason)
1678 {
1679 u64 guest_rip = vmcs_read(GUEST_RIP);
1680 u32 insn_len = vmcs_read(EXI_INST_LEN);
1681
1682 switch (exit_reason.basic) {
1683 case VMX_VMCALL:
1684 switch (vmx_get_test_stage()) {
1685 case 0:
1686 case 2:
1687 case 5:
1688 vmcs_write(PIN_CONTROLS,
1689 vmcs_read(PIN_CONTROLS) | PIN_EXTINT);
1690 break;
1691 case 7:
1692 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA);
1693 vmcs_write(PIN_CONTROLS,
1694 vmcs_read(PIN_CONTROLS) | PIN_EXTINT);
1695 break;
1696 case 1:
1697 case 3:
1698 vmcs_write(PIN_CONTROLS,
1699 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT);
1700 break;
1701 case 4:
1702 case 6:
1703 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT);
1704 break;
1705
1706 case 8:
1707 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT);
1708 vmcs_write(ENT_INTR_INFO,
1709 TIMER_VECTOR |
1710 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) |
1711 INTR_INFO_VALID_MASK);
1712 break;
1713 }
1714 vmx_inc_test_stage();
1715 vmcs_write(GUEST_RIP, guest_rip + insn_len);
1716 return VMX_TEST_RESUME;
1717 case VMX_EXTINT:
1718 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) {
1719 int vector = vmcs_read(EXI_INTR_INFO) & 0xff;
1720 handle_external_interrupt(vector);
1721 } else {
1722 sti_nop_cli();
1723 }
1724 if (vmx_get_test_stage() >= 2)
1725 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE);
1726 return VMX_TEST_RESUME;
1727 default:
1728 report_fail("Unknown exit reason, 0x%x", exit_reason.full);
1729 print_vmexit_info(exit_reason);
1730 }
1731
1732 return VMX_TEST_VMEXIT;
1733 }
1734
1735
1736 static volatile int nmi_fired;
1737
1738 #define NMI_DELAY 100000000ULL
1739
nmi_isr(isr_regs_t * regs)1740 static void nmi_isr(isr_regs_t *regs)
1741 {
1742 nmi_fired = true;
1743 }
1744
nmi_hlt_init(struct vmcs * vmcs)1745 static int nmi_hlt_init(struct vmcs *vmcs)
1746 {
1747 msr_bmp_init();
1748 handle_irq(NMI_VECTOR, nmi_isr);
1749 vmcs_write(PIN_CONTROLS,
1750 vmcs_read(PIN_CONTROLS) & ~PIN_NMI);
1751 vmcs_write(PIN_CONTROLS,
1752 vmcs_read(PIN_CONTROLS) & ~PIN_VIRT_NMI);
1753 return VMX_TEST_START;
1754 }
1755
nmi_message_thread(void * data)1756 static void nmi_message_thread(void *data)
1757 {
1758 while (vmx_get_test_stage() != 1)
1759 pause();
1760
1761 delay(NMI_DELAY);
1762 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]);
1763
1764 while (vmx_get_test_stage() != 2)
1765 pause();
1766
1767 delay(NMI_DELAY);
1768 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]);
1769 }
1770
nmi_hlt_main(void)1771 static void nmi_hlt_main(void)
1772 {
1773 long long start;
1774
1775 if (cpu_count() < 2) {
1776 report_skip("%s : CPU count < 2", __func__);
1777 vmx_set_test_stage(-1);
1778 return;
1779 }
1780
1781 vmx_set_test_stage(0);
1782 on_cpu_async(1, nmi_message_thread, NULL);
1783 start = rdtsc();
1784 vmx_set_test_stage(1);
1785 asm volatile ("hlt");
1786 report((rdtsc() - start > NMI_DELAY) && nmi_fired,
1787 "direct NMI + hlt");
1788 if (!nmi_fired)
1789 vmx_set_test_stage(-1);
1790 nmi_fired = false;
1791
1792 vmcall();
1793
1794 start = rdtsc();
1795 vmx_set_test_stage(2);
1796 asm volatile ("hlt");
1797 report((rdtsc() - start > NMI_DELAY) && !nmi_fired,
1798 "intercepted NMI + hlt");
1799 if (nmi_fired) {
1800 report(!nmi_fired, "intercepted NMI was dispatched");
1801 vmx_set_test_stage(-1);
1802 return;
1803 }
1804 vmx_set_test_stage(3);
1805 }
1806
nmi_hlt_exit_handler(union exit_reason exit_reason)1807 static int nmi_hlt_exit_handler(union exit_reason exit_reason)
1808 {
1809 u64 guest_rip = vmcs_read(GUEST_RIP);
1810 u32 insn_len = vmcs_read(EXI_INST_LEN);
1811
1812 switch (vmx_get_test_stage()) {
1813 case 1:
1814 if (exit_reason.basic != VMX_VMCALL) {
1815 report_fail("VMEXIT not due to vmcall. Exit reason 0x%x",
1816 exit_reason.full);
1817 print_vmexit_info(exit_reason);
1818 return VMX_TEST_VMEXIT;
1819 }
1820
1821 vmcs_write(PIN_CONTROLS,
1822 vmcs_read(PIN_CONTROLS) | PIN_NMI);
1823 vmcs_write(PIN_CONTROLS,
1824 vmcs_read(PIN_CONTROLS) | PIN_VIRT_NMI);
1825 vmcs_write(GUEST_RIP, guest_rip + insn_len);
1826 break;
1827
1828 case 2:
1829 if (exit_reason.basic != VMX_EXC_NMI) {
1830 report_fail("VMEXIT not due to NMI intercept. Exit reason 0x%x",
1831 exit_reason.full);
1832 print_vmexit_info(exit_reason);
1833 return VMX_TEST_VMEXIT;
1834 }
1835 report_pass("NMI intercept while running guest");
1836 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE);
1837 break;
1838
1839 case 3:
1840 break;
1841
1842 default:
1843 return VMX_TEST_VMEXIT;
1844 }
1845
1846 if (vmx_get_test_stage() == 3)
1847 return VMX_TEST_VMEXIT;
1848
1849 return VMX_TEST_RESUME;
1850 }
1851
1852
dbgctls_init(struct vmcs * vmcs)1853 static int dbgctls_init(struct vmcs *vmcs)
1854 {
1855 u64 dr7 = 0x402;
1856 u64 zero = 0;
1857
1858 msr_bmp_init();
1859 asm volatile(
1860 "mov %0,%%dr0\n\t"
1861 "mov %0,%%dr1\n\t"
1862 "mov %0,%%dr2\n\t"
1863 "mov %1,%%dr7\n\t"
1864 : : "r" (zero), "r" (dr7));
1865 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1);
1866 vmcs_write(GUEST_DR7, 0x404);
1867 vmcs_write(GUEST_DEBUGCTL, 0x2);
1868
1869 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS);
1870 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS);
1871
1872 return VMX_TEST_START;
1873 }
1874
dbgctls_main(void)1875 static void dbgctls_main(void)
1876 {
1877 u64 dr7, debugctl;
1878
1879 asm volatile("mov %%dr7,%0" : "=r" (dr7));
1880 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR);
1881 /* Commented out: KVM does not support DEBUGCTL so far */
1882 (void)debugctl;
1883 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */);
1884
1885 dr7 = 0x408;
1886 asm volatile("mov %0,%%dr7" : : "r" (dr7));
1887 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3);
1888
1889 vmx_set_test_stage(0);
1890 vmcall();
1891 report(vmx_get_test_stage() == 1, "Save debug controls");
1892
1893 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS ||
1894 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) {
1895 printf("\tDebug controls are always loaded/saved\n");
1896 return;
1897 }
1898 vmx_set_test_stage(2);
1899 vmcall();
1900
1901 asm volatile("mov %%dr7,%0" : "=r" (dr7));
1902 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR);
1903 /* Commented out: KVM does not support DEBUGCTL so far */
1904 (void)debugctl;
1905 report(dr7 == 0x402,
1906 "Guest=host debug controls" /* && debugctl == 0x1 */);
1907
1908 dr7 = 0x408;
1909 asm volatile("mov %0,%%dr7" : : "r" (dr7));
1910 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3);
1911
1912 vmx_set_test_stage(3);
1913 vmcall();
1914 report(vmx_get_test_stage() == 4, "Don't save debug controls");
1915 }
1916
dbgctls_exit_handler(union exit_reason exit_reason)1917 static int dbgctls_exit_handler(union exit_reason exit_reason)
1918 {
1919 u32 insn_len = vmcs_read(EXI_INST_LEN);
1920 u64 guest_rip = vmcs_read(GUEST_RIP);
1921 u64 dr7, debugctl;
1922
1923 asm volatile("mov %%dr7,%0" : "=r" (dr7));
1924 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR);
1925
1926 switch (exit_reason.basic) {
1927 case VMX_VMCALL:
1928 switch (vmx_get_test_stage()) {
1929 case 0:
1930 if (dr7 == 0x400 && debugctl == 0 &&
1931 vmcs_read(GUEST_DR7) == 0x408 /* &&
1932 Commented out: KVM does not support DEBUGCTL so far
1933 vmcs_read(GUEST_DEBUGCTL) == 0x3 */)
1934 vmx_inc_test_stage();
1935 break;
1936 case 2:
1937 dr7 = 0x402;
1938 asm volatile("mov %0,%%dr7" : : "r" (dr7));
1939 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1);
1940 vmcs_write(GUEST_DR7, 0x404);
1941 vmcs_write(GUEST_DEBUGCTL, 0x2);
1942
1943 vmcs_write(ENT_CONTROLS,
1944 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS);
1945 vmcs_write(EXI_CONTROLS,
1946 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS);
1947 break;
1948 case 3:
1949 if (dr7 == 0x400 && debugctl == 0 &&
1950 vmcs_read(GUEST_DR7) == 0x404 /* &&
1951 Commented out: KVM does not support DEBUGCTL so far
1952 vmcs_read(GUEST_DEBUGCTL) == 0x2 */)
1953 vmx_inc_test_stage();
1954 break;
1955 }
1956 vmcs_write(GUEST_RIP, guest_rip + insn_len);
1957 return VMX_TEST_RESUME;
1958 default:
1959 report_fail("Unknown exit reason, %d", exit_reason.full);
1960 print_vmexit_info(exit_reason);
1961 }
1962 return VMX_TEST_VMEXIT;
1963 }
1964
1965 struct vmx_msr_entry {
1966 u32 index;
1967 u32 reserved;
1968 u64 value;
1969 } __attribute__((packed));
1970
1971 #define MSR_MAGIC 0x31415926
1972 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load;
1973
msr_switch_init(struct vmcs * vmcs)1974 static int msr_switch_init(struct vmcs *vmcs)
1975 {
1976 msr_bmp_init();
1977 exit_msr_store = alloc_page();
1978 exit_msr_load = alloc_page();
1979 entry_msr_load = alloc_page();
1980 entry_msr_load[0].index = MSR_KERNEL_GS_BASE;
1981 entry_msr_load[0].value = MSR_MAGIC;
1982
1983 vmx_set_test_stage(1);
1984 vmcs_write(ENT_MSR_LD_CNT, 1);
1985 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load);
1986 vmcs_write(EXI_MSR_ST_CNT, 1);
1987 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store);
1988 vmcs_write(EXI_MSR_LD_CNT, 1);
1989 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load);
1990 return VMX_TEST_START;
1991 }
1992
msr_switch_main(void)1993 static void msr_switch_main(void)
1994 {
1995 if (vmx_get_test_stage() == 1) {
1996 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC,
1997 "VM entry MSR load");
1998 vmx_set_test_stage(2);
1999 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1);
2000 exit_msr_store[0].index = MSR_KERNEL_GS_BASE;
2001 exit_msr_load[0].index = MSR_KERNEL_GS_BASE;
2002 exit_msr_load[0].value = MSR_MAGIC + 2;
2003 }
2004 vmcall();
2005 }
2006
msr_switch_exit_handler(union exit_reason exit_reason)2007 static int msr_switch_exit_handler(union exit_reason exit_reason)
2008 {
2009 if (exit_reason.basic == VMX_VMCALL && vmx_get_test_stage() == 2) {
2010 report(exit_msr_store[0].value == MSR_MAGIC + 1,
2011 "VM exit MSR store");
2012 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2,
2013 "VM exit MSR load");
2014 vmx_set_test_stage(3);
2015 entry_msr_load[0].index = MSR_FS_BASE;
2016 return VMX_TEST_RESUME;
2017 }
2018 printf("ERROR %s: unexpected stage=%u or reason=0x%x\n",
2019 __func__, vmx_get_test_stage(), exit_reason.full);
2020 return VMX_TEST_EXIT;
2021 }
2022
msr_switch_entry_failure(struct vmentry_result * result)2023 static int msr_switch_entry_failure(struct vmentry_result *result)
2024 {
2025 if (result->vm_fail) {
2026 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr);
2027 return VMX_TEST_EXIT;
2028 }
2029
2030 if (result->exit_reason.failed_vmentry &&
2031 result->exit_reason.basic == VMX_FAIL_MSR &&
2032 vmx_get_test_stage() == 3) {
2033 report(vmcs_read(EXI_QUALIFICATION) == 1,
2034 "VM entry MSR load: try to load FS_BASE");
2035 return VMX_TEST_VMEXIT;
2036 }
2037 printf("ERROR %s: unexpected stage=%u or reason=%x\n",
2038 __func__, vmx_get_test_stage(), result->exit_reason.full);
2039 return VMX_TEST_EXIT;
2040 }
2041
vmmcall_init(struct vmcs * vmcs)2042 static int vmmcall_init(struct vmcs *vmcs)
2043 {
2044 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR);
2045 return VMX_TEST_START;
2046 }
2047
vmmcall_main(void)2048 static void vmmcall_main(void)
2049 {
2050 asm volatile(
2051 "mov $0xABCD, %%rax\n\t"
2052 "vmmcall\n\t"
2053 ::: "rax");
2054
2055 report_fail("VMMCALL");
2056 }
2057
vmmcall_exit_handler(union exit_reason exit_reason)2058 static int vmmcall_exit_handler(union exit_reason exit_reason)
2059 {
2060 switch (exit_reason.basic) {
2061 case VMX_VMCALL:
2062 printf("here\n");
2063 report_fail("VMMCALL triggers #UD");
2064 break;
2065 case VMX_EXC_NMI:
2066 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR,
2067 "VMMCALL triggers #UD");
2068 break;
2069 default:
2070 report_fail("Unknown exit reason, 0x%x", exit_reason.full);
2071 print_vmexit_info(exit_reason);
2072 }
2073
2074 return VMX_TEST_VMEXIT;
2075 }
2076
disable_rdtscp_init(struct vmcs * vmcs)2077 static int disable_rdtscp_init(struct vmcs *vmcs)
2078 {
2079 u32 ctrl_cpu1;
2080
2081 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) {
2082 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1);
2083 ctrl_cpu1 &= ~CPU_RDTSCP;
2084 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1);
2085 }
2086
2087 return VMX_TEST_START;
2088 }
2089
disable_rdtscp_ud_handler(struct ex_regs * regs)2090 static void disable_rdtscp_ud_handler(struct ex_regs *regs)
2091 {
2092 switch (vmx_get_test_stage()) {
2093 case 0:
2094 report_pass("RDTSCP triggers #UD");
2095 vmx_inc_test_stage();
2096 regs->rip += 3;
2097 break;
2098 case 2:
2099 report_pass("RDPID triggers #UD");
2100 vmx_inc_test_stage();
2101 regs->rip += 4;
2102 break;
2103 }
2104 return;
2105
2106 }
2107
disable_rdtscp_main(void)2108 static void disable_rdtscp_main(void)
2109 {
2110 /* Test that #UD is properly injected in L2. */
2111 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler);
2112
2113 vmx_set_test_stage(0);
2114 asm volatile("rdtscp" : : : "eax", "ecx", "edx");
2115 vmcall();
2116 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax");
2117
2118 handle_exception(UD_VECTOR, 0);
2119 vmcall();
2120 }
2121
disable_rdtscp_exit_handler(union exit_reason exit_reason)2122 static int disable_rdtscp_exit_handler(union exit_reason exit_reason)
2123 {
2124 switch (exit_reason.basic) {
2125 case VMX_VMCALL:
2126 switch (vmx_get_test_stage()) {
2127 case 0:
2128 report_fail("RDTSCP triggers #UD");
2129 vmx_inc_test_stage();
2130 /* fallthrough */
2131 case 1:
2132 vmx_inc_test_stage();
2133 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3);
2134 return VMX_TEST_RESUME;
2135 case 2:
2136 report_fail("RDPID triggers #UD");
2137 break;
2138 }
2139 break;
2140
2141 default:
2142 report_fail("Unknown exit reason, 0x%x", exit_reason.full);
2143 print_vmexit_info(exit_reason);
2144 }
2145 return VMX_TEST_VMEXIT;
2146 }
2147
exit_monitor_from_l2_main(void)2148 static void exit_monitor_from_l2_main(void)
2149 {
2150 printf("Calling exit(0) from l2...\n");
2151 exit(0);
2152 }
2153
exit_monitor_from_l2_handler(union exit_reason exit_reason)2154 static int exit_monitor_from_l2_handler(union exit_reason exit_reason)
2155 {
2156 report_fail("The guest should have killed the VMM");
2157 return VMX_TEST_EXIT;
2158 }
2159
assert_exit_reason(u64 expected)2160 static void assert_exit_reason(u64 expected)
2161 {
2162 u64 actual = vmcs_read(EXI_REASON);
2163
2164 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.",
2165 exit_reason_description(expected),
2166 exit_reason_description(actual));
2167 }
2168
skip_exit_insn(void)2169 static void skip_exit_insn(void)
2170 {
2171 u64 guest_rip = vmcs_read(GUEST_RIP);
2172 u32 insn_len = vmcs_read(EXI_INST_LEN);
2173 vmcs_write(GUEST_RIP, guest_rip + insn_len);
2174 }
2175
skip_exit_vmcall(void)2176 static void skip_exit_vmcall(void)
2177 {
2178 assert_exit_reason(VMX_VMCALL);
2179 skip_exit_insn();
2180 }
2181
v2_null_test_guest(void)2182 static void v2_null_test_guest(void)
2183 {
2184 }
2185
v2_null_test(void)2186 static void v2_null_test(void)
2187 {
2188 test_set_guest(v2_null_test_guest);
2189 enter_guest();
2190 report_pass(__func__);
2191 }
2192
v2_multiple_entries_test_guest(void)2193 static void v2_multiple_entries_test_guest(void)
2194 {
2195 vmx_set_test_stage(1);
2196 vmcall();
2197 vmx_set_test_stage(2);
2198 }
2199
v2_multiple_entries_test(void)2200 static void v2_multiple_entries_test(void)
2201 {
2202 test_set_guest(v2_multiple_entries_test_guest);
2203 enter_guest();
2204 TEST_ASSERT_EQ(vmx_get_test_stage(), 1);
2205 skip_exit_vmcall();
2206 enter_guest();
2207 TEST_ASSERT_EQ(vmx_get_test_stage(), 2);
2208 report_pass(__func__);
2209 }
2210
2211 static int fixture_test_data = 1;
2212
fixture_test_teardown(void * data)2213 static void fixture_test_teardown(void *data)
2214 {
2215 *((int *) data) = 1;
2216 }
2217
fixture_test_guest(void)2218 static void fixture_test_guest(void)
2219 {
2220 fixture_test_data++;
2221 }
2222
2223
fixture_test_setup(void)2224 static void fixture_test_setup(void)
2225 {
2226 TEST_ASSERT_EQ_MSG(1, fixture_test_data,
2227 "fixture_test_teardown didn't run?!");
2228 fixture_test_data = 2;
2229 test_add_teardown(fixture_test_teardown, &fixture_test_data);
2230 test_set_guest(fixture_test_guest);
2231 }
2232
fixture_test_case1(void)2233 static void fixture_test_case1(void)
2234 {
2235 fixture_test_setup();
2236 TEST_ASSERT_EQ(2, fixture_test_data);
2237 enter_guest();
2238 TEST_ASSERT_EQ(3, fixture_test_data);
2239 report_pass(__func__);
2240 }
2241
fixture_test_case2(void)2242 static void fixture_test_case2(void)
2243 {
2244 fixture_test_setup();
2245 TEST_ASSERT_EQ(2, fixture_test_data);
2246 enter_guest();
2247 TEST_ASSERT_EQ(3, fixture_test_data);
2248 report_pass(__func__);
2249 }
2250
2251 enum ept_access_op {
2252 OP_READ,
2253 OP_WRITE,
2254 OP_EXEC,
2255 OP_FLUSH_TLB,
2256 OP_EXIT,
2257 };
2258
2259 static struct ept_access_test_data {
2260 unsigned long gpa;
2261 unsigned long *gva;
2262 unsigned long hpa;
2263 unsigned long *hva;
2264 enum ept_access_op op;
2265 } ept_access_test_data;
2266
2267 extern unsigned char ret42_start;
2268 extern unsigned char ret42_end;
2269
2270 /* Returns 42. */
2271 asm(
2272 ".align 64\n"
2273 "ret42_start:\n"
2274 "mov $42, %eax\n"
2275 "ret\n"
2276 "ret42_end:\n"
2277 );
2278
2279 static void
diagnose_ept_violation_qual(u64 expected,u64 actual)2280 diagnose_ept_violation_qual(u64 expected, u64 actual)
2281 {
2282
2283 #define DIAGNOSE(flag) \
2284 do { \
2285 if ((expected & flag) != (actual & flag)) \
2286 printf(#flag " %sexpected\n", \
2287 (expected & flag) ? "" : "un"); \
2288 } while (0)
2289
2290 DIAGNOSE(EPT_VLT_RD);
2291 DIAGNOSE(EPT_VLT_WR);
2292 DIAGNOSE(EPT_VLT_FETCH);
2293 DIAGNOSE(EPT_VLT_PERM_RD);
2294 DIAGNOSE(EPT_VLT_PERM_WR);
2295 DIAGNOSE(EPT_VLT_PERM_EX);
2296 DIAGNOSE(EPT_VLT_LADDR_VLD);
2297 DIAGNOSE(EPT_VLT_PADDR);
2298
2299 #undef DIAGNOSE
2300 }
2301
do_ept_access_op(enum ept_access_op op)2302 static void do_ept_access_op(enum ept_access_op op)
2303 {
2304 ept_access_test_data.op = op;
2305 enter_guest();
2306 }
2307
2308 /*
2309 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only
2310 * needed by tests that modify guest PTEs.
2311 */
ept_access_test_guest_flush_tlb(void)2312 static void ept_access_test_guest_flush_tlb(void)
2313 {
2314 do_ept_access_op(OP_FLUSH_TLB);
2315 skip_exit_vmcall();
2316 }
2317
2318 /*
2319 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the
2320 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into
2321 * a huge page.
2322 */
ept_twiddle(unsigned long gpa,bool mkhuge,int level,unsigned long clear,unsigned long set)2323 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level,
2324 unsigned long clear, unsigned long set)
2325 {
2326 struct ept_access_test_data *data = &ept_access_test_data;
2327 unsigned long orig_pte;
2328 unsigned long pte;
2329
2330 /* Screw with the mapping at the requested level. */
2331 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte));
2332 pte = orig_pte;
2333 if (mkhuge)
2334 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE;
2335 else
2336 pte = orig_pte;
2337 pte = (pte & ~clear) | set;
2338 set_ept_pte(pml4, gpa, level, pte);
2339 invept(INVEPT_SINGLE, eptp);
2340
2341 return orig_pte;
2342 }
2343
ept_untwiddle(unsigned long gpa,int level,unsigned long orig_pte)2344 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte)
2345 {
2346 set_ept_pte(pml4, gpa, level, orig_pte);
2347 invept(INVEPT_SINGLE, eptp);
2348 }
2349
do_ept_violation(bool leaf,enum ept_access_op op,u64 expected_qual,u64 expected_paddr)2350 static void do_ept_violation(bool leaf, enum ept_access_op op,
2351 u64 expected_qual, u64 expected_paddr)
2352 {
2353 u64 qual;
2354
2355 /* Try the access and observe the violation. */
2356 do_ept_access_op(op);
2357
2358 assert_exit_reason(VMX_EPT_VIOLATION);
2359
2360 qual = vmcs_read(EXI_QUALIFICATION);
2361
2362 /* Mask undefined bits (which may later be defined in certain cases). */
2363 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX |
2364 EPT_VLT_PERM_USER_EX);
2365
2366 diagnose_ept_violation_qual(expected_qual, qual);
2367 TEST_EXPECT_EQ(expected_qual, qual);
2368
2369 #if 0
2370 /* Disable for now otherwise every test will fail */
2371 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS),
2372 (unsigned long) (
2373 op == OP_EXEC ? data->gva + 1 : data->gva));
2374 #endif
2375 /*
2376 * TODO: tests that probe expected_paddr in pages other than the one at
2377 * the beginning of the 1g region.
2378 */
2379 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr);
2380 }
2381
2382 static void
ept_violation_at_level_mkhuge(bool mkhuge,int level,unsigned long clear,unsigned long set,enum ept_access_op op,u64 expected_qual)2383 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear,
2384 unsigned long set, enum ept_access_op op,
2385 u64 expected_qual)
2386 {
2387 struct ept_access_test_data *data = &ept_access_test_data;
2388 unsigned long orig_pte;
2389
2390 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set);
2391
2392 do_ept_violation(level == 1 || mkhuge, op, expected_qual,
2393 op == OP_EXEC ? data->gpa + sizeof(unsigned long) :
2394 data->gpa);
2395
2396 /* Fix the violation and resume the op loop. */
2397 ept_untwiddle(data->gpa, level, orig_pte);
2398 enter_guest();
2399 skip_exit_vmcall();
2400 }
2401
2402 static void
ept_violation_at_level(int level,unsigned long clear,unsigned long set,enum ept_access_op op,u64 expected_qual)2403 ept_violation_at_level(int level, unsigned long clear, unsigned long set,
2404 enum ept_access_op op, u64 expected_qual)
2405 {
2406 ept_violation_at_level_mkhuge(false, level, clear, set, op,
2407 expected_qual);
2408 if (ept_huge_pages_supported(level))
2409 ept_violation_at_level_mkhuge(true, level, clear, set, op,
2410 expected_qual);
2411 }
2412
ept_violation(unsigned long clear,unsigned long set,enum ept_access_op op,u64 expected_qual)2413 static void ept_violation(unsigned long clear, unsigned long set,
2414 enum ept_access_op op, u64 expected_qual)
2415 {
2416 ept_violation_at_level(1, clear, set, op, expected_qual);
2417 ept_violation_at_level(2, clear, set, op, expected_qual);
2418 ept_violation_at_level(3, clear, set, op, expected_qual);
2419 ept_violation_at_level(4, clear, set, op, expected_qual);
2420 }
2421
ept_access_violation(unsigned long access,enum ept_access_op op,u64 expected_qual)2422 static void ept_access_violation(unsigned long access, enum ept_access_op op,
2423 u64 expected_qual)
2424 {
2425 ept_violation(EPT_PRESENT, access, op,
2426 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR);
2427 }
2428
2429 /*
2430 * For translations that don't involve a GVA, that is physical address (paddr)
2431 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical
2432 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain
2433 * translations don't involve GVAs, such as when the hardware does the guest
2434 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU
2435 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides
2436 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and
2437 * the EPT_VLT_PADDR bit will be clear in the exit qualification.
2438 *
2439 * Note that paddr violations can also be triggered by loading PAE page tables
2440 * with wonky addresses. We don't test that yet.
2441 *
2442 * This function modifies the EPT entry that maps the GPA that the guest page
2443 * table entry mapping ept_access_test_data.gva resides on.
2444 *
2445 * @ept_access EPT permissions to set. Other permissions are cleared.
2446 *
2447 * @pte_ad Set the A/D bits on the guest PTE accordingly.
2448 *
2449 * @op Guest operation to perform with
2450 * ept_access_test_data.gva.
2451 *
2452 * @expect_violation
2453 * Is a violation expected during the paddr access?
2454 *
2455 * @expected_qual Expected qualification for the EPT violation.
2456 * EPT_VLT_PADDR should be clear.
2457 */
ept_access_paddr(unsigned long ept_access,unsigned long pte_ad,enum ept_access_op op,bool expect_violation,u64 expected_qual)2458 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad,
2459 enum ept_access_op op, bool expect_violation,
2460 u64 expected_qual)
2461 {
2462 struct ept_access_test_data *data = &ept_access_test_data;
2463 unsigned long *ptep;
2464 unsigned long gpa;
2465 unsigned long orig_epte;
2466 unsigned long epte;
2467 int i;
2468
2469 /* Modify the guest PTE mapping data->gva according to @pte_ad. */
2470 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1);
2471 TEST_ASSERT(ptep);
2472 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa);
2473 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad;
2474 ept_access_test_guest_flush_tlb();
2475
2476 /*
2477 * Now modify the access bits on the EPT entry for the GPA that the
2478 * guest PTE resides on. Note that by modifying a single EPT entry,
2479 * we're potentially affecting 512 guest PTEs. However, we've carefully
2480 * constructed our test such that those other 511 PTEs aren't used by
2481 * the guest: data->gva is at the beginning of a 1G huge page, thus the
2482 * PTE we're modifying is at the beginning of a 4K page and the
2483 * following 511 entries are also under our control (and not touched by
2484 * the guest).
2485 */
2486 gpa = virt_to_phys(ptep);
2487 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0);
2488 /*
2489 * Make sure the guest page table page is mapped with a 4K EPT entry,
2490 * otherwise our level=1 twiddling below will fail. We use the
2491 * identity map (gpa = gpa) since page tables are shared with the host.
2492 */
2493 install_ept(pml4, gpa, gpa, EPT_PRESENT);
2494 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1,
2495 /*clear=*/EPT_PRESENT, /*set=*/ept_access);
2496
2497 if (expect_violation) {
2498 do_ept_violation(/*leaf=*/true, op,
2499 expected_qual | EPT_VLT_LADDR_VLD, gpa);
2500 ept_untwiddle(gpa, /*level=*/1, orig_epte);
2501 do_ept_access_op(op);
2502 } else {
2503 do_ept_access_op(op);
2504 if (ept_ad_enabled()) {
2505 for (i = EPT_PAGE_LEVEL; i > 0; i--) {
2506 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte));
2507 TEST_ASSERT(epte & EPT_ACCESS_FLAG);
2508 if (i == 1)
2509 TEST_ASSERT(epte & EPT_DIRTY_FLAG);
2510 else
2511 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0);
2512 }
2513 }
2514
2515 ept_untwiddle(gpa, /*level=*/1, orig_epte);
2516 }
2517
2518 TEST_ASSERT(*ptep & PT_ACCESSED_MASK);
2519 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE)
2520 TEST_ASSERT(*ptep & PT_DIRTY_MASK);
2521
2522 skip_exit_vmcall();
2523 }
2524
ept_access_allowed_paddr(unsigned long ept_access,unsigned long pte_ad,enum ept_access_op op)2525 static void ept_access_allowed_paddr(unsigned long ept_access,
2526 unsigned long pte_ad,
2527 enum ept_access_op op)
2528 {
2529 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false,
2530 /*expected_qual=*/-1);
2531 }
2532
ept_access_violation_paddr(unsigned long ept_access,unsigned long pte_ad,enum ept_access_op op,u64 expected_qual)2533 static void ept_access_violation_paddr(unsigned long ept_access,
2534 unsigned long pte_ad,
2535 enum ept_access_op op,
2536 u64 expected_qual)
2537 {
2538 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true,
2539 expected_qual);
2540 }
2541
2542
ept_allowed_at_level_mkhuge(bool mkhuge,int level,unsigned long clear,unsigned long set,enum ept_access_op op)2543 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level,
2544 unsigned long clear,
2545 unsigned long set,
2546 enum ept_access_op op)
2547 {
2548 struct ept_access_test_data *data = &ept_access_test_data;
2549 unsigned long orig_pte;
2550
2551 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set);
2552
2553 /* No violation. Should proceed to vmcall. */
2554 do_ept_access_op(op);
2555 skip_exit_vmcall();
2556
2557 ept_untwiddle(data->gpa, level, orig_pte);
2558 }
2559
ept_allowed_at_level(int level,unsigned long clear,unsigned long set,enum ept_access_op op)2560 static void ept_allowed_at_level(int level, unsigned long clear,
2561 unsigned long set, enum ept_access_op op)
2562 {
2563 ept_allowed_at_level_mkhuge(false, level, clear, set, op);
2564 if (ept_huge_pages_supported(level))
2565 ept_allowed_at_level_mkhuge(true, level, clear, set, op);
2566 }
2567
ept_allowed(unsigned long clear,unsigned long set,enum ept_access_op op)2568 static void ept_allowed(unsigned long clear, unsigned long set,
2569 enum ept_access_op op)
2570 {
2571 ept_allowed_at_level(1, clear, set, op);
2572 ept_allowed_at_level(2, clear, set, op);
2573 ept_allowed_at_level(3, clear, set, op);
2574 ept_allowed_at_level(4, clear, set, op);
2575 }
2576
ept_ignored_bit(int bit)2577 static void ept_ignored_bit(int bit)
2578 {
2579 /* Set the bit. */
2580 ept_allowed(0, 1ul << bit, OP_READ);
2581 ept_allowed(0, 1ul << bit, OP_WRITE);
2582 ept_allowed(0, 1ul << bit, OP_EXEC);
2583
2584 /* Clear the bit. */
2585 ept_allowed(1ul << bit, 0, OP_READ);
2586 ept_allowed(1ul << bit, 0, OP_WRITE);
2587 ept_allowed(1ul << bit, 0, OP_EXEC);
2588 }
2589
ept_access_allowed(unsigned long access,enum ept_access_op op)2590 static void ept_access_allowed(unsigned long access, enum ept_access_op op)
2591 {
2592 ept_allowed(EPT_PRESENT, access, op);
2593 }
2594
2595
ept_misconfig_at_level_mkhuge_op(bool mkhuge,int level,unsigned long clear,unsigned long set,enum ept_access_op op)2596 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level,
2597 unsigned long clear,
2598 unsigned long set,
2599 enum ept_access_op op)
2600 {
2601 struct ept_access_test_data *data = &ept_access_test_data;
2602 unsigned long orig_pte;
2603
2604 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set);
2605
2606 do_ept_access_op(op);
2607 assert_exit_reason(VMX_EPT_MISCONFIG);
2608
2609 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */
2610 #if 0
2611 /* broken: */
2612 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0);
2613 #endif
2614 #if 0
2615 /*
2616 * broken:
2617 * According to description of exit qual for EPT violation,
2618 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid.
2619 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought
2620 * to be set for msiconfig.
2621 */
2622 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS),
2623 (unsigned long) (
2624 op == OP_EXEC ? data->gva + 1 : data->gva));
2625 #endif
2626
2627 /* Fix the violation and resume the op loop. */
2628 ept_untwiddle(data->gpa, level, orig_pte);
2629 enter_guest();
2630 skip_exit_vmcall();
2631 }
2632
ept_misconfig_at_level_mkhuge(bool mkhuge,int level,unsigned long clear,unsigned long set)2633 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level,
2634 unsigned long clear,
2635 unsigned long set)
2636 {
2637 /* The op shouldn't matter (read, write, exec), so try them all! */
2638 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ);
2639 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE);
2640 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC);
2641 }
2642
ept_misconfig_at_level(int level,unsigned long clear,unsigned long set)2643 static void ept_misconfig_at_level(int level, unsigned long clear,
2644 unsigned long set)
2645 {
2646 ept_misconfig_at_level_mkhuge(false, level, clear, set);
2647 if (ept_huge_pages_supported(level))
2648 ept_misconfig_at_level_mkhuge(true, level, clear, set);
2649 }
2650
ept_misconfig(unsigned long clear,unsigned long set)2651 static void ept_misconfig(unsigned long clear, unsigned long set)
2652 {
2653 ept_misconfig_at_level(1, clear, set);
2654 ept_misconfig_at_level(2, clear, set);
2655 ept_misconfig_at_level(3, clear, set);
2656 ept_misconfig_at_level(4, clear, set);
2657 }
2658
ept_access_misconfig(unsigned long access)2659 static void ept_access_misconfig(unsigned long access)
2660 {
2661 ept_misconfig(EPT_PRESENT, access);
2662 }
2663
ept_reserved_bit_at_level_nohuge(int level,int bit)2664 static void ept_reserved_bit_at_level_nohuge(int level, int bit)
2665 {
2666 /* Setting the bit causes a misconfig. */
2667 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit);
2668
2669 /* Making the entry non-present turns reserved bits into ignored. */
2670 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ,
2671 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR);
2672 }
2673
ept_reserved_bit_at_level_huge(int level,int bit)2674 static void ept_reserved_bit_at_level_huge(int level, int bit)
2675 {
2676 /* Setting the bit causes a misconfig. */
2677 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit);
2678
2679 /* Making the entry non-present turns reserved bits into ignored. */
2680 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ,
2681 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR);
2682 }
2683
ept_reserved_bit_at_level(int level,int bit)2684 static void ept_reserved_bit_at_level(int level, int bit)
2685 {
2686 /* Setting the bit causes a misconfig. */
2687 ept_misconfig_at_level(level, 0, 1ul << bit);
2688
2689 /* Making the entry non-present turns reserved bits into ignored. */
2690 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ,
2691 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR);
2692 }
2693
ept_reserved_bit(int bit)2694 static void ept_reserved_bit(int bit)
2695 {
2696 ept_reserved_bit_at_level(1, bit);
2697 ept_reserved_bit_at_level(2, bit);
2698 ept_reserved_bit_at_level(3, bit);
2699 ept_reserved_bit_at_level(4, bit);
2700 }
2701
2702 #define PAGE_2M_ORDER 9
2703 #define PAGE_1G_ORDER 18
2704
get_1g_page(void)2705 static void *get_1g_page(void)
2706 {
2707 static void *alloc;
2708
2709 if (!alloc)
2710 alloc = alloc_pages(PAGE_1G_ORDER);
2711 return alloc;
2712 }
2713
ept_access_test_teardown(void * unused)2714 static void ept_access_test_teardown(void *unused)
2715 {
2716 /* Exit the guest cleanly. */
2717 do_ept_access_op(OP_EXIT);
2718 }
2719
ept_access_test_guest(void)2720 static void ept_access_test_guest(void)
2721 {
2722 struct ept_access_test_data *data = &ept_access_test_data;
2723 int (*code)(void) = (int (*)(void)) &data->gva[1];
2724
2725 while (true) {
2726 switch (data->op) {
2727 case OP_READ:
2728 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1);
2729 break;
2730 case OP_WRITE:
2731 *data->gva = MAGIC_VAL_2;
2732 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2);
2733 *data->gva = MAGIC_VAL_1;
2734 break;
2735 case OP_EXEC:
2736 TEST_ASSERT_EQ(42, code());
2737 break;
2738 case OP_FLUSH_TLB:
2739 write_cr3(read_cr3());
2740 break;
2741 case OP_EXIT:
2742 return;
2743 default:
2744 TEST_ASSERT_MSG(false, "Unknown op %d", data->op);
2745 }
2746 vmcall();
2747 }
2748 }
2749
ept_access_test_setup(void)2750 static void ept_access_test_setup(void)
2751 {
2752 struct ept_access_test_data *data = &ept_access_test_data;
2753 unsigned long npages = 1ul << PAGE_1G_ORDER;
2754 unsigned long size = npages * PAGE_SIZE;
2755 unsigned long *page_table = current_page_table();
2756 unsigned long pte;
2757
2758 if (setup_ept(false))
2759 test_skip("EPT not supported");
2760
2761 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */
2762 if (cpuid_maxphyaddr() < 40)
2763 test_skip("Test needs MAXPHYADDR >= 40");
2764
2765 test_set_guest(ept_access_test_guest);
2766 test_add_teardown(ept_access_test_teardown, NULL);
2767
2768 data->hva = get_1g_page();
2769 TEST_ASSERT(data->hva);
2770 data->hpa = virt_to_phys(data->hva);
2771
2772 data->gpa = 1ul << 39;
2773 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2),
2774 size);
2775 TEST_ASSERT(!any_present_pages(page_table, data->gva, size));
2776 install_pages(page_table, data->gpa, size, data->gva);
2777
2778 /*
2779 * Make sure nothing's mapped here so the tests that screw with the
2780 * pml4 entry don't inadvertently break something.
2781 */
2782 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0);
2783 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0);
2784 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT);
2785
2786 data->hva[0] = MAGIC_VAL_1;
2787 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start);
2788 }
2789
ept_access_test_not_present(void)2790 static void ept_access_test_not_present(void)
2791 {
2792 ept_access_test_setup();
2793 /* --- */
2794 ept_access_violation(0, OP_READ, EPT_VLT_RD);
2795 ept_access_violation(0, OP_WRITE, EPT_VLT_WR);
2796 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH);
2797 }
2798
ept_access_test_read_only(void)2799 static void ept_access_test_read_only(void)
2800 {
2801 ept_access_test_setup();
2802
2803 /* r-- */
2804 ept_access_allowed(EPT_RA, OP_READ);
2805 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD);
2806 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD);
2807 }
2808
ept_access_test_write_only(void)2809 static void ept_access_test_write_only(void)
2810 {
2811 ept_access_test_setup();
2812 /* -w- */
2813 ept_access_misconfig(EPT_WA);
2814 }
2815
ept_access_test_read_write(void)2816 static void ept_access_test_read_write(void)
2817 {
2818 ept_access_test_setup();
2819 /* rw- */
2820 ept_access_allowed(EPT_RA | EPT_WA, OP_READ);
2821 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE);
2822 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC,
2823 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR);
2824 }
2825
2826
ept_access_test_execute_only(void)2827 static void ept_access_test_execute_only(void)
2828 {
2829 ept_access_test_setup();
2830 /* --x */
2831 if (ept_execute_only_supported()) {
2832 ept_access_violation(EPT_EA, OP_READ,
2833 EPT_VLT_RD | EPT_VLT_PERM_EX);
2834 ept_access_violation(EPT_EA, OP_WRITE,
2835 EPT_VLT_WR | EPT_VLT_PERM_EX);
2836 ept_access_allowed(EPT_EA, OP_EXEC);
2837 } else {
2838 ept_access_misconfig(EPT_EA);
2839 }
2840 }
2841
ept_access_test_read_execute(void)2842 static void ept_access_test_read_execute(void)
2843 {
2844 ept_access_test_setup();
2845 /* r-x */
2846 ept_access_allowed(EPT_RA | EPT_EA, OP_READ);
2847 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE,
2848 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX);
2849 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC);
2850 }
2851
ept_access_test_write_execute(void)2852 static void ept_access_test_write_execute(void)
2853 {
2854 ept_access_test_setup();
2855 /* -wx */
2856 ept_access_misconfig(EPT_WA | EPT_EA);
2857 }
2858
ept_access_test_read_write_execute(void)2859 static void ept_access_test_read_write_execute(void)
2860 {
2861 ept_access_test_setup();
2862 /* rwx */
2863 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ);
2864 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE);
2865 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC);
2866 }
2867
ept_access_test_reserved_bits(void)2868 static void ept_access_test_reserved_bits(void)
2869 {
2870 int i;
2871 int maxphyaddr;
2872
2873 ept_access_test_setup();
2874
2875 /* Reserved bits above maxphyaddr. */
2876 maxphyaddr = cpuid_maxphyaddr();
2877 for (i = maxphyaddr; i <= 51; i++) {
2878 report_prefix_pushf("reserved_bit=%d", i);
2879 ept_reserved_bit(i);
2880 report_prefix_pop();
2881 }
2882
2883 /* Level-specific reserved bits. */
2884 ept_reserved_bit_at_level_nohuge(2, 3);
2885 ept_reserved_bit_at_level_nohuge(2, 4);
2886 ept_reserved_bit_at_level_nohuge(2, 5);
2887 ept_reserved_bit_at_level_nohuge(2, 6);
2888 /* 2M alignment. */
2889 for (i = 12; i < 20; i++) {
2890 report_prefix_pushf("reserved_bit=%d", i);
2891 ept_reserved_bit_at_level_huge(2, i);
2892 report_prefix_pop();
2893 }
2894 ept_reserved_bit_at_level_nohuge(3, 3);
2895 ept_reserved_bit_at_level_nohuge(3, 4);
2896 ept_reserved_bit_at_level_nohuge(3, 5);
2897 ept_reserved_bit_at_level_nohuge(3, 6);
2898 /* 1G alignment. */
2899 for (i = 12; i < 29; i++) {
2900 report_prefix_pushf("reserved_bit=%d", i);
2901 ept_reserved_bit_at_level_huge(3, i);
2902 report_prefix_pop();
2903 }
2904 ept_reserved_bit_at_level(4, 3);
2905 ept_reserved_bit_at_level(4, 4);
2906 ept_reserved_bit_at_level(4, 5);
2907 ept_reserved_bit_at_level(4, 6);
2908 ept_reserved_bit_at_level(4, 7);
2909 }
2910
ept_access_test_ignored_bits(void)2911 static void ept_access_test_ignored_bits(void)
2912 {
2913 ept_access_test_setup();
2914 /*
2915 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as
2916 * far as translation is concerned even if AD bits are enabled in the
2917 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution
2918 * control is 0.
2919 */
2920 ept_ignored_bit(8);
2921 ept_ignored_bit(9);
2922 ept_ignored_bit(10);
2923 ept_ignored_bit(11);
2924 ept_ignored_bit(52);
2925 ept_ignored_bit(53);
2926 ept_ignored_bit(54);
2927 ept_ignored_bit(55);
2928 ept_ignored_bit(56);
2929 ept_ignored_bit(57);
2930 ept_ignored_bit(58);
2931 ept_ignored_bit(59);
2932 ept_ignored_bit(60);
2933 ept_ignored_bit(61);
2934 ept_ignored_bit(62);
2935 ept_ignored_bit(63);
2936 }
2937
ept_access_test_paddr_not_present_ad_disabled(void)2938 static void ept_access_test_paddr_not_present_ad_disabled(void)
2939 {
2940 ept_access_test_setup();
2941 ept_disable_ad_bits();
2942
2943 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD);
2944 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD);
2945 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD);
2946 }
2947
ept_access_test_paddr_not_present_ad_enabled(void)2948 static void ept_access_test_paddr_not_present_ad_enabled(void)
2949 {
2950 u64 qual = EPT_VLT_RD | EPT_VLT_WR;
2951
2952 ept_access_test_setup();
2953 ept_enable_ad_bits_or_skip_test();
2954
2955 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual);
2956 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual);
2957 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual);
2958 }
2959
ept_access_test_paddr_read_only_ad_disabled(void)2960 static void ept_access_test_paddr_read_only_ad_disabled(void)
2961 {
2962 /*
2963 * When EPT AD bits are disabled, all accesses to guest paging
2964 * structures are reported separately as a read and (after
2965 * translation of the GPA to host physical address) a read+write
2966 * if the A/D bits have to be set.
2967 */
2968 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD;
2969
2970 ept_access_test_setup();
2971 ept_disable_ad_bits();
2972
2973 /* Can't update A bit, so all accesses fail. */
2974 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual);
2975 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual);
2976 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual);
2977 /* AD bits disabled, so only writes try to update the D bit. */
2978 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ);
2979 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual);
2980 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC);
2981 /* Both A and D already set, so read-only is OK. */
2982 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ);
2983 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE);
2984 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC);
2985 }
2986
ept_access_test_paddr_read_only_ad_enabled(void)2987 static void ept_access_test_paddr_read_only_ad_enabled(void)
2988 {
2989 /*
2990 * When EPT AD bits are enabled, all accesses to guest paging
2991 * structures are considered writes as far as EPT translation
2992 * is concerned.
2993 */
2994 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD;
2995
2996 ept_access_test_setup();
2997 ept_enable_ad_bits_or_skip_test();
2998
2999 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual);
3000 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual);
3001 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual);
3002 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual);
3003 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual);
3004 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual);
3005 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual);
3006 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual);
3007 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual);
3008 }
3009
ept_access_test_paddr_read_write(void)3010 static void ept_access_test_paddr_read_write(void)
3011 {
3012 ept_access_test_setup();
3013 /* Read-write access to paging structure. */
3014 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ);
3015 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE);
3016 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC);
3017 }
3018
ept_access_test_paddr_read_write_execute(void)3019 static void ept_access_test_paddr_read_write_execute(void)
3020 {
3021 ept_access_test_setup();
3022 /* RWX access to paging structure. */
3023 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ);
3024 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE);
3025 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC);
3026 }
3027
ept_access_test_paddr_read_execute_ad_disabled(void)3028 static void ept_access_test_paddr_read_execute_ad_disabled(void)
3029 {
3030 /*
3031 * When EPT AD bits are disabled, all accesses to guest paging
3032 * structures are reported separately as a read and (after
3033 * translation of the GPA to host physical address) a read+write
3034 * if the A/D bits have to be set.
3035 */
3036 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX;
3037
3038 ept_access_test_setup();
3039 ept_disable_ad_bits();
3040
3041 /* Can't update A bit, so all accesses fail. */
3042 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual);
3043 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual);
3044 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual);
3045 /* AD bits disabled, so only writes try to update the D bit. */
3046 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ);
3047 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual);
3048 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC);
3049 /* Both A and D already set, so read-only is OK. */
3050 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ);
3051 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE);
3052 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC);
3053 }
3054
ept_access_test_paddr_read_execute_ad_enabled(void)3055 static void ept_access_test_paddr_read_execute_ad_enabled(void)
3056 {
3057 /*
3058 * When EPT AD bits are enabled, all accesses to guest paging
3059 * structures are considered writes as far as EPT translation
3060 * is concerned.
3061 */
3062 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX;
3063
3064 ept_access_test_setup();
3065 ept_enable_ad_bits_or_skip_test();
3066
3067 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual);
3068 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual);
3069 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual);
3070 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual);
3071 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual);
3072 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual);
3073 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual);
3074 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual);
3075 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual);
3076 }
3077
ept_access_test_paddr_not_present_page_fault(void)3078 static void ept_access_test_paddr_not_present_page_fault(void)
3079 {
3080 ept_access_test_setup();
3081 /*
3082 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is
3083 * page is read-only in EPT but GVA is also mapped read only in PT.
3084 * Thus guest page fault before host takes EPT violation for trying to
3085 * update A bit.
3086 */
3087 }
3088
ept_access_test_force_2m_page(void)3089 static void ept_access_test_force_2m_page(void)
3090 {
3091 ept_access_test_setup();
3092
3093 TEST_ASSERT_EQ(ept_2m_supported(), true);
3094 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ);
3095 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE,
3096 EPT_VLT_WR | EPT_VLT_PERM_RD |
3097 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR);
3098 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA);
3099 }
3100
invvpid_valid(u64 type,u64 vpid,u64 gla)3101 static bool invvpid_valid(u64 type, u64 vpid, u64 gla)
3102 {
3103 if (!is_invvpid_type_supported(type))
3104 return false;
3105
3106 if (vpid >> 16)
3107 return false;
3108
3109 if (type != INVVPID_ALL && !vpid)
3110 return false;
3111
3112 if (type == INVVPID_ADDR && !is_canonical(gla))
3113 return false;
3114
3115 return true;
3116 }
3117
try_invvpid(u64 type,u64 vpid,u64 gla)3118 static void try_invvpid(u64 type, u64 vpid, u64 gla)
3119 {
3120 int rc;
3121 bool valid = invvpid_valid(type, vpid, gla);
3122 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT
3123 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID;
3124 /*
3125 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so
3126 * that we can tell if it is updated by INVVPID.
3127 */
3128 vmcs_read(~0);
3129 rc = __invvpid(type, vpid, gla);
3130 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type,
3131 vpid, gla,
3132 valid ? "passes" : "fails");
3133 report(vmcs_read(VMX_INST_ERROR) == expected,
3134 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)",
3135 rc ? "failed" : "successful",
3136 expected, vmcs_read(VMX_INST_ERROR));
3137 }
3138
get_first_supported_invvpid_type(void)3139 static inline unsigned long get_first_supported_invvpid_type(void)
3140 {
3141 u64 type = ffs(ept_vpid.val >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1;
3142
3143 __TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL);
3144 return type;
3145 }
3146
ds_invvpid(void * data)3147 static void ds_invvpid(void *data)
3148 {
3149 asm volatile("invvpid %0, %1"
3150 :
3151 : "m"(*(struct invvpid_operand *)data),
3152 "r"(get_first_supported_invvpid_type()));
3153 }
3154
3155 /*
3156 * The SS override is ignored in 64-bit mode, so we use an addressing
3157 * mode with %rsp as the base register to generate an implicit SS
3158 * reference.
3159 */
ss_invvpid(void * data)3160 static void ss_invvpid(void *data)
3161 {
3162 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1"
3163 : "+r"(data)
3164 : "r"(get_first_supported_invvpid_type()));
3165 }
3166
invvpid_test_gp(void)3167 static void invvpid_test_gp(void)
3168 {
3169 bool fault;
3170
3171 fault = test_for_exception(GP_VECTOR, &ds_invvpid,
3172 (void *)NONCANONICAL);
3173 report(fault, "INVVPID with non-canonical DS operand raises #GP");
3174 }
3175
invvpid_test_ss(void)3176 static void invvpid_test_ss(void)
3177 {
3178 bool fault;
3179
3180 fault = test_for_exception(SS_VECTOR, &ss_invvpid,
3181 (void *)NONCANONICAL);
3182 report(fault, "INVVPID with non-canonical SS operand raises #SS");
3183 }
3184
invvpid_test_pf(void)3185 static void invvpid_test_pf(void)
3186 {
3187 void *vpage = alloc_vpage();
3188 bool fault;
3189
3190 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage);
3191 report(fault, "INVVPID with unmapped operand raises #PF");
3192 }
3193
try_compat_invvpid(void * unused)3194 static void try_compat_invvpid(void *unused)
3195 {
3196 struct far_pointer32 fp = {
3197 .offset = (uintptr_t)&&invvpid,
3198 .selector = KERNEL_CS32,
3199 };
3200 uintptr_t rsp;
3201
3202 asm volatile ("mov %%rsp, %0" : "=r"(rsp));
3203
3204 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid,
3205 "Code address too high.");
3206 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high.");
3207
3208 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid);
3209 return;
3210 invvpid:
3211 asm volatile (".code32;"
3212 "invvpid (%eax), %eax;"
3213 "lret;"
3214 ".code64");
3215 __builtin_unreachable();
3216 }
3217
invvpid_test_compatibility_mode(void)3218 static void invvpid_test_compatibility_mode(void)
3219 {
3220 bool fault;
3221
3222 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL);
3223 report(fault, "Compatibility mode INVVPID raises #UD");
3224 }
3225
invvpid_test_not_in_vmx_operation(void)3226 static void invvpid_test_not_in_vmx_operation(void)
3227 {
3228 bool fault;
3229
3230 TEST_ASSERT(!vmx_off());
3231 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL);
3232 report(fault, "INVVPID outside of VMX operation raises #UD");
3233 TEST_ASSERT(!vmx_on());
3234 }
3235
3236 /* LAM doesn't apply to the linear address inside the descriptor of invvpid */
invvpid_test_lam(void)3237 static void invvpid_test_lam(void)
3238 {
3239 void *vaddr;
3240 struct invvpid_operand *operand;
3241 u64 lam_mask;
3242 bool fault;
3243
3244 if (!this_cpu_has(X86_FEATURE_LAM)) {
3245 report_skip("LAM is not supported, skip INVVPID with LAM");
3246 return;
3247 }
3248
3249 write_cr4(read_cr4() | X86_CR4_LAM_SUP);
3250 lam_mask = is_la57_enabled() ? LAM57_MASK : LAM48_MASK;
3251
3252 vaddr = alloc_vpage();
3253 install_page(current_page_table(), virt_to_phys(alloc_page()), vaddr);
3254 /*
3255 * Since the stack memory address in KUT doesn't follow kernel address
3256 * space partition rule, reuse the memory address for descriptor and
3257 * the target address in the descriptor of invvpid.
3258 */
3259 operand = (struct invvpid_operand *)vaddr;
3260 operand->vpid = 0xffff;
3261 operand->gla = (u64)vaddr;
3262 operand = (struct invvpid_operand *)get_non_canonical((u64)operand, lam_mask);
3263 fault = test_for_exception(GP_VECTOR, ds_invvpid, operand);
3264 report(!fault, "Expected INVVPID with tagged operand when LAM is enabled to succeed");
3265
3266 /*
3267 * Verify that LAM doesn't apply to the address inside the descriptor
3268 * even when LAM is enabled. i.e., the address in the descriptor should
3269 * be canonical.
3270 */
3271 try_invvpid(INVVPID_ADDR, 0xffff, (u64)operand);
3272
3273 write_cr4(read_cr4() & ~X86_CR4_LAM_SUP);
3274 }
3275
3276 /*
3277 * This does not test real-address mode, virtual-8086 mode, protected mode,
3278 * or CPL > 0.
3279 */
invvpid_test(void)3280 static void invvpid_test(void)
3281 {
3282 int i;
3283 unsigned types = 0;
3284 unsigned type;
3285
3286 if (!is_vpid_supported())
3287 test_skip("VPID not supported");
3288
3289 if (!is_invvpid_supported())
3290 test_skip("INVVPID not supported.\n");
3291
3292 if (is_invvpid_type_supported(INVVPID_ADDR))
3293 types |= 1u << INVVPID_ADDR;
3294 if (is_invvpid_type_supported(INVVPID_CONTEXT_GLOBAL))
3295 types |= 1u << INVVPID_CONTEXT_GLOBAL;
3296 if (is_invvpid_type_supported(INVVPID_ALL))
3297 types |= 1u << INVVPID_ALL;
3298 if (is_invvpid_type_supported(INVVPID_CONTEXT_LOCAL))
3299 types |= 1u << INVVPID_CONTEXT_LOCAL;
3300
3301 if (!types)
3302 test_skip("No INVVPID types supported.\n");
3303
3304 for (i = -127; i < 128; i++)
3305 try_invvpid(i, 0xffff, 0);
3306
3307 /*
3308 * VPID must not be more than 16 bits.
3309 */
3310 for (i = 0; i < 64; i++)
3311 for (type = 0; type < 4; type++)
3312 if (types & (1u << type))
3313 try_invvpid(type, 1ul << i, 0);
3314
3315 /*
3316 * VPID must not be zero, except for "all contexts."
3317 */
3318 for (type = 0; type < 4; type++)
3319 if (types & (1u << type))
3320 try_invvpid(type, 0, 0);
3321
3322 /*
3323 * The gla operand is only validated for single-address INVVPID.
3324 */
3325 if (types & (1u << INVVPID_ADDR)) {
3326 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL);
3327 invvpid_test_lam();
3328 }
3329
3330 invvpid_test_gp();
3331 invvpid_test_ss();
3332 invvpid_test_pf();
3333 invvpid_test_compatibility_mode();
3334 invvpid_test_not_in_vmx_operation();
3335 }
3336
test_assert_vmlaunch_inst_error(u32 expected_error)3337 static void test_assert_vmlaunch_inst_error(u32 expected_error)
3338 {
3339 u32 vmx_inst_err = vmcs_read(VMX_INST_ERROR);
3340
3341 report(vmx_inst_err == expected_error,
3342 "VMX inst error is %d (actual %d)", expected_error, vmx_inst_err);
3343 }
3344
3345 /*
3346 * This version is wildly unsafe and should _only_ be used to test VM-Fail
3347 * scenarios involving HOST_RIP.
3348 */
test_vmx_vmlaunch_must_fail(u32 expected_error)3349 static void test_vmx_vmlaunch_must_fail(u32 expected_error)
3350 {
3351 /* Read the function name. */
3352 TEST_ASSERT(expected_error);
3353
3354 /*
3355 * Don't bother with any prep work, if VMLAUNCH passes the VM-Fail
3356 * consistency checks and generates a VM-Exit, then the test is doomed
3357 * no matter what as it will jump to a garbage RIP.
3358 */
3359 __asm__ __volatile__ ("vmlaunch");
3360 test_assert_vmlaunch_inst_error(expected_error);
3361 }
3362
3363 /*
3364 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it
3365 * at least as far as the guest-state checks. Returns false if the
3366 * VMLAUNCH fails early and execution falls through to the next
3367 * instruction.
3368 */
vmlaunch(void)3369 static bool vmlaunch(void)
3370 {
3371 u32 exit_reason;
3372
3373 /*
3374 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to
3375 * unsupported VMCS component"). The caller can then check
3376 * to see if a failed VM-entry sets VMX_INST_ERR as expected.
3377 */
3378 vmcs_write(~0u, 0);
3379
3380 vmcs_write(HOST_RIP, (uintptr_t)&&success);
3381 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch"
3382 :
3383 : "r" ((u64)HOST_RSP)
3384 : "cc", "memory"
3385 : success);
3386 return false;
3387 success:
3388 exit_reason = vmcs_read(EXI_REASON);
3389 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) ||
3390 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE));
3391 return true;
3392 }
3393
3394 /*
3395 * Try to launch the current VMCS.
3396 */
test_vmx_vmlaunch(u32 xerror)3397 static void test_vmx_vmlaunch(u32 xerror)
3398 {
3399 bool success = vmlaunch();
3400
3401 report(success == !xerror, "vmlaunch %s",
3402 !xerror ? "succeeds" : "fails");
3403 if (!success && xerror)
3404 test_assert_vmlaunch_inst_error(xerror);
3405 }
3406
3407 /*
3408 * Try to launch the current VMCS, and expect one of two possible
3409 * errors (or success) codes.
3410 */
test_vmx_vmlaunch2(u32 xerror1,u32 xerror2)3411 static void test_vmx_vmlaunch2(u32 xerror1, u32 xerror2)
3412 {
3413 bool success = vmlaunch();
3414 u32 vmx_inst_err;
3415
3416 if (!xerror1 == !xerror2)
3417 report(success == !xerror1, "vmlaunch %s",
3418 !xerror1 ? "succeeds" : "fails");
3419
3420 if (!success && (xerror1 || xerror2)) {
3421 vmx_inst_err = vmcs_read(VMX_INST_ERROR);
3422 report(vmx_inst_err == xerror1 || vmx_inst_err == xerror2,
3423 "VMX inst error is %d or %d (actual %d)", xerror1,
3424 xerror2, vmx_inst_err);
3425 }
3426 }
3427
test_vmx_invalid_controls(void)3428 static void test_vmx_invalid_controls(void)
3429 {
3430 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD);
3431 }
3432
test_vmx_valid_controls(void)3433 static void test_vmx_valid_controls(void)
3434 {
3435 test_vmx_vmlaunch(0);
3436 }
3437
3438 /*
3439 * Test a particular value of a VM-execution control bit, if the value
3440 * is required or if the value is zero.
3441 */
test_rsvd_ctl_bit_value(const char * name,union vmx_ctrl_msr msr,enum Encoding encoding,unsigned bit,unsigned val)3442 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr,
3443 enum Encoding encoding, unsigned bit,
3444 unsigned val)
3445 {
3446 u32 mask = 1u << bit;
3447 bool expected;
3448 u32 controls;
3449
3450 if (msr.set & mask)
3451 TEST_ASSERT(msr.clr & mask);
3452
3453 /*
3454 * We can't arbitrarily turn on a control bit, because it may
3455 * introduce dependencies on other VMCS fields. So, we only
3456 * test turning on bits that have a required setting.
3457 */
3458 if (val && (msr.clr & mask) && !(msr.set & mask))
3459 return;
3460
3461 report_prefix_pushf("%s %s bit %d",
3462 val ? "Set" : "Clear", name, bit);
3463
3464 controls = vmcs_read(encoding);
3465 if (val) {
3466 vmcs_write(encoding, msr.set | mask);
3467 expected = (msr.clr & mask);
3468 } else {
3469 vmcs_write(encoding, msr.set & ~mask);
3470 expected = !(msr.set & mask);
3471 }
3472 if (expected)
3473 test_vmx_valid_controls();
3474 else
3475 test_vmx_invalid_controls();
3476 vmcs_write(encoding, controls);
3477 report_prefix_pop();
3478 }
3479
3480 /*
3481 * Test reserved values of a VM-execution control bit, based on the
3482 * allowed bit settings from the corresponding VMX capability MSR.
3483 */
test_rsvd_ctl_bit(const char * name,union vmx_ctrl_msr msr,enum Encoding encoding,unsigned bit)3484 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr,
3485 enum Encoding encoding, unsigned bit)
3486 {
3487 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0);
3488 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1);
3489 }
3490
3491 /*
3492 * Reserved bits in the pin-based VM-execution controls must be set
3493 * properly. Software may consult the VMX capability MSRs to determine
3494 * the proper settings.
3495 * [Intel SDM]
3496 */
test_pin_based_ctls(void)3497 static void test_pin_based_ctls(void)
3498 {
3499 unsigned bit;
3500
3501 printf("%s: %lx\n", basic_msr.ctrl ? "MSR_IA32_VMX_TRUE_PIN" :
3502 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val);
3503 for (bit = 0; bit < 32; bit++)
3504 test_rsvd_ctl_bit("pin-based controls",
3505 ctrl_pin_rev, PIN_CONTROLS, bit);
3506 }
3507
3508 /*
3509 * Reserved bits in the primary processor-based VM-execution controls
3510 * must be set properly. Software may consult the VMX capability MSRs
3511 * to determine the proper settings.
3512 * [Intel SDM]
3513 */
test_primary_processor_based_ctls(void)3514 static void test_primary_processor_based_ctls(void)
3515 {
3516 unsigned bit;
3517
3518 printf("\n%s: %lx\n", basic_msr.ctrl ? "MSR_IA32_VMX_TRUE_PROC" :
3519 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val);
3520 for (bit = 0; bit < 32; bit++)
3521 test_rsvd_ctl_bit("primary processor-based controls",
3522 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit);
3523 }
3524
3525 /*
3526 * If the "activate secondary controls" primary processor-based
3527 * VM-execution control is 1, reserved bits in the secondary
3528 * processor-based VM-execution controls must be cleared. Software may
3529 * consult the VMX capability MSRs to determine which bits are
3530 * reserved.
3531 * If the "activate secondary controls" primary processor-based
3532 * VM-execution control is 0 (or if the processor does not support the
3533 * 1-setting of that control), no checks are performed on the
3534 * secondary processor-based VM-execution controls.
3535 * [Intel SDM]
3536 */
test_secondary_processor_based_ctls(void)3537 static void test_secondary_processor_based_ctls(void)
3538 {
3539 u32 primary;
3540 u32 secondary;
3541 unsigned bit;
3542
3543 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY))
3544 return;
3545
3546 primary = vmcs_read(CPU_EXEC_CTRL0);
3547 secondary = vmcs_read(CPU_EXEC_CTRL1);
3548
3549 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY);
3550 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val);
3551 for (bit = 0; bit < 32; bit++)
3552 test_rsvd_ctl_bit("secondary processor-based controls",
3553 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit);
3554
3555 /*
3556 * When the "activate secondary controls" VM-execution control
3557 * is clear, there are no checks on the secondary controls.
3558 */
3559 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY);
3560 vmcs_write(CPU_EXEC_CTRL1, ~0);
3561 report(vmlaunch(),
3562 "Secondary processor-based controls ignored");
3563 vmcs_write(CPU_EXEC_CTRL1, secondary);
3564 vmcs_write(CPU_EXEC_CTRL0, primary);
3565 }
3566
try_cr3_target_count(unsigned i,unsigned max)3567 static void try_cr3_target_count(unsigned i, unsigned max)
3568 {
3569 report_prefix_pushf("CR3 target count 0x%x", i);
3570 vmcs_write(CR3_TARGET_COUNT, i);
3571 if (i <= max)
3572 test_vmx_valid_controls();
3573 else
3574 test_vmx_invalid_controls();
3575 report_prefix_pop();
3576 }
3577
3578 /*
3579 * The CR3-target count must not be greater than 4. Future processors
3580 * may support a different number of CR3-target values. Software
3581 * should read the VMX capability MSR IA32_VMX_MISC to determine the
3582 * number of values supported.
3583 * [Intel SDM]
3584 */
test_cr3_targets(void)3585 static void test_cr3_targets(void)
3586 {
3587 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff;
3588 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT);
3589 unsigned i;
3590
3591 printf("\nSupported CR3 targets: %d\n", supported_targets);
3592 TEST_ASSERT(supported_targets <= 256);
3593
3594 try_cr3_target_count(-1u, supported_targets);
3595 try_cr3_target_count(0x80000000, supported_targets);
3596 try_cr3_target_count(0x7fffffff, supported_targets);
3597 for (i = 0; i <= supported_targets + 1; i++)
3598 try_cr3_target_count(i, supported_targets);
3599 vmcs_write(CR3_TARGET_COUNT, cr3_targets);
3600
3601 /* VMWRITE to nonexistent target fields should fail. */
3602 for (i = supported_targets; i < 256; i++)
3603 TEST_ASSERT(vmcs_write(CR3_TARGET_0 + i*2, 0));
3604 }
3605
3606 /*
3607 * Test a particular address setting in the VMCS
3608 */
test_vmcs_addr(const char * name,enum Encoding encoding,u64 align,bool ignored,bool skip_beyond_mapped_ram,u64 addr)3609 static void test_vmcs_addr(const char *name,
3610 enum Encoding encoding,
3611 u64 align,
3612 bool ignored,
3613 bool skip_beyond_mapped_ram,
3614 u64 addr)
3615 {
3616 report_prefix_pushf("%s = %lx", name, addr);
3617 vmcs_write(encoding, addr);
3618 if (skip_beyond_mapped_ram &&
3619 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align &&
3620 addr < (1ul << cpuid_maxphyaddr()))
3621 printf("Skipping physical address beyond mapped RAM\n");
3622 else if (ignored || (IS_ALIGNED(addr, align) &&
3623 addr < (1ul << cpuid_maxphyaddr())))
3624 test_vmx_valid_controls();
3625 else
3626 test_vmx_invalid_controls();
3627 report_prefix_pop();
3628 }
3629
3630 /*
3631 * Test interesting values for a VMCS address
3632 */
test_vmcs_addr_values(const char * name,enum Encoding encoding,u64 align,bool ignored,bool skip_beyond_mapped_ram,u32 bit_start,u32 bit_end)3633 static void test_vmcs_addr_values(const char *name,
3634 enum Encoding encoding,
3635 u64 align,
3636 bool ignored,
3637 bool skip_beyond_mapped_ram,
3638 u32 bit_start, u32 bit_end)
3639 {
3640 unsigned i;
3641 u64 orig_val = vmcs_read(encoding);
3642
3643 for (i = bit_start; i <= bit_end; i++)
3644 test_vmcs_addr(name, encoding, align, ignored,
3645 skip_beyond_mapped_ram, 1ul << i);
3646
3647 test_vmcs_addr(name, encoding, align, ignored,
3648 skip_beyond_mapped_ram, PAGE_SIZE - 1);
3649 test_vmcs_addr(name, encoding, align, ignored,
3650 skip_beyond_mapped_ram, PAGE_SIZE);
3651 test_vmcs_addr(name, encoding, align, ignored,
3652 skip_beyond_mapped_ram,
3653 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE);
3654 test_vmcs_addr(name, encoding, align, ignored,
3655 skip_beyond_mapped_ram, -1ul);
3656
3657 vmcs_write(encoding, orig_val);
3658 }
3659
3660 /*
3661 * Test a physical address reference in the VMCS, when the corresponding
3662 * feature is enabled and when the corresponding feature is disabled.
3663 */
test_vmcs_addr_reference(u32 control_bit,enum Encoding field,const char * field_name,const char * control_name,u64 align,bool skip_beyond_mapped_ram,bool control_primary)3664 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field,
3665 const char *field_name,
3666 const char *control_name, u64 align,
3667 bool skip_beyond_mapped_ram,
3668 bool control_primary)
3669 {
3670 u32 primary = vmcs_read(CPU_EXEC_CTRL0);
3671 u32 secondary = vmcs_read(CPU_EXEC_CTRL1);
3672 u64 page_addr;
3673
3674 if (control_primary) {
3675 if (!(ctrl_cpu_rev[0].clr & control_bit))
3676 return;
3677 } else {
3678 if (!(ctrl_cpu_rev[1].clr & control_bit))
3679 return;
3680 }
3681
3682 page_addr = vmcs_read(field);
3683
3684 report_prefix_pushf("%s enabled", control_name);
3685 if (control_primary) {
3686 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit);
3687 } else {
3688 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY);
3689 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit);
3690 }
3691
3692 test_vmcs_addr_values(field_name, field, align, false,
3693 skip_beyond_mapped_ram, 0, 63);
3694 report_prefix_pop();
3695
3696 report_prefix_pushf("%s disabled", control_name);
3697 if (control_primary) {
3698 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit);
3699 } else {
3700 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY);
3701 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit);
3702 }
3703
3704 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63);
3705 report_prefix_pop();
3706
3707 vmcs_write(field, page_addr);
3708 vmcs_write(CPU_EXEC_CTRL0, primary);
3709 vmcs_write(CPU_EXEC_CTRL1, secondary);
3710 }
3711
3712 /*
3713 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of
3714 * each I/O-bitmap address must be 0. Neither address should set any
3715 * bits beyond the processor's physical-address width.
3716 * [Intel SDM]
3717 */
test_io_bitmaps(void)3718 static void test_io_bitmaps(void)
3719 {
3720 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A,
3721 "I/O bitmap A", "Use I/O bitmaps",
3722 PAGE_SIZE, false, true);
3723 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B,
3724 "I/O bitmap B", "Use I/O bitmaps",
3725 PAGE_SIZE, false, true);
3726 }
3727
3728 /*
3729 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of
3730 * the MSR-bitmap address must be 0. The address should not set any
3731 * bits beyond the processor's physical-address width.
3732 * [Intel SDM]
3733 */
test_msr_bitmap(void)3734 static void test_msr_bitmap(void)
3735 {
3736 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP,
3737 "MSR bitmap", "Use MSR bitmaps",
3738 PAGE_SIZE, false, true);
3739 }
3740
3741 /*
3742 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC
3743 * address must satisfy the following checks:
3744 * - Bits 11:0 of the address must be 0.
3745 * - The address should not set any bits beyond the processor's
3746 * physical-address width.
3747 * [Intel SDM]
3748 */
test_apic_virt_addr(void)3749 static void test_apic_virt_addr(void)
3750 {
3751 /*
3752 * Ensure the processor will never use the virtual-APIC page, since
3753 * we will point it to invalid RAM. Otherwise KVM is puzzled about
3754 * what we're trying to achieve and fails vmentry.
3755 */
3756 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0);
3757 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE);
3758 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR,
3759 "virtual-APIC address", "Use TPR shadow",
3760 PAGE_SIZE, false, true);
3761 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0);
3762 }
3763
3764 /*
3765 * If the "virtualize APIC-accesses" VM-execution control is 1, the
3766 * APIC-access address must satisfy the following checks:
3767 * - Bits 11:0 of the address must be 0.
3768 * - The address should not set any bits beyond the processor's
3769 * physical-address width.
3770 * [Intel SDM]
3771 */
test_apic_access_addr(void)3772 static void test_apic_access_addr(void)
3773 {
3774 void *apic_access_page = alloc_page();
3775
3776 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page));
3777
3778 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR,
3779 "APIC-access address",
3780 "virtualize APIC-accesses", PAGE_SIZE,
3781 true, false);
3782 }
3783
set_bit_pattern(u8 mask,u32 * secondary)3784 static bool set_bit_pattern(u8 mask, u32 *secondary)
3785 {
3786 u8 i;
3787 bool flag = false;
3788 u32 test_bits[3] = {
3789 CPU_VIRT_X2APIC,
3790 CPU_APIC_REG_VIRT,
3791 CPU_VINTD
3792 };
3793
3794 for (i = 0; i < ARRAY_SIZE(test_bits); i++) {
3795 if ((mask & (1u << i)) &&
3796 (ctrl_cpu_rev[1].clr & test_bits[i])) {
3797 *secondary |= test_bits[i];
3798 flag = true;
3799 }
3800 }
3801
3802 return (flag);
3803 }
3804
3805 /*
3806 * If the "use TPR shadow" VM-execution control is 0, the following
3807 * VM-execution controls must also be 0:
3808 * - virtualize x2APIC mode
3809 * - APIC-register virtualization
3810 * - virtual-interrupt delivery
3811 * [Intel SDM]
3812 *
3813 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the
3814 * "virtualize APIC accesses" VM-execution control must be 0.
3815 * [Intel SDM]
3816 */
test_apic_virtual_ctls(void)3817 static void test_apic_virtual_ctls(void)
3818 {
3819 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0);
3820 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1);
3821 u32 primary = saved_primary;
3822 u32 secondary = saved_secondary;
3823 bool is_ctrl_valid = false;
3824 char str[10] = "disabled";
3825 u8 i = 0, j;
3826
3827 /*
3828 * First test
3829 */
3830 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) ==
3831 (CPU_SECONDARY | CPU_TPR_SHADOW)))
3832 return;
3833
3834 primary |= CPU_SECONDARY;
3835 primary &= ~CPU_TPR_SHADOW;
3836 vmcs_write(CPU_EXEC_CTRL0, primary);
3837
3838 while (1) {
3839 for (j = 1; j < 8; j++) {
3840 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD);
3841 if (primary & CPU_TPR_SHADOW) {
3842 is_ctrl_valid = true;
3843 } else {
3844 if (! set_bit_pattern(j, &secondary))
3845 is_ctrl_valid = true;
3846 else
3847 is_ctrl_valid = false;
3848 }
3849
3850 vmcs_write(CPU_EXEC_CTRL1, secondary);
3851 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s",
3852 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled");
3853 if (is_ctrl_valid)
3854 test_vmx_valid_controls();
3855 else
3856 test_vmx_invalid_controls();
3857 report_prefix_pop();
3858 }
3859
3860 if (i == 1)
3861 break;
3862 i++;
3863
3864 primary |= CPU_TPR_SHADOW;
3865 vmcs_write(CPU_EXEC_CTRL0, primary);
3866 strcpy(str, "enabled");
3867 }
3868
3869 /*
3870 * Second test
3871 */
3872 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES);
3873
3874 primary = saved_primary;
3875 secondary = saved_secondary;
3876 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls))
3877 return;
3878
3879 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY);
3880 secondary &= ~CPU_VIRT_APIC_ACCESSES;
3881 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC);
3882 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled");
3883 test_vmx_valid_controls();
3884 report_prefix_pop();
3885
3886 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES);
3887 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled");
3888 test_vmx_valid_controls();
3889 report_prefix_pop();
3890
3891 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC);
3892 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled");
3893 test_vmx_invalid_controls();
3894 report_prefix_pop();
3895
3896 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES);
3897 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled");
3898 test_vmx_valid_controls();
3899 report_prefix_pop();
3900
3901 vmcs_write(CPU_EXEC_CTRL0, saved_primary);
3902 vmcs_write(CPU_EXEC_CTRL1, saved_secondary);
3903 }
3904
3905 /*
3906 * If the "virtual-interrupt delivery" VM-execution control is 1, the
3907 * "external-interrupt exiting" VM-execution control must be 1.
3908 * [Intel SDM]
3909 */
test_virtual_intr_ctls(void)3910 static void test_virtual_intr_ctls(void)
3911 {
3912 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0);
3913 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1);
3914 u32 saved_pin = vmcs_read(PIN_CONTROLS);
3915 u32 primary = saved_primary;
3916 u32 secondary = saved_secondary;
3917 u32 pin = saved_pin;
3918
3919 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) &&
3920 (ctrl_pin_rev.clr & PIN_EXTINT)))
3921 return;
3922
3923 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW);
3924 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD);
3925 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT);
3926 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled");
3927 test_vmx_valid_controls();
3928 report_prefix_pop();
3929
3930 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD);
3931 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled");
3932 test_vmx_invalid_controls();
3933 report_prefix_pop();
3934
3935 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT);
3936 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled");
3937 test_vmx_valid_controls();
3938 report_prefix_pop();
3939
3940 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT);
3941 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled");
3942 test_vmx_invalid_controls();
3943 report_prefix_pop();
3944
3945 vmcs_write(CPU_EXEC_CTRL0, saved_primary);
3946 vmcs_write(CPU_EXEC_CTRL1, saved_secondary);
3947 vmcs_write(PIN_CONTROLS, saved_pin);
3948 }
3949
test_pi_desc_addr(u64 addr,bool is_ctrl_valid)3950 static void test_pi_desc_addr(u64 addr, bool is_ctrl_valid)
3951 {
3952 vmcs_write(POSTED_INTR_DESC_ADDR, addr);
3953 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr);
3954 if (is_ctrl_valid)
3955 test_vmx_valid_controls();
3956 else
3957 test_vmx_invalid_controls();
3958 report_prefix_pop();
3959 }
3960
3961 /*
3962 * If the "process posted interrupts" VM-execution control is 1, the
3963 * following must be true:
3964 *
3965 * - The "virtual-interrupt delivery" VM-execution control is 1.
3966 * - The "acknowledge interrupt on exit" VM-exit control is 1.
3967 * - The posted-interrupt notification vector has a value in the
3968 * - range 0 - 255 (bits 15:8 are all 0).
3969 * - Bits 5:0 of the posted-interrupt descriptor address are all 0.
3970 * - The posted-interrupt descriptor address does not set any bits
3971 * beyond the processor's physical-address width.
3972 * [Intel SDM]
3973 */
test_posted_intr(void)3974 static void test_posted_intr(void)
3975 {
3976 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0);
3977 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1);
3978 u32 saved_pin = vmcs_read(PIN_CONTROLS);
3979 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS);
3980 u32 primary = saved_primary;
3981 u32 secondary = saved_secondary;
3982 u32 pin = saved_pin;
3983 u32 exit_ctl = exit_ctl_saved;
3984 u16 vec;
3985 int i;
3986
3987 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) &&
3988 (ctrl_cpu_rev[1].clr & CPU_VINTD) &&
3989 (ctrl_exit_rev.clr & EXI_INTA)))
3990 return;
3991
3992 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW);
3993
3994 /*
3995 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit
3996 */
3997 pin |= PIN_POST_INTR;
3998 vmcs_write(PIN_CONTROLS, pin);
3999 secondary &= ~CPU_VINTD;
4000 vmcs_write(CPU_EXEC_CTRL1, secondary);
4001 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled");
4002 test_vmx_invalid_controls();
4003 report_prefix_pop();
4004
4005 secondary |= CPU_VINTD;
4006 vmcs_write(CPU_EXEC_CTRL1, secondary);
4007 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled");
4008 test_vmx_invalid_controls();
4009 report_prefix_pop();
4010
4011 exit_ctl &= ~EXI_INTA;
4012 vmcs_write(EXI_CONTROLS, exit_ctl);
4013 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled");
4014 test_vmx_invalid_controls();
4015 report_prefix_pop();
4016
4017 exit_ctl |= EXI_INTA;
4018 vmcs_write(EXI_CONTROLS, exit_ctl);
4019 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled");
4020 test_vmx_valid_controls();
4021 report_prefix_pop();
4022
4023 secondary &= ~CPU_VINTD;
4024 vmcs_write(CPU_EXEC_CTRL1, secondary);
4025 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled");
4026 test_vmx_invalid_controls();
4027 report_prefix_pop();
4028
4029 secondary |= CPU_VINTD;
4030 vmcs_write(CPU_EXEC_CTRL1, secondary);
4031 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled");
4032 test_vmx_valid_controls();
4033 report_prefix_pop();
4034
4035 /*
4036 * Test posted-interrupt notification vector
4037 */
4038 for (i = 0; i < 8; i++) {
4039 vec = (1ul << i);
4040 vmcs_write(PINV, vec);
4041 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec);
4042 test_vmx_valid_controls();
4043 report_prefix_pop();
4044 }
4045 for (i = 8; i < 16; i++) {
4046 vec = (1ul << i);
4047 vmcs_write(PINV, vec);
4048 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec);
4049 test_vmx_invalid_controls();
4050 report_prefix_pop();
4051 }
4052
4053 vec &= ~(0xff << 8);
4054 vmcs_write(PINV, vec);
4055 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec);
4056 test_vmx_valid_controls();
4057 report_prefix_pop();
4058
4059 /*
4060 * Test posted-interrupt descriptor address
4061 */
4062 for (i = 0; i < 6; i++) {
4063 test_pi_desc_addr(1ul << i, false);
4064 }
4065
4066 test_pi_desc_addr(0xf0, false);
4067 test_pi_desc_addr(0xff, false);
4068 test_pi_desc_addr(0x0f, false);
4069 test_pi_desc_addr(0x8000, true);
4070 test_pi_desc_addr(0x00, true);
4071 test_pi_desc_addr(0xc000, true);
4072
4073 test_vmcs_addr_values("process-posted interrupts",
4074 POSTED_INTR_DESC_ADDR, 64,
4075 false, false, 0, 63);
4076
4077 vmcs_write(CPU_EXEC_CTRL0, saved_primary);
4078 vmcs_write(CPU_EXEC_CTRL1, saved_secondary);
4079 vmcs_write(PIN_CONTROLS, saved_pin);
4080 }
4081
test_apic_ctls(void)4082 static void test_apic_ctls(void)
4083 {
4084 test_apic_virt_addr();
4085 test_apic_access_addr();
4086 test_apic_virtual_ctls();
4087 test_virtual_intr_ctls();
4088 test_posted_intr();
4089 }
4090
4091 /*
4092 * If the "enable VPID" VM-execution control is 1, the value of the
4093 * of the VPID VM-execution control field must not be 0000H.
4094 * [Intel SDM]
4095 */
test_vpid(void)4096 static void test_vpid(void)
4097 {
4098 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0);
4099 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1);
4100 u16 vpid = 0x0000;
4101 int i;
4102
4103 if (!is_vpid_supported()) {
4104 report_skip("%s : Secondary controls and/or VPID not supported", __func__);
4105 return;
4106 }
4107
4108 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY);
4109 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID);
4110 vmcs_write(VPID, vpid);
4111 report_prefix_pushf("VPID disabled; VPID value %x", vpid);
4112 test_vmx_valid_controls();
4113 report_prefix_pop();
4114
4115 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID);
4116 report_prefix_pushf("VPID enabled; VPID value %x", vpid);
4117 test_vmx_invalid_controls();
4118 report_prefix_pop();
4119
4120 for (i = 0; i < 16; i++) {
4121 vpid = (short)1 << i;;
4122 vmcs_write(VPID, vpid);
4123 report_prefix_pushf("VPID enabled; VPID value %x", vpid);
4124 test_vmx_valid_controls();
4125 report_prefix_pop();
4126 }
4127
4128 vmcs_write(CPU_EXEC_CTRL0, saved_primary);
4129 vmcs_write(CPU_EXEC_CTRL1, saved_secondary);
4130 }
4131
set_vtpr(unsigned vtpr)4132 static void set_vtpr(unsigned vtpr)
4133 {
4134 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr;
4135 }
4136
try_tpr_threshold_and_vtpr(unsigned threshold,unsigned vtpr)4137 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr)
4138 {
4139 bool valid = true;
4140 u32 primary = vmcs_read(CPU_EXEC_CTRL0);
4141 u32 secondary = vmcs_read(CPU_EXEC_CTRL1);
4142
4143 if ((primary & CPU_TPR_SHADOW) &&
4144 (!(primary & CPU_SECONDARY) ||
4145 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES))))
4146 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf);
4147
4148 set_vtpr(vtpr);
4149 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x",
4150 threshold, (vtpr >> 4) & 0xf);
4151 if (valid)
4152 test_vmx_valid_controls();
4153 else
4154 test_vmx_invalid_controls();
4155 report_prefix_pop();
4156 }
4157
test_invalid_event_injection(void)4158 static void test_invalid_event_injection(void)
4159 {
4160 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO);
4161 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR);
4162 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN);
4163 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0);
4164 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1);
4165 u64 guest_cr0_save = vmcs_read(GUEST_CR0);
4166 u32 ent_intr_info_base = INTR_INFO_VALID_MASK;
4167 u32 ent_intr_info, ent_intr_err, ent_intr_len;
4168 u32 cnt;
4169
4170 /* Setup */
4171 report_prefix_push("invalid event injection");
4172 vmcs_write(ENT_INTR_ERROR, 0x00000000);
4173 vmcs_write(ENT_INST_LEN, 0x00000001);
4174
4175 /* The field's interruption type is not set to a reserved value. */
4176 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR;
4177 report_prefix_pushf("%s, VM-entry intr info=0x%x",
4178 "RESERVED interruption type invalid [-]",
4179 ent_intr_info);
4180 vmcs_write(ENT_INTR_INFO, ent_intr_info);
4181 test_vmx_invalid_controls();
4182 report_prefix_pop();
4183
4184 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR |
4185 DE_VECTOR;
4186 report_prefix_pushf("%s, VM-entry intr info=0x%x",
4187 "RESERVED interruption type invalid [+]",
4188 ent_intr_info);
4189 vmcs_write(ENT_INTR_INFO, ent_intr_info);
4190 test_vmx_valid_controls();
4191 report_prefix_pop();
4192
4193 /* If the interruption type is other event, the vector is 0. */
4194 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR;
4195 report_prefix_pushf("%s, VM-entry intr info=0x%x",
4196 "(OTHER EVENT && vector != 0) invalid [-]",
4197 ent_intr_info);
4198 vmcs_write(ENT_INTR_INFO, ent_intr_info);
4199 test_vmx_invalid_controls();
4200 report_prefix_pop();
4201
4202 /* If the interruption type is NMI, the vector is 2 (negative case). */
4203 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR;
4204 report_prefix_pushf("%s, VM-entry intr info=0x%x",
4205 "(NMI && vector != 2) invalid [-]", ent_intr_info);
4206 vmcs_write(ENT_INTR_INFO, ent_intr_info);
4207 test_vmx_invalid_controls();
4208 report_prefix_pop();
4209
4210 /* If the interruption type is NMI, the vector is 2 (positive case). */
4211 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR;
4212 report_prefix_pushf("%s, VM-entry intr info=0x%x",
4213 "(NMI && vector == 2) valid [+]", ent_intr_info);
4214 vmcs_write(ENT_INTR_INFO, ent_intr_info);
4215 test_vmx_valid_controls();
4216 report_prefix_pop();
4217
4218 /*
4219 * If the interruption type
4220 * is HW exception, the vector is at most 31.
4221 */
4222 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20;
4223 report_prefix_pushf("%s, VM-entry intr info=0x%x",
4224 "(HW exception && vector > 31) invalid [-]",
4225 ent_intr_info);
4226 vmcs_write(ENT_INTR_INFO, ent_intr_info);
4227 test_vmx_invalid_controls();
4228 report_prefix_pop();
4229
4230 /*
4231 * deliver-error-code is 1 iff either
4232 * (a) the "unrestricted guest" VM-execution control is 0
4233 * (b) CR0.PE is set.
4234 */
4235
4236 /* Assert that unrestricted guest is disabled or unsupported */
4237 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) ||
4238 !(secondary_save & CPU_URG));
4239
4240 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION |
4241 GP_VECTOR;
4242 report_prefix_pushf("%s, VM-entry intr info=0x%x",
4243 "error code <-> (!URG || prot_mode) [-]",
4244 ent_intr_info);
4245 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG);
4246 vmcs_write(ENT_INTR_INFO, ent_intr_info);
4247 if (basic_msr.no_hw_errcode_cc)
4248 test_vmx_valid_controls();
4249 else
4250 test_vmx_invalid_controls();
4251 report_prefix_pop();
4252
4253 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK |
4254 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR;
4255 report_prefix_pushf("%s, VM-entry intr info=0x%x",
4256 "error code <-> (!URG || prot_mode) [+]",
4257 ent_intr_info);
4258 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG);
4259 vmcs_write(ENT_INTR_INFO, ent_intr_info);
4260 test_vmx_valid_controls();
4261 report_prefix_pop();
4262
4263 if (enable_unrestricted_guest(false))
4264 goto skip_unrestricted_guest;
4265
4266 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK |
4267 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR;
4268 report_prefix_pushf("%s, VM-entry intr info=0x%x",
4269 "error code <-> (!URG || prot_mode) [-]",
4270 ent_intr_info);
4271 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG);
4272 vmcs_write(ENT_INTR_INFO, ent_intr_info);
4273 test_vmx_invalid_controls();
4274 report_prefix_pop();
4275
4276 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION |
4277 GP_VECTOR;
4278 report_prefix_pushf("%s, VM-entry intr info=0x%x",
4279 "error code <-> (!URG || prot_mode) [-]",
4280 ent_intr_info);
4281 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE);
4282 vmcs_write(ENT_INTR_INFO, ent_intr_info);
4283 if (basic_msr.no_hw_errcode_cc)
4284 test_vmx_valid_controls();
4285 else
4286 test_vmx_invalid_controls();
4287 report_prefix_pop();
4288
4289 vmcs_write(CPU_EXEC_CTRL1, secondary_save);
4290 vmcs_write(CPU_EXEC_CTRL0, primary_save);
4291
4292 skip_unrestricted_guest:
4293 vmcs_write(GUEST_CR0, guest_cr0_save);
4294
4295 /* deliver-error-code is 1 iff the interruption type is HW exception */
4296 report_prefix_push("error code <-> HW exception");
4297 for (cnt = 0; cnt < 8; cnt++) {
4298 u32 exception_type_mask = cnt << 8;
4299 u32 deliver_error_code_mask =
4300 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ?
4301 INTR_INFO_DELIVER_CODE_MASK : 0;
4302
4303 ent_intr_info = ent_intr_info_base | deliver_error_code_mask |
4304 exception_type_mask | GP_VECTOR;
4305 report_prefix_pushf("VM-entry intr info=0x%x [-]",
4306 ent_intr_info);
4307 vmcs_write(ENT_INTR_INFO, ent_intr_info);
4308 if (exception_type_mask == INTR_TYPE_HARD_EXCEPTION &&
4309 basic_msr.no_hw_errcode_cc)
4310 test_vmx_valid_controls();
4311 else
4312 test_vmx_invalid_controls();
4313 report_prefix_pop();
4314 }
4315 report_prefix_pop();
4316
4317 /*
4318 * deliver-error-code is 1 iff the the vector
4319 * indicates an exception that would normally deliver an error code
4320 */
4321 report_prefix_push("error code <-> vector delivers error code");
4322 for (cnt = 0; cnt < 32; cnt++) {
4323 bool has_error_code = false;
4324 u32 deliver_error_code_mask;
4325
4326 switch (cnt) {
4327 case DF_VECTOR:
4328 case TS_VECTOR:
4329 case NP_VECTOR:
4330 case SS_VECTOR:
4331 case GP_VECTOR:
4332 case PF_VECTOR:
4333 case AC_VECTOR:
4334 has_error_code = true;
4335 case CP_VECTOR:
4336 /* Some CPUs have error code and some do not, skip */
4337 continue;
4338 }
4339
4340 /* Negative case */
4341 deliver_error_code_mask = has_error_code ?
4342 0 :
4343 INTR_INFO_DELIVER_CODE_MASK;
4344 ent_intr_info = ent_intr_info_base | deliver_error_code_mask |
4345 INTR_TYPE_HARD_EXCEPTION | cnt;
4346 report_prefix_pushf("VM-entry intr info=0x%x [-]",
4347 ent_intr_info);
4348 vmcs_write(ENT_INTR_INFO, ent_intr_info);
4349 if (basic_msr.no_hw_errcode_cc)
4350 test_vmx_valid_controls();
4351 else
4352 test_vmx_invalid_controls();
4353 report_prefix_pop();
4354
4355 /* Positive case */
4356 deliver_error_code_mask = has_error_code ?
4357 INTR_INFO_DELIVER_CODE_MASK :
4358 0;
4359 ent_intr_info = ent_intr_info_base | deliver_error_code_mask |
4360 INTR_TYPE_HARD_EXCEPTION | cnt;
4361 report_prefix_pushf("VM-entry intr info=0x%x [+]",
4362 ent_intr_info);
4363 vmcs_write(ENT_INTR_INFO, ent_intr_info);
4364 test_vmx_valid_controls();
4365 report_prefix_pop();
4366 }
4367 report_prefix_pop();
4368
4369 /* Reserved bits in the field (30:12) are 0. */
4370 report_prefix_push("reserved bits clear");
4371 for (cnt = 12; cnt <= 30; cnt++) {
4372 ent_intr_info = ent_intr_info_base |
4373 INTR_INFO_DELIVER_CODE_MASK |
4374 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR |
4375 (1U << cnt);
4376 report_prefix_pushf("VM-entry intr info=0x%x [-]",
4377 ent_intr_info);
4378 vmcs_write(ENT_INTR_INFO, ent_intr_info);
4379 test_vmx_invalid_controls();
4380 report_prefix_pop();
4381 }
4382 report_prefix_pop();
4383
4384 /*
4385 * If deliver-error-code is 1
4386 * bits 31:16 of the VM-entry exception error-code field are 0.
4387 */
4388 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK |
4389 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR;
4390 report_prefix_pushf("%s, VM-entry intr info=0x%x",
4391 "VM-entry exception error code[31:16] clear",
4392 ent_intr_info);
4393 vmcs_write(ENT_INTR_INFO, ent_intr_info);
4394 for (cnt = 16; cnt <= 31; cnt++) {
4395 ent_intr_err = 1U << cnt;
4396 report_prefix_pushf("VM-entry intr error=0x%x [-]",
4397 ent_intr_err);
4398 vmcs_write(ENT_INTR_ERROR, ent_intr_err);
4399 test_vmx_invalid_controls();
4400 report_prefix_pop();
4401 }
4402 vmcs_write(ENT_INTR_ERROR, 0x00000000);
4403 report_prefix_pop();
4404
4405 /*
4406 * If the interruption type is software interrupt, software exception,
4407 * or privileged software exception, the VM-entry instruction-length
4408 * field is in the range 0 - 15.
4409 */
4410
4411 for (cnt = 0; cnt < 3; cnt++) {
4412 switch (cnt) {
4413 case 0:
4414 ent_intr_info = ent_intr_info_base |
4415 INTR_TYPE_SOFT_INTR;
4416 break;
4417 case 1:
4418 ent_intr_info = ent_intr_info_base |
4419 INTR_TYPE_SOFT_EXCEPTION;
4420 break;
4421 case 2:
4422 ent_intr_info = ent_intr_info_base |
4423 INTR_TYPE_PRIV_SW_EXCEPTION;
4424 break;
4425 }
4426 report_prefix_pushf("%s, VM-entry intr info=0x%x",
4427 "VM-entry instruction-length check",
4428 ent_intr_info);
4429 vmcs_write(ENT_INTR_INFO, ent_intr_info);
4430
4431 /* Instruction length set to -1 (0xFFFFFFFF) should fail */
4432 ent_intr_len = -1;
4433 report_prefix_pushf("VM-entry intr length = 0x%x [-]",
4434 ent_intr_len);
4435 vmcs_write(ENT_INST_LEN, ent_intr_len);
4436 test_vmx_invalid_controls();
4437 report_prefix_pop();
4438
4439 /* Instruction length set to 16 should fail */
4440 ent_intr_len = 0x00000010;
4441 report_prefix_pushf("VM-entry intr length = 0x%x [-]",
4442 ent_intr_len);
4443 vmcs_write(ENT_INST_LEN, 0x00000010);
4444 test_vmx_invalid_controls();
4445 report_prefix_pop();
4446
4447 report_prefix_pop();
4448 }
4449
4450 /* Cleanup */
4451 vmcs_write(ENT_INTR_INFO, ent_intr_info_save);
4452 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save);
4453 vmcs_write(ENT_INST_LEN, ent_inst_len_save);
4454 vmcs_write(CPU_EXEC_CTRL0, primary_save);
4455 vmcs_write(CPU_EXEC_CTRL1, secondary_save);
4456 vmcs_write(GUEST_CR0, guest_cr0_save);
4457 report_prefix_pop();
4458 }
4459
4460 /*
4461 * Test interesting vTPR values for a given TPR threshold.
4462 */
test_vtpr_values(unsigned threshold)4463 static void test_vtpr_values(unsigned threshold)
4464 {
4465 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4);
4466 try_tpr_threshold_and_vtpr(threshold, threshold << 4);
4467 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4);
4468 }
4469
try_tpr_threshold(unsigned threshold)4470 static void try_tpr_threshold(unsigned threshold)
4471 {
4472 bool valid = true;
4473
4474 u32 primary = vmcs_read(CPU_EXEC_CTRL0);
4475 u32 secondary = vmcs_read(CPU_EXEC_CTRL1);
4476
4477 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) &&
4478 (secondary & CPU_VINTD)))
4479 valid = !(threshold >> 4);
4480
4481 set_vtpr(-1);
4482 vmcs_write(TPR_THRESHOLD, threshold);
4483 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold);
4484 if (valid)
4485 test_vmx_valid_controls();
4486 else
4487 test_vmx_invalid_controls();
4488 report_prefix_pop();
4489
4490 if (valid)
4491 test_vtpr_values(threshold);
4492 }
4493
4494 /*
4495 * Test interesting TPR threshold values.
4496 */
test_tpr_threshold_values(void)4497 static void test_tpr_threshold_values(void)
4498 {
4499 unsigned i;
4500
4501 for (i = 0; i < 0x10; i++)
4502 try_tpr_threshold(i);
4503 for (i = 4; i < 32; i++)
4504 try_tpr_threshold(1u << i);
4505 try_tpr_threshold(-1u);
4506 try_tpr_threshold(0x7fffffff);
4507 }
4508
4509 /*
4510 * This test covers the following two VM entry checks:
4511 *
4512 * i) If the "use TPR shadow" VM-execution control is 1 and the
4513 * "virtual-interrupt delivery" VM-execution control is 0, bits
4514 * 31:4 of the TPR threshold VM-execution control field must
4515 be 0.
4516 * [Intel SDM]
4517 *
4518 * ii) If the "use TPR shadow" VM-execution control is 1, the
4519 * "virtual-interrupt delivery" VM-execution control is 0
4520 * and the "virtualize APIC accesses" VM-execution control
4521 * is 0, the value of bits 3:0 of the TPR threshold VM-execution
4522 * control field must not be greater than the value of bits
4523 * 7:4 of VTPR.
4524 * [Intel SDM]
4525 */
test_tpr_threshold(void)4526 static void test_tpr_threshold(void)
4527 {
4528 u32 primary = vmcs_read(CPU_EXEC_CTRL0);
4529 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR);
4530 u64 threshold = vmcs_read(TPR_THRESHOLD);
4531 void *virtual_apic_page;
4532
4533 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW))
4534 return;
4535
4536 virtual_apic_page = alloc_page();
4537 memset(virtual_apic_page, 0xff, PAGE_SIZE);
4538 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page));
4539
4540 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY));
4541 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled");
4542 test_tpr_threshold_values();
4543 report_prefix_pop();
4544 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW);
4545 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled");
4546 test_tpr_threshold_values();
4547 report_prefix_pop();
4548
4549 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) &&
4550 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES))))
4551 goto out;
4552 u32 secondary = vmcs_read(CPU_EXEC_CTRL1);
4553
4554 if (ctrl_cpu_rev[1].clr & CPU_VINTD) {
4555 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD);
4556 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled");
4557 test_tpr_threshold_values();
4558 report_prefix_pop();
4559
4560 vmcs_write(CPU_EXEC_CTRL0,
4561 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY);
4562 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled");
4563 test_tpr_threshold_values();
4564 report_prefix_pop();
4565 }
4566
4567 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) {
4568 vmcs_write(CPU_EXEC_CTRL0,
4569 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY);
4570 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES);
4571 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled");
4572 test_tpr_threshold_values();
4573 report_prefix_pop();
4574
4575 vmcs_write(CPU_EXEC_CTRL0,
4576 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY);
4577 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled");
4578 test_tpr_threshold_values();
4579 report_prefix_pop();
4580 }
4581
4582 if ((ctrl_cpu_rev[1].clr &
4583 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) ==
4584 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) {
4585 vmcs_write(CPU_EXEC_CTRL0,
4586 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY);
4587 vmcs_write(CPU_EXEC_CTRL1,
4588 CPU_VINTD | CPU_VIRT_APIC_ACCESSES);
4589 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled");
4590 test_tpr_threshold_values();
4591 report_prefix_pop();
4592
4593 vmcs_write(CPU_EXEC_CTRL0,
4594 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY);
4595 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled");
4596 test_tpr_threshold_values();
4597 report_prefix_pop();
4598 }
4599
4600 vmcs_write(CPU_EXEC_CTRL1, secondary);
4601 out:
4602 vmcs_write(TPR_THRESHOLD, threshold);
4603 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr);
4604 vmcs_write(CPU_EXEC_CTRL0, primary);
4605 }
4606
4607 /*
4608 * This test verifies the following two vmentry checks:
4609 *
4610 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs"
4611 * VM-execution control must be 0.
4612 * [Intel SDM]
4613 *
4614 * If the "virtual NMIs" VM-execution control is 0, the "NMI-window
4615 * exiting" VM-execution control must be 0.
4616 * [Intel SDM]
4617 */
test_nmi_ctrls(void)4618 static void test_nmi_ctrls(void)
4619 {
4620 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0;
4621
4622 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) !=
4623 (PIN_NMI | PIN_VIRT_NMI)) {
4624 report_skip("%s : NMI exiting and/or Virtual NMIs not supported", __func__);
4625 return;
4626 }
4627
4628 /* Save the controls so that we can restore them after our tests */
4629 pin_ctrls = vmcs_read(PIN_CONTROLS);
4630 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0);
4631
4632 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI);
4633 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW;
4634
4635 vmcs_write(PIN_CONTROLS, test_pin_ctrls);
4636 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled");
4637 test_vmx_valid_controls();
4638 report_prefix_pop();
4639
4640 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI);
4641 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled");
4642 test_vmx_invalid_controls();
4643 report_prefix_pop();
4644
4645 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI));
4646 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled");
4647 test_vmx_valid_controls();
4648 report_prefix_pop();
4649
4650 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI);
4651 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled");
4652 test_vmx_valid_controls();
4653 report_prefix_pop();
4654
4655 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) {
4656 report_info("NMI-window exiting is not supported, skipping...");
4657 goto done;
4658 }
4659
4660 vmcs_write(PIN_CONTROLS, test_pin_ctrls);
4661 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW);
4662 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled");
4663 test_vmx_invalid_controls();
4664 report_prefix_pop();
4665
4666 vmcs_write(PIN_CONTROLS, test_pin_ctrls);
4667 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0);
4668 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled");
4669 test_vmx_valid_controls();
4670 report_prefix_pop();
4671
4672 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI));
4673 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW);
4674 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled");
4675 test_vmx_valid_controls();
4676 report_prefix_pop();
4677
4678 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI));
4679 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0);
4680 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled");
4681 test_vmx_valid_controls();
4682 report_prefix_pop();
4683
4684 /* Restore the controls to their original values */
4685 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0);
4686 done:
4687 vmcs_write(PIN_CONTROLS, pin_ctrls);
4688 }
4689
test_eptp_ad_bit(u64 eptp,bool is_ctrl_valid)4690 static void test_eptp_ad_bit(u64 eptp, bool is_ctrl_valid)
4691 {
4692 vmcs_write(EPTP, eptp);
4693 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s",
4694 (eptp & EPTP_AD_FLAG) ? "1": "0");
4695 if (is_ctrl_valid)
4696 test_vmx_valid_controls();
4697 else
4698 test_vmx_invalid_controls();
4699 report_prefix_pop();
4700
4701 }
4702
4703 /*
4704 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution"
4705 * control field must satisfy the following checks:
4706 *
4707 * - The EPT memory type (bits 2:0) must be a value supported by the
4708 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR.
4709 * - Bits 5:3 (1 less than the EPT page-walk length) must indicate a
4710 * supported EPT page-walk length.
4711 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be
4712 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0,
4713 * indicating that the processor does not support accessed and dirty
4714 * dirty flags for EPT.
4715 * - Reserved bits 11:7 and 63:N (where N is the processor's
4716 * physical-address width) must all be 0.
4717 *
4718 * 2. If the "unrestricted guest" VM-execution control is 1, the
4719 * "enable EPT" VM-execution control must also be 1.
4720 */
test_ept_eptp(void)4721 static void test_ept_eptp(void)
4722 {
4723 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0);
4724 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1);
4725 u64 eptp_saved = vmcs_read(EPTP);
4726 u32 secondary;
4727 u64 eptp;
4728 u32 i, maxphysaddr;
4729 u64 j, resv_bits_mask = 0;
4730
4731 if (__setup_ept(0xfed40000, false)) {
4732 report_skip("%s : EPT not supported", __func__);
4733 return;
4734 }
4735
4736 test_vmx_valid_controls();
4737
4738 setup_dummy_ept();
4739
4740 secondary = vmcs_read(CPU_EXEC_CTRL1);
4741 eptp = vmcs_read(EPTP);
4742
4743 for (i = 0; i < 8; i++) {
4744 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i;
4745 vmcs_write(EPTP, eptp);
4746 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu",
4747 eptp & EPT_MEM_TYPE_MASK);
4748 if (is_ept_memtype_supported(i))
4749 test_vmx_valid_controls();
4750 else
4751 test_vmx_invalid_controls();
4752 report_prefix_pop();
4753 }
4754
4755 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul;
4756
4757 /*
4758 * Page walk length (bits 5:3). Note, the value in VMCS.EPTP "is 1
4759 * less than the EPT page-walk length".
4760 */
4761 for (i = 0; i < 8; i++) {
4762 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) |
4763 (i << EPTP_PG_WALK_LEN_SHIFT);
4764
4765 vmcs_write(EPTP, eptp);
4766 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu",
4767 eptp & EPTP_PG_WALK_LEN_MASK);
4768 if (i == 3 || (i == 4 && is_5_level_ept_supported()))
4769 test_vmx_valid_controls();
4770 else
4771 test_vmx_invalid_controls();
4772 report_prefix_pop();
4773 }
4774
4775 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) |
4776 3ul << EPTP_PG_WALK_LEN_SHIFT;
4777
4778 /*
4779 * Accessed and dirty flag (bit 6)
4780 */
4781 if (ept_ad_bits_supported()) {
4782 report_info("Processor supports accessed and dirty flag");
4783 eptp &= ~EPTP_AD_FLAG;
4784 test_eptp_ad_bit(eptp, true);
4785
4786 eptp |= EPTP_AD_FLAG;
4787 test_eptp_ad_bit(eptp, true);
4788 } else {
4789 report_info("Processor does not supports accessed and dirty flag");
4790 eptp &= ~EPTP_AD_FLAG;
4791 test_eptp_ad_bit(eptp, true);
4792
4793 eptp |= EPTP_AD_FLAG;
4794 test_eptp_ad_bit(eptp, false);
4795
4796 eptp &= ~EPTP_AD_FLAG;
4797 }
4798
4799 /*
4800 * Reserved bits [11:7] and [63:N]
4801 */
4802 for (i = 0; i < 32; i++) {
4803 eptp = (eptp &
4804 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) |
4805 (i << EPTP_RESERV_BITS_SHIFT);
4806 vmcs_write(EPTP, eptp);
4807 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu",
4808 (eptp >> EPTP_RESERV_BITS_SHIFT) &
4809 EPTP_RESERV_BITS_MASK);
4810 if (i == 0)
4811 test_vmx_valid_controls();
4812 else
4813 test_vmx_invalid_controls();
4814 report_prefix_pop();
4815 }
4816
4817 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT));
4818
4819 maxphysaddr = cpuid_maxphyaddr();
4820 for (i = 0; i < (63 - maxphysaddr + 1); i++) {
4821 resv_bits_mask |= 1ul << i;
4822 }
4823
4824 for (j = maxphysaddr - 1; j <= 63; j++) {
4825 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) |
4826 (j < maxphysaddr ? 0 : 1ul << j);
4827 vmcs_write(EPTP, eptp);
4828 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu",
4829 (eptp >> maxphysaddr) & resv_bits_mask);
4830 if (j < maxphysaddr)
4831 test_vmx_valid_controls();
4832 else
4833 test_vmx_invalid_controls();
4834 report_prefix_pop();
4835 }
4836
4837 secondary &= ~(CPU_EPT | CPU_URG);
4838 vmcs_write(CPU_EXEC_CTRL1, secondary);
4839 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled");
4840 test_vmx_valid_controls();
4841 report_prefix_pop();
4842
4843 if (!(ctrl_cpu_rev[1].clr & CPU_URG))
4844 goto skip_unrestricted_guest;
4845
4846 secondary |= CPU_URG;
4847 vmcs_write(CPU_EXEC_CTRL1, secondary);
4848 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled");
4849 test_vmx_invalid_controls();
4850 report_prefix_pop();
4851
4852 secondary |= CPU_EPT;
4853 setup_dummy_ept();
4854 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled");
4855 test_vmx_valid_controls();
4856 report_prefix_pop();
4857
4858 skip_unrestricted_guest:
4859 secondary &= ~CPU_URG;
4860 vmcs_write(CPU_EXEC_CTRL1, secondary);
4861 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled");
4862 test_vmx_valid_controls();
4863 report_prefix_pop();
4864
4865 vmcs_write(CPU_EXEC_CTRL0, primary_saved);
4866 vmcs_write(CPU_EXEC_CTRL1, secondary_saved);
4867 vmcs_write(EPTP, eptp_saved);
4868 }
4869
4870 /*
4871 * If the 'enable PML' VM-execution control is 1, the 'enable EPT'
4872 * VM-execution control must also be 1. In addition, the PML address
4873 * must satisfy the following checks:
4874 *
4875 * * Bits 11:0 of the address must be 0.
4876 * * The address should not set any bits beyond the processor's
4877 * physical-address width.
4878 *
4879 * [Intel SDM]
4880 */
test_pml(void)4881 static void test_pml(void)
4882 {
4883 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0);
4884 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1);
4885 u32 primary = primary_saved;
4886 u32 secondary = secondary_saved;
4887
4888 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) &&
4889 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) {
4890 report_skip("%s : \"Secondary execution\" or \"enable EPT\" or \"enable PML\" control not supported", __func__);
4891 return;
4892 }
4893
4894 primary |= CPU_SECONDARY;
4895 vmcs_write(CPU_EXEC_CTRL0, primary);
4896 secondary &= ~(CPU_PML | CPU_EPT);
4897 vmcs_write(CPU_EXEC_CTRL1, secondary);
4898 report_prefix_pushf("enable-PML disabled, enable-EPT disabled");
4899 test_vmx_valid_controls();
4900 report_prefix_pop();
4901
4902 secondary |= CPU_PML;
4903 vmcs_write(CPU_EXEC_CTRL1, secondary);
4904 report_prefix_pushf("enable-PML enabled, enable-EPT disabled");
4905 test_vmx_invalid_controls();
4906 report_prefix_pop();
4907
4908 secondary |= CPU_EPT;
4909 setup_dummy_ept();
4910 report_prefix_pushf("enable-PML enabled, enable-EPT enabled");
4911 test_vmx_valid_controls();
4912 report_prefix_pop();
4913
4914 secondary &= ~CPU_PML;
4915 vmcs_write(CPU_EXEC_CTRL1, secondary);
4916 report_prefix_pushf("enable-PML disabled, enable EPT enabled");
4917 test_vmx_valid_controls();
4918 report_prefix_pop();
4919
4920 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML",
4921 PAGE_SIZE, false, false);
4922
4923 vmcs_write(CPU_EXEC_CTRL0, primary_saved);
4924 vmcs_write(CPU_EXEC_CTRL1, secondary_saved);
4925 }
4926
4927 /*
4928 * If the "activate VMX-preemption timer" VM-execution control is 0, the
4929 * the "save VMX-preemption timer value" VM-exit control must also be 0.
4930 *
4931 * [Intel SDM]
4932 */
test_vmx_preemption_timer(void)4933 static void test_vmx_preemption_timer(void)
4934 {
4935 u32 saved_pin = vmcs_read(PIN_CONTROLS);
4936 u32 saved_exit = vmcs_read(EXI_CONTROLS);
4937 u32 pin = saved_pin;
4938 u32 exit = saved_exit;
4939
4940 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) ||
4941 (ctrl_pin_rev.clr & PIN_PREEMPT))) {
4942 report_skip("%s : \"Save-VMX-preemption-timer\" and/or \"Enable-VMX-preemption-timer\" control not supported", __func__);
4943 return;
4944 }
4945
4946 pin |= PIN_PREEMPT;
4947 vmcs_write(PIN_CONTROLS, pin);
4948 exit &= ~EXI_SAVE_PREEMPT;
4949 vmcs_write(EXI_CONTROLS, exit);
4950 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled");
4951 test_vmx_valid_controls();
4952 report_prefix_pop();
4953
4954 exit |= EXI_SAVE_PREEMPT;
4955 vmcs_write(EXI_CONTROLS, exit);
4956 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled");
4957 test_vmx_valid_controls();
4958 report_prefix_pop();
4959
4960 pin &= ~PIN_PREEMPT;
4961 vmcs_write(PIN_CONTROLS, pin);
4962 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled");
4963 test_vmx_invalid_controls();
4964 report_prefix_pop();
4965
4966 exit &= ~EXI_SAVE_PREEMPT;
4967 vmcs_write(EXI_CONTROLS, exit);
4968 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled");
4969 test_vmx_valid_controls();
4970 report_prefix_pop();
4971
4972 vmcs_write(PIN_CONTROLS, saved_pin);
4973 vmcs_write(EXI_CONTROLS, saved_exit);
4974 }
4975
4976 extern unsigned char test_mtf1;
4977 extern unsigned char test_mtf2;
4978 extern unsigned char test_mtf3;
4979 extern unsigned char test_mtf4;
4980
test_mtf_guest(void)4981 static void test_mtf_guest(void)
4982 {
4983 asm ("vmcall;\n\t"
4984 "out %al, $0x80;\n\t"
4985 "test_mtf1:\n\t"
4986 "vmcall;\n\t"
4987 "out %al, $0x80;\n\t"
4988 "test_mtf2:\n\t"
4989 /*
4990 * Prepare for the 'MOV CR3' test. Attempt to induce a
4991 * general-protection fault by moving a non-canonical address into
4992 * CR3. The 'MOV CR3' instruction does not take an imm64 operand,
4993 * so we must MOV the desired value into a register first.
4994 *
4995 * MOV RAX is done before the VMCALL such that MTF is only enabled
4996 * for the instruction under test.
4997 */
4998 "mov $0xaaaaaaaaaaaaaaaa, %rax;\n\t"
4999 "vmcall;\n\t"
5000 "mov %rax, %cr3;\n\t"
5001 "test_mtf3:\n\t"
5002 "vmcall;\n\t"
5003 /*
5004 * ICEBP/INT1 instruction. Though the instruction is now
5005 * documented, don't rely on assemblers enumerating the
5006 * instruction. Resort to hand assembly.
5007 */
5008 ".byte 0xf1;\n\t"
5009 "vmcall;\n\t"
5010 "test_mtf4:\n\t"
5011 "mov $0, %eax;\n\t");
5012 }
5013
test_mtf_gp_handler(struct ex_regs * regs)5014 static void test_mtf_gp_handler(struct ex_regs *regs)
5015 {
5016 regs->rip = (unsigned long) &test_mtf3;
5017 }
5018
test_mtf_db_handler(struct ex_regs * regs)5019 static void test_mtf_db_handler(struct ex_regs *regs)
5020 {
5021 }
5022
enable_mtf(void)5023 static void enable_mtf(void)
5024 {
5025 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0);
5026
5027 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF);
5028 }
5029
disable_mtf(void)5030 static void disable_mtf(void)
5031 {
5032 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0);
5033
5034 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF);
5035 }
5036
enable_tf(void)5037 static void enable_tf(void)
5038 {
5039 unsigned long rflags = vmcs_read(GUEST_RFLAGS);
5040
5041 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF);
5042 }
5043
disable_tf(void)5044 static void disable_tf(void)
5045 {
5046 unsigned long rflags = vmcs_read(GUEST_RFLAGS);
5047
5048 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF);
5049 }
5050
report_mtf(const char * insn_name,unsigned long exp_rip)5051 static void report_mtf(const char *insn_name, unsigned long exp_rip)
5052 {
5053 unsigned long rip = vmcs_read(GUEST_RIP);
5054
5055 assert_exit_reason(VMX_MTF);
5056 report(rip == exp_rip, "MTF VM-exit after %s. RIP: 0x%lx (expected 0x%lx)",
5057 insn_name, rip, exp_rip);
5058 }
5059
vmx_mtf_test(void)5060 static void vmx_mtf_test(void)
5061 {
5062 unsigned long pending_dbg;
5063 handler old_gp, old_db;
5064
5065 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) {
5066 report_skip("%s : \"Monitor trap flag\" exec control not supported", __func__);
5067 return;
5068 }
5069
5070 test_set_guest(test_mtf_guest);
5071
5072 /* Expect an MTF VM-exit after OUT instruction */
5073 enter_guest();
5074 skip_exit_vmcall();
5075
5076 enable_mtf();
5077 enter_guest();
5078 report_mtf("OUT", (unsigned long) &test_mtf1);
5079 disable_mtf();
5080
5081 /*
5082 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF
5083 * VM-exit with populated 'pending debug exceptions' VMCS field.
5084 */
5085 enter_guest();
5086 skip_exit_vmcall();
5087
5088 enable_mtf();
5089 enable_tf();
5090
5091 enter_guest();
5092 report_mtf("OUT", (unsigned long) &test_mtf2);
5093 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG);
5094 report(pending_dbg & DR6_BS,
5095 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)",
5096 pending_dbg, (unsigned long) DR6_BS);
5097
5098 disable_mtf();
5099 disable_tf();
5100 vmcs_write(GUEST_PENDING_DEBUG, 0);
5101
5102 /*
5103 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP
5104 * advanced to first instruction of #GP handler.
5105 */
5106 enter_guest();
5107 skip_exit_vmcall();
5108
5109 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler);
5110
5111 enable_mtf();
5112 enter_guest();
5113 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR]));
5114 disable_mtf();
5115
5116 /*
5117 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1).
5118 * MTF should follow the delivery of #DB trap, though the SDM doesn't
5119 * provide clear indication of the relative priority.
5120 */
5121 enter_guest();
5122 skip_exit_vmcall();
5123
5124 handle_exception(GP_VECTOR, old_gp);
5125 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler);
5126
5127 enable_mtf();
5128 enter_guest();
5129 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR]));
5130 disable_mtf();
5131
5132 enter_guest();
5133 skip_exit_vmcall();
5134 handle_exception(DB_VECTOR, old_db);
5135 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | INTR_TYPE_OTHER_EVENT);
5136 enter_guest();
5137 report_mtf("injected MTF", (unsigned long) &test_mtf4);
5138 enter_guest();
5139 }
5140
5141 extern char vmx_mtf_pdpte_guest_begin;
5142 extern char vmx_mtf_pdpte_guest_end;
5143
5144 asm("vmx_mtf_pdpte_guest_begin:\n\t"
5145 "mov %cr0, %rax\n\t" /* save CR0 with PG=1 */
5146 "vmcall\n\t" /* on return from this CR0.PG=0 */
5147 "mov %rax, %cr0\n\t" /* restore CR0.PG=1 to enter PAE mode */
5148 "vmcall\n\t"
5149 "retq\n\t"
5150 "vmx_mtf_pdpte_guest_end:");
5151
vmx_mtf_pdpte_test(void)5152 static void vmx_mtf_pdpte_test(void)
5153 {
5154 void *test_mtf_pdpte_guest;
5155 pteval_t *pdpt;
5156 u32 guest_ar_cs;
5157 u64 guest_efer;
5158 pteval_t *pte;
5159 u64 guest_cr0;
5160 u64 guest_cr3;
5161 u64 guest_cr4;
5162 u64 ent_ctls;
5163 int i;
5164
5165 if (setup_ept(false))
5166 return;
5167
5168 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) {
5169 report_skip("%s : \"Monitor trap flag\" exec control not supported", __func__);
5170 return;
5171 }
5172
5173 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) {
5174 report_skip("%s : \"Unrestricted guest\" exec control not supported", __func__);
5175 return;
5176 }
5177
5178 vmcs_write(EXC_BITMAP, ~0);
5179 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG);
5180
5181 /*
5182 * Copy the guest code to an identity-mapped page.
5183 */
5184 test_mtf_pdpte_guest = alloc_page();
5185 memcpy(test_mtf_pdpte_guest, &vmx_mtf_pdpte_guest_begin,
5186 &vmx_mtf_pdpte_guest_end - &vmx_mtf_pdpte_guest_begin);
5187
5188 test_set_guest(test_mtf_pdpte_guest);
5189
5190 enter_guest();
5191 skip_exit_vmcall();
5192
5193 /*
5194 * Put the guest in non-paged 32-bit protected mode, ready to enter
5195 * PAE mode when CR0.PG is set. CR4.PAE will already have been set
5196 * when the guest started out in long mode.
5197 */
5198 ent_ctls = vmcs_read(ENT_CONTROLS);
5199 vmcs_write(ENT_CONTROLS, ent_ctls & ~ENT_GUEST_64);
5200
5201 guest_efer = vmcs_read(GUEST_EFER);
5202 vmcs_write(GUEST_EFER, guest_efer & ~(EFER_LMA | EFER_LME));
5203
5204 /*
5205 * Set CS access rights bits for 32-bit protected mode:
5206 * 3:0 B execute/read/accessed
5207 * 4 1 code or data
5208 * 6:5 0 descriptor privilege level
5209 * 7 1 present
5210 * 11:8 0 reserved
5211 * 12 0 available for use by system software
5212 * 13 0 64 bit mode not active
5213 * 14 1 default operation size 32-bit segment
5214 * 15 1 page granularity: segment limit in 4K units
5215 * 16 0 segment usable
5216 * 31:17 0 reserved
5217 */
5218 guest_ar_cs = vmcs_read(GUEST_AR_CS);
5219 vmcs_write(GUEST_AR_CS, 0xc09b);
5220
5221 guest_cr0 = vmcs_read(GUEST_CR0);
5222 vmcs_write(GUEST_CR0, guest_cr0 & ~X86_CR0_PG);
5223
5224 guest_cr4 = vmcs_read(GUEST_CR4);
5225 vmcs_write(GUEST_CR4, guest_cr4 & ~X86_CR4_PCIDE);
5226
5227 guest_cr3 = vmcs_read(GUEST_CR3);
5228
5229 /*
5230 * Turn the 4-level page table into a PAE page table by following the 0th
5231 * PML4 entry to a PDPT page, and grab the first four PDPTEs from that
5232 * page.
5233 *
5234 * Why does this work?
5235 *
5236 * PAE uses 32-bit addressing which implies:
5237 * Bits 11:0 page offset
5238 * Bits 20:12 entry into 512-entry page table
5239 * Bits 29:21 entry into a 512-entry directory table
5240 * Bits 31:30 entry into the page directory pointer table.
5241 * Bits 63:32 zero
5242 *
5243 * As only 2 bits are needed to select the PDPTEs for the entire
5244 * 32-bit address space, take the first 4 PDPTEs in the level 3 page
5245 * directory pointer table. It doesn't matter which of these PDPTEs
5246 * are present because they must cover the guest code given that it
5247 * has already run successfully.
5248 *
5249 * Get a pointer to PTE for GVA=0 in the page directory pointer table
5250 */
5251 pte = get_pte_level(
5252 (pgd_t *)phys_to_virt(guest_cr3 & ~X86_CR3_PCID_MASK), 0,
5253 PDPT_LEVEL);
5254
5255 /*
5256 * Need some memory for the 4-entry PAE page directory pointer
5257 * table. Use the end of the identity-mapped page where the guest code
5258 * is stored. There is definitely space as the guest code is only a
5259 * few bytes.
5260 */
5261 pdpt = test_mtf_pdpte_guest + PAGE_SIZE - 4 * sizeof(pteval_t);
5262
5263 /*
5264 * Copy the first four PDPTEs into the PAE page table with reserved
5265 * bits cleared. Note that permission bits from the PML4E and PDPTE
5266 * are not propagated.
5267 */
5268 for (i = 0; i < 4; i++) {
5269 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_RSVD_MASK),
5270 "PDPTE has invalid reserved bits");
5271 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_PAGE_SIZE_MASK),
5272 "Cannot use 1GB super pages for PAE");
5273 pdpt[i] = pte[i] & ~(PAE_PDPTE_RSVD_MASK);
5274 }
5275 vmcs_write(GUEST_CR3, virt_to_phys(pdpt));
5276
5277 enable_mtf();
5278 enter_guest();
5279 assert_exit_reason(VMX_MTF);
5280 disable_mtf();
5281
5282 /*
5283 * The four PDPTEs should have been loaded into the VMCS when
5284 * the guest set CR0.PG to enter PAE mode.
5285 */
5286 for (i = 0; i < 4; i++) {
5287 u64 pdpte = vmcs_read(GUEST_PDPTE + 2 * i);
5288
5289 report(pdpte == pdpt[i], "PDPTE%d is 0x%lx (expected 0x%lx)",
5290 i, pdpte, pdpt[i]);
5291 }
5292
5293 /*
5294 * Now, try to enter the guest in PAE mode. If the PDPTEs in the
5295 * vmcs are wrong, this will fail.
5296 */
5297 enter_guest();
5298 skip_exit_vmcall();
5299
5300 /*
5301 * Return guest to 64-bit mode and wrap up.
5302 */
5303 vmcs_write(ENT_CONTROLS, ent_ctls);
5304 vmcs_write(GUEST_EFER, guest_efer);
5305 vmcs_write(GUEST_AR_CS, guest_ar_cs);
5306 vmcs_write(GUEST_CR0, guest_cr0);
5307 vmcs_write(GUEST_CR4, guest_cr4);
5308 vmcs_write(GUEST_CR3, guest_cr3);
5309
5310 enter_guest();
5311 }
5312
5313 /*
5314 * Tests for VM-execution control fields
5315 */
test_vm_execution_ctls(void)5316 static void test_vm_execution_ctls(void)
5317 {
5318 test_pin_based_ctls();
5319 test_primary_processor_based_ctls();
5320 test_secondary_processor_based_ctls();
5321 test_cr3_targets();
5322 test_io_bitmaps();
5323 test_msr_bitmap();
5324 test_apic_ctls();
5325 test_tpr_threshold();
5326 test_nmi_ctrls();
5327 test_pml();
5328 test_vpid();
5329 test_ept_eptp();
5330 test_vmx_preemption_timer();
5331 }
5332
5333 /*
5334 * The following checks are performed for the VM-entry MSR-load address if
5335 * the VM-entry MSR-load count field is non-zero:
5336 *
5337 * - The lower 4 bits of the VM-entry MSR-load address must be 0.
5338 * The address should not set any bits beyond the processor's
5339 * physical-address width.
5340 *
5341 * - The address of the last byte in the VM-entry MSR-load area
5342 * should not set any bits beyond the processor's physical-address
5343 * width. The address of this last byte is VM-entry MSR-load address
5344 * + (MSR count * 16) - 1. (The arithmetic used for the computation
5345 * uses more bits than the processor's physical-address width.)
5346 *
5347 *
5348 * [Intel SDM]
5349 */
test_entry_msr_load(void)5350 static void test_entry_msr_load(void)
5351 {
5352 entry_msr_load = alloc_page();
5353 u64 tmp;
5354 u32 entry_msr_ld_cnt = 1;
5355 int i;
5356 u32 addr_len = 64;
5357
5358 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt);
5359
5360 /* Check first 4 bits of VM-entry MSR-load address */
5361 for (i = 0; i < 4; i++) {
5362 tmp = (u64)entry_msr_load | 1ull << i;
5363 vmcs_write(ENTER_MSR_LD_ADDR, tmp);
5364 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx",
5365 tmp & 0xf);
5366 test_vmx_invalid_controls();
5367 report_prefix_pop();
5368 }
5369
5370 if (basic_msr.val & (1ul << 48))
5371 addr_len = 32;
5372
5373 test_vmcs_addr_values("VM-entry-MSR-load address",
5374 ENTER_MSR_LD_ADDR, 16, false, false,
5375 4, addr_len - 1);
5376
5377 /*
5378 * Check last byte of VM-entry MSR-load address
5379 */
5380 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf);
5381
5382 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len);
5383 i < 64; i++) {
5384 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) |
5385 1ul << i;
5386 vmcs_write(ENTER_MSR_LD_ADDR,
5387 tmp - (entry_msr_ld_cnt * 16 - 1));
5388 test_vmx_invalid_controls();
5389 }
5390
5391 vmcs_write(ENT_MSR_LD_CNT, 2);
5392 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16);
5393 test_vmx_invalid_controls();
5394 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32);
5395 test_vmx_valid_controls();
5396 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48);
5397 test_vmx_valid_controls();
5398 }
5399
5400 static struct vmx_state_area_test_data {
5401 u32 msr;
5402 u64 exp;
5403 bool enabled;
5404 } vmx_state_area_test_data;
5405
guest_state_test_main(void)5406 static void guest_state_test_main(void)
5407 {
5408 u64 obs;
5409 struct vmx_state_area_test_data *data = &vmx_state_area_test_data;
5410
5411 while (1) {
5412 if (vmx_get_test_stage() == 2)
5413 break;
5414
5415 if (data->enabled) {
5416 obs = rdmsr(data->msr);
5417 report(data->exp == obs,
5418 "Guest state is 0x%lx (expected 0x%lx)",
5419 obs, data->exp);
5420 }
5421
5422 vmcall();
5423 }
5424
5425 asm volatile("fnop");
5426 }
5427
test_guest_state(const char * test,bool xfail,u64 field,const char * field_name)5428 static void test_guest_state(const char *test, bool xfail, u64 field,
5429 const char * field_name)
5430 {
5431 struct vmentry_result result;
5432 u8 abort_flags;
5433
5434 abort_flags = ABORT_ON_EARLY_VMENTRY_FAIL;
5435 if (!xfail)
5436 abort_flags = ABORT_ON_INVALID_GUEST_STATE;
5437
5438 __enter_guest(abort_flags, &result);
5439
5440 report(result.exit_reason.failed_vmentry == xfail &&
5441 ((xfail && result.exit_reason.basic == VMX_FAIL_STATE) ||
5442 (!xfail && result.exit_reason.basic == VMX_VMCALL)) &&
5443 (!xfail || vmcs_read(EXI_QUALIFICATION) == ENTRY_FAIL_DEFAULT),
5444 "%s, %s = %lx", test, field_name, field);
5445
5446 if (!result.exit_reason.failed_vmentry)
5447 skip_exit_insn();
5448 }
5449
5450 /*
5451 * Tests for VM-entry control fields
5452 */
test_vm_entry_ctls(void)5453 static void test_vm_entry_ctls(void)
5454 {
5455 test_invalid_event_injection();
5456 test_entry_msr_load();
5457 }
5458
5459 /*
5460 * The following checks are performed for the VM-exit MSR-store address if
5461 * the VM-exit MSR-store count field is non-zero:
5462 *
5463 * - The lower 4 bits of the VM-exit MSR-store address must be 0.
5464 * The address should not set any bits beyond the processor's
5465 * physical-address width.
5466 *
5467 * - The address of the last byte in the VM-exit MSR-store area
5468 * should not set any bits beyond the processor's physical-address
5469 * width. The address of this last byte is VM-exit MSR-store address
5470 * + (MSR count * 16) - 1. (The arithmetic used for the computation
5471 * uses more bits than the processor's physical-address width.)
5472 *
5473 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits
5474 * in the range 63:32.
5475 *
5476 * [Intel SDM]
5477 */
test_exit_msr_store(void)5478 static void test_exit_msr_store(void)
5479 {
5480 exit_msr_store = alloc_page();
5481 u64 tmp;
5482 u32 exit_msr_st_cnt = 1;
5483 int i;
5484 u32 addr_len = 64;
5485
5486 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt);
5487
5488 /* Check first 4 bits of VM-exit MSR-store address */
5489 for (i = 0; i < 4; i++) {
5490 tmp = (u64)exit_msr_store | 1ull << i;
5491 vmcs_write(EXIT_MSR_ST_ADDR, tmp);
5492 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx",
5493 tmp & 0xf);
5494 test_vmx_invalid_controls();
5495 report_prefix_pop();
5496 }
5497
5498 if (basic_msr.val & (1ul << 48))
5499 addr_len = 32;
5500
5501 test_vmcs_addr_values("VM-exit-MSR-store address",
5502 EXIT_MSR_ST_ADDR, 16, false, false,
5503 4, addr_len - 1);
5504
5505 /*
5506 * Check last byte of VM-exit MSR-store address
5507 */
5508 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf);
5509
5510 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len);
5511 i < 64; i++) {
5512 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) |
5513 1ul << i;
5514 vmcs_write(EXIT_MSR_ST_ADDR,
5515 tmp - (exit_msr_st_cnt * 16 - 1));
5516 test_vmx_invalid_controls();
5517 }
5518
5519 vmcs_write(EXI_MSR_ST_CNT, 2);
5520 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16);
5521 test_vmx_invalid_controls();
5522 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32);
5523 test_vmx_valid_controls();
5524 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48);
5525 test_vmx_valid_controls();
5526 }
5527
5528 /*
5529 * Tests for VM-exit controls
5530 */
test_vm_exit_ctls(void)5531 static void test_vm_exit_ctls(void)
5532 {
5533 test_exit_msr_store();
5534 }
5535
5536 /*
5537 * Check that the virtual CPU checks all of the VMX controls as
5538 * documented in the Intel SDM.
5539 */
vmx_controls_test(void)5540 static void vmx_controls_test(void)
5541 {
5542 /*
5543 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will
5544 * fail due to invalid guest state, should we make it that
5545 * far.
5546 */
5547 vmcs_write(GUEST_RFLAGS, 0);
5548
5549 test_vm_execution_ctls();
5550 test_vm_exit_ctls();
5551 test_vm_entry_ctls();
5552 }
5553
5554 struct apic_reg_virt_config {
5555 bool apic_register_virtualization;
5556 bool use_tpr_shadow;
5557 bool virtualize_apic_accesses;
5558 bool virtualize_x2apic_mode;
5559 bool activate_secondary_controls;
5560 };
5561
5562 struct apic_reg_test {
5563 const char *name;
5564 struct apic_reg_virt_config apic_reg_virt_config;
5565 };
5566
5567 struct apic_reg_virt_expectation {
5568 enum Reason rd_exit_reason;
5569 enum Reason wr_exit_reason;
5570 u32 val;
5571 u32 (*virt_fn)(u32);
5572
5573 /*
5574 * If false, accessing the APIC access address from L2 is treated as a
5575 * normal memory operation, rather than triggering virtualization.
5576 */
5577 bool virtualize_apic_accesses;
5578 };
5579
apic_virt_identity(u32 val)5580 static u32 apic_virt_identity(u32 val)
5581 {
5582 return val;
5583 }
5584
apic_virt_nibble1(u32 val)5585 static u32 apic_virt_nibble1(u32 val)
5586 {
5587 return val & 0xf0;
5588 }
5589
apic_virt_byte3(u32 val)5590 static u32 apic_virt_byte3(u32 val)
5591 {
5592 return val & (0xff << 24);
5593 }
5594
apic_reg_virt_exit_expectation(u32 reg,struct apic_reg_virt_config * config,struct apic_reg_virt_expectation * expectation)5595 static bool apic_reg_virt_exit_expectation(
5596 u32 reg, struct apic_reg_virt_config *config,
5597 struct apic_reg_virt_expectation *expectation)
5598 {
5599 /* Good configs, where some L2 APIC accesses are virtualized. */
5600 bool virtualize_apic_accesses_only =
5601 config->virtualize_apic_accesses &&
5602 !config->use_tpr_shadow &&
5603 !config->apic_register_virtualization &&
5604 !config->virtualize_x2apic_mode &&
5605 config->activate_secondary_controls;
5606 bool virtualize_apic_accesses_and_use_tpr_shadow =
5607 config->virtualize_apic_accesses &&
5608 config->use_tpr_shadow &&
5609 !config->apic_register_virtualization &&
5610 !config->virtualize_x2apic_mode &&
5611 config->activate_secondary_controls;
5612 bool apic_register_virtualization =
5613 config->virtualize_apic_accesses &&
5614 config->use_tpr_shadow &&
5615 config->apic_register_virtualization &&
5616 !config->virtualize_x2apic_mode &&
5617 config->activate_secondary_controls;
5618
5619 expectation->val = MAGIC_VAL_1;
5620 expectation->virt_fn = apic_virt_identity;
5621 expectation->virtualize_apic_accesses =
5622 config->virtualize_apic_accesses &&
5623 config->activate_secondary_controls;
5624 if (virtualize_apic_accesses_only) {
5625 expectation->rd_exit_reason = VMX_APIC_ACCESS;
5626 expectation->wr_exit_reason = VMX_APIC_ACCESS;
5627 } else if (virtualize_apic_accesses_and_use_tpr_shadow) {
5628 switch (reg) {
5629 case APIC_TASKPRI:
5630 expectation->rd_exit_reason = VMX_VMCALL;
5631 expectation->wr_exit_reason = VMX_VMCALL;
5632 expectation->virt_fn = apic_virt_nibble1;
5633 break;
5634 default:
5635 expectation->rd_exit_reason = VMX_APIC_ACCESS;
5636 expectation->wr_exit_reason = VMX_APIC_ACCESS;
5637 }
5638 } else if (apic_register_virtualization) {
5639 expectation->rd_exit_reason = VMX_VMCALL;
5640
5641 switch (reg) {
5642 case APIC_ID:
5643 case APIC_EOI:
5644 case APIC_LDR:
5645 case APIC_DFR:
5646 case APIC_SPIV:
5647 case APIC_ESR:
5648 case APIC_ICR:
5649 case APIC_LVTT:
5650 case APIC_LVTTHMR:
5651 case APIC_LVTPC:
5652 case APIC_LVT0:
5653 case APIC_LVT1:
5654 case APIC_LVTERR:
5655 case APIC_TMICT:
5656 case APIC_TDCR:
5657 expectation->wr_exit_reason = VMX_APIC_WRITE;
5658 break;
5659 case APIC_LVR:
5660 case APIC_ISR ... APIC_ISR + 0x70:
5661 case APIC_TMR ... APIC_TMR + 0x70:
5662 case APIC_IRR ... APIC_IRR + 0x70:
5663 expectation->wr_exit_reason = VMX_APIC_ACCESS;
5664 break;
5665 case APIC_TASKPRI:
5666 expectation->wr_exit_reason = VMX_VMCALL;
5667 expectation->virt_fn = apic_virt_nibble1;
5668 break;
5669 case APIC_ICR2:
5670 expectation->wr_exit_reason = VMX_VMCALL;
5671 expectation->virt_fn = apic_virt_byte3;
5672 break;
5673 default:
5674 expectation->rd_exit_reason = VMX_APIC_ACCESS;
5675 expectation->wr_exit_reason = VMX_APIC_ACCESS;
5676 }
5677 } else if (!expectation->virtualize_apic_accesses) {
5678 /*
5679 * No APIC registers are directly virtualized. This includes
5680 * VTPR, which can be virtualized through MOV to/from CR8 via
5681 * the use TPR shadow control, but not through directly
5682 * accessing VTPR.
5683 */
5684 expectation->rd_exit_reason = VMX_VMCALL;
5685 expectation->wr_exit_reason = VMX_VMCALL;
5686 } else {
5687 printf("Cannot parse APIC register virtualization config:\n"
5688 "\tvirtualize_apic_accesses: %d\n"
5689 "\tuse_tpr_shadow: %d\n"
5690 "\tapic_register_virtualization: %d\n"
5691 "\tvirtualize_x2apic_mode: %d\n"
5692 "\tactivate_secondary_controls: %d\n",
5693 config->virtualize_apic_accesses,
5694 config->use_tpr_shadow,
5695 config->apic_register_virtualization,
5696 config->virtualize_x2apic_mode,
5697 config->activate_secondary_controls);
5698
5699 return false;
5700 }
5701
5702 return true;
5703 }
5704
5705 struct apic_reg_test apic_reg_tests[] = {
5706 /* Good configs, where some L2 APIC accesses are virtualized. */
5707 {
5708 .name = "Virtualize APIC accesses",
5709 .apic_reg_virt_config = {
5710 .virtualize_apic_accesses = true,
5711 .use_tpr_shadow = false,
5712 .apic_register_virtualization = false,
5713 .virtualize_x2apic_mode = false,
5714 .activate_secondary_controls = true,
5715 },
5716 },
5717 {
5718 .name = "Virtualize APIC accesses + Use TPR shadow",
5719 .apic_reg_virt_config = {
5720 .virtualize_apic_accesses = true,
5721 .use_tpr_shadow = true,
5722 .apic_register_virtualization = false,
5723 .virtualize_x2apic_mode = false,
5724 .activate_secondary_controls = true,
5725 },
5726 },
5727 {
5728 .name = "APIC-register virtualization",
5729 .apic_reg_virt_config = {
5730 .virtualize_apic_accesses = true,
5731 .use_tpr_shadow = true,
5732 .apic_register_virtualization = true,
5733 .virtualize_x2apic_mode = false,
5734 .activate_secondary_controls = true,
5735 },
5736 },
5737
5738 /*
5739 * Test that the secondary processor-based VM-execution controls are
5740 * correctly ignored when "activate secondary controls" is disabled.
5741 */
5742 {
5743 .name = "Activate secondary controls off",
5744 .apic_reg_virt_config = {
5745 .virtualize_apic_accesses = true,
5746 .use_tpr_shadow = false,
5747 .apic_register_virtualization = true,
5748 .virtualize_x2apic_mode = true,
5749 .activate_secondary_controls = false,
5750 },
5751 },
5752 {
5753 .name = "Activate secondary controls off + Use TPR shadow",
5754 .apic_reg_virt_config = {
5755 .virtualize_apic_accesses = true,
5756 .use_tpr_shadow = true,
5757 .apic_register_virtualization = true,
5758 .virtualize_x2apic_mode = true,
5759 .activate_secondary_controls = false,
5760 },
5761 },
5762
5763 /*
5764 * Test that the APIC access address is treated like an arbitrary memory
5765 * address when "virtualize APIC accesses" is disabled.
5766 */
5767 {
5768 .name = "Virtualize APIC accesses off + Use TPR shadow",
5769 .apic_reg_virt_config = {
5770 .virtualize_apic_accesses = false,
5771 .use_tpr_shadow = true,
5772 .apic_register_virtualization = true,
5773 .virtualize_x2apic_mode = true,
5774 .activate_secondary_controls = true,
5775 },
5776 },
5777
5778 /*
5779 * Test that VM entry fails due to invalid controls when
5780 * "APIC-register virtualization" is enabled while "use TPR shadow" is
5781 * disabled.
5782 */
5783 {
5784 .name = "APIC-register virtualization + Use TPR shadow off",
5785 .apic_reg_virt_config = {
5786 .virtualize_apic_accesses = true,
5787 .use_tpr_shadow = false,
5788 .apic_register_virtualization = true,
5789 .virtualize_x2apic_mode = false,
5790 .activate_secondary_controls = true,
5791 },
5792 },
5793
5794 /*
5795 * Test that VM entry fails due to invalid controls when
5796 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is
5797 * disabled.
5798 */
5799 {
5800 .name = "Virtualize x2APIC mode + Use TPR shadow off",
5801 .apic_reg_virt_config = {
5802 .virtualize_apic_accesses = false,
5803 .use_tpr_shadow = false,
5804 .apic_register_virtualization = false,
5805 .virtualize_x2apic_mode = true,
5806 .activate_secondary_controls = true,
5807 },
5808 },
5809 {
5810 .name = "Virtualize x2APIC mode + Use TPR shadow off v2",
5811 .apic_reg_virt_config = {
5812 .virtualize_apic_accesses = false,
5813 .use_tpr_shadow = false,
5814 .apic_register_virtualization = true,
5815 .virtualize_x2apic_mode = true,
5816 .activate_secondary_controls = true,
5817 },
5818 },
5819
5820 /*
5821 * Test that VM entry fails due to invalid controls when
5822 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses"
5823 * is enabled.
5824 */
5825 {
5826 .name = "Virtualize x2APIC mode + Virtualize APIC accesses",
5827 .apic_reg_virt_config = {
5828 .virtualize_apic_accesses = true,
5829 .use_tpr_shadow = true,
5830 .apic_register_virtualization = false,
5831 .virtualize_x2apic_mode = true,
5832 .activate_secondary_controls = true,
5833 },
5834 },
5835 {
5836 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2",
5837 .apic_reg_virt_config = {
5838 .virtualize_apic_accesses = true,
5839 .use_tpr_shadow = true,
5840 .apic_register_virtualization = true,
5841 .virtualize_x2apic_mode = true,
5842 .activate_secondary_controls = true,
5843 },
5844 },
5845 };
5846
5847 enum Apic_op {
5848 APIC_OP_XAPIC_RD,
5849 APIC_OP_XAPIC_WR,
5850 TERMINATE,
5851 };
5852
vmx_xapic_read(u32 * apic_access_address,u32 reg)5853 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg)
5854 {
5855 return *(volatile u32 *)((uintptr_t)apic_access_address + reg);
5856 }
5857
vmx_xapic_write(u32 * apic_access_address,u32 reg,u32 val)5858 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val)
5859 {
5860 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val;
5861 }
5862
5863 struct apic_reg_virt_guest_args {
5864 enum Apic_op op;
5865 u32 *apic_access_address;
5866 u32 reg;
5867 u32 val;
5868 bool check_rd;
5869 u32 (*virt_fn)(u32);
5870 } apic_reg_virt_guest_args;
5871
apic_reg_virt_guest(void)5872 static void apic_reg_virt_guest(void)
5873 {
5874 volatile struct apic_reg_virt_guest_args *args =
5875 &apic_reg_virt_guest_args;
5876
5877 for (;;) {
5878 enum Apic_op op = args->op;
5879 u32 *apic_access_address = args->apic_access_address;
5880 u32 reg = args->reg;
5881 u32 val = args->val;
5882 bool check_rd = args->check_rd;
5883 u32 (*virt_fn)(u32) = args->virt_fn;
5884
5885 if (op == TERMINATE)
5886 break;
5887
5888 if (op == APIC_OP_XAPIC_RD) {
5889 u32 ret = vmx_xapic_read(apic_access_address, reg);
5890
5891 if (check_rd) {
5892 u32 want = virt_fn(val);
5893 u32 got = virt_fn(ret);
5894
5895 report(got == want,
5896 "read 0x%x, expected 0x%x.", got, want);
5897 }
5898 } else if (op == APIC_OP_XAPIC_WR) {
5899 vmx_xapic_write(apic_access_address, reg, val);
5900 }
5901
5902 /*
5903 * The L1 should always execute a vmcall after it's done testing
5904 * an individual APIC operation. This helps to validate that the
5905 * L1 and L2 are in sync with each other, as expected.
5906 */
5907 vmcall();
5908 }
5909 }
5910
test_xapic_rd(u32 reg,struct apic_reg_virt_expectation * expectation,u32 * apic_access_address,u32 * virtual_apic_page)5911 static void test_xapic_rd(
5912 u32 reg, struct apic_reg_virt_expectation *expectation,
5913 u32 *apic_access_address, u32 *virtual_apic_page)
5914 {
5915 u32 val = expectation->val;
5916 u32 exit_reason_want = expectation->rd_exit_reason;
5917 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args;
5918
5919 report_prefix_pushf("xapic - reading 0x%03x", reg);
5920
5921 /* Configure guest to do an xapic read */
5922 args->op = APIC_OP_XAPIC_RD;
5923 args->apic_access_address = apic_access_address;
5924 args->reg = reg;
5925 args->val = val;
5926 args->check_rd = exit_reason_want == VMX_VMCALL;
5927 args->virt_fn = expectation->virt_fn;
5928
5929 /* Setup virtual APIC page */
5930 if (!expectation->virtualize_apic_accesses) {
5931 apic_access_address[apic_reg_index(reg)] = val;
5932 virtual_apic_page[apic_reg_index(reg)] = 0;
5933 } else if (exit_reason_want == VMX_VMCALL) {
5934 apic_access_address[apic_reg_index(reg)] = 0;
5935 virtual_apic_page[apic_reg_index(reg)] = val;
5936 }
5937
5938 /* Enter guest */
5939 enter_guest();
5940
5941 /*
5942 * Validate the behavior and
5943 * pass a magic value back to the guest.
5944 */
5945 if (exit_reason_want == VMX_APIC_ACCESS) {
5946 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff;
5947
5948 assert_exit_reason(exit_reason_want);
5949 report(apic_page_offset == reg,
5950 "got APIC access exit @ page offset 0x%03x, want 0x%03x",
5951 apic_page_offset, reg);
5952 skip_exit_insn();
5953
5954 /* Reenter guest so it can consume/check rcx and exit again. */
5955 enter_guest();
5956 } else if (exit_reason_want != VMX_VMCALL) {
5957 report_fail("Oops, bad exit expectation: %u.", exit_reason_want);
5958 }
5959
5960 skip_exit_vmcall();
5961 report_prefix_pop();
5962 }
5963
test_xapic_wr(u32 reg,struct apic_reg_virt_expectation * expectation,u32 * apic_access_address,u32 * virtual_apic_page)5964 static void test_xapic_wr(
5965 u32 reg, struct apic_reg_virt_expectation *expectation,
5966 u32 *apic_access_address, u32 *virtual_apic_page)
5967 {
5968 u32 val = expectation->val;
5969 u32 exit_reason_want = expectation->wr_exit_reason;
5970 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args;
5971 bool virtualized =
5972 expectation->virtualize_apic_accesses &&
5973 (exit_reason_want == VMX_APIC_WRITE ||
5974 exit_reason_want == VMX_VMCALL);
5975 bool checked = false;
5976
5977 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg);
5978
5979 /* Configure guest to do an xapic read */
5980 args->op = APIC_OP_XAPIC_WR;
5981 args->apic_access_address = apic_access_address;
5982 args->reg = reg;
5983 args->val = val;
5984
5985 /* Setup virtual APIC page */
5986 if (virtualized || !expectation->virtualize_apic_accesses) {
5987 apic_access_address[apic_reg_index(reg)] = 0;
5988 virtual_apic_page[apic_reg_index(reg)] = 0;
5989 }
5990
5991 /* Enter guest */
5992 enter_guest();
5993
5994 /*
5995 * Validate the behavior and
5996 * pass a magic value back to the guest.
5997 */
5998 if (exit_reason_want == VMX_APIC_ACCESS) {
5999 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff;
6000
6001 assert_exit_reason(exit_reason_want);
6002 report(apic_page_offset == reg,
6003 "got APIC access exit @ page offset 0x%03x, want 0x%03x",
6004 apic_page_offset, reg);
6005 skip_exit_insn();
6006
6007 /* Reenter guest so it can consume/check rcx and exit again. */
6008 enter_guest();
6009 } else if (exit_reason_want == VMX_APIC_WRITE) {
6010 assert_exit_reason(exit_reason_want);
6011 report(virtual_apic_page[apic_reg_index(reg)] == val,
6012 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x",
6013 apic_reg_index(reg),
6014 virtual_apic_page[apic_reg_index(reg)], val);
6015 checked = true;
6016
6017 /* Reenter guest so it can consume/check rcx and exit again. */
6018 enter_guest();
6019 } else if (exit_reason_want != VMX_VMCALL) {
6020 report_fail("Oops, bad exit expectation: %u.", exit_reason_want);
6021 }
6022
6023 assert_exit_reason(VMX_VMCALL);
6024 if (virtualized && !checked) {
6025 u32 want = expectation->virt_fn(val);
6026 u32 got = virtual_apic_page[apic_reg_index(reg)];
6027 got = expectation->virt_fn(got);
6028
6029 report(got == want, "exitless write; val is 0x%x, want 0x%x",
6030 got, want);
6031 } else if (!expectation->virtualize_apic_accesses && !checked) {
6032 u32 got = apic_access_address[apic_reg_index(reg)];
6033
6034 report(got == val,
6035 "non-virtualized write; val is 0x%x, want 0x%x", got,
6036 val);
6037 } else if (!expectation->virtualize_apic_accesses && checked) {
6038 report_fail("Non-virtualized write was prematurely checked!");
6039 }
6040
6041 skip_exit_vmcall();
6042 report_prefix_pop();
6043 }
6044
6045 enum Config_type {
6046 CONFIG_TYPE_GOOD,
6047 CONFIG_TYPE_UNSUPPORTED,
6048 CONFIG_TYPE_VMENTRY_FAILS_EARLY,
6049 };
6050
configure_apic_reg_virt_test(struct apic_reg_virt_config * apic_reg_virt_config)6051 static enum Config_type configure_apic_reg_virt_test(
6052 struct apic_reg_virt_config *apic_reg_virt_config)
6053 {
6054 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0);
6055 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1);
6056 /* Configs where L2 entry fails early, due to invalid controls. */
6057 bool use_tpr_shadow_incorrectly_off =
6058 !apic_reg_virt_config->use_tpr_shadow &&
6059 (apic_reg_virt_config->apic_register_virtualization ||
6060 apic_reg_virt_config->virtualize_x2apic_mode) &&
6061 apic_reg_virt_config->activate_secondary_controls;
6062 bool virtualize_apic_accesses_incorrectly_on =
6063 apic_reg_virt_config->virtualize_apic_accesses &&
6064 apic_reg_virt_config->virtualize_x2apic_mode &&
6065 apic_reg_virt_config->activate_secondary_controls;
6066 bool vmentry_fails_early =
6067 use_tpr_shadow_incorrectly_off ||
6068 virtualize_apic_accesses_incorrectly_on;
6069
6070 if (apic_reg_virt_config->activate_secondary_controls) {
6071 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) {
6072 printf("VM-execution control \"activate secondary controls\" NOT supported.\n");
6073 return CONFIG_TYPE_UNSUPPORTED;
6074 }
6075 cpu_exec_ctrl0 |= CPU_SECONDARY;
6076 } else {
6077 cpu_exec_ctrl0 &= ~CPU_SECONDARY;
6078 }
6079
6080 if (apic_reg_virt_config->virtualize_apic_accesses) {
6081 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) {
6082 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n");
6083 return CONFIG_TYPE_UNSUPPORTED;
6084 }
6085 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES;
6086 } else {
6087 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES;
6088 }
6089
6090 if (apic_reg_virt_config->use_tpr_shadow) {
6091 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) {
6092 printf("VM-execution control \"use TPR shadow\" NOT supported.\n");
6093 return CONFIG_TYPE_UNSUPPORTED;
6094 }
6095 cpu_exec_ctrl0 |= CPU_TPR_SHADOW;
6096 } else {
6097 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW;
6098 }
6099
6100 if (apic_reg_virt_config->apic_register_virtualization) {
6101 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) {
6102 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n");
6103 return CONFIG_TYPE_UNSUPPORTED;
6104 }
6105 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT;
6106 } else {
6107 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT;
6108 }
6109
6110 if (apic_reg_virt_config->virtualize_x2apic_mode) {
6111 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) {
6112 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n");
6113 return CONFIG_TYPE_UNSUPPORTED;
6114 }
6115 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC;
6116 } else {
6117 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC;
6118 }
6119
6120 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0);
6121 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1);
6122
6123 if (vmentry_fails_early)
6124 return CONFIG_TYPE_VMENTRY_FAILS_EARLY;
6125
6126 return CONFIG_TYPE_GOOD;
6127 }
6128
cpu_has_apicv(void)6129 static bool cpu_has_apicv(void)
6130 {
6131 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) &&
6132 (ctrl_cpu_rev[1].clr & CPU_VINTD) &&
6133 (ctrl_pin_rev.clr & PIN_POST_INTR));
6134 }
6135
6136 /* Validates APIC register access across valid virtualization configurations. */
apic_reg_virt_test(void)6137 static void apic_reg_virt_test(void)
6138 {
6139 u32 *apic_access_address;
6140 u32 *virtual_apic_page;
6141 u64 control;
6142 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0);
6143 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1);
6144 int i;
6145 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args;
6146
6147 if (!cpu_has_apicv()) {
6148 report_skip("%s : Not all required APICv bits supported", __func__);
6149 return;
6150 }
6151
6152 control = cpu_exec_ctrl1;
6153 control &= ~CPU_VINTD;
6154 vmcs_write(CPU_EXEC_CTRL1, control);
6155
6156 test_set_guest(apic_reg_virt_guest);
6157
6158 /*
6159 * From the SDM: The 1-setting of the "virtualize APIC accesses"
6160 * VM-execution is guaranteed to apply only if translations to the
6161 * APIC-access address use a 4-KByte page.
6162 */
6163 apic_access_address = alloc_page();
6164 force_4k_page(apic_access_address);
6165 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address));
6166
6167 virtual_apic_page = alloc_page();
6168 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page));
6169
6170 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) {
6171 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i];
6172 struct apic_reg_virt_config *apic_reg_virt_config =
6173 &apic_reg_test->apic_reg_virt_config;
6174 enum Config_type config_type;
6175 u32 reg;
6176
6177 printf("--- %s test ---\n", apic_reg_test->name);
6178 config_type =
6179 configure_apic_reg_virt_test(apic_reg_virt_config);
6180 if (config_type == CONFIG_TYPE_UNSUPPORTED) {
6181 printf("Skip because of missing features.\n");
6182 continue;
6183 }
6184
6185 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) {
6186 enter_guest_with_bad_controls();
6187 continue;
6188 }
6189
6190 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) {
6191 struct apic_reg_virt_expectation expectation = {};
6192 bool ok;
6193
6194 ok = apic_reg_virt_exit_expectation(
6195 reg, apic_reg_virt_config, &expectation);
6196 if (!ok) {
6197 report_fail("Malformed test.");
6198 break;
6199 }
6200
6201 test_xapic_rd(reg, &expectation, apic_access_address,
6202 virtual_apic_page);
6203 test_xapic_wr(reg, &expectation, apic_access_address,
6204 virtual_apic_page);
6205 }
6206 }
6207
6208 /* Terminate the guest */
6209 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0);
6210 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1);
6211 args->op = TERMINATE;
6212 enter_guest();
6213 assert_exit_reason(VMX_VMCALL);
6214 }
6215
6216 struct virt_x2apic_mode_config {
6217 struct apic_reg_virt_config apic_reg_virt_config;
6218 bool virtual_interrupt_delivery;
6219 bool use_msr_bitmaps;
6220 bool disable_x2apic_msr_intercepts;
6221 bool disable_x2apic;
6222 };
6223
6224 struct virt_x2apic_mode_test_case {
6225 const char *name;
6226 struct virt_x2apic_mode_config virt_x2apic_mode_config;
6227 };
6228
6229 enum Virt_x2apic_mode_behavior_type {
6230 X2APIC_ACCESS_VIRTUALIZED,
6231 X2APIC_ACCESS_PASSED_THROUGH,
6232 X2APIC_ACCESS_TRIGGERS_GP,
6233 };
6234
6235 struct virt_x2apic_mode_expectation {
6236 enum Reason rd_exit_reason;
6237 enum Reason wr_exit_reason;
6238
6239 /*
6240 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of
6241 * the x2APIC registers are 32 bits. Notice:
6242 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers.
6243 * 2. vmx_x2apic_write() expects the val arg to be well-formed.
6244 */
6245 u64 rd_val;
6246 u64 wr_val;
6247
6248 /*
6249 * Compares input to virtualized output;
6250 * 1st arg is pointer to return expected virtualization output.
6251 */
6252 u64 (*virt_fn)(u64);
6253
6254 enum Virt_x2apic_mode_behavior_type rd_behavior;
6255 enum Virt_x2apic_mode_behavior_type wr_behavior;
6256 bool wr_only;
6257 };
6258
virt_x2apic_mode_identity(u64 val)6259 static u64 virt_x2apic_mode_identity(u64 val)
6260 {
6261 return val;
6262 }
6263
virt_x2apic_mode_nibble1(u64 val)6264 static u64 virt_x2apic_mode_nibble1(u64 val)
6265 {
6266 return val & 0xf0;
6267 }
6268
virt_x2apic_mode_rd_expectation(u32 reg,bool virt_x2apic_mode_on,bool disable_x2apic,bool apic_register_virtualization,bool virtual_interrupt_delivery,struct virt_x2apic_mode_expectation * expectation)6269 static void virt_x2apic_mode_rd_expectation(
6270 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic,
6271 bool apic_register_virtualization, bool virtual_interrupt_delivery,
6272 struct virt_x2apic_mode_expectation *expectation)
6273 {
6274 enum x2apic_reg_semantics semantics = get_x2apic_reg_semantics(reg);
6275
6276 expectation->rd_exit_reason = VMX_VMCALL;
6277 expectation->virt_fn = virt_x2apic_mode_identity;
6278 if (virt_x2apic_mode_on && apic_register_virtualization) {
6279 expectation->rd_val = MAGIC_VAL_1;
6280 if (reg == APIC_PROCPRI && virtual_interrupt_delivery)
6281 expectation->virt_fn = virt_x2apic_mode_nibble1;
6282 else if (reg == APIC_TASKPRI)
6283 expectation->virt_fn = virt_x2apic_mode_nibble1;
6284 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED;
6285 } else if (virt_x2apic_mode_on && !apic_register_virtualization &&
6286 reg == APIC_TASKPRI) {
6287 expectation->rd_val = MAGIC_VAL_1;
6288 expectation->virt_fn = virt_x2apic_mode_nibble1;
6289 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED;
6290 } else if (!disable_x2apic && (semantics & X2APIC_READABLE)) {
6291 expectation->rd_val = apic_read(reg);
6292 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH;
6293 } else {
6294 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP;
6295 }
6296 }
6297
6298 /*
6299 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register.
6300 *
6301 * For writable registers, get_x2apic_wr_val() deposits the write value into the
6302 * val pointer arg and returns true. For non-writable registers, val is not
6303 * modified and get_x2apic_wr_val() returns false.
6304 */
get_x2apic_wr_val(u32 reg,u64 * val)6305 static bool get_x2apic_wr_val(u32 reg, u64 *val)
6306 {
6307 switch (reg) {
6308 case APIC_TASKPRI:
6309 /* Bits 31:8 are reserved. */
6310 *val &= 0xff;
6311 break;
6312 case APIC_EOI:
6313 case APIC_ESR:
6314 case APIC_TMICT:
6315 /*
6316 * EOI, ESR: WRMSR of a non-zero value causes #GP(0).
6317 * TMICT: A write of 0 to the initial-count register effectively
6318 * stops the local APIC timer, in both one-shot and
6319 * periodic mode.
6320 */
6321 *val = 0;
6322 break;
6323 case APIC_SPIV:
6324 case APIC_LVTT:
6325 case APIC_LVTTHMR:
6326 case APIC_LVTPC:
6327 case APIC_LVT0:
6328 case APIC_LVT1:
6329 case APIC_LVTERR:
6330 case APIC_TDCR:
6331 /*
6332 * To avoid writing a 1 to a reserved bit or causing some other
6333 * unintended side effect, read the current value and use it as
6334 * the write value.
6335 */
6336 *val = apic_read(reg);
6337 break;
6338 case APIC_CMCI:
6339 if (!apic_lvt_entry_supported(6))
6340 return false;
6341 *val = apic_read(reg);
6342 break;
6343 case APIC_ICR:
6344 *val = 0x40000 | 0xf1;
6345 break;
6346 case APIC_SELF_IPI:
6347 /*
6348 * With special processing (i.e., virtualize x2APIC mode +
6349 * virtual interrupt delivery), writing zero causes an
6350 * APIC-write VM exit. We plan to add a test for enabling
6351 * "virtual-interrupt delivery" in VMCS12, and that's where we
6352 * will test a self IPI with special processing.
6353 */
6354 *val = 0x0;
6355 break;
6356 default:
6357 return false;
6358 }
6359
6360 return true;
6361 }
6362
special_processing_applies(u32 reg,u64 * val,bool virt_int_delivery)6363 static bool special_processing_applies(u32 reg, u64 *val,
6364 bool virt_int_delivery)
6365 {
6366 bool special_processing =
6367 (reg == APIC_TASKPRI) ||
6368 (virt_int_delivery &&
6369 (reg == APIC_EOI || reg == APIC_SELF_IPI));
6370
6371 if (special_processing) {
6372 TEST_ASSERT(get_x2apic_wr_val(reg, val));
6373 return true;
6374 }
6375
6376 return false;
6377 }
6378
virt_x2apic_mode_wr_expectation(u32 reg,bool virt_x2apic_mode_on,bool disable_x2apic,bool virt_int_delivery,struct virt_x2apic_mode_expectation * expectation)6379 static void virt_x2apic_mode_wr_expectation(
6380 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic,
6381 bool virt_int_delivery,
6382 struct virt_x2apic_mode_expectation *expectation)
6383 {
6384 expectation->wr_exit_reason = VMX_VMCALL;
6385 expectation->wr_val = MAGIC_VAL_1;
6386 expectation->wr_only = false;
6387
6388 if (virt_x2apic_mode_on &&
6389 special_processing_applies(reg, &expectation->wr_val,
6390 virt_int_delivery)) {
6391 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED;
6392 if (reg == APIC_SELF_IPI)
6393 expectation->wr_exit_reason = VMX_APIC_WRITE;
6394 } else if (!disable_x2apic &&
6395 get_x2apic_wr_val(reg, &expectation->wr_val)) {
6396 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH;
6397 if (reg == APIC_EOI || reg == APIC_SELF_IPI)
6398 expectation->wr_only = true;
6399 if (reg == APIC_ICR)
6400 expectation->wr_exit_reason = VMX_EXTINT;
6401 } else {
6402 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP;
6403 /*
6404 * Writing 1 to a reserved bit triggers a #GP.
6405 * Thus, set the write value to 0, which seems
6406 * the most likely to detect a missed #GP.
6407 */
6408 expectation->wr_val = 0;
6409 }
6410 }
6411
virt_x2apic_mode_exit_expectation(u32 reg,struct virt_x2apic_mode_config * config,struct virt_x2apic_mode_expectation * expectation)6412 static void virt_x2apic_mode_exit_expectation(
6413 u32 reg, struct virt_x2apic_mode_config *config,
6414 struct virt_x2apic_mode_expectation *expectation)
6415 {
6416 struct apic_reg_virt_config *base_config =
6417 &config->apic_reg_virt_config;
6418 bool virt_x2apic_mode_on =
6419 base_config->virtualize_x2apic_mode &&
6420 config->use_msr_bitmaps &&
6421 config->disable_x2apic_msr_intercepts &&
6422 base_config->activate_secondary_controls;
6423
6424 virt_x2apic_mode_wr_expectation(
6425 reg, virt_x2apic_mode_on, config->disable_x2apic,
6426 config->virtual_interrupt_delivery, expectation);
6427 virt_x2apic_mode_rd_expectation(
6428 reg, virt_x2apic_mode_on, config->disable_x2apic,
6429 base_config->apic_register_virtualization,
6430 config->virtual_interrupt_delivery, expectation);
6431 }
6432
6433 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = {
6434 /*
6435 * Baseline "virtualize x2APIC mode" configuration:
6436 * - virtualize x2APIC mode
6437 * - virtual-interrupt delivery
6438 * - APIC-register virtualization
6439 * - x2APIC MSR intercepts disabled
6440 *
6441 * Reads come from virtual APIC page, special processing applies to
6442 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1
6443 * APIC.
6444 */
6445 {
6446 .name = "Baseline",
6447 .virt_x2apic_mode_config = {
6448 .virtual_interrupt_delivery = true,
6449 .use_msr_bitmaps = true,
6450 .disable_x2apic_msr_intercepts = true,
6451 .disable_x2apic = false,
6452 .apic_reg_virt_config = {
6453 .apic_register_virtualization = true,
6454 .use_tpr_shadow = true,
6455 .virtualize_apic_accesses = false,
6456 .virtualize_x2apic_mode = true,
6457 .activate_secondary_controls = true,
6458 },
6459 },
6460 },
6461 {
6462 .name = "Baseline w/ x2apic disabled",
6463 .virt_x2apic_mode_config = {
6464 .virtual_interrupt_delivery = true,
6465 .use_msr_bitmaps = true,
6466 .disable_x2apic_msr_intercepts = true,
6467 .disable_x2apic = true,
6468 .apic_reg_virt_config = {
6469 .apic_register_virtualization = true,
6470 .use_tpr_shadow = true,
6471 .virtualize_apic_accesses = false,
6472 .virtualize_x2apic_mode = true,
6473 .activate_secondary_controls = true,
6474 },
6475 },
6476 },
6477
6478 /*
6479 * Baseline, minus virtual-interrupt delivery. Reads come from virtual
6480 * APIC page, special processing applies to VTPR, and all other writes
6481 * pass through to L1 APIC.
6482 */
6483 {
6484 .name = "Baseline - virtual interrupt delivery",
6485 .virt_x2apic_mode_config = {
6486 .virtual_interrupt_delivery = false,
6487 .use_msr_bitmaps = true,
6488 .disable_x2apic_msr_intercepts = true,
6489 .disable_x2apic = false,
6490 .apic_reg_virt_config = {
6491 .apic_register_virtualization = true,
6492 .use_tpr_shadow = true,
6493 .virtualize_apic_accesses = false,
6494 .virtualize_x2apic_mode = true,
6495 .activate_secondary_controls = true,
6496 },
6497 },
6498 },
6499
6500 /*
6501 * Baseline, minus APIC-register virtualization. x2APIC reads pass
6502 * through to L1's APIC, unless reading VTPR
6503 */
6504 {
6505 .name = "Virtualize x2APIC mode, no APIC reg virt",
6506 .virt_x2apic_mode_config = {
6507 .virtual_interrupt_delivery = true,
6508 .use_msr_bitmaps = true,
6509 .disable_x2apic_msr_intercepts = true,
6510 .disable_x2apic = false,
6511 .apic_reg_virt_config = {
6512 .apic_register_virtualization = false,
6513 .use_tpr_shadow = true,
6514 .virtualize_apic_accesses = false,
6515 .virtualize_x2apic_mode = true,
6516 .activate_secondary_controls = true,
6517 },
6518 },
6519 },
6520 {
6521 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off",
6522 .virt_x2apic_mode_config = {
6523 .virtual_interrupt_delivery = true,
6524 .use_msr_bitmaps = true,
6525 .disable_x2apic_msr_intercepts = true,
6526 .disable_x2apic = true,
6527 .apic_reg_virt_config = {
6528 .apic_register_virtualization = false,
6529 .use_tpr_shadow = true,
6530 .virtualize_apic_accesses = false,
6531 .virtualize_x2apic_mode = true,
6532 .activate_secondary_controls = true,
6533 },
6534 },
6535 },
6536
6537 /*
6538 * Enable "virtualize x2APIC mode" and "APIC-register virtualization",
6539 * and disable intercepts for the x2APIC MSRs, but fail to enable
6540 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC
6541 * MSRs).
6542 */
6543 {
6544 .name = "Fail to enable activate secondary controls",
6545 .virt_x2apic_mode_config = {
6546 .virtual_interrupt_delivery = true,
6547 .use_msr_bitmaps = true,
6548 .disable_x2apic_msr_intercepts = true,
6549 .disable_x2apic = false,
6550 .apic_reg_virt_config = {
6551 .apic_register_virtualization = true,
6552 .use_tpr_shadow = true,
6553 .virtualize_apic_accesses = false,
6554 .virtualize_x2apic_mode = true,
6555 .activate_secondary_controls = false,
6556 },
6557 },
6558 },
6559
6560 /*
6561 * Enable "APIC-register virtualization" and enable "activate secondary
6562 * controls" and disable intercepts for the x2APIC MSRs, but do not
6563 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2
6564 * gets access to L1's x2APIC MSRs).
6565 */
6566 {
6567 .name = "Fail to enable virtualize x2APIC mode",
6568 .virt_x2apic_mode_config = {
6569 .virtual_interrupt_delivery = true,
6570 .use_msr_bitmaps = true,
6571 .disable_x2apic_msr_intercepts = true,
6572 .disable_x2apic = false,
6573 .apic_reg_virt_config = {
6574 .apic_register_virtualization = true,
6575 .use_tpr_shadow = true,
6576 .virtualize_apic_accesses = false,
6577 .virtualize_x2apic_mode = false,
6578 .activate_secondary_controls = true,
6579 },
6580 },
6581 },
6582
6583 /*
6584 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and
6585 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs.
6586 */
6587 {
6588 .name = "Baseline",
6589 .virt_x2apic_mode_config = {
6590 .virtual_interrupt_delivery = true,
6591 .use_msr_bitmaps = true,
6592 .disable_x2apic_msr_intercepts = true,
6593 .disable_x2apic = false,
6594 .apic_reg_virt_config = {
6595 .apic_register_virtualization = true,
6596 .use_tpr_shadow = true,
6597 .virtualize_apic_accesses = false,
6598 .virtualize_x2apic_mode = false,
6599 .activate_secondary_controls = true,
6600 },
6601 },
6602 },
6603 };
6604
6605 enum X2apic_op {
6606 X2APIC_OP_RD,
6607 X2APIC_OP_WR,
6608 X2APIC_TERMINATE,
6609 };
6610
vmx_x2apic_read(u32 reg)6611 static u64 vmx_x2apic_read(u32 reg)
6612 {
6613 u32 msr_addr = x2apic_msr(reg);
6614 u64 val;
6615
6616 val = rdmsr(msr_addr);
6617
6618 return val;
6619 }
6620
vmx_x2apic_write(u32 reg,u64 val)6621 static void vmx_x2apic_write(u32 reg, u64 val)
6622 {
6623 u32 msr_addr = x2apic_msr(reg);
6624
6625 wrmsr(msr_addr, val);
6626 }
6627
6628 struct virt_x2apic_mode_guest_args {
6629 enum X2apic_op op;
6630 u32 reg;
6631 u64 val;
6632 bool should_gp;
6633 u64 (*virt_fn)(u64);
6634 } virt_x2apic_mode_guest_args;
6635
6636 static volatile bool handle_x2apic_gp_ran;
6637 static volatile u32 handle_x2apic_gp_insn_len;
handle_x2apic_gp(struct ex_regs * regs)6638 static void handle_x2apic_gp(struct ex_regs *regs)
6639 {
6640 handle_x2apic_gp_ran = true;
6641 regs->rip += handle_x2apic_gp_insn_len;
6642 }
6643
setup_x2apic_gp_handler(void)6644 static handler setup_x2apic_gp_handler(void)
6645 {
6646 handler old_handler;
6647
6648 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp);
6649 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */
6650 handle_x2apic_gp_insn_len = 2;
6651
6652 return old_handler;
6653 }
6654
teardown_x2apic_gp_handler(handler old_handler)6655 static void teardown_x2apic_gp_handler(handler old_handler)
6656 {
6657 handle_exception(GP_VECTOR, old_handler);
6658
6659 /*
6660 * Defensively reset instruction length, so that if the handler is
6661 * incorrectly used, it will loop infinitely, rather than run off into
6662 * la la land.
6663 */
6664 handle_x2apic_gp_insn_len = 0;
6665 handle_x2apic_gp_ran = false;
6666 }
6667
virt_x2apic_mode_guest(void)6668 static void virt_x2apic_mode_guest(void)
6669 {
6670 volatile struct virt_x2apic_mode_guest_args *args =
6671 &virt_x2apic_mode_guest_args;
6672
6673 for (;;) {
6674 enum X2apic_op op = args->op;
6675 u32 reg = args->reg;
6676 u64 val = args->val;
6677 bool should_gp = args->should_gp;
6678 u64 (*virt_fn)(u64) = args->virt_fn;
6679 handler old_handler;
6680
6681 if (op == X2APIC_TERMINATE)
6682 break;
6683
6684 if (should_gp) {
6685 TEST_ASSERT(!handle_x2apic_gp_ran);
6686 old_handler = setup_x2apic_gp_handler();
6687 }
6688
6689 if (op == X2APIC_OP_RD) {
6690 u64 ret = vmx_x2apic_read(reg);
6691
6692 if (!should_gp) {
6693 u64 want = virt_fn(val);
6694 u64 got = virt_fn(ret);
6695
6696 report(got == want,
6697 "APIC read; got 0x%lx, want 0x%lx.",
6698 got, want);
6699 }
6700 } else if (op == X2APIC_OP_WR) {
6701 vmx_x2apic_write(reg, val);
6702 }
6703
6704 if (should_gp) {
6705 report(handle_x2apic_gp_ran,
6706 "x2APIC op triggered GP.");
6707 teardown_x2apic_gp_handler(old_handler);
6708 }
6709
6710 /*
6711 * The L1 should always execute a vmcall after it's done testing
6712 * an individual APIC operation. This helps to validate that the
6713 * L1 and L2 are in sync with each other, as expected.
6714 */
6715 vmcall();
6716 }
6717 }
6718
test_x2apic_rd(u32 reg,struct virt_x2apic_mode_expectation * expectation,u32 * virtual_apic_page)6719 static void test_x2apic_rd(
6720 u32 reg, struct virt_x2apic_mode_expectation *expectation,
6721 u32 *virtual_apic_page)
6722 {
6723 u64 val = expectation->rd_val;
6724 u32 exit_reason_want = expectation->rd_exit_reason;
6725 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args;
6726
6727 report_prefix_pushf("x2apic - reading 0x%03x", reg);
6728
6729 /* Configure guest to do an x2apic read */
6730 args->op = X2APIC_OP_RD;
6731 args->reg = reg;
6732 args->val = val;
6733 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP;
6734 args->virt_fn = expectation->virt_fn;
6735
6736 /* Setup virtual APIC page */
6737 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED)
6738 virtual_apic_page[apic_reg_index(reg)] = (u32)val;
6739
6740 /* Enter guest */
6741 enter_guest();
6742
6743 if (exit_reason_want != VMX_VMCALL) {
6744 report_fail("Oops, bad exit expectation: %u.", exit_reason_want);
6745 }
6746
6747 skip_exit_vmcall();
6748 report_prefix_pop();
6749 }
6750
6751 static volatile bool handle_x2apic_ipi_ran;
handle_x2apic_ipi(isr_regs_t * regs)6752 static void handle_x2apic_ipi(isr_regs_t *regs)
6753 {
6754 handle_x2apic_ipi_ran = true;
6755 eoi();
6756 }
6757
test_x2apic_wr(u32 reg,struct virt_x2apic_mode_expectation * expectation,u32 * virtual_apic_page)6758 static void test_x2apic_wr(
6759 u32 reg, struct virt_x2apic_mode_expectation *expectation,
6760 u32 *virtual_apic_page)
6761 {
6762 u64 val = expectation->wr_val;
6763 u32 exit_reason_want = expectation->wr_exit_reason;
6764 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args;
6765 int ipi_vector = 0xf1;
6766 u32 restore_val = 0;
6767
6768 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg);
6769
6770 /* Configure guest to do an x2apic read */
6771 args->op = X2APIC_OP_WR;
6772 args->reg = reg;
6773 args->val = val;
6774 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP;
6775
6776 /* Setup virtual APIC page */
6777 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED)
6778 virtual_apic_page[apic_reg_index(reg)] = 0;
6779 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only)
6780 restore_val = apic_read(reg);
6781
6782 /* Setup IPI handler */
6783 handle_x2apic_ipi_ran = false;
6784 handle_irq(ipi_vector, handle_x2apic_ipi);
6785
6786 /* Enter guest */
6787 enter_guest();
6788
6789 /*
6790 * Validate the behavior and
6791 * pass a magic value back to the guest.
6792 */
6793 if (exit_reason_want == VMX_EXTINT) {
6794 assert_exit_reason(exit_reason_want);
6795
6796 /* Clear the external interrupt. */
6797 sti_nop_cli();
6798 report(handle_x2apic_ipi_ran,
6799 "Got pending interrupt after IRQ enabled.");
6800
6801 enter_guest();
6802 } else if (exit_reason_want == VMX_APIC_WRITE) {
6803 assert_exit_reason(exit_reason_want);
6804 report(virtual_apic_page[apic_reg_index(reg)] == val,
6805 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx",
6806 apic_reg_index(reg),
6807 virtual_apic_page[apic_reg_index(reg)], val);
6808
6809 /* Reenter guest so it can consume/check rcx and exit again. */
6810 enter_guest();
6811 } else if (exit_reason_want != VMX_VMCALL) {
6812 report_fail("Oops, bad exit expectation: %u.", exit_reason_want);
6813 }
6814
6815 assert_exit_reason(VMX_VMCALL);
6816 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) {
6817 u64 want = val;
6818 u32 got = virtual_apic_page[apic_reg_index(reg)];
6819
6820 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got,
6821 want);
6822 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) {
6823 if (!expectation->wr_only) {
6824 u32 got = apic_read(reg);
6825 bool ok;
6826
6827 /*
6828 * When L1's TPR is passed through to L2, the lower
6829 * nibble can be lost. For example, if L2 executes
6830 * WRMSR(0x808, 0x78), then, L1 might read 0x70.
6831 *
6832 * Here's how the lower nibble can get lost:
6833 * 1. L2 executes WRMSR(0x808, 0x78).
6834 * 2. L2 exits to L0 with a WRMSR exit.
6835 * 3. L0 emulates WRMSR, by writing L1's TPR.
6836 * 4. L0 re-enters L2.
6837 * 5. L2 exits to L0 (reason doesn't matter).
6838 * 6. L0 reflects L2's exit to L1.
6839 * 7. Before entering L1, L0 exits to user-space
6840 * (e.g., to satisfy TPR access reporting).
6841 * 8. User-space executes KVM_SET_REGS ioctl, which
6842 * clears the lower nibble of L1's TPR.
6843 */
6844 if (reg == APIC_TASKPRI) {
6845 got = apic_virt_nibble1(got);
6846 val = apic_virt_nibble1(val);
6847 }
6848
6849 ok = got == val;
6850 report(ok,
6851 "non-virtualized write; val is 0x%x, want 0x%lx",
6852 got, val);
6853 apic_write(reg, restore_val);
6854 } else {
6855 report_pass("non-virtualized and write-only OK");
6856 }
6857 }
6858 skip_exit_insn();
6859
6860 report_prefix_pop();
6861 }
6862
configure_virt_x2apic_mode_test(struct virt_x2apic_mode_config * virt_x2apic_mode_config,u8 * msr_bitmap_page)6863 static enum Config_type configure_virt_x2apic_mode_test(
6864 struct virt_x2apic_mode_config *virt_x2apic_mode_config,
6865 u8 *msr_bitmap_page)
6866 {
6867 int msr;
6868 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0);
6869 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1);
6870
6871 /* x2apic-specific VMCS config */
6872 if (virt_x2apic_mode_config->use_msr_bitmaps) {
6873 /* virt_x2apic_mode_test() checks for MSR bitmaps support */
6874 cpu_exec_ctrl0 |= CPU_MSR_BITMAP;
6875 } else {
6876 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP;
6877 }
6878
6879 if (virt_x2apic_mode_config->virtual_interrupt_delivery) {
6880 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) {
6881 report_skip("%s : \"virtual-interrupt delivery\" exec control not supported", __func__);
6882 return CONFIG_TYPE_UNSUPPORTED;
6883 }
6884 cpu_exec_ctrl1 |= CPU_VINTD;
6885 } else {
6886 cpu_exec_ctrl1 &= ~CPU_VINTD;
6887 }
6888
6889 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0);
6890 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1);
6891
6892 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */
6893 for (msr = 0x800; msr <= 0x8ff; msr++) {
6894 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) {
6895 clear_bit(msr, msr_bitmap_page + 0x000);
6896 clear_bit(msr, msr_bitmap_page + 0x800);
6897 } else {
6898 set_bit(msr, msr_bitmap_page + 0x000);
6899 set_bit(msr, msr_bitmap_page + 0x800);
6900 }
6901 }
6902
6903 /* x2APIC mode can impact virtualization */
6904 reset_apic();
6905 if (!virt_x2apic_mode_config->disable_x2apic)
6906 enable_x2apic();
6907
6908 return configure_apic_reg_virt_test(
6909 &virt_x2apic_mode_config->apic_reg_virt_config);
6910 }
6911
virt_x2apic_mode_test(void)6912 static void virt_x2apic_mode_test(void)
6913 {
6914 u32 *virtual_apic_page;
6915 u8 *msr_bitmap_page;
6916 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0);
6917 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1);
6918 int i;
6919 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args;
6920
6921 if (!cpu_has_apicv()) {
6922 report_skip("%s : Not all required APICv bits supported", __func__);
6923 return;
6924 }
6925
6926 /*
6927 * This is to exercise an issue in KVM's logic to merge L0's and L1's
6928 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by
6929 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would
6930 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the
6931 * "Virtualize x2APIC mod" control set, even when it didn't.
6932 */
6933 if (this_cpu_has(X86_FEATURE_SPEC_CTRL))
6934 wrmsr(MSR_IA32_SPEC_CTRL, 1);
6935
6936 /*
6937 * Check that VMCS12 supports:
6938 * - "Virtual-APIC address", indicated by "use TPR shadow"
6939 * - "MSR-bitmap address", indicated by "use MSR bitmaps"
6940 */
6941 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) {
6942 report_skip("%s : \"Use TPR shadow\" exec control not supported", __func__);
6943 return;
6944 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) {
6945 report_skip("%s : \"Use MSR bitmaps\" exec control not supported", __func__);
6946 return;
6947 }
6948
6949 test_set_guest(virt_x2apic_mode_guest);
6950
6951 virtual_apic_page = alloc_page();
6952 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page));
6953
6954 msr_bitmap_page = alloc_page();
6955 memset(msr_bitmap_page, 0xff, PAGE_SIZE);
6956 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page));
6957
6958 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) {
6959 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case =
6960 &virt_x2apic_mode_tests[i];
6961 struct virt_x2apic_mode_config *virt_x2apic_mode_config =
6962 &virt_x2apic_mode_test_case->virt_x2apic_mode_config;
6963 enum Config_type config_type;
6964 u32 reg;
6965
6966 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name);
6967 config_type =
6968 configure_virt_x2apic_mode_test(virt_x2apic_mode_config,
6969 msr_bitmap_page);
6970 if (config_type == CONFIG_TYPE_UNSUPPORTED) {
6971 report_skip("Skip because of missing features.");
6972 continue;
6973 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) {
6974 enter_guest_with_bad_controls();
6975 continue;
6976 }
6977
6978 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) {
6979 struct virt_x2apic_mode_expectation expectation;
6980
6981 virt_x2apic_mode_exit_expectation(
6982 reg, virt_x2apic_mode_config, &expectation);
6983
6984 test_x2apic_rd(reg, &expectation, virtual_apic_page);
6985 test_x2apic_wr(reg, &expectation, virtual_apic_page);
6986 }
6987 }
6988
6989
6990 /* Terminate the guest */
6991 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0);
6992 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1);
6993 args->op = X2APIC_TERMINATE;
6994 enter_guest();
6995 assert_exit_reason(VMX_VMCALL);
6996 }
6997
test_ctl_reg(const char * cr_name,u64 cr,u64 fixed0,u64 fixed1)6998 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1)
6999 {
7000 u64 val;
7001 u64 cr_saved = vmcs_read(cr);
7002 int i;
7003
7004 val = fixed0 & fixed1;
7005 if (cr == HOST_CR4)
7006 vmcs_write(cr, val | X86_CR4_PAE);
7007 else
7008 vmcs_write(cr, val);
7009 report_prefix_pushf("%s %lx", cr_name, val);
7010 if (val == fixed0)
7011 test_vmx_vmlaunch(0);
7012 else
7013 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7014 report_prefix_pop();
7015
7016 for (i = 0; i < 64; i++) {
7017
7018 /* Set a bit when the corresponding bit in fixed1 is 0 */
7019 if ((fixed1 & (1ull << i)) == 0) {
7020 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP ||
7021 (1ull << i) & X86_CR4_SMAP))
7022 continue;
7023
7024 vmcs_write(cr, cr_saved | (1ull << i));
7025 report_prefix_pushf("%s %llx", cr_name,
7026 cr_saved | (1ull << i));
7027 test_vmx_vmlaunch(
7028 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7029 report_prefix_pop();
7030 }
7031
7032 /* Unset a bit when the corresponding bit in fixed0 is 1 */
7033 if (fixed0 & (1ull << i)) {
7034 vmcs_write(cr, cr_saved & ~(1ull << i));
7035 report_prefix_pushf("%s %llx", cr_name,
7036 cr_saved & ~(1ull << i));
7037 test_vmx_vmlaunch(
7038 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7039 report_prefix_pop();
7040 }
7041 }
7042
7043 vmcs_write(cr, cr_saved);
7044 }
7045
7046 /*
7047 * 1. The CR0 field must not set any bit to a value not supported in VMX
7048 * operation.
7049 * 2. The CR4 field must not set any bit to a value not supported in VMX
7050 * operation.
7051 * 3. On processors that support Intel 64 architecture, the CR3 field must
7052 * be such that bits 63:52 and bits in the range 51:32 beyond the
7053 * processor's physical-address width must be 0.
7054 *
7055 * [Intel SDM]
7056 */
test_host_ctl_regs(void)7057 static void test_host_ctl_regs(void)
7058 {
7059 u64 fixed0, fixed1, cr3, cr3_saved;
7060 int i;
7061
7062 /* Test CR0 */
7063 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0);
7064 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1);
7065 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1);
7066
7067 /* Test CR4 */
7068 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0);
7069 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) &
7070 ~(X86_CR4_SMEP | X86_CR4_SMAP);
7071 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1);
7072
7073 /* Test CR3 */
7074 cr3_saved = vmcs_read(HOST_CR3);
7075 for (i = cpuid_maxphyaddr(); i < 64; i++) {
7076 cr3 = cr3_saved | (1ul << i);
7077 vmcs_write(HOST_CR3, cr3);
7078 report_prefix_pushf("HOST_CR3 %lx", cr3);
7079 if (this_cpu_has(X86_FEATURE_LAM) &&
7080 ((i == X86_CR3_LAM_U57_BIT) || (i == X86_CR3_LAM_U48_BIT)))
7081 test_vmx_vmlaunch(0);
7082 else
7083 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7084 report_prefix_pop();
7085 }
7086
7087 vmcs_write(HOST_CR3, cr3_saved);
7088 }
7089
test_efer_vmlaunch(u32 fld,bool ok)7090 static void test_efer_vmlaunch(u32 fld, bool ok)
7091 {
7092 if (fld == HOST_EFER) {
7093 if (ok)
7094 test_vmx_vmlaunch(0);
7095 else
7096 test_vmx_vmlaunch2(VMXERR_ENTRY_INVALID_CONTROL_FIELD,
7097 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7098 } else {
7099 test_guest_state("EFER test", !ok, GUEST_EFER, "GUEST_EFER");
7100 }
7101 }
7102
test_efer_one(u32 fld,const char * fld_name,u64 efer,u32 ctrl_fld,u64 ctrl,int i,const char * efer_bit_name)7103 static void test_efer_one(u32 fld, const char * fld_name, u64 efer,
7104 u32 ctrl_fld, u64 ctrl,
7105 int i, const char *efer_bit_name)
7106 {
7107 bool ok;
7108
7109 ok = true;
7110 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) {
7111 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64))
7112 ok = false;
7113 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64))
7114 ok = false;
7115 }
7116 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) {
7117 /* Check LMA too since CR0.PG is set. */
7118 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64))
7119 ok = false;
7120 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64))
7121 ok = false;
7122 }
7123
7124 /*
7125 * Skip the test if it would enter the guest in 32-bit mode.
7126 * Perhaps write the test in assembly and make sure it
7127 * can be run in either mode?
7128 */
7129 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64))
7130 return;
7131
7132 vmcs_write(ctrl_fld, ctrl);
7133 vmcs_write(fld, efer);
7134 report_prefix_pushf("%s %s bit turned %s, controls %s",
7135 fld_name, efer_bit_name,
7136 (i & 1) ? "on" : "off",
7137 (i & 2) ? "on" : "off");
7138
7139 test_efer_vmlaunch(fld, ok);
7140 report_prefix_pop();
7141 }
7142
test_efer_bit(u32 fld,const char * fld_name,u32 ctrl_fld,u64 ctrl_bit,u64 efer_bit,const char * efer_bit_name)7143 static void test_efer_bit(u32 fld, const char * fld_name,
7144 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit,
7145 const char *efer_bit_name)
7146 {
7147 u64 efer_saved = vmcs_read(fld);
7148 u32 ctrl_saved = vmcs_read(ctrl_fld);
7149 int i;
7150
7151 for (i = 0; i < 4; i++) {
7152 u64 efer = efer_saved & ~efer_bit;
7153 u64 ctrl = ctrl_saved & ~ctrl_bit;
7154
7155 if (i & 1)
7156 efer |= efer_bit;
7157 if (i & 2)
7158 ctrl |= ctrl_bit;
7159
7160 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl,
7161 i, efer_bit_name);
7162 }
7163
7164 vmcs_write(ctrl_fld, ctrl_saved);
7165 vmcs_write(fld, efer_saved);
7166 }
7167
test_efer(u32 fld,const char * fld_name,u32 ctrl_fld,u64 ctrl_bit1,u64 ctrl_bit2)7168 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld,
7169 u64 ctrl_bit1, u64 ctrl_bit2)
7170 {
7171 u64 efer_saved = vmcs_read(fld);
7172 u32 ctrl_saved = vmcs_read(ctrl_fld);
7173 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
7174 u64 i;
7175 u64 efer;
7176
7177 if (this_cpu_has(X86_FEATURE_NX))
7178 efer_reserved_bits &= ~EFER_NX;
7179
7180 if (!ctrl_bit1) {
7181 report_skip("%s : \"Load-IA32-EFER\" exit control not supported", __func__);
7182 goto test_entry_exit_mode;
7183 }
7184
7185 report_prefix_pushf("%s %lx", fld_name, efer_saved);
7186 test_efer_vmlaunch(fld, true);
7187 report_prefix_pop();
7188
7189 /*
7190 * Check reserved bits
7191 */
7192 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1);
7193 for (i = 0; i < 64; i++) {
7194 if ((1ull << i) & efer_reserved_bits) {
7195 efer = efer_saved | (1ull << i);
7196 vmcs_write(fld, efer);
7197 report_prefix_pushf("%s %lx", fld_name, efer);
7198 test_efer_vmlaunch(fld, true);
7199 report_prefix_pop();
7200 }
7201 }
7202
7203 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1);
7204 for (i = 0; i < 64; i++) {
7205 if ((1ull << i) & efer_reserved_bits) {
7206 efer = efer_saved | (1ull << i);
7207 vmcs_write(fld, efer);
7208 report_prefix_pushf("%s %lx", fld_name, efer);
7209 test_efer_vmlaunch(fld, false);
7210 report_prefix_pop();
7211 }
7212 }
7213
7214 vmcs_write(ctrl_fld, ctrl_saved);
7215 vmcs_write(fld, efer_saved);
7216
7217 /*
7218 * Check LMA and LME bits
7219 */
7220 test_efer_bit(fld, fld_name,
7221 ctrl_fld, ctrl_bit1,
7222 EFER_LMA,
7223 "EFER_LMA");
7224 test_efer_bit(fld, fld_name,
7225 ctrl_fld, ctrl_bit1,
7226 EFER_LME,
7227 "EFER_LME");
7228
7229 test_entry_exit_mode:
7230 test_efer_bit(fld, fld_name,
7231 ctrl_fld, ctrl_bit2,
7232 EFER_LMA,
7233 "EFER_LMA");
7234 test_efer_bit(fld, fld_name,
7235 ctrl_fld, ctrl_bit2,
7236 EFER_LME,
7237 "EFER_LME");
7238 }
7239
7240 /*
7241 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the
7242 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7243 * the values of the LMA and LME bits in the field must each be that of
7244 * the 'host address-space size' VM-exit control.
7245 *
7246 * [Intel SDM]
7247 */
test_host_efer(void)7248 static void test_host_efer(void)
7249 {
7250 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS,
7251 ctrl_exit_rev.clr & EXI_LOAD_EFER,
7252 EXI_HOST_64);
7253 }
7254
7255 /*
7256 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the
7257 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7258 * the values of the LMA and LME bits in the field must each be that of
7259 * the 'IA32e-mode guest' VM-exit control.
7260 */
test_guest_efer(void)7261 static void test_guest_efer(void)
7262 {
7263 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) {
7264 report_skip("%s : \"Load-IA32-EFER\" entry control not supported", __func__);
7265 return;
7266 }
7267
7268 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER));
7269 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS,
7270 ctrl_enter_rev.clr & ENT_LOAD_EFER,
7271 ENT_GUEST_64);
7272 }
7273
7274 /*
7275 * PAT values higher than 8 are uninteresting since they're likely lumped
7276 * in with "8". We only test values above 8 one bit at a time,
7277 * in order to reduce the number of VM-Entries and keep the runtime reasonable.
7278 */
7279 #define PAT_VAL_LIMIT 8
7280
test_pat(u32 field,const char * field_name,u32 ctrl_field,u64 ctrl_bit)7281 static void test_pat(u32 field, const char * field_name, u32 ctrl_field,
7282 u64 ctrl_bit)
7283 {
7284 u64 pat_msr_saved = rdmsr(MSR_IA32_CR_PAT);
7285 u32 ctrl_saved = vmcs_read(ctrl_field);
7286 u64 pat_saved = vmcs_read(field);
7287 u64 i, val;
7288 u32 j;
7289 int error;
7290
7291 vmcs_clear_bits(ctrl_field, ctrl_bit);
7292
7293 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) {
7294 /* Test PAT0..PAT7 fields */
7295 for (j = 0; j < (i ? 8 : 1); j++) {
7296 val = i << j * 8;
7297 vmcs_write(field, val);
7298 if (field == HOST_PAT) {
7299 report_prefix_pushf("%s %lx", field_name, val);
7300 test_vmx_vmlaunch(0);
7301 report_prefix_pop();
7302
7303 } else { // GUEST_PAT
7304 test_guest_state("ENT_LOAD_PAT disabled", false,
7305 val, "GUEST_PAT");
7306 }
7307 }
7308 }
7309
7310 vmcs_set_bits(ctrl_field, ctrl_bit);
7311 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) {
7312 /* Test PAT0..PAT7 fields */
7313 for (j = 0; j < (i ? 8 : 1); j++) {
7314 val = i << j * 8;
7315 vmcs_write(field, val);
7316
7317 if (field == HOST_PAT) {
7318 report_prefix_pushf("%s %lx", field_name, val);
7319 if (i == 0x2 || i == 0x3 || i >= 0x8)
7320 error =
7321 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
7322 else
7323 error = 0;
7324
7325 test_vmx_vmlaunch(error);
7326
7327 if (!error)
7328 report(rdmsr(MSR_IA32_CR_PAT) == val,
7329 "Expected PAT = 0x%lx, got 0x%lx",
7330 val, rdmsr(MSR_IA32_CR_PAT));
7331 wrmsr(MSR_IA32_CR_PAT, pat_msr_saved);
7332
7333 report_prefix_pop();
7334
7335 } else { // GUEST_PAT
7336 error = (i == 0x2 || i == 0x3 || i >= 0x8);
7337 test_guest_state("ENT_LOAD_PAT enabled", !!error,
7338 val, "GUEST_PAT");
7339
7340 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT))
7341 wrmsr(MSR_IA32_CR_PAT, pat_msr_saved);
7342 }
7343
7344 }
7345 }
7346
7347 vmcs_write(ctrl_field, ctrl_saved);
7348 vmcs_write(field, pat_saved);
7349 }
7350
7351 /*
7352 * If the "load IA32_PAT" VM-exit control is 1, the value of the field
7353 * for the IA32_PAT MSR must be one that could be written by WRMSR
7354 * without fault at CPL 0. Specifically, each of the 8 bytes in the
7355 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP),
7356 * 6 (WB), or 7 (UC-).
7357 *
7358 * [Intel SDM]
7359 */
test_load_host_pat(void)7360 static void test_load_host_pat(void)
7361 {
7362 /*
7363 * "load IA32_PAT" VM-exit control
7364 */
7365 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) {
7366 report_skip("%s : \"Load-IA32-PAT\" exit control not supported", __func__);
7367 return;
7368 }
7369
7370 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT);
7371 }
7372
7373 union cpuidA_eax {
7374 struct {
7375 unsigned int version_id:8;
7376 unsigned int num_counters_gp:8;
7377 unsigned int bit_width:8;
7378 unsigned int mask_length:8;
7379 } split;
7380 unsigned int full;
7381 };
7382
7383 union cpuidA_ecx {
7384 unsigned int fixed_counters_mask;
7385 unsigned int full;
7386 };
7387
7388 union cpuidA_edx {
7389 struct {
7390 unsigned int num_contiguous_fixed_counters:5;
7391 unsigned int bit_width_fixed:8;
7392 unsigned int reserved1:2;
7393 unsigned int anythread_deprecated:1;
7394 unsigned int reserved2:16;
7395 } split;
7396 unsigned int full;
7397 };
7398
valid_pgc(u64 val)7399 static bool valid_pgc(u64 val)
7400 {
7401 struct cpuid id;
7402 union cpuidA_eax eax;
7403 union cpuidA_ecx ecx;
7404 union cpuidA_edx edx;
7405 u64 mask;
7406
7407 id = cpuid(0xA);
7408 eax.full = id.a;
7409 ecx.full = id.c;
7410 edx.full = id.d;
7411
7412 /* FxCtr[i]_is_supported := ECX[i] || (EDX[4:0] > i); */
7413 mask = ~(((1ull << eax.split.num_counters_gp) - 1) |
7414 (((1ull << edx.split.num_contiguous_fixed_counters) - 1) << 32) |
7415 ((u64)ecx.fixed_counters_mask << 32));
7416
7417 return !(val & mask);
7418 }
7419
test_pgc_vmlaunch(u32 xerror,u32 xreason,bool xfail,bool host)7420 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host)
7421 {
7422 u32 inst_err;
7423 u64 obs;
7424 bool success;
7425 struct vmx_state_area_test_data *data = &vmx_state_area_test_data;
7426
7427 if (host) {
7428 success = vmlaunch();
7429 obs = rdmsr(data->msr);
7430 if (!success) {
7431 inst_err = vmcs_read(VMX_INST_ERROR);
7432 report(xerror == inst_err, "vmlaunch failed, "
7433 "VMX Inst Error is %d (expected %d)",
7434 inst_err, xerror);
7435 } else {
7436 report(!data->enabled || data->exp == obs,
7437 "Host state is 0x%lx (expected 0x%lx)",
7438 obs, data->exp);
7439 report(success != xfail, "vmlaunch succeeded");
7440 }
7441 } else {
7442 test_guest_state("load GUEST_PERF_GLOBAL_CTRL", xfail,
7443 GUEST_PERF_GLOBAL_CTRL,
7444 "GUEST_PERF_GLOBAL_CTRL");
7445 }
7446 }
7447
7448 /*
7449 * test_load_perf_global_ctrl is a generic function for testing the
7450 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function
7451 * tests the provided ctrl_val when disabled and enabled.
7452 *
7453 * @nr: VMCS field number corresponding to the host/guest state field
7454 * @name: Name of the above VMCS field for printing in test report
7455 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control
7456 * @ctrl_val: Bit to set on the ctrl_field
7457 */
test_perf_global_ctrl(u32 nr,const char * name,u32 ctrl_nr,const char * ctrl_name,u64 ctrl_val)7458 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr,
7459 const char *ctrl_name, u64 ctrl_val)
7460 {
7461 u64 ctrl_saved = vmcs_read(ctrl_nr);
7462 u64 pgc_saved = vmcs_read(nr);
7463 u64 i, val;
7464 bool host = nr == HOST_PERF_GLOBAL_CTRL;
7465 struct vmx_state_area_test_data *data = &vmx_state_area_test_data;
7466
7467 data->msr = MSR_CORE_PERF_GLOBAL_CTRL;
7468 msr_bmp_init();
7469 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val);
7470 data->enabled = false;
7471 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s",
7472 ctrl_name);
7473
7474 for (i = 0; i < 64; i++) {
7475 val = 1ull << i;
7476 vmcs_write(nr, val);
7477 report_prefix_pushf("%s = 0x%lx", name, val);
7478 test_pgc_vmlaunch(0, VMX_VMCALL, false, host);
7479 report_prefix_pop();
7480 }
7481 report_prefix_pop();
7482
7483 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val);
7484 data->enabled = true;
7485 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s",
7486 ctrl_name);
7487 for (i = 0; i < 64; i++) {
7488 val = 1ull << i;
7489 data->exp = val;
7490 vmcs_write(nr, val);
7491 report_prefix_pushf("%s = 0x%lx", name, val);
7492 if (valid_pgc(val)) {
7493 test_pgc_vmlaunch(0, VMX_VMCALL, false, host);
7494 } else {
7495 if (host)
7496 test_pgc_vmlaunch(
7497 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD,
7498 0,
7499 true,
7500 host);
7501 else
7502 test_pgc_vmlaunch(
7503 0,
7504 VMX_ENTRY_FAILURE | VMX_FAIL_STATE,
7505 true,
7506 host);
7507 }
7508 report_prefix_pop();
7509 }
7510
7511 data->enabled = false;
7512 report_prefix_pop();
7513 vmcs_write(ctrl_nr, ctrl_saved);
7514 vmcs_write(nr, pgc_saved);
7515 }
7516
test_load_host_perf_global_ctrl(void)7517 static void test_load_host_perf_global_ctrl(void)
7518 {
7519 if (!this_cpu_has_perf_global_ctrl()) {
7520 report_skip("%s : \"IA32_PERF_GLOBAL_CTRL\" MSR not supported", __func__);
7521 return;
7522 }
7523
7524 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) {
7525 report_skip("%s : \"Load IA32_PERF_GLOBAL_CTRL\" exit control not supported", __func__);
7526 return;
7527 }
7528
7529 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL",
7530 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF);
7531 }
7532
7533
test_load_guest_perf_global_ctrl(void)7534 static void test_load_guest_perf_global_ctrl(void)
7535 {
7536 if (!this_cpu_has_perf_global_ctrl()) {
7537 report_skip("%s : \"IA32_PERF_GLOBAL_CTRL\" MSR not supported", __func__);
7538 return;
7539 }
7540
7541 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) {
7542 report_skip("%s : \"Load IA32_PERF_GLOBAL_CTRL\" entry control not supported", __func__);
7543 return;
7544 }
7545
7546 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL",
7547 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF);
7548 }
7549
7550
7551 /*
7552 * test_vmcs_field - test a value for the given VMCS field
7553 * @field: VMCS field
7554 * @field_name: string name of VMCS field
7555 * @bit_start: starting bit
7556 * @bit_end: ending bit
7557 * @val: value that the bit range must or must not contain
7558 * @valid_val: whether value given in 'val' must be valid or not
7559 * @error: expected VMCS error when vmentry fails for an invalid value
7560 */
test_vmcs_field(u64 field,const char * field_name,u32 bit_start,u32 bit_end,u64 val,bool valid_val,u32 error)7561 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start,
7562 u32 bit_end, u64 val, bool valid_val, u32 error)
7563 {
7564 u64 field_saved = vmcs_read(field);
7565 u32 i;
7566 u64 tmp;
7567 u32 bit_on;
7568 u64 mask = ~0ull;
7569
7570 mask = (mask >> bit_end) << bit_end;
7571 mask = mask | ((1 << bit_start) - 1);
7572 tmp = (field_saved & mask) | (val << bit_start);
7573
7574 vmcs_write(field, tmp);
7575 report_prefix_pushf("%s %lx", field_name, tmp);
7576 if (valid_val)
7577 test_vmx_vmlaunch(0);
7578 else
7579 test_vmx_vmlaunch(error);
7580 report_prefix_pop();
7581
7582 for (i = bit_start; i <= bit_end; i = i + 2) {
7583 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1;
7584 if (bit_on)
7585 tmp = field_saved | (1ull << i);
7586 else
7587 tmp = field_saved & ~(1ull << i);
7588 vmcs_write(field, tmp);
7589 report_prefix_pushf("%s %lx", field_name, tmp);
7590 if (valid_val)
7591 test_vmx_vmlaunch(error);
7592 else
7593 test_vmx_vmlaunch(0);
7594 report_prefix_pop();
7595 }
7596
7597 vmcs_write(field, field_saved);
7598 }
7599
test_canonical(u64 field,const char * field_name,bool host)7600 static void test_canonical(u64 field, const char * field_name, bool host)
7601 {
7602 u64 addr_saved = vmcs_read(field);
7603
7604 /*
7605 * Use the existing value if possible. Writing a random canonical
7606 * value is not an option as doing so would corrupt the field being
7607 * tested and likely hose the test.
7608 */
7609 if (is_canonical(addr_saved)) {
7610 if (host) {
7611 report_prefix_pushf("%s %lx", field_name, addr_saved);
7612 test_vmx_vmlaunch(0);
7613 report_prefix_pop();
7614 } else {
7615 test_guest_state("Test canonical address", false,
7616 addr_saved, field_name);
7617 }
7618 }
7619
7620 vmcs_write(field, NONCANONICAL);
7621
7622 if (host) {
7623 report_prefix_pushf("%s %llx", field_name, NONCANONICAL);
7624 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7625 report_prefix_pop();
7626 } else {
7627 test_guest_state("Test non-canonical address", true,
7628 NONCANONICAL, field_name);
7629 }
7630
7631 vmcs_write(field, addr_saved);
7632 }
7633
7634 #define TEST_RPL_TI_FLAGS(reg, name) \
7635 test_vmcs_field(reg, name, 0, 2, 0x0, true, \
7636 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7637
7638 #define TEST_CS_TR_FLAGS(reg, name) \
7639 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \
7640 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7641
7642 /*
7643 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the
7644 * RPL (bits 1:0) and the TI flag (bit 2) must be 0.
7645 * 2. The selector fields for CS and TR cannot be 0000H.
7646 * 3. The selector field for SS cannot be 0000H if the "host address-space
7647 * size" VM-exit control is 0.
7648 * 4. On processors that support Intel 64 architecture, the base-address
7649 * fields for FS, GS and TR must contain canonical addresses.
7650 */
test_host_segment_regs(void)7651 static void test_host_segment_regs(void)
7652 {
7653 u16 selector_saved;
7654
7655 /*
7656 * Test RPL and TI flags
7657 */
7658 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS");
7659 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS");
7660 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS");
7661 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES");
7662 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS");
7663 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS");
7664 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR");
7665
7666 /*
7667 * Test that CS and TR fields can not be 0x0000
7668 */
7669 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS");
7670 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR");
7671
7672 /*
7673 * SS field can not be 0x0000 if "host address-space size" VM-exit
7674 * control is 0
7675 */
7676 selector_saved = vmcs_read(HOST_SEL_SS);
7677 vmcs_write(HOST_SEL_SS, 0);
7678 report_prefix_pushf("HOST_SEL_SS 0");
7679 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) {
7680 test_vmx_vmlaunch(0);
7681 } else {
7682 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7683 }
7684 report_prefix_pop();
7685
7686 vmcs_write(HOST_SEL_SS, selector_saved);
7687
7688 /*
7689 * Base address for FS, GS and TR must be canonical
7690 */
7691 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true);
7692 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true);
7693 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true);
7694 }
7695
7696 /*
7697 * On processors that support Intel 64 architecture, the base-address
7698 * fields for GDTR and IDTR must contain canonical addresses.
7699 */
test_host_desc_tables(void)7700 static void test_host_desc_tables(void)
7701 {
7702 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true);
7703 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true);
7704 }
7705
7706 /*
7707 * If the "host address-space size" VM-exit control is 0, the following must
7708 * hold:
7709 * - The "IA-32e mode guest" VM-entry control is 0.
7710 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0.
7711 * - Bits 63:32 in the RIP field are 0.
7712 *
7713 * If the "host address-space size" VM-exit control is 1, the following must
7714 * hold:
7715 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1.
7716 * - The RIP field contains a canonical address.
7717 *
7718 */
test_host_addr_size(void)7719 static void test_host_addr_size(void)
7720 {
7721 u64 cr4_saved = vmcs_read(HOST_CR4);
7722 u64 rip_saved = vmcs_read(HOST_RIP);
7723 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS);
7724
7725 assert(vmcs_read(EXI_CONTROLS) & EXI_HOST_64);
7726 assert(cr4_saved & X86_CR4_PAE);
7727
7728 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64);
7729 report_prefix_pushf("\"IA-32e mode guest\" enabled");
7730 test_vmx_vmlaunch(0);
7731 report_prefix_pop();
7732
7733 if (this_cpu_has(X86_FEATURE_PCID)) {
7734 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE);
7735 report_prefix_pushf("\"CR4.PCIDE\" set");
7736 test_vmx_vmlaunch(0);
7737 report_prefix_pop();
7738 }
7739
7740 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE);
7741 report_prefix_pushf("\"CR4.PAE\" unset");
7742 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7743 vmcs_write(HOST_CR4, cr4_saved);
7744 report_prefix_pop();
7745
7746 vmcs_write(HOST_RIP, NONCANONICAL);
7747 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL);
7748 test_vmx_vmlaunch_must_fail(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7749 report_prefix_pop();
7750
7751 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64);
7752 vmcs_write(HOST_RIP, rip_saved);
7753 vmcs_write(HOST_CR4, cr4_saved);
7754
7755 /*
7756 * Restore host's active CR4 and RIP values by triggering a VM-Exit.
7757 * The original CR4 and RIP values in the VMCS are restored between
7758 * testcases as needed, but don't guarantee a VM-Exit and so the active
7759 * CR4 and RIP may still hold a test value. Running with the test CR4
7760 * and RIP values at some point is unavoidable, and the active values
7761 * are unlikely to affect VM-Enter, so the above doesn't force a VM-exit
7762 * between testcases. Note, if VM-Enter is surrounded by CALL+RET then
7763 * the active RIP will already be restored, but that's also not
7764 * guaranteed, and CR4 needs to be restored regardless.
7765 */
7766 report_prefix_pushf("restore host state");
7767 test_vmx_vmlaunch(0);
7768 report_prefix_pop();
7769 }
7770
7771 /*
7772 * Check that the virtual CPU checks the VMX Host State Area as
7773 * documented in the Intel SDM.
7774 */
vmx_host_state_area_test(void)7775 static void vmx_host_state_area_test(void)
7776 {
7777 /*
7778 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will
7779 * fail due to invalid guest state, should we make it that
7780 * far.
7781 */
7782 vmcs_write(GUEST_RFLAGS, 0);
7783
7784 test_host_ctl_regs();
7785
7786 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true);
7787 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true);
7788
7789 test_host_efer();
7790 test_load_host_pat();
7791 test_host_segment_regs();
7792 test_host_desc_tables();
7793 test_host_addr_size();
7794 test_load_host_perf_global_ctrl();
7795 }
7796
7797 /*
7798 * If the "load debug controls" VM-entry control is 1, bits 63:32 in
7799 * the DR7 field must be 0.
7800 *
7801 * [Intel SDM]
7802 */
test_guest_dr7(void)7803 static void test_guest_dr7(void)
7804 {
7805 u32 ent_saved = vmcs_read(ENT_CONTROLS);
7806 u64 dr7_saved = vmcs_read(GUEST_DR7);
7807 u64 val;
7808 int i;
7809
7810 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) {
7811 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS);
7812 for (i = 0; i < 64; i++) {
7813 val = 1ull << i;
7814 vmcs_write(GUEST_DR7, val);
7815 test_guest_state("ENT_LOAD_DBGCTLS disabled", false,
7816 val, "GUEST_DR7");
7817 }
7818 }
7819 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) {
7820 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS);
7821 for (i = 0; i < 64; i++) {
7822 val = 1ull << i;
7823 vmcs_write(GUEST_DR7, val);
7824 test_guest_state("ENT_LOAD_DBGCTLS enabled", i >= 32,
7825 val, "GUEST_DR7");
7826 }
7827 }
7828 vmcs_write(GUEST_DR7, dr7_saved);
7829 vmcs_write(ENT_CONTROLS, ent_saved);
7830 }
7831
7832 /*
7833 * If the "load IA32_PAT" VM-entry control is 1, the value of the field
7834 * for the IA32_PAT MSR must be one that could be written by WRMSR
7835 * without fault at CPL 0. Specifically, each of the 8 bytes in the
7836 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP),
7837 * 6 (WB), or 7 (UC-).
7838 *
7839 * [Intel SDM]
7840 */
test_load_guest_pat(void)7841 static void test_load_guest_pat(void)
7842 {
7843 /*
7844 * "load IA32_PAT" VM-entry control
7845 */
7846 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) {
7847 report_skip("%s : \"Load-IA32-PAT\" entry control not supported", __func__);
7848 return;
7849 }
7850
7851 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT);
7852 }
7853
7854 #define MSR_IA32_BNDCFGS_RSVD_MASK 0x00000ffc
7855
7856 /*
7857 * If the "load IA32_BNDCFGS" VM-entry control is 1, the following
7858 * checks are performed on the field for the IA32_BNDCFGS MSR:
7859 *
7860 * - Bits reserved in the IA32_BNDCFGS MSR must be 0.
7861 * - The linear address in bits 63:12 must be canonical.
7862 *
7863 * [Intel SDM]
7864 */
test_load_guest_bndcfgs(void)7865 static void test_load_guest_bndcfgs(void)
7866 {
7867 u64 bndcfgs_saved = vmcs_read(GUEST_BNDCFGS);
7868 u64 bndcfgs;
7869
7870 if (!(ctrl_enter_rev.clr & ENT_LOAD_BNDCFGS)) {
7871 report_skip("%s : \"Load-IA32-BNDCFGS\" entry control not supported", __func__);
7872 return;
7873 }
7874
7875 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS);
7876
7877 vmcs_write(GUEST_BNDCFGS, NONCANONICAL);
7878 test_guest_state("ENT_LOAD_BNDCFGS disabled", false,
7879 GUEST_BNDCFGS, "GUEST_BNDCFGS");
7880 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK;
7881 vmcs_write(GUEST_BNDCFGS, bndcfgs);
7882 test_guest_state("ENT_LOAD_BNDCFGS disabled", false,
7883 GUEST_BNDCFGS, "GUEST_BNDCFGS");
7884
7885 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS);
7886
7887 vmcs_write(GUEST_BNDCFGS, NONCANONICAL);
7888 test_guest_state("ENT_LOAD_BNDCFGS enabled", true,
7889 GUEST_BNDCFGS, "GUEST_BNDCFGS");
7890 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK;
7891 vmcs_write(GUEST_BNDCFGS, bndcfgs);
7892 test_guest_state("ENT_LOAD_BNDCFGS enabled", true,
7893 GUEST_BNDCFGS, "GUEST_BNDCFGS");
7894
7895 vmcs_write(GUEST_BNDCFGS, bndcfgs_saved);
7896 }
7897
7898 #define GUEST_SEG_UNUSABLE_MASK (1u << 16)
7899 #define GUEST_SEG_SEL_TI_MASK (1u << 2)
7900
7901
7902 #define TEST_SEGMENT_SEL(test, xfail, sel, val) \
7903 do { \
7904 vmcs_write(sel, val); \
7905 test_guest_state(test " segment", xfail, val, xstr(sel)); \
7906 } while (0)
7907
7908 #define TEST_INVALID_SEG_SEL(sel, val) \
7909 TEST_SEGMENT_SEL("Invalid: " xstr(val), true, sel, val);
7910
7911 #define TEST_VALID_SEG_SEL(sel, val) \
7912 TEST_SEGMENT_SEL("Valid: " xstr(val), false, sel, val);
7913
7914 /*
7915 * The following checks are done on the Selector field of the Guest Segment
7916 * Registers:
7917 * - TR. The TI flag (bit 2) must be 0.
7918 * - LDTR. If LDTR is usable, the TI flag (bit 2) must be 0.
7919 * - SS. If the guest will not be virtual-8086 and the "unrestricted
7920 * guest" VM-execution control is 0, the RPL (bits 1:0) must equal
7921 * the RPL of the selector field for CS.
7922 *
7923 * [Intel SDM]
7924 */
test_guest_segment_sel_fields(void)7925 static void test_guest_segment_sel_fields(void)
7926 {
7927 u16 sel_saved;
7928 u32 ar_saved;
7929 u32 cpu_ctrl0_saved;
7930 u32 cpu_ctrl1_saved;
7931 u16 cs_rpl_bits;
7932
7933 /*
7934 * Test for GUEST_SEL_TR
7935 */
7936 sel_saved = vmcs_read(GUEST_SEL_TR);
7937 TEST_INVALID_SEG_SEL(GUEST_SEL_TR, sel_saved | GUEST_SEG_SEL_TI_MASK);
7938 vmcs_write(GUEST_SEL_TR, sel_saved);
7939
7940 /*
7941 * Test for GUEST_SEL_LDTR
7942 */
7943 sel_saved = vmcs_read(GUEST_SEL_LDTR);
7944 ar_saved = vmcs_read(GUEST_AR_LDTR);
7945 /* LDTR is set unusable */
7946 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK);
7947 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK);
7948 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK);
7949 /* LDTR is set usable */
7950 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK);
7951 TEST_INVALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK);
7952
7953 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK);
7954
7955 vmcs_write(GUEST_AR_LDTR, ar_saved);
7956 vmcs_write(GUEST_SEL_LDTR, sel_saved);
7957
7958 /*
7959 * Test for GUEST_SEL_SS
7960 */
7961 cpu_ctrl0_saved = vmcs_read(CPU_EXEC_CTRL0);
7962 cpu_ctrl1_saved = vmcs_read(CPU_EXEC_CTRL1);
7963 ar_saved = vmcs_read(GUEST_AR_SS);
7964 /* Turn off "unrestricted guest" vm-execution control */
7965 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved & ~CPU_URG);
7966 cs_rpl_bits = vmcs_read(GUEST_SEL_CS) & 0x3;
7967 sel_saved = vmcs_read(GUEST_SEL_SS);
7968 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3)));
7969 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3)));
7970 /* Make SS usable if it's unusable or vice-versa */
7971 if (ar_saved & GUEST_SEG_UNUSABLE_MASK)
7972 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK);
7973 else
7974 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK);
7975 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3)));
7976 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3)));
7977
7978 /* Need a valid EPTP as the passing case fully enters the guest. */
7979 if (enable_unrestricted_guest(true))
7980 goto skip_ss_tests;
7981
7982 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3)));
7983 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3)));
7984
7985 /* Make SS usable if it's unusable or vice-versa */
7986 if (vmcs_read(GUEST_AR_SS) & GUEST_SEG_UNUSABLE_MASK)
7987 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK);
7988 else
7989 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK);
7990 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3)));
7991 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3)));
7992 skip_ss_tests:
7993
7994 vmcs_write(GUEST_AR_SS, ar_saved);
7995 vmcs_write(GUEST_SEL_SS, sel_saved);
7996 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrl0_saved);
7997 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved);
7998 }
7999
8000 #define TEST_SEGMENT_BASE_ADDR_UPPER_BITS(xfail, seg_base) \
8001 do { \
8002 addr_saved = vmcs_read(seg_base); \
8003 for (i = 32; i < 63; i = i + 4) { \
8004 addr = addr_saved | 1ull << i; \
8005 vmcs_write(seg_base, addr); \
8006 test_guest_state("seg.BASE[63:32] != 0, usable = " xstr(xfail), \
8007 xfail, addr, xstr(seg_base)); \
8008 } \
8009 vmcs_write(seg_base, addr_saved); \
8010 } while (0)
8011
8012 #define TEST_SEGMENT_BASE_ADDR_CANONICAL(xfail, seg_base) \
8013 do { \
8014 addr_saved = vmcs_read(seg_base); \
8015 vmcs_write(seg_base, NONCANONICAL); \
8016 test_guest_state("seg.BASE non-canonical, usable = " xstr(xfail), \
8017 xfail, NONCANONICAL, xstr(seg_base)); \
8018 vmcs_write(seg_base, addr_saved); \
8019 } while (0)
8020
8021 /*
8022 * The following checks are done on the Base Address field of the Guest
8023 * Segment Registers on processors that support Intel 64 architecture:
8024 * - TR, FS, GS : The address must be canonical.
8025 * - LDTR : If LDTR is usable, the address must be canonical.
8026 * - CS : Bits 63:32 of the address must be zero.
8027 * - SS, DS, ES : If the register is usable, bits 63:32 of the address
8028 * must be zero.
8029 *
8030 * [Intel SDM]
8031 */
test_guest_segment_base_addr_fields(void)8032 static void test_guest_segment_base_addr_fields(void)
8033 {
8034 u64 addr_saved;
8035 u64 addr;
8036 u32 ar_saved;
8037 int i;
8038
8039 /*
8040 * The address of TR, FS, GS and LDTR must be canonical.
8041 */
8042 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_TR);
8043 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_FS);
8044 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_GS);
8045 ar_saved = vmcs_read(GUEST_AR_LDTR);
8046 /* Make LDTR unusable */
8047 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK);
8048 TEST_SEGMENT_BASE_ADDR_CANONICAL(false, GUEST_BASE_LDTR);
8049 /* Make LDTR usable */
8050 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK);
8051 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_LDTR);
8052
8053 vmcs_write(GUEST_AR_LDTR, ar_saved);
8054
8055 /*
8056 * Bits 63:32 in CS, SS, DS and ES base address must be zero
8057 */
8058 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_CS);
8059 ar_saved = vmcs_read(GUEST_AR_SS);
8060 /* Make SS unusable */
8061 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK);
8062 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_SS);
8063 /* Make SS usable */
8064 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK);
8065 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_SS);
8066 vmcs_write(GUEST_AR_SS, ar_saved);
8067
8068 ar_saved = vmcs_read(GUEST_AR_DS);
8069 /* Make DS unusable */
8070 vmcs_write(GUEST_AR_DS, ar_saved | GUEST_SEG_UNUSABLE_MASK);
8071 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_DS);
8072 /* Make DS usable */
8073 vmcs_write(GUEST_AR_DS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK);
8074 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_DS);
8075 vmcs_write(GUEST_AR_DS, ar_saved);
8076
8077 ar_saved = vmcs_read(GUEST_AR_ES);
8078 /* Make ES unusable */
8079 vmcs_write(GUEST_AR_ES, ar_saved | GUEST_SEG_UNUSABLE_MASK);
8080 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_ES);
8081 /* Make ES usable */
8082 vmcs_write(GUEST_AR_ES, ar_saved & ~GUEST_SEG_UNUSABLE_MASK);
8083 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_ES);
8084 vmcs_write(GUEST_AR_ES, ar_saved);
8085 }
8086
8087 /*
8088 * Check that the virtual CPU checks the VMX Guest State Area as
8089 * documented in the Intel SDM.
8090 */
vmx_guest_state_area_test(void)8091 static void vmx_guest_state_area_test(void)
8092 {
8093 vmx_set_test_stage(1);
8094 test_set_guest(guest_state_test_main);
8095
8096 /*
8097 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field
8098 * must each contain a canonical address.
8099 */
8100 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false);
8101 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false);
8102
8103 test_guest_dr7();
8104 test_load_guest_pat();
8105 test_guest_efer();
8106 test_load_guest_perf_global_ctrl();
8107 test_load_guest_bndcfgs();
8108
8109 test_guest_segment_sel_fields();
8110 test_guest_segment_base_addr_fields();
8111
8112 test_canonical(GUEST_BASE_GDTR, "GUEST_BASE_GDTR", false);
8113 test_canonical(GUEST_BASE_IDTR, "GUEST_BASE_IDTR", false);
8114
8115 u32 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_GDTR);
8116 int i;
8117 for (i = 16; i <= 31; i++) {
8118 u32 tmp = guest_desc_limit_saved | (1ull << i);
8119 vmcs_write(GUEST_LIMIT_GDTR, tmp);
8120 test_guest_state("GDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_GDTR");
8121 }
8122 vmcs_write(GUEST_LIMIT_GDTR, guest_desc_limit_saved);
8123
8124 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_IDTR);
8125 for (i = 16; i <= 31; i++) {
8126 u32 tmp = guest_desc_limit_saved | (1ull << i);
8127 vmcs_write(GUEST_LIMIT_IDTR, tmp);
8128 test_guest_state("IDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_IDTR");
8129 }
8130 vmcs_write(GUEST_LIMIT_IDTR, guest_desc_limit_saved);
8131
8132 /*
8133 * Let the guest finish execution
8134 */
8135 vmx_set_test_stage(2);
8136 enter_guest();
8137 }
8138
8139 extern void unrestricted_guest_main(void);
8140 asm (".code32\n"
8141 "unrestricted_guest_main:\n"
8142 "vmcall\n"
8143 "nop\n"
8144 "mov $1, %edi\n"
8145 "call hypercall\n"
8146 ".code64\n");
8147
setup_unrestricted_guest(void)8148 static void setup_unrestricted_guest(void)
8149 {
8150 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) & ~(X86_CR0_PG));
8151 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) & ~ENT_GUEST_64);
8152 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) & ~EFER_LMA);
8153 vmcs_write(GUEST_RIP, virt_to_phys(unrestricted_guest_main));
8154 }
8155
unsetup_unrestricted_guest(void)8156 static void unsetup_unrestricted_guest(void)
8157 {
8158 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) | X86_CR0_PG);
8159 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_GUEST_64);
8160 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) | EFER_LMA);
8161 vmcs_write(GUEST_RIP, (u64) phys_to_virt(vmcs_read(GUEST_RIP)));
8162 vmcs_write(GUEST_RSP, (u64) phys_to_virt(vmcs_read(GUEST_RSP)));
8163 }
8164
8165 /*
8166 * If "unrestricted guest" secondary VM-execution control is set, guests
8167 * can run in unpaged protected mode.
8168 */
vmentry_unrestricted_guest_test(void)8169 static void vmentry_unrestricted_guest_test(void)
8170 {
8171 if (enable_unrestricted_guest(true)) {
8172 report_skip("%s: \"Unrestricted guest\" exec control not supported", __func__);
8173 return;
8174 }
8175
8176 test_set_guest(unrestricted_guest_main);
8177 setup_unrestricted_guest();
8178 test_guest_state("Unrestricted guest test", false, CPU_URG, "CPU_URG");
8179
8180 /*
8181 * Let the guest finish execution as a regular guest
8182 */
8183 unsetup_unrestricted_guest();
8184 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) & ~CPU_URG);
8185 enter_guest();
8186 }
8187
valid_vmcs_for_vmentry(void)8188 static bool valid_vmcs_for_vmentry(void)
8189 {
8190 struct vmcs *current_vmcs = NULL;
8191
8192 if (vmcs_save(¤t_vmcs))
8193 return false;
8194
8195 return current_vmcs && !current_vmcs->hdr.shadow_vmcs;
8196 }
8197
try_vmentry_in_movss_shadow(void)8198 static void try_vmentry_in_movss_shadow(void)
8199 {
8200 u32 vm_inst_err;
8201 u32 flags;
8202 bool early_failure = false;
8203 u32 expected_flags = X86_EFLAGS_FIXED;
8204 bool valid_vmcs = valid_vmcs_for_vmentry();
8205
8206 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF;
8207
8208 /*
8209 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to
8210 * unsupported VMCS component").
8211 */
8212 vmcs_write(~0u, 0);
8213
8214 __asm__ __volatile__ ("mov %[host_rsp], %%edx;"
8215 "vmwrite %%rsp, %%rdx;"
8216 "mov 0f, %%rax;"
8217 "mov %[host_rip], %%edx;"
8218 "vmwrite %%rax, %%rdx;"
8219 "mov $-1, %%ah;"
8220 "sahf;"
8221 "mov %%ss, %%ax;"
8222 "mov %%ax, %%ss;"
8223 "vmlaunch;"
8224 "mov $1, %[early_failure];"
8225 "0: lahf;"
8226 "movzbl %%ah, %[flags]"
8227 : [early_failure] "+r" (early_failure),
8228 [flags] "=&a" (flags)
8229 : [host_rsp] "i" (HOST_RSP),
8230 [host_rip] "i" (HOST_RIP)
8231 : "rdx", "cc", "memory");
8232 vm_inst_err = vmcs_read(VMX_INST_ERROR);
8233
8234 report(early_failure, "Early VM-entry failure");
8235 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)",
8236 expected_flags, flags);
8237 if (valid_vmcs)
8238 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS,
8239 "VM-instruction error is %d (actual %d)",
8240 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err);
8241 }
8242
vmentry_movss_shadow_test(void)8243 static void vmentry_movss_shadow_test(void)
8244 {
8245 struct vmcs *orig_vmcs;
8246
8247 TEST_ASSERT(!vmcs_save(&orig_vmcs));
8248
8249 /*
8250 * Set the launched flag on the current VMCS to verify the correct
8251 * error priority, below.
8252 */
8253 test_set_guest(v2_null_test_guest);
8254 enter_guest();
8255
8256 /*
8257 * With bit 1 of the guest's RFLAGS clear, VM-entry should
8258 * fail due to invalid guest state (if we make it that far).
8259 */
8260 vmcs_write(GUEST_RFLAGS, 0);
8261
8262 /*
8263 * "VM entry with events blocked by MOV SS" takes precedence over
8264 * "VMLAUNCH with non-clear VMCS."
8265 */
8266 report_prefix_push("valid current-VMCS");
8267 try_vmentry_in_movss_shadow();
8268 report_prefix_pop();
8269
8270 /*
8271 * VMfailInvalid takes precedence over "VM entry with events
8272 * blocked by MOV SS."
8273 */
8274 TEST_ASSERT(!vmcs_clear(orig_vmcs));
8275 report_prefix_push("no current-VMCS");
8276 try_vmentry_in_movss_shadow();
8277 report_prefix_pop();
8278
8279 TEST_ASSERT(!make_vmcs_current(orig_vmcs));
8280 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED);
8281 }
8282
vmx_ldtr_test_guest(void)8283 static void vmx_ldtr_test_guest(void)
8284 {
8285 u16 ldtr = sldt();
8286
8287 report(ldtr == NP_SEL, "Expected %x for L2 LDTR selector (got %x)",
8288 NP_SEL, ldtr);
8289 }
8290
8291 /*
8292 * Ensure that the L1 LDTR is set to 0 on VM-exit.
8293 */
vmx_ldtr_test(void)8294 static void vmx_ldtr_test(void)
8295 {
8296 const u8 ldt_ar = 0x82; /* Present LDT */
8297 u16 sel = FIRST_SPARE_SEL;
8298
8299 /* Set up a non-zero L1 LDTR prior to VM-entry. */
8300 set_gdt_entry(sel, 0, 0, ldt_ar, 0);
8301 lldt(sel);
8302
8303 test_set_guest(vmx_ldtr_test_guest);
8304 /*
8305 * Set up a different LDTR for L2. The actual GDT contents are
8306 * irrelevant, since we stuff the hidden descriptor state
8307 * straight into the VMCS rather than reading it from the GDT.
8308 */
8309 vmcs_write(GUEST_SEL_LDTR, NP_SEL);
8310 vmcs_write(GUEST_AR_LDTR, ldt_ar);
8311 enter_guest();
8312
8313 /*
8314 * VM-exit should clear LDTR (and make it unusable, but we
8315 * won't verify that here).
8316 */
8317 sel = sldt();
8318 report(!sel, "Expected 0 for L1 LDTR selector (got %x)", sel);
8319 }
8320
vmx_single_vmcall_guest(void)8321 static void vmx_single_vmcall_guest(void)
8322 {
8323 vmcall();
8324 }
8325
vmx_cr_load_test(void)8326 static void vmx_cr_load_test(void)
8327 {
8328 unsigned long cr3, cr4, orig_cr3, orig_cr4;
8329 u32 ctrls[2] = {0};
8330 pgd_t *pml5;
8331
8332 orig_cr4 = read_cr4();
8333 orig_cr3 = read_cr3();
8334
8335 if (!this_cpu_has(X86_FEATURE_PCID)) {
8336 report_skip("%s : PCID not detected", __func__);
8337 return;
8338 }
8339 if (!this_cpu_has(X86_FEATURE_MCE)) {
8340 report_skip("%s : MCE not detected", __func__);
8341 return;
8342 }
8343
8344 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK));
8345
8346 /* Enable PCID for L1. */
8347 cr4 = orig_cr4 | X86_CR4_PCIDE;
8348 cr3 = orig_cr3 | 0x1;
8349 TEST_ASSERT(!write_cr4_safe(cr4));
8350 write_cr3(cr3);
8351
8352 test_set_guest(vmx_single_vmcall_guest);
8353 vmcs_write(HOST_CR4, cr4);
8354 vmcs_write(HOST_CR3, cr3);
8355 enter_guest();
8356
8357 /*
8358 * No exception is expected.
8359 *
8360 * NB. KVM loads the last guest write to CR4 into CR4 read
8361 * shadow. In order to trigger an exit to KVM, we can toggle a
8362 * bit that is owned by KVM. We use CR4.MCE, which shall
8363 * have no side effect because normally no guest MCE (e.g., as the
8364 * result of bad memory) would happen during this test.
8365 */
8366 TEST_ASSERT(!write_cr4_safe(cr4 ^ X86_CR4_MCE));
8367
8368 /* Cleanup L1 state. */
8369 write_cr3(orig_cr3);
8370 TEST_ASSERT(!write_cr4_safe(orig_cr4));
8371
8372 if (!this_cpu_has(X86_FEATURE_LA57))
8373 goto done;
8374
8375 /*
8376 * Allocate a full page for PML5 to guarantee alignment, though only
8377 * the first entry needs to be filled (the test's virtual addresses
8378 * most definitely do not have any of bits 56:48 set).
8379 */
8380 pml5 = alloc_page();
8381 *pml5 = orig_cr3 | PT_PRESENT_MASK | PT_WRITABLE_MASK;
8382
8383 /*
8384 * Transition to/from 5-level paging in the host via VM-Exit. CR4.LA57
8385 * can't be toggled while long is active via MOV CR4, but there are no
8386 * such restrictions on VM-Exit.
8387 */
8388 lol_5level:
8389 vmcs_write(HOST_CR4, orig_cr4 | X86_CR4_LA57);
8390 vmcs_write(HOST_CR3, virt_to_phys(pml5));
8391 enter_guest();
8392
8393 /*
8394 * VMREAD with a memory operand to verify KVM detects the LA57 change,
8395 * e.g. uses the correct guest root level in gva_to_gpa().
8396 */
8397 TEST_ASSERT(vmcs_readm(HOST_CR3) == virt_to_phys(pml5));
8398 TEST_ASSERT(vmcs_readm(HOST_CR4) == (orig_cr4 | X86_CR4_LA57));
8399
8400 vmcs_write(HOST_CR4, orig_cr4);
8401 vmcs_write(HOST_CR3, orig_cr3);
8402 enter_guest();
8403
8404 TEST_ASSERT(vmcs_readm(HOST_CR3) == orig_cr3);
8405 TEST_ASSERT(vmcs_readm(HOST_CR4) == orig_cr4);
8406
8407 /*
8408 * And now do the same LA57 shenanigans with EPT enabled. KVM uses
8409 * two separate MMUs when L1 uses TDP, whereas the above shadow paging
8410 * version shares an MMU between L1 and L2.
8411 *
8412 * If the saved execution controls are non-zero then the EPT version
8413 * has already run. In that case, restore the old controls. If EPT
8414 * setup fails, e.g. EPT isn't supported, fall through and finish up.
8415 */
8416 if (ctrls[0]) {
8417 vmcs_write(CPU_EXEC_CTRL0, ctrls[0]);
8418 vmcs_write(CPU_EXEC_CTRL1, ctrls[1]);
8419 } else if (!setup_ept(false)) {
8420 ctrls[0] = vmcs_read(CPU_EXEC_CTRL0);
8421 ctrls[1] = vmcs_read(CPU_EXEC_CTRL1);
8422 goto lol_5level;
8423 }
8424
8425 free_page(pml5);
8426
8427 done:
8428 skip_exit_vmcall();
8429 enter_guest();
8430 }
8431
vmx_cr4_osxsave_test_guest(void)8432 static void vmx_cr4_osxsave_test_guest(void)
8433 {
8434 write_cr4(read_cr4() & ~X86_CR4_OSXSAVE);
8435 }
8436
8437 /*
8438 * Ensure that kvm recalculates the L1 guest's CPUID.01H:ECX.OSXSAVE
8439 * after VM-exit from an L2 guest that sets CR4.OSXSAVE to a different
8440 * value than in L1.
8441 */
vmx_cr4_osxsave_test(void)8442 static void vmx_cr4_osxsave_test(void)
8443 {
8444 if (!this_cpu_has(X86_FEATURE_XSAVE)) {
8445 report_skip("%s : XSAVE not detected", __func__);
8446 return;
8447 }
8448
8449 if (!(read_cr4() & X86_CR4_OSXSAVE)) {
8450 unsigned long cr4 = read_cr4() | X86_CR4_OSXSAVE;
8451
8452 write_cr4(cr4);
8453 vmcs_write(GUEST_CR4, cr4);
8454 vmcs_write(HOST_CR4, cr4);
8455 }
8456
8457 TEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE));
8458
8459 test_set_guest(vmx_cr4_osxsave_test_guest);
8460 enter_guest();
8461
8462 TEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE));
8463 }
8464
8465 /*
8466 * FNOP with both CR0.TS and CR0.EM clear should not generate #NM, and the L2
8467 * guest should exit normally.
8468 */
vmx_no_nm_test(void)8469 static void vmx_no_nm_test(void)
8470 {
8471 test_set_guest(fnop);
8472 vmcs_write(GUEST_CR0, read_cr0() & ~(X86_CR0_TS | X86_CR0_EM));
8473 enter_guest();
8474 }
8475
8476 bool vmx_pending_event_ipi_fired;
vmx_pending_event_ipi_isr(isr_regs_t * regs)8477 static void vmx_pending_event_ipi_isr(isr_regs_t *regs)
8478 {
8479 vmx_pending_event_ipi_fired = true;
8480 eoi();
8481 }
8482
8483 bool vmx_pending_event_guest_run;
vmx_pending_event_guest(void)8484 static void vmx_pending_event_guest(void)
8485 {
8486 vmcall();
8487 vmx_pending_event_guest_run = true;
8488 }
8489
vmx_pending_event_test_core(bool guest_hlt)8490 static void vmx_pending_event_test_core(bool guest_hlt)
8491 {
8492 int ipi_vector = 0xf1;
8493
8494 vmx_pending_event_ipi_fired = false;
8495 handle_irq(ipi_vector, vmx_pending_event_ipi_isr);
8496
8497 vmx_pending_event_guest_run = false;
8498 test_set_guest(vmx_pending_event_guest);
8499
8500 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT);
8501
8502 enter_guest();
8503 skip_exit_vmcall();
8504
8505 if (guest_hlt)
8506 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT);
8507
8508 cli();
8509 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL |
8510 APIC_DM_FIXED | ipi_vector,
8511 0);
8512
8513 enter_guest();
8514
8515 assert_exit_reason(VMX_EXTINT);
8516 report(!vmx_pending_event_guest_run,
8517 "Guest did not run before host received IPI");
8518
8519 sti_nop_cli();
8520 report(vmx_pending_event_ipi_fired,
8521 "Got pending interrupt after IRQ enabled");
8522
8523 if (guest_hlt)
8524 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE);
8525
8526 enter_guest();
8527 report(vmx_pending_event_guest_run,
8528 "Guest finished running when no interrupt");
8529 }
8530
vmx_pending_event_test(void)8531 static void vmx_pending_event_test(void)
8532 {
8533 vmx_pending_event_test_core(false);
8534 }
8535
vmx_pending_event_hlt_test(void)8536 static void vmx_pending_event_hlt_test(void)
8537 {
8538 vmx_pending_event_test_core(true);
8539 }
8540
8541 static int vmx_window_test_db_count;
8542
vmx_window_test_db_handler(struct ex_regs * regs)8543 static void vmx_window_test_db_handler(struct ex_regs *regs)
8544 {
8545 vmx_window_test_db_count++;
8546 }
8547
vmx_nmi_window_test_guest(void)8548 static void vmx_nmi_window_test_guest(void)
8549 {
8550 handle_exception(DB_VECTOR, vmx_window_test_db_handler);
8551
8552 asm volatile("vmcall\n\t"
8553 "nop\n\t");
8554
8555 handle_exception(DB_VECTOR, NULL);
8556 }
8557
verify_nmi_window_exit(u64 rip)8558 static void verify_nmi_window_exit(u64 rip)
8559 {
8560 u32 exit_reason = vmcs_read(EXI_REASON);
8561
8562 report(exit_reason == VMX_NMI_WINDOW,
8563 "Exit reason (%d) is 'NMI window'", exit_reason);
8564 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx",
8565 vmcs_read(GUEST_RIP), rip);
8566 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE);
8567 }
8568
vmx_nmi_window_test(void)8569 static void vmx_nmi_window_test(void)
8570 {
8571 u64 nop_addr;
8572 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]);
8573
8574 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) {
8575 report_skip("%s : \"Virtual NMIs\" exec control not supported", __func__);
8576 return;
8577 }
8578
8579 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) {
8580 report_skip("%s : \"NMI-window exiting\" exec control not supported", __func__);
8581 return;
8582 }
8583
8584 vmx_window_test_db_count = 0;
8585
8586 report_prefix_push("NMI-window");
8587 test_set_guest(vmx_nmi_window_test_guest);
8588 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI);
8589 enter_guest();
8590 skip_exit_vmcall();
8591 nop_addr = vmcs_read(GUEST_RIP);
8592
8593 /*
8594 * Ask for "NMI-window exiting," and expect an immediate VM-exit.
8595 * RIP will not advance.
8596 */
8597 report_prefix_push("active, no blocking");
8598 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW);
8599 enter_guest();
8600 verify_nmi_window_exit(nop_addr);
8601 report_prefix_pop();
8602
8603 /*
8604 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect
8605 * a VM-exit on the next instruction after the nop. (The nop
8606 * is one byte.)
8607 */
8608 report_prefix_push("active, blocking by MOV-SS");
8609 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS);
8610 enter_guest();
8611 verify_nmi_window_exit(nop_addr + 1);
8612 report_prefix_pop();
8613
8614 /*
8615 * Ask for "NMI-window exiting" (with event injection), and
8616 * expect a VM-exit after the event is injected. (RIP should
8617 * be at the address specified in the IDT entry for #DB.)
8618 */
8619 report_prefix_push("active, no blocking, injecting #DB");
8620 vmcs_write(ENT_INTR_INFO,
8621 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR);
8622 enter_guest();
8623 verify_nmi_window_exit((u64)db_fault_addr);
8624 report_prefix_pop();
8625
8626 /*
8627 * Ask for "NMI-window exiting" with NMI blocking, and expect
8628 * a VM-exit after the next IRET (i.e. after the #DB handler
8629 * returns). So, RIP should be back at one byte past the nop.
8630 */
8631 report_prefix_push("active, blocking by NMI");
8632 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI);
8633 enter_guest();
8634 verify_nmi_window_exit(nop_addr + 1);
8635 report(vmx_window_test_db_count == 1,
8636 "#DB handler executed once (actual %d times)",
8637 vmx_window_test_db_count);
8638 report_prefix_pop();
8639
8640 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) {
8641 report_skip("CPU does not support activity state HLT.");
8642 } else {
8643 /*
8644 * Ask for "NMI-window exiting" when entering activity
8645 * state HLT, and expect an immediate VM-exit. RIP is
8646 * still one byte past the nop.
8647 */
8648 report_prefix_push("halted, no blocking");
8649 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT);
8650 enter_guest();
8651 verify_nmi_window_exit(nop_addr + 1);
8652 report_prefix_pop();
8653
8654 /*
8655 * Ask for "NMI-window exiting" when entering activity
8656 * state HLT (with event injection), and expect a
8657 * VM-exit after the event is injected. (RIP should be
8658 * at the address specified in the IDT entry for #DB.)
8659 */
8660 report_prefix_push("halted, no blocking, injecting #DB");
8661 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT);
8662 vmcs_write(ENT_INTR_INFO,
8663 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION |
8664 DB_VECTOR);
8665 enter_guest();
8666 verify_nmi_window_exit((u64)db_fault_addr);
8667 report_prefix_pop();
8668 }
8669
8670 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW);
8671 enter_guest();
8672 report_prefix_pop();
8673 }
8674
vmx_intr_window_test_guest(void)8675 static void vmx_intr_window_test_guest(void)
8676 {
8677 handle_exception(DB_VECTOR, vmx_window_test_db_handler);
8678
8679 /*
8680 * The two consecutive STIs are to ensure that only the first
8681 * one has a shadow. Note that NOP and STI are one byte
8682 * instructions.
8683 */
8684 asm volatile("vmcall\n\t"
8685 "nop\n\t"
8686 "sti\n\t"
8687 "sti\n\t");
8688
8689 handle_exception(DB_VECTOR, NULL);
8690 }
8691
verify_intr_window_exit(u64 rip)8692 static void verify_intr_window_exit(u64 rip)
8693 {
8694 u32 exit_reason = vmcs_read(EXI_REASON);
8695
8696 report(exit_reason == VMX_INTR_WINDOW,
8697 "Exit reason (%d) is 'interrupt window'", exit_reason);
8698 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx",
8699 vmcs_read(GUEST_RIP), rip);
8700 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE);
8701 }
8702
vmx_intr_window_test(void)8703 static void vmx_intr_window_test(void)
8704 {
8705 u64 vmcall_addr;
8706 u64 nop_addr;
8707 unsigned int orig_db_gate_type;
8708 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]);
8709
8710 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) {
8711 report_skip("%s : \"Interrupt-window exiting\" exec control not supported", __func__);
8712 return;
8713 }
8714
8715 /*
8716 * Change the IDT entry for #DB from interrupt gate to trap gate,
8717 * so that it won't clear RFLAGS.IF. We don't want interrupts to
8718 * be disabled after vectoring a #DB.
8719 */
8720 orig_db_gate_type = boot_idt[DB_VECTOR].type;
8721 boot_idt[DB_VECTOR].type = 15;
8722
8723 report_prefix_push("interrupt-window");
8724 test_set_guest(vmx_intr_window_test_guest);
8725 enter_guest();
8726 assert_exit_reason(VMX_VMCALL);
8727 vmcall_addr = vmcs_read(GUEST_RIP);
8728
8729 /*
8730 * Ask for "interrupt-window exiting" with RFLAGS.IF set and
8731 * no blocking; expect an immediate VM-exit. Note that we have
8732 * not advanced past the vmcall instruction yet, so RIP should
8733 * point to the vmcall instruction.
8734 */
8735 report_prefix_push("active, no blocking, RFLAGS.IF=1");
8736 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW);
8737 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF);
8738 enter_guest();
8739 verify_intr_window_exit(vmcall_addr);
8740 report_prefix_pop();
8741
8742 /*
8743 * Ask for "interrupt-window exiting" (with event injection)
8744 * with RFLAGS.IF set and no blocking; expect a VM-exit after
8745 * the event is injected. That is, RIP should should be at the
8746 * address specified in the IDT entry for #DB.
8747 */
8748 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB");
8749 vmcs_write(ENT_INTR_INFO,
8750 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR);
8751 vmcall_addr = vmcs_read(GUEST_RIP);
8752 enter_guest();
8753 verify_intr_window_exit((u64)db_fault_addr);
8754 report_prefix_pop();
8755
8756 /*
8757 * Let the L2 guest run through the IRET, back to the VMCALL.
8758 * We have to clear the "interrupt-window exiting"
8759 * VM-execution control, or it would just keep causing
8760 * VM-exits. Then, advance past the VMCALL and set the
8761 * "interrupt-window exiting" VM-execution control again.
8762 */
8763 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW);
8764 enter_guest();
8765 skip_exit_vmcall();
8766 nop_addr = vmcs_read(GUEST_RIP);
8767 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW);
8768
8769 /*
8770 * Ask for "interrupt-window exiting" in a MOV-SS shadow with
8771 * RFLAGS.IF set, and expect a VM-exit on the next
8772 * instruction. (NOP is one byte.)
8773 */
8774 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1");
8775 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS);
8776 enter_guest();
8777 verify_intr_window_exit(nop_addr + 1);
8778 report_prefix_pop();
8779
8780 /*
8781 * Back up to the NOP and ask for "interrupt-window exiting"
8782 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit
8783 * on the next instruction. (NOP is one byte.)
8784 */
8785 report_prefix_push("active, blocking by STI, RFLAGS.IF=1");
8786 vmcs_write(GUEST_RIP, nop_addr);
8787 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI);
8788 enter_guest();
8789 verify_intr_window_exit(nop_addr + 1);
8790 report_prefix_pop();
8791
8792 /*
8793 * Ask for "interrupt-window exiting" with RFLAGS.IF clear,
8794 * and expect a VM-exit on the instruction following the STI
8795 * shadow. Only the first STI (which is one byte past the NOP)
8796 * should have a shadow. The second STI (which is two bytes
8797 * past the NOP) has no shadow. Therefore, the interrupt
8798 * window opens at three bytes past the NOP.
8799 */
8800 report_prefix_push("active, RFLAGS.IF = 0");
8801 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED);
8802 enter_guest();
8803 verify_intr_window_exit(nop_addr + 3);
8804 report_prefix_pop();
8805
8806 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) {
8807 report_skip("CPU does not support activity state HLT.");
8808 } else {
8809 /*
8810 * Ask for "interrupt-window exiting" when entering
8811 * activity state HLT, and expect an immediate
8812 * VM-exit. RIP is still three bytes past the nop.
8813 */
8814 report_prefix_push("halted, no blocking");
8815 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT);
8816 enter_guest();
8817 verify_intr_window_exit(nop_addr + 3);
8818 report_prefix_pop();
8819
8820 /*
8821 * Ask for "interrupt-window exiting" when entering
8822 * activity state HLT (with event injection), and
8823 * expect a VM-exit after the event is injected. That
8824 * is, RIP should should be at the address specified
8825 * in the IDT entry for #DB.
8826 */
8827 report_prefix_push("halted, no blocking, injecting #DB");
8828 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT);
8829 vmcs_write(ENT_INTR_INFO,
8830 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION |
8831 DB_VECTOR);
8832 enter_guest();
8833 verify_intr_window_exit((u64)db_fault_addr);
8834 report_prefix_pop();
8835 }
8836
8837 boot_idt[DB_VECTOR].type = orig_db_gate_type;
8838 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW);
8839 enter_guest();
8840 report_prefix_pop();
8841 }
8842
8843 #define GUEST_TSC_OFFSET (1u << 30)
8844
8845 static u64 guest_tsc;
8846
vmx_store_tsc_test_guest(void)8847 static void vmx_store_tsc_test_guest(void)
8848 {
8849 guest_tsc = rdtsc();
8850 }
8851
8852 /*
8853 * This test ensures that when IA32_TSC is in the VM-exit MSR-store
8854 * list, the value saved is not subject to the TSC offset that is
8855 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution.
8856 */
vmx_store_tsc_test(void)8857 static void vmx_store_tsc_test(void)
8858 {
8859 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC };
8860 u64 low, high;
8861
8862 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) {
8863 report_skip("%s : \"Use TSC offsetting\" exec control not supported", __func__);
8864 return;
8865 }
8866
8867 test_set_guest(vmx_store_tsc_test_guest);
8868
8869 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET);
8870 vmcs_write(EXI_MSR_ST_CNT, 1);
8871 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry));
8872 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET);
8873
8874 low = rdtsc();
8875 enter_guest();
8876 high = rdtsc();
8877
8878 report(low + GUEST_TSC_OFFSET <= guest_tsc &&
8879 guest_tsc <= high + GUEST_TSC_OFFSET,
8880 "RDTSC value in the guest (%lu) is in range [%lu, %lu]",
8881 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET);
8882 report(low <= msr_entry.value && msr_entry.value <= high,
8883 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]",
8884 msr_entry.value, low, high);
8885 }
8886
vmx_preemption_timer_zero_test_db_handler(struct ex_regs * regs)8887 static void vmx_preemption_timer_zero_test_db_handler(struct ex_regs *regs)
8888 {
8889 }
8890
vmx_preemption_timer_zero_test_guest(void)8891 static void vmx_preemption_timer_zero_test_guest(void)
8892 {
8893 while (vmx_get_test_stage() < 3)
8894 vmcall();
8895 }
8896
vmx_preemption_timer_zero_activate_preemption_timer(void)8897 static void vmx_preemption_timer_zero_activate_preemption_timer(void)
8898 {
8899 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT);
8900 vmcs_write(PREEMPT_TIMER_VALUE, 0);
8901 }
8902
vmx_preemption_timer_zero_advance_past_vmcall(void)8903 static void vmx_preemption_timer_zero_advance_past_vmcall(void)
8904 {
8905 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT);
8906 enter_guest();
8907 skip_exit_vmcall();
8908 }
8909
vmx_preemption_timer_zero_inject_db(bool intercept_db)8910 static void vmx_preemption_timer_zero_inject_db(bool intercept_db)
8911 {
8912 vmx_preemption_timer_zero_activate_preemption_timer();
8913 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK |
8914 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR);
8915 vmcs_write(EXC_BITMAP, intercept_db ? 1 << DB_VECTOR : 0);
8916 enter_guest();
8917 }
8918
vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap)8919 static void vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap)
8920 {
8921 vmx_preemption_timer_zero_activate_preemption_timer();
8922 vmcs_write(GUEST_PENDING_DEBUG, PENDING_DBG_TRAP | DR6_TRAP1);
8923 vmcs_write(EXC_BITMAP, exception_bitmap);
8924 enter_guest();
8925 }
8926
vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip)8927 static void vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip)
8928 {
8929 u32 reason = (u32)vmcs_read(EXI_REASON);
8930 u64 guest_rip = vmcs_read(GUEST_RIP);
8931
8932 report(reason == VMX_PREEMPT && guest_rip == expected_rip,
8933 "Exit reason is 0x%x (expected 0x%x) and guest RIP is %lx (0x%lx expected).",
8934 reason, VMX_PREEMPT, guest_rip, expected_rip);
8935 }
8936
8937 /*
8938 * This test ensures that when the VMX preemption timer is zero at
8939 * VM-entry, a VM-exit occurs after any event injection and after any
8940 * pending debug exceptions are raised, but before execution of any
8941 * guest instructions.
8942 */
vmx_preemption_timer_zero_test(void)8943 static void vmx_preemption_timer_zero_test(void)
8944 {
8945 u64 db_fault_address = (u64)get_idt_addr(&boot_idt[DB_VECTOR]);
8946 handler old_db;
8947 u32 reason;
8948
8949 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) {
8950 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__);
8951 return;
8952 }
8953
8954 /*
8955 * Install a custom #DB handler that doesn't abort.
8956 */
8957 old_db = handle_exception(DB_VECTOR,
8958 vmx_preemption_timer_zero_test_db_handler);
8959
8960 test_set_guest(vmx_preemption_timer_zero_test_guest);
8961
8962 /*
8963 * VMX-preemption timer should fire after event injection.
8964 */
8965 vmx_set_test_stage(0);
8966 vmx_preemption_timer_zero_inject_db(0);
8967 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address);
8968 vmx_preemption_timer_zero_advance_past_vmcall();
8969
8970 /*
8971 * VMX-preemption timer should fire after event injection.
8972 * Exception bitmap is irrelevant, since you can't intercept
8973 * an event that you injected.
8974 */
8975 vmx_set_test_stage(1);
8976 vmx_preemption_timer_zero_inject_db(true);
8977 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address);
8978 vmx_preemption_timer_zero_advance_past_vmcall();
8979
8980 /*
8981 * VMX-preemption timer should fire after pending debug exceptions
8982 * have delivered a #DB trap.
8983 */
8984 vmx_set_test_stage(2);
8985 vmx_preemption_timer_zero_set_pending_dbg(0);
8986 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address);
8987 vmx_preemption_timer_zero_advance_past_vmcall();
8988
8989 /*
8990 * VMX-preemption timer would fire after pending debug exceptions
8991 * have delivered a #DB trap, but in this case, the #DB trap is
8992 * intercepted.
8993 */
8994 vmx_set_test_stage(3);
8995 vmx_preemption_timer_zero_set_pending_dbg(1 << DB_VECTOR);
8996 reason = (u32)vmcs_read(EXI_REASON);
8997 report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)",
8998 reason, VMX_EXC_NMI);
8999
9000 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT);
9001 enter_guest();
9002
9003 handle_exception(DB_VECTOR, old_db);
9004 }
9005
9006 static u64 vmx_preemption_timer_tf_test_prev_rip;
9007
vmx_preemption_timer_tf_test_db_handler(struct ex_regs * regs)9008 static void vmx_preemption_timer_tf_test_db_handler(struct ex_regs *regs)
9009 {
9010 extern char vmx_preemption_timer_tf_test_endloop;
9011
9012 if (vmx_get_test_stage() == 2) {
9013 /*
9014 * Stage 2 means that we're done, one way or another.
9015 * Arrange for the iret to drop us out of the wbinvd
9016 * loop and stop single-stepping.
9017 */
9018 regs->rip = (u64)&vmx_preemption_timer_tf_test_endloop;
9019 regs->rflags &= ~X86_EFLAGS_TF;
9020 } else if (regs->rip == vmx_preemption_timer_tf_test_prev_rip) {
9021 /*
9022 * The RIP should alternate between the wbinvd and the
9023 * jmp instruction in the code below. If we ever see
9024 * the same instruction twice in a row, that means a
9025 * single-step trap has been dropped. Let the
9026 * hypervisor know about the failure by executing a
9027 * VMCALL.
9028 */
9029 vmcall();
9030 }
9031 vmx_preemption_timer_tf_test_prev_rip = regs->rip;
9032 }
9033
vmx_preemption_timer_tf_test_guest(void)9034 static void vmx_preemption_timer_tf_test_guest(void)
9035 {
9036 /*
9037 * The hypervisor doesn't intercept WBINVD, so the loop below
9038 * shouldn't be a problem--it's just two instructions
9039 * executing in VMX non-root mode. However, when the
9040 * hypervisor is running in a virtual environment, the parent
9041 * hypervisor might intercept WBINVD and emulate it. If the
9042 * parent hypervisor is broken, the single-step trap after the
9043 * WBINVD might be lost.
9044 */
9045 asm volatile("vmcall\n\t"
9046 "0: wbinvd\n\t"
9047 "1: jmp 0b\n\t"
9048 "vmx_preemption_timer_tf_test_endloop:");
9049 }
9050
9051 /*
9052 * Ensure that the delivery of a "VMX-preemption timer expired"
9053 * VM-exit doesn't disrupt single-stepping in the guest. Note that
9054 * passing this test doesn't ensure correctness, because the test will
9055 * only fail if the VMX-preemtion timer fires at the right time (or
9056 * the wrong time, as it were).
9057 */
vmx_preemption_timer_tf_test(void)9058 static void vmx_preemption_timer_tf_test(void)
9059 {
9060 handler old_db;
9061 u32 reason;
9062 int i;
9063
9064 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) {
9065 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__);
9066 return;
9067 }
9068
9069 old_db = handle_exception(DB_VECTOR,
9070 vmx_preemption_timer_tf_test_db_handler);
9071
9072 test_set_guest(vmx_preemption_timer_tf_test_guest);
9073
9074 enter_guest();
9075 skip_exit_vmcall();
9076
9077 vmx_set_test_stage(1);
9078 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT);
9079 vmcs_write(PREEMPT_TIMER_VALUE, 50000);
9080 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF);
9081
9082 /*
9083 * The only exit we should see is "VMX-preemption timer
9084 * expired." If we get a VMCALL exit, that means the #DB
9085 * handler has detected a missing single-step trap. It doesn't
9086 * matter where the guest RIP is when the VMX-preemption timer
9087 * expires (whether it's in the WBINVD loop or in the #DB
9088 * handler)--a single-step trap should never be discarded.
9089 */
9090 for (i = 0; i < 10000; i++) {
9091 enter_guest();
9092 reason = (u32)vmcs_read(EXI_REASON);
9093 if (reason == VMX_PREEMPT)
9094 continue;
9095 TEST_ASSERT(reason == VMX_VMCALL);
9096 skip_exit_insn();
9097 break;
9098 }
9099
9100 report(reason == VMX_PREEMPT, "No single-step traps skipped");
9101
9102 vmx_set_test_stage(2);
9103 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT);
9104 enter_guest();
9105
9106 handle_exception(DB_VECTOR, old_db);
9107 }
9108
9109 #define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000
9110
9111 static u64 vmx_preemption_timer_expiry_start;
9112 static u64 vmx_preemption_timer_expiry_finish;
9113
vmx_preemption_timer_expiry_test_guest(void)9114 static void vmx_preemption_timer_expiry_test_guest(void)
9115 {
9116 vmcall();
9117 vmx_preemption_timer_expiry_start = fenced_rdtsc();
9118
9119 while (vmx_get_test_stage() == 0)
9120 vmx_preemption_timer_expiry_finish = fenced_rdtsc();
9121 }
9122
9123 /*
9124 * Test that the VMX-preemption timer is not excessively delayed.
9125 *
9126 * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer
9127 * with the unsigned value in the VMX-preemption timer-value field,
9128 * and the VMX-preemption timer counts down by 1 every time bit X in
9129 * the TSC changes due to a TSC increment (where X is
9130 * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state
9131 * other than the wait-for-SIPI state, the logical processor
9132 * transitions to the C0 C-state and causes a VM-exit.
9133 *
9134 * The guest code above reads the starting TSC after VM-entry. At this
9135 * point, the VMX-preemption timer has already been activated. Next,
9136 * the guest code reads the current TSC in a loop, storing the value
9137 * read to memory.
9138 *
9139 * If the RDTSC in the loop reads a value past the VMX-preemption
9140 * timer deadline, then the VMX-preemption timer VM-exit must be
9141 * delivered before the next instruction retires. Even if a higher
9142 * priority SMI is delivered first, the VMX-preemption timer VM-exit
9143 * must be delivered before the next instruction retires. Hence, a TSC
9144 * value past the VMX-preemption timer deadline might be read, but it
9145 * cannot be stored. If a TSC value past the deadline *is* stored,
9146 * then the architectural specification has been violated.
9147 */
vmx_preemption_timer_expiry_test(void)9148 static void vmx_preemption_timer_expiry_test(void)
9149 {
9150 u32 preemption_timer_value;
9151 union vmx_misc misc;
9152 u64 tsc_deadline;
9153 u32 reason;
9154
9155 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) {
9156 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__);
9157 return;
9158 }
9159
9160 test_set_guest(vmx_preemption_timer_expiry_test_guest);
9161
9162 enter_guest();
9163 skip_exit_vmcall();
9164
9165 misc.val = rdmsr(MSR_IA32_VMX_MISC);
9166 preemption_timer_value =
9167 VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit;
9168
9169 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT);
9170 vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value);
9171 vmx_set_test_stage(0);
9172
9173 enter_guest();
9174 reason = (u32)vmcs_read(EXI_REASON);
9175 TEST_ASSERT(reason == VMX_PREEMPT);
9176
9177 tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) <<
9178 misc.pt_bit) + (preemption_timer_value << misc.pt_bit);
9179
9180 report(vmx_preemption_timer_expiry_finish < tsc_deadline,
9181 "Last stored guest TSC (%lu) < TSC deadline (%lu)",
9182 vmx_preemption_timer_expiry_finish, tsc_deadline);
9183
9184 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT);
9185 vmx_set_test_stage(1);
9186 enter_guest();
9187 }
9188
vmx_db_test_guest(void)9189 static void vmx_db_test_guest(void)
9190 {
9191 /*
9192 * For a hardware generated single-step #DB.
9193 */
9194 asm volatile("vmcall;"
9195 "nop;"
9196 ".Lpost_nop:");
9197 /*
9198 * ...in a MOVSS shadow, with pending debug exceptions.
9199 */
9200 asm volatile("vmcall;"
9201 "nop;"
9202 ".Lpost_movss_nop:");
9203 /*
9204 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and
9205 * emulates it in software.)
9206 */
9207 asm volatile("vmcall;"
9208 "wbinvd;"
9209 ".Lpost_wbinvd:");
9210 /*
9211 * ...in a MOVSS shadow, with pending debug exceptions.
9212 */
9213 asm volatile("vmcall;"
9214 "wbinvd;"
9215 ".Lpost_movss_wbinvd:");
9216 /*
9217 * For a hardware generated single-step #DB in a transactional region.
9218 */
9219 asm volatile("vmcall;"
9220 ".Lxbegin: xbegin .Lskip_rtm;"
9221 "xend;"
9222 ".Lskip_rtm:");
9223 }
9224
9225 /*
9226 * Clear the pending debug exceptions and RFLAGS.TF and re-enter
9227 * L2. No #DB is delivered and L2 continues to the next point of
9228 * interest.
9229 */
dismiss_db(void)9230 static void dismiss_db(void)
9231 {
9232 vmcs_write(GUEST_PENDING_DEBUG, 0);
9233 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED);
9234 enter_guest();
9235 }
9236
9237 /*
9238 * Check a variety of VMCS fields relevant to an intercepted #DB exception.
9239 * Then throw away the #DB exception and resume L2.
9240 */
check_db_exit(bool xfail_qual,bool xfail_dr6,bool xfail_pdbg,void * expected_rip,u64 expected_exit_qual,u64 expected_dr6)9241 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg,
9242 void *expected_rip, u64 expected_exit_qual,
9243 u64 expected_dr6)
9244 {
9245 u32 reason = vmcs_read(EXI_REASON);
9246 u32 intr_info = vmcs_read(EXI_INTR_INFO);
9247 u64 exit_qual = vmcs_read(EXI_QUALIFICATION);
9248 u64 guest_rip = vmcs_read(GUEST_RIP);
9249 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG);
9250 u64 dr6 = read_dr6();
9251 const u32 expected_intr_info = INTR_INFO_VALID_MASK |
9252 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR;
9253
9254 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info,
9255 "Expected #DB VM-exit");
9256 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)",
9257 expected_rip, guest_rip);
9258 report_xfail(xfail_pdbg, 0 == guest_pending_dbg,
9259 "Expected pending debug exceptions 0 (actual %lx)",
9260 guest_pending_dbg);
9261 report_xfail(xfail_qual, expected_exit_qual == exit_qual,
9262 "Expected exit qualification %lx (actual %lx)",
9263 expected_exit_qual, exit_qual);
9264 report_xfail(xfail_dr6, expected_dr6 == dr6,
9265 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6);
9266 dismiss_db();
9267 }
9268
9269 /*
9270 * Assuming the guest has just exited on a VMCALL instruction, skip
9271 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If
9272 * pending debug exceptions are non-zero, set the VMCS up as if the
9273 * previous instruction was a MOVSS that generated the indicated
9274 * pending debug exceptions. Then enter L2.
9275 */
single_step_guest(const char * test_name,u64 starting_dr6,u64 pending_debug_exceptions)9276 static void single_step_guest(const char *test_name, u64 starting_dr6,
9277 u64 pending_debug_exceptions)
9278 {
9279 printf("\n%s\n", test_name);
9280 skip_exit_vmcall();
9281 write_dr6(starting_dr6);
9282 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF);
9283 if (pending_debug_exceptions) {
9284 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions);
9285 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS);
9286 }
9287 enter_guest();
9288 }
9289
9290 /*
9291 * When L1 intercepts #DB, verify that a single-step trap clears
9292 * pending debug exceptions, populates the exit qualification field
9293 * properly, and that DR6 is not prematurely clobbered. In a
9294 * (simulated) MOVSS shadow, make sure that the pending debug
9295 * exception bits are properly accumulated into the exit qualification
9296 * field.
9297 */
vmx_db_test(void)9298 static void vmx_db_test(void)
9299 {
9300 /*
9301 * We are going to set a few arbitrary bits in DR6 to verify that
9302 * (a) DR6 is not modified by an intercepted #DB, and
9303 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into
9304 * the exit qualification field for a subsequent #DB exception.
9305 */
9306 const u64 starting_dr6 = DR6_ACTIVE_LOW | DR6_BS | DR6_TRAP3 | DR6_TRAP1;
9307 extern char post_nop asm(".Lpost_nop");
9308 extern char post_movss_nop asm(".Lpost_movss_nop");
9309 extern char post_wbinvd asm(".Lpost_wbinvd");
9310 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd");
9311 extern char xbegin asm(".Lxbegin");
9312 extern char skip_rtm asm(".Lskip_rtm");
9313
9314 /*
9315 * L1 wants to intercept #DB exceptions encountered in L2.
9316 */
9317 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR));
9318
9319 /*
9320 * Start L2 and run it up to the first point of interest.
9321 */
9322 test_set_guest(vmx_db_test_guest);
9323 enter_guest();
9324
9325 /*
9326 * Hardware-delivered #DB trap for single-step sets the
9327 * standard that L0 has to follow for emulated instructions.
9328 */
9329 single_step_guest("Hardware delivered single-step", starting_dr6, 0);
9330 check_db_exit(false, false, false, &post_nop, DR6_BS, starting_dr6);
9331
9332 /*
9333 * Hardware-delivered #DB trap for single-step in MOVSS shadow
9334 * also sets the standard that L0 has to follow for emulated
9335 * instructions. Here, we establish the VMCS pending debug
9336 * exceptions to indicate that the simulated MOVSS triggered a
9337 * data breakpoint as well as the single-step trap.
9338 */
9339 single_step_guest("Hardware delivered single-step in MOVSS shadow",
9340 starting_dr6, DR6_BS | PENDING_DBG_TRAP | DR6_TRAP0);
9341 check_db_exit(false, false, false, &post_movss_nop, DR6_BS | DR6_TRAP0,
9342 starting_dr6);
9343
9344 /*
9345 * L0 synthesized #DB trap for single-step is buggy, because
9346 * kvm (a) clobbers DR6 too early, and (b) tries its best to
9347 * reconstitute the exit qualification from the prematurely
9348 * modified DR6, but fails miserably.
9349 */
9350 single_step_guest("Software synthesized single-step", starting_dr6, 0);
9351 check_db_exit(false, false, false, &post_wbinvd, DR6_BS, starting_dr6);
9352
9353 /*
9354 * L0 synthesized #DB trap for single-step in MOVSS shadow is
9355 * even worse, because L0 also leaves the pending debug
9356 * exceptions in the VMCS instead of accumulating them into
9357 * the exit qualification field for the #DB exception.
9358 */
9359 single_step_guest("Software synthesized single-step in MOVSS shadow",
9360 starting_dr6, DR6_BS | PENDING_DBG_TRAP | DR6_TRAP0);
9361 check_db_exit(true, false, true, &post_movss_wbinvd, DR6_BS | DR6_TRAP0,
9362 starting_dr6);
9363
9364 /*
9365 * Optional RTM test for hardware that supports RTM, to
9366 * demonstrate that the current volume 3 of the SDM
9367 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit
9368 * qualification for debug exceptions is not reserved. It is
9369 * set to 1 if a debug exception (#DB) or a breakpoint
9370 * exception (#BP) occurs inside an RTM region while advanced
9371 * debugging of RTM transactional regions is enabled.
9372 */
9373 if (this_cpu_has(X86_FEATURE_RTM)) {
9374 vmcs_write(ENT_CONTROLS,
9375 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS);
9376 /*
9377 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15]
9378 * in the guest to enable advanced debugging of RTM
9379 * transactional regions.
9380 */
9381 vmcs_write(GUEST_DR7, BIT(11));
9382 vmcs_write(GUEST_DEBUGCTL, BIT(15));
9383 single_step_guest("Hardware delivered single-step in "
9384 "transactional region", starting_dr6, 0);
9385 check_db_exit(false, false, false, &xbegin, BIT(16),
9386 starting_dr6);
9387 } else {
9388 vmcs_write(GUEST_RIP, (u64)&skip_rtm);
9389 enter_guest();
9390 }
9391 }
9392
enable_vid(void)9393 static void enable_vid(void)
9394 {
9395 void *virtual_apic_page;
9396
9397 assert(cpu_has_apicv());
9398
9399 enable_x2apic();
9400 disable_intercept_for_x2apic_msrs();
9401
9402 virtual_apic_page = alloc_page();
9403 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page);
9404
9405 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT);
9406
9407 vmcs_write(EOI_EXIT_BITMAP0, 0x0);
9408 vmcs_write(EOI_EXIT_BITMAP1, 0x0);
9409 vmcs_write(EOI_EXIT_BITMAP2, 0x0);
9410 vmcs_write(EOI_EXIT_BITMAP3, 0x0);
9411
9412 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW);
9413 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC);
9414 }
9415
9416 #define PI_VECTOR 255
9417
enable_posted_interrupts(void)9418 static void enable_posted_interrupts(void)
9419 {
9420 void *pi_desc = alloc_page();
9421
9422 vmcs_set_bits(PIN_CONTROLS, PIN_POST_INTR);
9423 vmcs_set_bits(EXI_CONTROLS, EXI_INTA);
9424 vmcs_write(PINV, PI_VECTOR);
9425 vmcs_write(POSTED_INTR_DESC_ADDR, (u64)pi_desc);
9426 }
9427
trigger_ioapic_scan_thread(void * data)9428 static void trigger_ioapic_scan_thread(void *data)
9429 {
9430 /* Wait until other CPU entered L2 */
9431 while (vmx_get_test_stage() != 1)
9432 ;
9433
9434 /* Trigger ioapic scan */
9435 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL);
9436 vmx_set_test_stage(2);
9437 }
9438
irq_79_handler_guest(isr_regs_t * regs)9439 static void irq_79_handler_guest(isr_regs_t *regs)
9440 {
9441 eoi();
9442
9443 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */
9444 vmcall();
9445 }
9446
9447 /*
9448 * Constant for num of busy-loop iterations after which
9449 * a timer interrupt should have happened in host
9450 */
9451 #define TIMER_INTERRUPT_DELAY 100000000
9452
vmx_eoi_bitmap_ioapic_scan_test_guest(void)9453 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void)
9454 {
9455 handle_irq(0x79, irq_79_handler_guest);
9456 sti();
9457
9458 /* Signal to L1 CPU to trigger ioapic scan */
9459 vmx_set_test_stage(1);
9460 /* Wait until L1 CPU to trigger ioapic scan */
9461 while (vmx_get_test_stage() != 2)
9462 ;
9463
9464 /*
9465 * Wait for L0 timer interrupt to be raised while we run in L2
9466 * such that L0 will process the IOAPIC scan request before
9467 * resuming L2
9468 */
9469 delay(TIMER_INTERRUPT_DELAY);
9470
9471 asm volatile ("int $0x79");
9472 }
9473
vmx_eoi_bitmap_ioapic_scan_test(void)9474 static void vmx_eoi_bitmap_ioapic_scan_test(void)
9475 {
9476 if (!cpu_has_apicv() || (cpu_count() < 2)) {
9477 report_skip("%s : Not all required APICv bits supported or CPU count < 2", __func__);
9478 return;
9479 }
9480
9481 enable_vid();
9482
9483 on_cpu_async(1, trigger_ioapic_scan_thread, NULL);
9484 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest);
9485
9486 /*
9487 * Launch L2.
9488 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED).
9489 * In case the reason isn't VMX_VMCALL, the assertion inside
9490 * skip_exit_vmcall() will fail.
9491 */
9492 enter_guest();
9493 skip_exit_vmcall();
9494
9495 /* Let L2 finish */
9496 enter_guest();
9497 report_pass(__func__);
9498 }
9499
9500 #define HLT_WITH_RVI_VECTOR (0xf1)
9501
9502 bool vmx_hlt_with_rvi_guest_isr_fired;
vmx_hlt_with_rvi_guest_isr(isr_regs_t * regs)9503 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs)
9504 {
9505 vmx_hlt_with_rvi_guest_isr_fired = true;
9506 eoi();
9507 }
9508
vmx_hlt_with_rvi_guest(void)9509 static void vmx_hlt_with_rvi_guest(void)
9510 {
9511 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr);
9512
9513 sti_nop();
9514 asm volatile ("nop");
9515
9516 vmcall();
9517 }
9518
vmx_hlt_with_rvi_test(void)9519 static void vmx_hlt_with_rvi_test(void)
9520 {
9521 if (!cpu_has_apicv()) {
9522 report_skip("%s : Not all required APICv bits supported", __func__);
9523 return;
9524 }
9525
9526 enable_vid();
9527
9528 vmx_hlt_with_rvi_guest_isr_fired = false;
9529 test_set_guest(vmx_hlt_with_rvi_guest);
9530
9531 enter_guest();
9532 skip_exit_vmcall();
9533
9534 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT);
9535 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR);
9536 enter_guest();
9537
9538 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest");
9539 }
9540
set_irq_line_thread(void * data)9541 static void set_irq_line_thread(void *data)
9542 {
9543 /* Wait until other CPU entered L2 */
9544 while (vmx_get_test_stage() != 1)
9545 ;
9546
9547 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */
9548 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL);
9549 vmx_set_test_stage(2);
9550 }
9551
9552 static bool irq_78_handler_vmcall_before_eoi;
irq_78_handler_guest(isr_regs_t * regs)9553 static void irq_78_handler_guest(isr_regs_t *regs)
9554 {
9555 set_irq_line(0xf, 0);
9556 if (irq_78_handler_vmcall_before_eoi)
9557 vmcall();
9558 eoi();
9559 vmcall();
9560 }
9561
vmx_apic_passthrough_guest(void)9562 static void vmx_apic_passthrough_guest(void)
9563 {
9564 handle_irq(0x78, irq_78_handler_guest);
9565 sti();
9566
9567 /* If requested, wait for other CPU to trigger ioapic scan */
9568 if (vmx_get_test_stage() < 1) {
9569 vmx_set_test_stage(1);
9570 while (vmx_get_test_stage() != 2)
9571 ;
9572 }
9573
9574 set_irq_line(0xf, 1);
9575 }
9576
vmx_apic_passthrough(bool set_irq_line_from_thread)9577 static void vmx_apic_passthrough(bool set_irq_line_from_thread)
9578 {
9579 if (set_irq_line_from_thread && (cpu_count() < 2)) {
9580 report_skip("%s : CPU count < 2", __func__);
9581 return;
9582 }
9583
9584 /* Test device is required for generating IRQs */
9585 if (!test_device_enabled()) {
9586 report_skip("%s : No test device enabled", __func__);
9587 return;
9588 }
9589 u64 cpu_ctrl_0 = CPU_SECONDARY;
9590 u64 cpu_ctrl_1 = 0;
9591
9592 disable_intercept_for_x2apic_msrs();
9593
9594 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT);
9595
9596 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0);
9597 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1);
9598
9599 if (set_irq_line_from_thread) {
9600 irq_78_handler_vmcall_before_eoi = false;
9601 on_cpu_async(1, set_irq_line_thread, NULL);
9602 } else {
9603 irq_78_handler_vmcall_before_eoi = true;
9604 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL);
9605 vmx_set_test_stage(2);
9606 }
9607 test_set_guest(vmx_apic_passthrough_guest);
9608
9609 if (irq_78_handler_vmcall_before_eoi) {
9610 /* Before EOI remote_irr should still be set */
9611 enter_guest();
9612 skip_exit_vmcall();
9613 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr,
9614 "IOAPIC pass-through: remote_irr=1 before EOI");
9615 }
9616
9617 /* After EOI remote_irr should be cleared */
9618 enter_guest();
9619 skip_exit_vmcall();
9620 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr,
9621 "IOAPIC pass-through: remote_irr=0 after EOI");
9622
9623 /* Let L2 finish */
9624 enter_guest();
9625 report_pass(__func__);
9626 }
9627
vmx_apic_passthrough_test(void)9628 static void vmx_apic_passthrough_test(void)
9629 {
9630 vmx_apic_passthrough(false);
9631 }
9632
vmx_apic_passthrough_thread_test(void)9633 static void vmx_apic_passthrough_thread_test(void)
9634 {
9635 vmx_apic_passthrough(true);
9636 }
9637
vmx_apic_passthrough_tpr_threshold_guest(void)9638 static void vmx_apic_passthrough_tpr_threshold_guest(void)
9639 {
9640 cli();
9641 apic_set_tpr(0);
9642 }
9643
9644 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired;
vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t * regs)9645 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs)
9646 {
9647 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true;
9648 eoi();
9649 }
9650
vmx_apic_passthrough_tpr_threshold_test(void)9651 static void vmx_apic_passthrough_tpr_threshold_test(void)
9652 {
9653 int ipi_vector = 0xe1;
9654
9655 disable_intercept_for_x2apic_msrs();
9656 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT);
9657
9658 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */
9659 cli();
9660 apic_set_tpr((ipi_vector >> 4) + 1);
9661 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL |
9662 APIC_DM_FIXED | ipi_vector,
9663 0);
9664
9665 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest);
9666 enter_guest();
9667
9668 report(apic_get_tpr() == 0, "TPR was zero by guest");
9669
9670 /* Clean pending self-IPI */
9671 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false;
9672 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr);
9673 sti_nop();
9674 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired");
9675
9676 report_pass(__func__);
9677 }
9678
9679 static u64 init_signal_test_exit_reason;
9680 static bool init_signal_test_thread_continued;
9681
init_signal_test_thread(void * data)9682 static void init_signal_test_thread(void *data)
9683 {
9684 struct vmcs *test_vmcs = data;
9685
9686 /* Enter VMX operation (i.e. exec VMXON) */
9687 u64 *ap_vmxon_region = alloc_page();
9688 enable_vmx();
9689 init_vmx(ap_vmxon_region);
9690 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region));
9691
9692 /* Signal CPU have entered VMX operation */
9693 vmx_set_test_stage(1);
9694
9695 /* Wait for BSP CPU to send INIT signal */
9696 while (vmx_get_test_stage() != 2)
9697 ;
9698
9699 /*
9700 * Signal that we continue as usual as INIT signal
9701 * should be blocked while CPU is in VMX operation
9702 */
9703 vmx_set_test_stage(3);
9704
9705 /* Wait for signal to enter VMX non-root mode */
9706 while (vmx_get_test_stage() != 4)
9707 ;
9708
9709 /* Enter VMX non-root mode */
9710 test_set_guest(v2_null_test_guest);
9711 make_vmcs_current(test_vmcs);
9712 enter_guest();
9713 /* Save exit reason for BSP CPU to compare to expected result */
9714 init_signal_test_exit_reason = vmcs_read(EXI_REASON);
9715 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */
9716 vmcs_clear(test_vmcs);
9717 launched = false;
9718 /* Signal that CPU exited to VMX root mode */
9719 vmx_set_test_stage(5);
9720
9721 /* Wait for BSP CPU to signal to exit VMX operation */
9722 while (vmx_get_test_stage() != 6)
9723 ;
9724
9725 /* Exit VMX operation (i.e. exec VMXOFF) */
9726 vmx_off();
9727
9728 /*
9729 * Signal to BSP CPU that we continue as usual as INIT signal
9730 * should have been consumed by VMX_INIT exit from guest
9731 */
9732 vmx_set_test_stage(7);
9733
9734 /* Wait for BSP CPU to signal to enter VMX operation */
9735 while (vmx_get_test_stage() != 8)
9736 ;
9737 /* Enter VMX operation (i.e. exec VMXON) */
9738 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region));
9739 /* Signal to BSP we are in VMX operation */
9740 vmx_set_test_stage(9);
9741
9742 /* Wait for BSP CPU to send INIT signal */
9743 while (vmx_get_test_stage() != 10)
9744 ;
9745
9746 /* Exit VMX operation (i.e. exec VMXOFF) */
9747 vmx_off();
9748
9749 /*
9750 * Exiting VMX operation should result in latched
9751 * INIT signal being processed. Therefore, we should
9752 * never reach the below code. Thus, signal to BSP
9753 * CPU if we have reached here so it is able to
9754 * report an issue if it happens.
9755 */
9756 init_signal_test_thread_continued = true;
9757 }
9758
9759 #define INIT_SIGNAL_TEST_DELAY 100000000ULL
9760
vmx_init_signal_test(void)9761 static void vmx_init_signal_test(void)
9762 {
9763 struct vmcs *test_vmcs;
9764
9765 if (cpu_count() < 2) {
9766 report_skip("%s : CPU count < 2", __func__);
9767 return;
9768 }
9769
9770 /* VMCLEAR test-vmcs so it could be loaded by other CPU */
9771 vmcs_save(&test_vmcs);
9772 vmcs_clear(test_vmcs);
9773
9774 vmx_set_test_stage(0);
9775 on_cpu_async(1, init_signal_test_thread, test_vmcs);
9776
9777 /* Wait for other CPU to enter VMX operation */
9778 while (vmx_get_test_stage() != 1)
9779 ;
9780
9781 /* Send INIT signal to other CPU */
9782 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT,
9783 id_map[1]);
9784 /* Signal other CPU we have sent INIT signal */
9785 vmx_set_test_stage(2);
9786
9787 /*
9788 * Wait reasonable amount of time for INIT signal to
9789 * be received on other CPU and verify that other CPU
9790 * have proceed as usual to next test stage as INIT
9791 * signal should be blocked while other CPU in
9792 * VMX operation
9793 */
9794 delay(INIT_SIGNAL_TEST_DELAY);
9795 report(vmx_get_test_stage() == 3,
9796 "INIT signal blocked when CPU in VMX operation");
9797 /* No point to continue if we failed at this point */
9798 if (vmx_get_test_stage() != 3)
9799 return;
9800
9801 /* Signal other CPU to enter VMX non-root mode */
9802 init_signal_test_exit_reason = -1ull;
9803 vmx_set_test_stage(4);
9804 /*
9805 * Wait reasonable amount of time for other CPU
9806 * to exit to VMX root mode
9807 */
9808 delay(INIT_SIGNAL_TEST_DELAY);
9809 if (vmx_get_test_stage() != 5) {
9810 report_fail("Pending INIT signal didn't result in VMX exit");
9811 return;
9812 }
9813 report(init_signal_test_exit_reason == VMX_INIT,
9814 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)",
9815 exit_reason_description(init_signal_test_exit_reason),
9816 init_signal_test_exit_reason);
9817
9818 /* Run guest to completion */
9819 make_vmcs_current(test_vmcs);
9820 enter_guest();
9821
9822 /* Signal other CPU to exit VMX operation */
9823 init_signal_test_thread_continued = false;
9824 vmx_set_test_stage(6);
9825
9826 /* Wait reasonable amount of time for other CPU to exit VMX operation */
9827 delay(INIT_SIGNAL_TEST_DELAY);
9828 report(vmx_get_test_stage() == 7,
9829 "INIT signal consumed on VMX_INIT exit");
9830 /* No point to continue if we failed at this point */
9831 if (vmx_get_test_stage() != 7)
9832 return;
9833
9834 /* Signal other CPU to enter VMX operation */
9835 vmx_set_test_stage(8);
9836 /* Wait for other CPU to enter VMX operation */
9837 while (vmx_get_test_stage() != 9)
9838 ;
9839
9840 /* Send INIT signal to other CPU */
9841 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT,
9842 id_map[1]);
9843 /* Signal other CPU we have sent INIT signal */
9844 vmx_set_test_stage(10);
9845
9846 /*
9847 * Wait reasonable amount of time for other CPU
9848 * to exit VMX operation and process INIT signal
9849 */
9850 delay(INIT_SIGNAL_TEST_DELAY);
9851 report(!init_signal_test_thread_continued,
9852 "INIT signal processed after exit VMX operation");
9853
9854 /*
9855 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S)
9856 * to re-init it to kvm-unit-tests standard environment.
9857 * Somehow (?) verify that SIPI was indeed received.
9858 */
9859 }
9860
9861 #define SIPI_SIGNAL_TEST_DELAY 100000000ULL
9862
vmx_sipi_test_guest(void)9863 static void vmx_sipi_test_guest(void)
9864 {
9865 if (apic_id() == 0) {
9866 /* wait AP enter guest with activity=WAIT_SIPI */
9867 while (vmx_get_test_stage() != 1)
9868 ;
9869 delay(SIPI_SIGNAL_TEST_DELAY);
9870
9871 /* First SIPI signal */
9872 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]);
9873 report_pass("BSP(L2): Send first SIPI to cpu[%d]", id_map[1]);
9874
9875 /* wait AP enter guest */
9876 while (vmx_get_test_stage() != 2)
9877 ;
9878 delay(SIPI_SIGNAL_TEST_DELAY);
9879
9880 /* Second SIPI signal should be ignored since AP is not in WAIT_SIPI state */
9881 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]);
9882 report_pass("BSP(L2): Send second SIPI to cpu[%d]", id_map[1]);
9883
9884 /* Delay a while to check whether second SIPI would cause VMExit */
9885 delay(SIPI_SIGNAL_TEST_DELAY);
9886
9887 /* Test is done, notify AP to exit test */
9888 vmx_set_test_stage(3);
9889
9890 /* wait AP exit non-root mode */
9891 while (vmx_get_test_stage() != 5)
9892 ;
9893 } else {
9894 /* wait BSP notify test is done */
9895 while (vmx_get_test_stage() != 3)
9896 ;
9897
9898 /* AP exit guest */
9899 vmx_set_test_stage(4);
9900 }
9901 }
9902
sipi_test_ap_thread(void * data)9903 static void sipi_test_ap_thread(void *data)
9904 {
9905 struct vmcs *ap_vmcs;
9906 u64 *ap_vmxon_region;
9907 void *ap_stack, *ap_syscall_stack;
9908 u64 cpu_ctrl_0 = CPU_SECONDARY;
9909 u64 cpu_ctrl_1 = 0;
9910
9911 /* Enter VMX operation (i.e. exec VMXON) */
9912 ap_vmxon_region = alloc_page();
9913 enable_vmx();
9914 init_vmx(ap_vmxon_region);
9915 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region));
9916 init_vmcs(&ap_vmcs);
9917 make_vmcs_current(ap_vmcs);
9918
9919 /* Set stack for AP */
9920 ap_stack = alloc_page();
9921 ap_syscall_stack = alloc_page();
9922 vmcs_write(GUEST_RSP, (u64)(ap_stack + PAGE_SIZE - 1));
9923 vmcs_write(GUEST_SYSENTER_ESP, (u64)(ap_syscall_stack + PAGE_SIZE - 1));
9924
9925 /* passthrough lapic to L2 */
9926 disable_intercept_for_x2apic_msrs();
9927 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT);
9928 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0);
9929 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1);
9930
9931 /* Set guest activity state to wait-for-SIPI state */
9932 vmcs_write(GUEST_ACTV_STATE, ACTV_WAIT_SIPI);
9933
9934 vmx_set_test_stage(1);
9935
9936 /* AP enter guest */
9937 enter_guest();
9938
9939 if (vmcs_read(EXI_REASON) == VMX_SIPI) {
9940 report_pass("AP: Handle SIPI VMExit");
9941 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE);
9942 vmx_set_test_stage(2);
9943 } else {
9944 report_fail("AP: Unexpected VMExit, reason=%ld", vmcs_read(EXI_REASON));
9945 vmx_off();
9946 return;
9947 }
9948
9949 /* AP enter guest */
9950 enter_guest();
9951
9952 report(vmcs_read(EXI_REASON) != VMX_SIPI,
9953 "AP: should no SIPI VMExit since activity is not in WAIT_SIPI state");
9954
9955 /* notify BSP that AP is already exit from non-root mode */
9956 vmx_set_test_stage(5);
9957
9958 /* Leave VMX operation */
9959 vmx_off();
9960 }
9961
vmx_sipi_signal_test(void)9962 static void vmx_sipi_signal_test(void)
9963 {
9964 if (!(rdmsr(MSR_IA32_VMX_MISC) & MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI)) {
9965 report_skip("%s : \"ACTIVITY_WAIT_SIPI state\" not supported", __func__);
9966 return;
9967 }
9968
9969 if (cpu_count() < 2) {
9970 report_skip("%s : CPU count < 2", __func__);
9971 return;
9972 }
9973
9974 u64 cpu_ctrl_0 = CPU_SECONDARY;
9975 u64 cpu_ctrl_1 = 0;
9976
9977 /* passthrough lapic to L2 */
9978 disable_intercept_for_x2apic_msrs();
9979 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT);
9980 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0);
9981 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1);
9982
9983 test_set_guest(vmx_sipi_test_guest);
9984
9985 /* update CR3 on AP */
9986 on_cpu(1, update_cr3, (void *)read_cr3());
9987
9988 /* start AP */
9989 on_cpu_async(1, sipi_test_ap_thread, NULL);
9990
9991 vmx_set_test_stage(0);
9992
9993 /* BSP enter guest */
9994 enter_guest();
9995 }
9996
9997
9998 enum vmcs_access {
9999 ACCESS_VMREAD,
10000 ACCESS_VMWRITE,
10001 ACCESS_NONE,
10002 };
10003
10004 struct vmcs_shadow_test_common {
10005 enum vmcs_access op;
10006 enum Reason reason;
10007 u64 field;
10008 u64 value;
10009 u64 flags;
10010 u64 time;
10011 } l1_l2_common;
10012
vmread_flags(u64 field,u64 * val)10013 static inline u64 vmread_flags(u64 field, u64 *val)
10014 {
10015 u64 flags;
10016
10017 asm volatile ("vmread %2, %1; pushf; pop %0"
10018 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc");
10019 return flags & X86_EFLAGS_ALU;
10020 }
10021
vmwrite_flags(u64 field,u64 val)10022 static inline u64 vmwrite_flags(u64 field, u64 val)
10023 {
10024 u64 flags;
10025
10026 asm volatile ("vmwrite %1, %2; pushf; pop %0"
10027 : "=r"(flags) : "rm" (val), "r" (field) : "cc");
10028 return flags & X86_EFLAGS_ALU;
10029 }
10030
vmx_vmcs_shadow_test_guest(void)10031 static void vmx_vmcs_shadow_test_guest(void)
10032 {
10033 struct vmcs_shadow_test_common *c = &l1_l2_common;
10034 u64 start;
10035
10036 while (c->op != ACCESS_NONE) {
10037 start = rdtsc();
10038 switch (c->op) {
10039 default:
10040 c->flags = -1ull;
10041 break;
10042 case ACCESS_VMREAD:
10043 c->flags = vmread_flags(c->field, &c->value);
10044 break;
10045 case ACCESS_VMWRITE:
10046 c->flags = vmwrite_flags(c->field, 0);
10047 break;
10048 }
10049 c->time = rdtsc() - start;
10050 vmcall();
10051 }
10052 }
10053
vmread_from_shadow(u64 field)10054 static u64 vmread_from_shadow(u64 field)
10055 {
10056 struct vmcs *primary;
10057 struct vmcs *shadow;
10058 u64 value;
10059
10060 TEST_ASSERT(!vmcs_save(&primary));
10061 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR);
10062 TEST_ASSERT(!make_vmcs_current(shadow));
10063 value = vmcs_read(field);
10064 TEST_ASSERT(!make_vmcs_current(primary));
10065 return value;
10066 }
10067
vmwrite_to_shadow(u64 field,u64 value)10068 static u64 vmwrite_to_shadow(u64 field, u64 value)
10069 {
10070 struct vmcs *primary;
10071 struct vmcs *shadow;
10072
10073 TEST_ASSERT(!vmcs_save(&primary));
10074 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR);
10075 TEST_ASSERT(!make_vmcs_current(shadow));
10076 vmcs_write(field, value);
10077 value = vmcs_read(field);
10078 TEST_ASSERT(!make_vmcs_current(primary));
10079 return value;
10080 }
10081
vmcs_shadow_test_access(u8 * bitmap[2],enum vmcs_access access)10082 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access)
10083 {
10084 struct vmcs_shadow_test_common *c = &l1_l2_common;
10085
10086 c->op = access;
10087 vmcs_write(VMX_INST_ERROR, 0);
10088 enter_guest();
10089 c->reason = vmcs_read(EXI_REASON) & 0xffff;
10090 if (c->reason != VMX_VMCALL) {
10091 skip_exit_insn();
10092 enter_guest();
10093 }
10094 skip_exit_vmcall();
10095 }
10096
vmcs_shadow_test_field(u8 * bitmap[2],u64 field)10097 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field)
10098 {
10099 struct vmcs_shadow_test_common *c = &l1_l2_common;
10100 struct vmcs *shadow;
10101 u64 value;
10102 uintptr_t flags[2];
10103 bool good_shadow;
10104 u32 vmx_inst_error;
10105
10106 report_prefix_pushf("field %lx", field);
10107 c->field = field;
10108
10109 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR);
10110 if (shadow != (struct vmcs *)-1ull) {
10111 flags[ACCESS_VMREAD] = vmread_flags(field, &value);
10112 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value);
10113 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE];
10114 } else {
10115 /*
10116 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on
10117 * shadowed-fields should fail with setting RFLAGS.CF.
10118 */
10119 flags[ACCESS_VMREAD] = X86_EFLAGS_CF;
10120 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF;
10121 good_shadow = false;
10122 }
10123
10124 /* Intercept both VMREAD and VMWRITE. */
10125 report_prefix_push("no VMREAD/VMWRITE permission");
10126 /* VMWRITE/VMREAD done on reserved-bit should always intercept */
10127 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) {
10128 set_bit(field, bitmap[ACCESS_VMREAD]);
10129 set_bit(field, bitmap[ACCESS_VMWRITE]);
10130 }
10131 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE);
10132 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE");
10133 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD);
10134 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD");
10135 report_prefix_pop();
10136
10137 if (field >> VMCS_FIELD_RESERVED_SHIFT)
10138 goto out;
10139
10140 /* Permit shadowed VMREAD. */
10141 report_prefix_push("VMREAD permission only");
10142 clear_bit(field, bitmap[ACCESS_VMREAD]);
10143 set_bit(field, bitmap[ACCESS_VMWRITE]);
10144 if (good_shadow)
10145 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field);
10146 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE);
10147 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE");
10148 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD);
10149 vmx_inst_error = vmcs_read(VMX_INST_ERROR);
10150 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)",
10151 c->time);
10152 report(c->flags == flags[ACCESS_VMREAD],
10153 "ALU flags after VMREAD (%lx) are as expected (%lx)",
10154 c->flags, flags[ACCESS_VMREAD]);
10155 if (good_shadow)
10156 report(c->value == value,
10157 "value read from shadow (%lx) is as expected (%lx)",
10158 c->value, value);
10159 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD])
10160 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT,
10161 "VMX_INST_ERROR (%d) is as expected (%d)",
10162 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
10163 report_prefix_pop();
10164
10165 /* Permit shadowed VMWRITE. */
10166 report_prefix_push("VMWRITE permission only");
10167 set_bit(field, bitmap[ACCESS_VMREAD]);
10168 clear_bit(field, bitmap[ACCESS_VMWRITE]);
10169 if (good_shadow)
10170 vmwrite_to_shadow(field, MAGIC_VAL_1 + field);
10171 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE);
10172 vmx_inst_error = vmcs_read(VMX_INST_ERROR);
10173 report(c->reason == VMX_VMCALL,
10174 "shadowed for VMWRITE (in %ld cycles)",
10175 c->time);
10176 report(c->flags == flags[ACCESS_VMREAD],
10177 "ALU flags after VMWRITE (%lx) are as expected (%lx)",
10178 c->flags, flags[ACCESS_VMREAD]);
10179 if (good_shadow) {
10180 value = vmread_from_shadow(field);
10181 report(value == 0,
10182 "shadow VMCS value (%lx) is as expected (%lx)", value,
10183 0ul);
10184 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) {
10185 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT,
10186 "VMX_INST_ERROR (%d) is as expected (%d)",
10187 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
10188 }
10189 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD);
10190 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD");
10191 report_prefix_pop();
10192
10193 /* Permit shadowed VMREAD and VMWRITE. */
10194 report_prefix_push("VMREAD and VMWRITE permission");
10195 clear_bit(field, bitmap[ACCESS_VMREAD]);
10196 clear_bit(field, bitmap[ACCESS_VMWRITE]);
10197 if (good_shadow)
10198 vmwrite_to_shadow(field, MAGIC_VAL_1 + field);
10199 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE);
10200 vmx_inst_error = vmcs_read(VMX_INST_ERROR);
10201 report(c->reason == VMX_VMCALL,
10202 "shadowed for VMWRITE (in %ld cycles)",
10203 c->time);
10204 report(c->flags == flags[ACCESS_VMREAD],
10205 "ALU flags after VMWRITE (%lx) are as expected (%lx)",
10206 c->flags, flags[ACCESS_VMREAD]);
10207 if (good_shadow) {
10208 value = vmread_from_shadow(field);
10209 report(value == 0,
10210 "shadow VMCS value (%lx) is as expected (%lx)", value,
10211 0ul);
10212 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) {
10213 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT,
10214 "VMX_INST_ERROR (%d) is as expected (%d)",
10215 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
10216 }
10217 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD);
10218 vmx_inst_error = vmcs_read(VMX_INST_ERROR);
10219 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)",
10220 c->time);
10221 report(c->flags == flags[ACCESS_VMREAD],
10222 "ALU flags after VMREAD (%lx) are as expected (%lx)",
10223 c->flags, flags[ACCESS_VMREAD]);
10224 if (good_shadow)
10225 report(c->value == 0,
10226 "value read from shadow (%lx) is as expected (%lx)",
10227 c->value, 0ul);
10228 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD])
10229 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT,
10230 "VMX_INST_ERROR (%d) is as expected (%d)",
10231 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
10232 report_prefix_pop();
10233
10234 out:
10235 report_prefix_pop();
10236 }
10237
vmx_vmcs_shadow_test_body(u8 * bitmap[2])10238 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2])
10239 {
10240 unsigned base;
10241 unsigned index;
10242 unsigned bit;
10243 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM);
10244
10245 /* Run test on all possible valid VMCS fields */
10246 for (base = 0;
10247 base < (1 << VMCS_FIELD_RESERVED_SHIFT);
10248 base += (1 << VMCS_FIELD_TYPE_SHIFT))
10249 for (index = 0; index <= highest_index; index++)
10250 vmcs_shadow_test_field(bitmap, base + index);
10251
10252 /*
10253 * Run tests on some invalid VMCS fields
10254 * (Have reserved bit set).
10255 */
10256 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++)
10257 vmcs_shadow_test_field(bitmap, (1ull << bit));
10258 }
10259
vmx_vmcs_shadow_test(void)10260 static void vmx_vmcs_shadow_test(void)
10261 {
10262 u8 *bitmap[2];
10263 struct vmcs *shadow;
10264
10265 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) {
10266 report_skip("%s : \"Activate secondary controls\" not supported", __func__);
10267 return;
10268 }
10269
10270 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) {
10271 report_skip("%s : \"VMCS shadowing\" not supported", __func__);
10272 return;
10273 }
10274
10275 if (!(rdmsr(MSR_IA32_VMX_MISC) &
10276 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) {
10277 report_skip("%s : VMWRITE can't modify VM-exit information fields.", __func__);
10278 return;
10279 }
10280
10281 test_set_guest(vmx_vmcs_shadow_test_guest);
10282
10283 bitmap[ACCESS_VMREAD] = alloc_page();
10284 bitmap[ACCESS_VMWRITE] = alloc_page();
10285
10286 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD]));
10287 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE]));
10288
10289 shadow = alloc_page();
10290 shadow->hdr.revision_id = basic_msr.revision;
10291 shadow->hdr.shadow_vmcs = 1;
10292 TEST_ASSERT(!vmcs_clear(shadow));
10293
10294 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC);
10295 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY);
10296 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS);
10297
10298 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow));
10299 report_prefix_push("valid link pointer");
10300 vmx_vmcs_shadow_test_body(bitmap);
10301 report_prefix_pop();
10302
10303 vmcs_write(VMCS_LINK_PTR, -1ull);
10304 report_prefix_push("invalid link pointer");
10305 vmx_vmcs_shadow_test_body(bitmap);
10306 report_prefix_pop();
10307
10308 l1_l2_common.op = ACCESS_NONE;
10309 enter_guest();
10310 }
10311
10312 /*
10313 * This test monitors the difference between a guest RDTSC instruction
10314 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12
10315 * VM-exit MSR-store list when taking a VM-exit on the instruction
10316 * following RDTSC.
10317 */
10318 #define RDTSC_DIFF_ITERS 100000
10319 #define RDTSC_DIFF_FAILS 100
10320 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750
10321
10322 /*
10323 * Set 'use TSC offsetting' and set the guest offset to the
10324 * inverse of the host's current TSC value, so that the guest starts running
10325 * with an effective TSC value of 0.
10326 */
reset_guest_tsc_to_zero(void)10327 static void reset_guest_tsc_to_zero(void)
10328 {
10329 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET);
10330 vmcs_write(TSC_OFFSET, -rdtsc());
10331 }
10332
rdtsc_vmexit_diff_test_guest(void)10333 static void rdtsc_vmexit_diff_test_guest(void)
10334 {
10335 int i;
10336
10337 for (i = 0; i < RDTSC_DIFF_ITERS; i++)
10338 /* Ensure rdtsc is the last instruction before the vmcall. */
10339 asm volatile("rdtsc; vmcall" : : : "eax", "edx");
10340 }
10341
10342 /*
10343 * This function only considers the "use TSC offsetting" VM-execution
10344 * control. It does not handle "use TSC scaling" (because the latter
10345 * isn't available to the host today.)
10346 */
host_time_to_guest_time(unsigned long long t)10347 static unsigned long long host_time_to_guest_time(unsigned long long t)
10348 {
10349 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) ||
10350 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING));
10351
10352 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET)
10353 t += vmcs_read(TSC_OFFSET);
10354
10355 return t;
10356 }
10357
rdtsc_vmexit_diff_test_iteration(void)10358 static unsigned long long rdtsc_vmexit_diff_test_iteration(void)
10359 {
10360 unsigned long long guest_tsc, host_to_guest_tsc;
10361
10362 enter_guest();
10363 skip_exit_vmcall();
10364 guest_tsc = (u32) regs.rax + (regs.rdx << 32);
10365 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value);
10366
10367 return host_to_guest_tsc - guest_tsc;
10368 }
10369
rdtsc_vmexit_diff_test(void)10370 static void rdtsc_vmexit_diff_test(void)
10371 {
10372 unsigned long long delta;
10373 int fail = 0;
10374 int i;
10375
10376 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET))
10377 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n");
10378
10379 test_set_guest(rdtsc_vmexit_diff_test_guest);
10380
10381 reset_guest_tsc_to_zero();
10382
10383 /*
10384 * Set up the VMCS12 VM-exit MSR-store list to store just one
10385 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is
10386 * in the host time domain (i.e., it is not adjusted according
10387 * to the TSC multiplier and TSC offset fields in the VMCS12,
10388 * as a guest RDTSC would be.)
10389 */
10390 exit_msr_store = alloc_page();
10391 exit_msr_store[0].index = MSR_IA32_TSC;
10392 vmcs_write(EXI_MSR_ST_CNT, 1);
10393 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store));
10394
10395 for (i = 0; i < RDTSC_DIFF_ITERS && fail < RDTSC_DIFF_FAILS; i++) {
10396 delta = rdtsc_vmexit_diff_test_iteration();
10397 if (delta >= HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD)
10398 fail++;
10399 }
10400
10401 enter_guest();
10402
10403 report(fail < RDTSC_DIFF_FAILS,
10404 "RDTSC to VM-exit delta too high in %d of %d iterations, last = %llu",
10405 fail, i, delta);
10406 }
10407
invalid_msr_init(struct vmcs * vmcs)10408 static int invalid_msr_init(struct vmcs *vmcs)
10409 {
10410 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) {
10411 printf("\tPreemption timer is not supported\n");
10412 return VMX_TEST_EXIT;
10413 }
10414 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT);
10415 preempt_val = 10000000;
10416 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val);
10417 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F;
10418
10419 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT))
10420 printf("\tSave preemption value is not supported\n");
10421
10422 vmcs_write(ENT_MSR_LD_CNT, 1);
10423 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000);
10424
10425 return VMX_TEST_START;
10426 }
10427
10428
invalid_msr_main(void)10429 static void invalid_msr_main(void)
10430 {
10431 report_fail("Invalid MSR load");
10432 }
10433
invalid_msr_exit_handler(union exit_reason exit_reason)10434 static int invalid_msr_exit_handler(union exit_reason exit_reason)
10435 {
10436 report_fail("Invalid MSR load");
10437 print_vmexit_info(exit_reason);
10438 return VMX_TEST_EXIT;
10439 }
10440
invalid_msr_entry_failure(struct vmentry_result * result)10441 static int invalid_msr_entry_failure(struct vmentry_result *result)
10442 {
10443 report(result->exit_reason.failed_vmentry &&
10444 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load");
10445 return VMX_TEST_VMEXIT;
10446 }
10447
10448 /*
10449 * The max number of MSRs in an atomic switch MSR list is:
10450 * (111B + 1) * 512 = 4096
10451 *
10452 * Each list entry consumes:
10453 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes
10454 *
10455 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some.
10456 */
10457 static const u32 msr_list_page_order = 5;
10458
atomic_switch_msr_limit_test_guest(void)10459 static void atomic_switch_msr_limit_test_guest(void)
10460 {
10461 vmcall();
10462 }
10463
populate_msr_list(struct vmx_msr_entry * msr_list,size_t byte_capacity,int count)10464 static void populate_msr_list(struct vmx_msr_entry *msr_list,
10465 size_t byte_capacity, int count)
10466 {
10467 int i;
10468
10469 for (i = 0; i < count; i++) {
10470 msr_list[i].index = MSR_IA32_TSC;
10471 msr_list[i].reserved = 0;
10472 msr_list[i].value = 0x1234567890abcdef;
10473 }
10474
10475 memset(msr_list + count, 0xff,
10476 byte_capacity - count * sizeof(*msr_list));
10477 }
10478
max_msr_list_size(void)10479 static int max_msr_list_size(void)
10480 {
10481 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC);
10482 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1;
10483
10484 return factor * 512;
10485 }
10486
atomic_switch_msrs_test(int count)10487 static void atomic_switch_msrs_test(int count)
10488 {
10489 struct vmx_msr_entry *vm_enter_load;
10490 struct vmx_msr_entry *vm_exit_load;
10491 struct vmx_msr_entry *vm_exit_store;
10492 int max_allowed = max_msr_list_size();
10493 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT);
10494 /* Exceeding the max MSR list size at exit triggers KVM to abort. */
10495 int exit_count = count > max_allowed ? max_allowed : count;
10496 int cleanup_count = count > max_allowed ? 2 : 1;
10497 int i;
10498
10499 /*
10500 * Check for the IA32_TSC MSR,
10501 * available with the "TSC flag" and used to populate the MSR lists.
10502 */
10503 if (!(cpuid(1).d & (1 << 4))) {
10504 report_skip("%s : \"Time Stamp Counter\" not supported", __func__);
10505 return;
10506 }
10507
10508 /* Set L2 guest. */
10509 test_set_guest(atomic_switch_msr_limit_test_guest);
10510
10511 /* Setup atomic MSR switch lists. */
10512 vm_enter_load = alloc_pages(msr_list_page_order);
10513 vm_exit_load = alloc_pages(msr_list_page_order);
10514 vm_exit_store = alloc_pages(msr_list_page_order);
10515
10516 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load);
10517 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load);
10518 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store);
10519
10520 /*
10521 * VM-Enter should succeed up to the max number of MSRs per list, and
10522 * should not consume junk beyond the last entry.
10523 */
10524 populate_msr_list(vm_enter_load, byte_capacity, count);
10525 populate_msr_list(vm_exit_load, byte_capacity, exit_count);
10526 populate_msr_list(vm_exit_store, byte_capacity, exit_count);
10527
10528 vmcs_write(ENT_MSR_LD_CNT, count);
10529 vmcs_write(EXI_MSR_LD_CNT, exit_count);
10530 vmcs_write(EXI_MSR_ST_CNT, exit_count);
10531
10532 if (count <= max_allowed) {
10533 enter_guest();
10534 assert_exit_reason(VMX_VMCALL);
10535 skip_exit_vmcall();
10536 } else {
10537 u32 exit_qual;
10538
10539 test_guest_state("Invalid MSR Load Count", true, count,
10540 "ENT_MSR_LD_CNT");
10541
10542 exit_qual = vmcs_read(EXI_QUALIFICATION);
10543 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.",
10544 exit_qual, max_allowed + 1);
10545 }
10546
10547 /* Cleanup. */
10548 vmcs_write(ENT_MSR_LD_CNT, 0);
10549 vmcs_write(EXI_MSR_LD_CNT, 0);
10550 vmcs_write(EXI_MSR_ST_CNT, 0);
10551 for (i = 0; i < cleanup_count; i++) {
10552 enter_guest();
10553 skip_exit_vmcall();
10554 }
10555 free_pages_by_order(vm_enter_load, msr_list_page_order);
10556 free_pages_by_order(vm_exit_load, msr_list_page_order);
10557 free_pages_by_order(vm_exit_store, msr_list_page_order);
10558 }
10559
atomic_switch_max_msrs_test(void)10560 static void atomic_switch_max_msrs_test(void)
10561 {
10562 atomic_switch_msrs_test(max_msr_list_size());
10563 }
10564
atomic_switch_overflow_msrs_test(void)10565 static void atomic_switch_overflow_msrs_test(void)
10566 {
10567 if (test_device_enabled())
10568 atomic_switch_msrs_test(max_msr_list_size() + 1);
10569 else
10570 test_skip("Test is only supported on KVM");
10571 }
10572
vmx_pf_exception_test_guest(void)10573 static void vmx_pf_exception_test_guest(void)
10574 {
10575 ac_test_run(PT_LEVEL_PML4, false);
10576 }
10577
vmx_pf_exception_forced_emulation_test_guest(void)10578 static void vmx_pf_exception_forced_emulation_test_guest(void)
10579 {
10580 ac_test_run(PT_LEVEL_PML4, true);
10581 }
10582
10583 typedef void (*invalidate_tlb_t)(void *data);
10584 typedef void (*pf_exception_test_guest_t)(void);
10585
10586
__vmx_pf_exception_test(invalidate_tlb_t inv_fn,void * data,pf_exception_test_guest_t guest_fn)10587 static void __vmx_pf_exception_test(invalidate_tlb_t inv_fn, void *data,
10588 pf_exception_test_guest_t guest_fn)
10589 {
10590 u64 efer;
10591 struct cpuid cpuid;
10592
10593 test_set_guest(guest_fn);
10594
10595 /* Intercept INVLPG when to perform TLB invalidation from L1 (this). */
10596 if (inv_fn)
10597 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INVLPG);
10598 else
10599 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INVLPG);
10600
10601 enter_guest();
10602
10603 while (vmcs_read(EXI_REASON) != VMX_VMCALL) {
10604 switch (vmcs_read(EXI_REASON)) {
10605 case VMX_RDMSR:
10606 assert(regs.rcx == MSR_EFER);
10607 efer = vmcs_read(GUEST_EFER);
10608 regs.rdx = efer >> 32;
10609 regs.rax = efer & 0xffffffff;
10610 break;
10611 case VMX_WRMSR:
10612 assert(regs.rcx == MSR_EFER);
10613 efer = regs.rdx << 32 | (regs.rax & 0xffffffff);
10614 vmcs_write(GUEST_EFER, efer);
10615 break;
10616 case VMX_CPUID:
10617 cpuid = (struct cpuid) {0, 0, 0, 0};
10618 cpuid = raw_cpuid(regs.rax, regs.rcx);
10619 regs.rax = cpuid.a;
10620 regs.rbx = cpuid.b;
10621 regs.rcx = cpuid.c;
10622 regs.rdx = cpuid.d;
10623 break;
10624 case VMX_INVLPG:
10625 inv_fn(data);
10626 break;
10627 default:
10628 assert_msg(false,
10629 "Unexpected exit to L1, exit_reason: %s (0x%lx)",
10630 exit_reason_description(vmcs_read(EXI_REASON)),
10631 vmcs_read(EXI_REASON));
10632 }
10633 skip_exit_insn();
10634 enter_guest();
10635 }
10636
10637 assert_exit_reason(VMX_VMCALL);
10638 }
10639
vmx_pf_exception_test(void)10640 static void vmx_pf_exception_test(void)
10641 {
10642 __vmx_pf_exception_test(NULL, NULL, vmx_pf_exception_test_guest);
10643 }
10644
vmx_pf_exception_forced_emulation_test(void)10645 static void vmx_pf_exception_forced_emulation_test(void)
10646 {
10647 __vmx_pf_exception_test(NULL, NULL, vmx_pf_exception_forced_emulation_test_guest);
10648 }
10649
invalidate_tlb_no_vpid(void * data)10650 static void invalidate_tlb_no_vpid(void *data)
10651 {
10652 /* If VPID is disabled, the TLB is flushed on VM-Enter and VM-Exit. */
10653 }
10654
vmx_pf_no_vpid_test(void)10655 static void vmx_pf_no_vpid_test(void)
10656 {
10657 if (is_vpid_supported())
10658 vmcs_clear_bits(CPU_EXEC_CTRL1, CPU_VPID);
10659
10660 __vmx_pf_exception_test(invalidate_tlb_no_vpid, NULL,
10661 vmx_pf_exception_test_guest);
10662 }
10663
invalidate_tlb_invvpid_addr(void * data)10664 static void invalidate_tlb_invvpid_addr(void *data)
10665 {
10666 invvpid(INVVPID_ALL, *(u16 *)data, vmcs_read(EXI_QUALIFICATION));
10667 }
10668
invalidate_tlb_new_vpid(void * data)10669 static void invalidate_tlb_new_vpid(void *data)
10670 {
10671 u16 *vpid = data;
10672
10673 /*
10674 * Bump VPID to effectively flush L2's TLB from L0's perspective.
10675 * Invalidate all VPIDs when the VPID wraps to zero as hardware/KVM is
10676 * architecturally allowed to keep TLB entries indefinitely.
10677 */
10678 ++(*vpid);
10679 if (*vpid == 0) {
10680 ++(*vpid);
10681 invvpid(INVVPID_ALL, 0, 0);
10682 }
10683 vmcs_write(VPID, *vpid);
10684 }
10685
__vmx_pf_vpid_test(invalidate_tlb_t inv_fn,u16 vpid)10686 static void __vmx_pf_vpid_test(invalidate_tlb_t inv_fn, u16 vpid)
10687 {
10688 if (!is_vpid_supported())
10689 test_skip("VPID unsupported");
10690
10691 if (!is_invvpid_supported())
10692 test_skip("INVVPID unsupported");
10693
10694 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY);
10695 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VPID);
10696 vmcs_write(VPID, vpid);
10697
10698 __vmx_pf_exception_test(inv_fn, &vpid, vmx_pf_exception_test_guest);
10699 }
10700
vmx_pf_invvpid_test(void)10701 static void vmx_pf_invvpid_test(void)
10702 {
10703 if (!is_invvpid_type_supported(INVVPID_ADDR))
10704 test_skip("INVVPID ADDR unsupported");
10705
10706 __vmx_pf_vpid_test(invalidate_tlb_invvpid_addr, 0xaaaa);
10707 }
10708
vmx_pf_vpid_test(void)10709 static void vmx_pf_vpid_test(void)
10710 {
10711 /* Need INVVPID(ALL) to flush VPIDs upon wrap/reuse. */
10712 if (!is_invvpid_type_supported(INVVPID_ALL))
10713 test_skip("INVVPID ALL unsupported");
10714
10715 __vmx_pf_vpid_test(invalidate_tlb_new_vpid, 1);
10716 }
10717
vmx_l2_ac_test(void)10718 static void vmx_l2_ac_test(void)
10719 {
10720 bool hit_ac = false;
10721
10722 write_cr0(read_cr0() | X86_CR0_AM);
10723 write_rflags(read_rflags() | X86_EFLAGS_AC);
10724
10725 run_in_user(generate_usermode_ac, AC_VECTOR, 0, 0, 0, 0, &hit_ac);
10726 report(hit_ac, "Usermode #AC handled in L2");
10727 vmcall();
10728 }
10729
10730 struct vmx_exception_test {
10731 u8 vector;
10732 void (*guest_code)(void);
10733 };
10734
10735 struct vmx_exception_test vmx_exception_tests[] = {
10736 { GP_VECTOR, generate_non_canonical_gp },
10737 { UD_VECTOR, generate_ud },
10738 { DE_VECTOR, generate_de },
10739 { DB_VECTOR, generate_single_step_db },
10740 { BP_VECTOR, generate_bp },
10741 { AC_VECTOR, vmx_l2_ac_test },
10742 { OF_VECTOR, generate_of },
10743 { NM_VECTOR, generate_cr0_ts_nm },
10744 { NM_VECTOR, generate_cr0_em_nm },
10745 };
10746
10747 static u8 vmx_exception_test_vector;
10748
vmx_exception_handler(struct ex_regs * regs)10749 static void vmx_exception_handler(struct ex_regs *regs)
10750 {
10751 report(regs->vector == vmx_exception_test_vector,
10752 "Handling %s in L2's exception handler",
10753 exception_mnemonic(vmx_exception_test_vector));
10754 vmcall();
10755 }
10756
handle_exception_in_l2(u8 vector)10757 static void handle_exception_in_l2(u8 vector)
10758 {
10759 handler old_handler = handle_exception(vector, vmx_exception_handler);
10760
10761 vmx_exception_test_vector = vector;
10762
10763 enter_guest();
10764 report(vmcs_read(EXI_REASON) == VMX_VMCALL,
10765 "%s handled by L2", exception_mnemonic(vector));
10766
10767 handle_exception(vector, old_handler);
10768 }
10769
handle_exception_in_l1(u32 vector)10770 static void handle_exception_in_l1(u32 vector)
10771 {
10772 u32 old_eb = vmcs_read(EXC_BITMAP);
10773 u32 intr_type;
10774 u32 intr_info;
10775
10776 vmcs_write(EXC_BITMAP, old_eb | (1u << vector));
10777
10778 enter_guest();
10779
10780 if (vector == BP_VECTOR || vector == OF_VECTOR)
10781 intr_type = VMX_INTR_TYPE_SOFT_EXCEPTION;
10782 else
10783 intr_type = VMX_INTR_TYPE_HARD_EXCEPTION;
10784
10785 intr_info = vmcs_read(EXI_INTR_INFO);
10786 report((vmcs_read(EXI_REASON) == VMX_EXC_NMI) &&
10787 (intr_info & INTR_INFO_VALID_MASK) &&
10788 (intr_info & INTR_INFO_VECTOR_MASK) == vector &&
10789 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> INTR_INFO_INTR_TYPE_SHIFT) == intr_type,
10790 "%s correctly routed to L1", exception_mnemonic(vector));
10791
10792 vmcs_write(EXC_BITMAP, old_eb);
10793 }
10794
vmx_exception_test(void)10795 static void vmx_exception_test(void)
10796 {
10797 struct vmx_exception_test *t;
10798 int i;
10799
10800 for (i = 0; i < ARRAY_SIZE(vmx_exception_tests); i++) {
10801 t = &vmx_exception_tests[i];
10802
10803 /*
10804 * Override the guest code before each run even though it's the
10805 * same code, the VMCS guest state needs to be reinitialized.
10806 */
10807 test_override_guest(t->guest_code);
10808 handle_exception_in_l2(t->vector);
10809
10810 test_override_guest(t->guest_code);
10811 handle_exception_in_l1(t->vector);
10812 }
10813
10814 test_set_guest_finished();
10815 }
10816
10817 /*
10818 * Arbitrary canonical values for validating direct writes in the host, e.g. to
10819 * an MSR, and for indirect writes via loads from VMCS fields on VM-Exit.
10820 */
10821 #define TEST_DIRECT_VALUE 0xff45454545000000
10822 #define TEST_VMCS_VALUE 0xff55555555000000
10823
vmx_canonical_test_guest(void)10824 static void vmx_canonical_test_guest(void)
10825 {
10826 while (true)
10827 vmcall();
10828 }
10829
get_host_value(u64 vmcs_field,u64 * value)10830 static int get_host_value(u64 vmcs_field, u64 *value)
10831 {
10832 struct descriptor_table_ptr dt_ptr;
10833
10834 switch (vmcs_field) {
10835 case HOST_SYSENTER_ESP:
10836 *value = rdmsr(MSR_IA32_SYSENTER_ESP);
10837 break;
10838 case HOST_SYSENTER_EIP:
10839 *value = rdmsr(MSR_IA32_SYSENTER_EIP);
10840 break;
10841 case HOST_BASE_FS:
10842 *value = rdmsr(MSR_FS_BASE);
10843 break;
10844 case HOST_BASE_GS:
10845 *value = rdmsr(MSR_GS_BASE);
10846 break;
10847 case HOST_BASE_GDTR:
10848 sgdt(&dt_ptr);
10849 *value = dt_ptr.base;
10850 break;
10851 case HOST_BASE_IDTR:
10852 sidt(&dt_ptr);
10853 *value = dt_ptr.base;
10854 break;
10855 case HOST_BASE_TR:
10856 *value = get_gdt_entry_base(get_tss_descr());
10857 /* value might not reflect the actual base if changed by VMX */
10858 return 1;
10859 default:
10860 assert(0);
10861 return 1;
10862 }
10863 return 0;
10864 }
10865
set_host_value(u64 vmcs_field,u64 value)10866 static int set_host_value(u64 vmcs_field, u64 value)
10867 {
10868 struct descriptor_table_ptr dt_ptr;
10869
10870 switch (vmcs_field) {
10871 case HOST_SYSENTER_ESP:
10872 return wrmsr_safe(MSR_IA32_SYSENTER_ESP, value);
10873 case HOST_SYSENTER_EIP:
10874 return wrmsr_safe(MSR_IA32_SYSENTER_EIP, value);
10875 case HOST_BASE_FS:
10876 return wrmsr_safe(MSR_FS_BASE, value);
10877 case HOST_BASE_GS:
10878 /* TODO: _safe variants assume per-cpu gs base*/
10879 wrmsr(MSR_GS_BASE, value);
10880 return 0;
10881 case HOST_BASE_GDTR:
10882 sgdt(&dt_ptr);
10883 dt_ptr.base = value;
10884 lgdt(&dt_ptr);
10885 return lgdt_fep_safe(&dt_ptr);
10886 case HOST_BASE_IDTR:
10887 sidt(&dt_ptr);
10888 dt_ptr.base = value;
10889 return lidt_fep_safe(&dt_ptr);
10890 case HOST_BASE_TR:
10891 /* Set the base and clear the busy bit */
10892 set_gdt_entry(FIRST_SPARE_SEL, value, 0x200, 0x89, 0);
10893 return ltr_safe(FIRST_SPARE_SEL);
10894 default:
10895 assert(0);
10896 }
10897 }
10898
test_host_value_direct(const char * field_name,u64 vmcs_field)10899 static void test_host_value_direct(const char *field_name, u64 vmcs_field)
10900 {
10901 u64 value = 0;
10902 int vector;
10903
10904 /*
10905 * Set the directly register via host ISA (e.g lgdt) and check that we
10906 * got no exception.
10907 */
10908 vector = set_host_value(vmcs_field, TEST_DIRECT_VALUE);
10909 if (vector) {
10910 report_fail("Exception %d when setting %s to 0x%lx via direct write",
10911 vector, field_name, TEST_DIRECT_VALUE);
10912 return;
10913 }
10914
10915 /*
10916 * Now check that the host value matches what we expect for fields
10917 * that can be read back (these that we can't we assume that are correct)
10918 */
10919 report(get_host_value(vmcs_field, &value) || value == TEST_DIRECT_VALUE,
10920 "%s: HOST value set to 0x%lx (wanted 0x%lx) via direct write",
10921 field_name, value, TEST_DIRECT_VALUE);
10922 }
10923
test_host_value_vmcs(const char * field_name,u64 vmcs_field)10924 static void test_host_value_vmcs(const char *field_name, u64 vmcs_field)
10925 {
10926 u64 value = 0;
10927
10928 /* Set host state field in the vmcs and do the VM entry
10929 * Success of VM entry already shows that L0 accepted the value
10930 */
10931 vmcs_write(vmcs_field, TEST_VMCS_VALUE);
10932 enter_guest();
10933 skip_exit_vmcall();
10934
10935 /*
10936 * Now check that the host value matches what we expect for fields
10937 * that can be read back (these that we can't we assume that are correct)
10938 */
10939 report(get_host_value(vmcs_field, &value) || value == TEST_VMCS_VALUE,
10940 "%s: HOST value set to 0x%lx (wanted 0x%lx) via VMLAUNCH/VMRESUME",
10941 field_name, value, TEST_VMCS_VALUE);
10942 }
10943
do_vmx_canonical_test_one_field(const char * field_name,u64 field)10944 static void do_vmx_canonical_test_one_field(const char *field_name, u64 field)
10945 {
10946 u64 host_org_value, field_org_value;
10947
10948 /* Backup the current host value and vmcs field value values */
10949 get_host_value(field, &host_org_value);
10950 field_org_value = vmcs_read(field);
10951
10952 test_host_value_direct(field_name, field);
10953 test_host_value_vmcs(field_name, field);
10954
10955 /* Restore original values */
10956 vmcs_write(field, field_org_value);
10957 set_host_value(field, host_org_value);
10958 }
10959
10960 #define vmx_canonical_test_one_field(field) \
10961 do_vmx_canonical_test_one_field(#field, field)
10962
vmx_canonical_test(void)10963 static void vmx_canonical_test(void)
10964 {
10965 report(!(read_cr4() & X86_CR4_LA57), "4 level paging");
10966
10967 if (!this_cpu_has(X86_FEATURE_LA57))
10968 test_skip("5 level paging not supported");
10969
10970 test_set_guest(vmx_canonical_test_guest);
10971
10972 vmx_canonical_test_one_field(HOST_SYSENTER_ESP);
10973 vmx_canonical_test_one_field(HOST_SYSENTER_EIP);
10974 vmx_canonical_test_one_field(HOST_BASE_FS);
10975 vmx_canonical_test_one_field(HOST_BASE_GS);
10976 vmx_canonical_test_one_field(HOST_BASE_GDTR);
10977 vmx_canonical_test_one_field(HOST_BASE_IDTR);
10978 vmx_canonical_test_one_field(HOST_BASE_TR);
10979
10980 test_set_guest_finished();
10981 }
10982
10983 enum Vid_op {
10984 VID_OP_SET_ISR,
10985 VID_OP_NOP,
10986 VID_OP_SET_CR8,
10987 VID_OP_SELF_IPI,
10988 VID_OP_TERMINATE,
10989 VID_OP_SPIN,
10990 VID_OP_SPIN_IRR,
10991 VID_OP_HLT,
10992 };
10993
10994 struct vmx_basic_vid_test_guest_args {
10995 enum Vid_op op;
10996 u8 nr;
10997 u32 isr_exec_cnt;
10998 u32 *virtual_apic_page;
10999 u64 *pi_desc;
11000 u32 dest;
11001 bool in_guest;
11002 } vmx_basic_vid_test_guest_args;
11003
11004 /*
11005 * From the SDM, Bit x of the VIRR is
11006 * at bit position (x & 1FH)
11007 * at offset (200H | ((x & E0H) >> 1)).
11008 */
set_virr_bit(volatile u32 * virtual_apic_page,u8 nr)11009 static void set_virr_bit(volatile u32 *virtual_apic_page, u8 nr)
11010 {
11011 u32 page_offset = (0x200 | ((nr & 0xE0) >> 1)) / sizeof(u32);
11012 u32 mask = 1 << (nr & 0x1f);
11013
11014 virtual_apic_page[page_offset] |= mask;
11015 }
11016
clear_virr_bit(volatile u32 * virtual_apic_page,u8 nr)11017 static void clear_virr_bit(volatile u32 *virtual_apic_page, u8 nr)
11018 {
11019 u32 page_offset = (0x200 | ((nr & 0xE0) >> 1)) / sizeof(u32);
11020 u32 mask = 1 << (nr & 0x1f);
11021
11022 virtual_apic_page[page_offset] &= ~mask;
11023 }
11024
get_virr_bit(volatile u32 * virtual_apic_page,u8 nr)11025 static bool get_virr_bit(volatile u32 *virtual_apic_page, u8 nr)
11026 {
11027 u32 page_offset = (0x200 | ((nr & 0xE0) >> 1)) / sizeof(u32);
11028 u32 mask = 1 << (nr & 0x1f);
11029
11030 return virtual_apic_page[page_offset] & mask;
11031 }
11032
vmx_vid_test_isr(isr_regs_t * regs)11033 static void vmx_vid_test_isr(isr_regs_t *regs)
11034 {
11035 volatile struct vmx_basic_vid_test_guest_args *args =
11036 &vmx_basic_vid_test_guest_args;
11037
11038 args->isr_exec_cnt++;
11039 barrier();
11040 eoi();
11041 }
11042
vmx_basic_vid_test_guest(void)11043 static void vmx_basic_vid_test_guest(void)
11044 {
11045 volatile struct vmx_basic_vid_test_guest_args *args =
11046 &vmx_basic_vid_test_guest_args;
11047
11048 sti_nop();
11049 for (;;) {
11050 enum Vid_op op = args->op;
11051 u8 nr = args->nr;
11052
11053 switch (op) {
11054 case VID_OP_TERMINATE:
11055 return;
11056 case VID_OP_SET_ISR:
11057 handle_irq(nr, vmx_vid_test_isr);
11058 break;
11059 case VID_OP_SET_CR8:
11060 write_cr8(nr);
11061 break;
11062 case VID_OP_SELF_IPI:
11063 vmx_x2apic_write(APIC_SELF_IPI, nr);
11064 break;
11065 case VID_OP_HLT:
11066 cli();
11067 barrier();
11068 args->in_guest = true;
11069 barrier();
11070 safe_halt();
11071 break;
11072 case VID_OP_SPIN:
11073 args->in_guest = true;
11074 while (!args->isr_exec_cnt)
11075 pause();
11076 break;
11077 case VID_OP_SPIN_IRR: {
11078 u32 *virtual_apic_page = args->virtual_apic_page;
11079 u8 nr = args->nr;
11080
11081 args->in_guest = true;
11082 while (!get_virr_bit(virtual_apic_page, nr))
11083 pause();
11084 clear_virr_bit(virtual_apic_page, nr);
11085 break;
11086 }
11087 default:
11088 break;
11089 }
11090
11091 vmcall();
11092 }
11093 }
11094
set_isrs_for_vmx_basic_vid_test(void)11095 static void set_isrs_for_vmx_basic_vid_test(void)
11096 {
11097 volatile struct vmx_basic_vid_test_guest_args *args =
11098 &vmx_basic_vid_test_guest_args;
11099 u16 nr;
11100
11101 /*
11102 * kvm-unit-tests uses vector 32 for IPIs, so don't install a test ISR
11103 * for that vector.
11104 */
11105 for (nr = 0x21; nr < 0x100; nr++) {
11106 vmcs_write(GUEST_INT_STATUS, 0);
11107 args->virtual_apic_page = get_vapic_page();
11108 args->op = VID_OP_SET_ISR;
11109 args->nr = nr;
11110 args->isr_exec_cnt = 0;
11111 enter_guest();
11112 skip_exit_vmcall();
11113 }
11114 report(true, "Set ISR for vectors 33-255.");
11115 }
11116
vmx_posted_interrupts_test_worker(void * data)11117 static void vmx_posted_interrupts_test_worker(void *data)
11118 {
11119 volatile struct vmx_basic_vid_test_guest_args *args =
11120 &vmx_basic_vid_test_guest_args;
11121
11122 while (!args->in_guest)
11123 pause();
11124
11125 test_and_set_bit(args->nr, args->pi_desc);
11126 test_and_set_bit(256, args->pi_desc);
11127 apic_icr_write(PI_VECTOR, args->dest);
11128 }
11129
11130 /*
11131 * Test virtual interrupt delivery (VID) at VM-entry or TPR virtualization
11132 *
11133 * Args:
11134 * nr: vector under test
11135 * tpr: task priority under test
11136 * tpr_virt: If true, then test VID during TPR virtualization. Otherwise,
11137 * test VID during VM-entry.
11138 */
test_basic_vid(u8 nr,u8 tpr,enum Vid_op op,u32 isr_exec_cnt_want,bool eoi_exit_induced)11139 static void test_basic_vid(u8 nr, u8 tpr, enum Vid_op op, u32 isr_exec_cnt_want,
11140 bool eoi_exit_induced)
11141 {
11142 volatile struct vmx_basic_vid_test_guest_args *args =
11143 &vmx_basic_vid_test_guest_args;
11144 u16 rvi_want = isr_exec_cnt_want ? 0 : nr;
11145 u16 int_status;
11146
11147 /*
11148 * From the SDM:
11149 * IF "interrupt-window exiting" is 0 AND
11150 * RVI[7:4] > VPPR[7:4] (see Section 29.1.1 for definition of VPPR)
11151 * THEN recognize a pending virtual interrupt;
11152 * ELSE
11153 * do not recognize a pending virtual interrupt;
11154 * FI;
11155 *
11156 * Thus, VPPR dictates whether a virtual interrupt is recognized.
11157 * However, PPR virtualization, which occurs before virtual interrupt
11158 * delivery, sets VPPR to VTPR, when SVI is 0.
11159 */
11160 args->isr_exec_cnt = 0;
11161 args->virtual_apic_page = get_vapic_page();
11162 args->op = op;
11163 args->in_guest = false;
11164 switch (op) {
11165 case VID_OP_SELF_IPI:
11166 vmcs_write(GUEST_INT_STATUS, 0);
11167 args->nr = nr;
11168 set_vtpr(0);
11169 break;
11170 case VID_OP_SET_CR8:
11171 vmcs_write(GUEST_INT_STATUS, nr);
11172 args->nr = task_priority_class(tpr);
11173 set_vtpr(0xff);
11174 break;
11175 case VID_OP_SPIN:
11176 case VID_OP_SPIN_IRR:
11177 case VID_OP_HLT:
11178 vmcs_write(GUEST_INT_STATUS, 0);
11179 args->nr = nr;
11180 set_vtpr(tpr);
11181 barrier();
11182 on_cpu_async(1, vmx_posted_interrupts_test_worker, NULL);
11183 break;
11184 default:
11185 vmcs_write(GUEST_INT_STATUS, nr);
11186 set_vtpr(tpr);
11187 break;
11188 }
11189
11190 enter_guest();
11191 if (eoi_exit_induced) {
11192 u32 exit_cnt;
11193
11194 assert_exit_reason(VMX_EOI_INDUCED);
11195 for (exit_cnt = 1; exit_cnt < isr_exec_cnt_want; exit_cnt++) {
11196 enter_guest();
11197 assert_exit_reason(VMX_EOI_INDUCED);
11198 }
11199 enter_guest();
11200 }
11201 skip_exit_vmcall();
11202 TEST_ASSERT_EQ(args->isr_exec_cnt, isr_exec_cnt_want);
11203 int_status = vmcs_read(GUEST_INT_STATUS);
11204 TEST_ASSERT_EQ(int_status, rvi_want);
11205 }
11206
11207 /*
11208 * Test recognizing and delivering virtual interrupts via "Virtual-interrupt
11209 * delivery" for two scenarios:
11210 * 1. When there is a pending interrupt at VM-entry.
11211 * 2. When there is a pending interrupt during TPR virtualization.
11212 */
vmx_basic_vid_test(void)11213 static void vmx_basic_vid_test(void)
11214 {
11215 volatile struct vmx_basic_vid_test_guest_args *args =
11216 &vmx_basic_vid_test_guest_args;
11217 u8 nr_class;
11218
11219 if (!cpu_has_apicv()) {
11220 report_skip("%s : Not all required APICv bits supported", __func__);
11221 return;
11222 }
11223
11224 enable_vid();
11225 test_set_guest(vmx_basic_vid_test_guest);
11226 set_isrs_for_vmx_basic_vid_test();
11227
11228 for (nr_class = 2; nr_class < 16; nr_class++) {
11229 u16 nr;
11230 u8 nr_sub_class;
11231
11232 for (nr_sub_class = 0; nr_sub_class < 16; nr_sub_class++) {
11233 u16 tpr;
11234
11235 nr = (nr_class << 4) | nr_sub_class;
11236
11237 /*
11238 * Don't test the reserved IPI vector, as the test ISR
11239 * was not installed.
11240 */
11241 if (nr == 0x20)
11242 continue;
11243
11244 test_basic_vid(nr, /*tpr=*/0, VID_OP_SELF_IPI,
11245 /*isr_exec_cnt_want=*/1,
11246 /*eoi_exit_induced=*/false);
11247 for (tpr = 0; tpr < 256; tpr++) {
11248 u32 isr_exec_cnt_want =
11249 task_priority_class(nr) >
11250 task_priority_class(tpr) ? 1 : 0;
11251
11252 test_basic_vid(nr, tpr, VID_OP_NOP,
11253 isr_exec_cnt_want,
11254 /*eoi_exit_induced=*/false);
11255 test_basic_vid(nr, tpr, VID_OP_SET_CR8,
11256 isr_exec_cnt_want,
11257 /*eoi_exit_induced=*/false);
11258 }
11259 report(true, "TPR 0-255 for vector 0x%x.", nr);
11260 }
11261 }
11262
11263 /* Terminate the guest */
11264 args->op = VID_OP_TERMINATE;
11265 enter_guest();
11266 assert_exit_reason(VMX_VMCALL);
11267 }
11268
test_eoi_virt(u8 nr,u8 lo_pri_nr,bool eoi_exit_induced)11269 static void test_eoi_virt(u8 nr, u8 lo_pri_nr, bool eoi_exit_induced)
11270 {
11271 u32 *virtual_apic_page = get_vapic_page();
11272
11273 set_virr_bit(virtual_apic_page, lo_pri_nr);
11274 test_basic_vid(nr, /*tpr=*/0, VID_OP_NOP, /*isr_exec_cnt_want=*/2,
11275 eoi_exit_induced);
11276 TEST_ASSERT(!get_virr_bit(virtual_apic_page, lo_pri_nr));
11277 TEST_ASSERT(!get_virr_bit(virtual_apic_page, nr));
11278 }
11279
vmx_eoi_virt_test(void)11280 static void vmx_eoi_virt_test(void)
11281 {
11282 volatile struct vmx_basic_vid_test_guest_args *args =
11283 &vmx_basic_vid_test_guest_args;
11284 u16 nr;
11285 u16 lo_pri_nr;
11286
11287 if (!cpu_has_apicv()) {
11288 report_skip("%s : Not all required APICv bits supported", __func__);
11289 return;
11290 }
11291
11292 enable_vid(); /* Note, enable_vid sets APIC_VIRT_ADDR field in VMCS. */
11293 test_set_guest(vmx_basic_vid_test_guest);
11294 set_isrs_for_vmx_basic_vid_test();
11295
11296 /* Now test EOI virtualization without induced EOI exits. */
11297 for (nr = 0x22; nr < 0x100; nr++) {
11298 for (lo_pri_nr = 0x21; lo_pri_nr < nr; lo_pri_nr++)
11299 test_eoi_virt(nr, lo_pri_nr,
11300 /*eoi_exit_induced=*/false);
11301
11302 report(true, "Low priority nrs 0x21-0x%x for nr 0x%x.",
11303 nr - 1, nr);
11304 }
11305
11306 /* Finally, test EOI virtualization with induced EOI exits. */
11307 vmcs_write(EOI_EXIT_BITMAP0, GENMASK_ULL(63, 0));
11308 vmcs_write(EOI_EXIT_BITMAP1, GENMASK_ULL(63, 0));
11309 vmcs_write(EOI_EXIT_BITMAP2, GENMASK_ULL(63, 0));
11310 vmcs_write(EOI_EXIT_BITMAP3, GENMASK_ULL(63, 0));
11311 for (nr = 0x22; nr < 0x100; nr++) {
11312 for (lo_pri_nr = 0x21; lo_pri_nr < nr; lo_pri_nr++)
11313 test_eoi_virt(nr, lo_pri_nr,
11314 /*eoi_exit_induced=*/true);
11315
11316 report(true,
11317 "Low priority nrs 0x21-0x%x for nr 0x%x, with induced EOI exits.",
11318 nr - 1, nr);
11319 }
11320
11321 /* Terminate the guest */
11322 args->op = VID_OP_TERMINATE;
11323 enter_guest();
11324 assert_exit_reason(VMX_VMCALL);
11325 }
11326
vmx_posted_interrupts_test(void)11327 static void vmx_posted_interrupts_test(void)
11328 {
11329 volatile struct vmx_basic_vid_test_guest_args *args =
11330 &vmx_basic_vid_test_guest_args;
11331 u16 vector;
11332 u8 class;
11333
11334 if (!cpu_has_apicv()) {
11335 report_skip("%s : Not all required APICv bits supported", __func__);
11336 return;
11337 }
11338
11339 if (cpu_count() < 2) {
11340 report_skip("%s : CPU count < 2", __func__);
11341 return;
11342 }
11343
11344 enable_vid();
11345 enable_posted_interrupts();
11346 args->pi_desc = get_pi_desc();
11347 args->dest = apic_id();
11348
11349 test_set_guest(vmx_basic_vid_test_guest);
11350 set_isrs_for_vmx_basic_vid_test();
11351
11352 for (class = 0; class < 16; class++) {
11353 for (vector = 33; vector < 256; vector++) {
11354 /*
11355 * If the vector isn't above TPR, then the vector should
11356 * be moved from PIR to the IRR, but never serviced.
11357 *
11358 * Only test posted interrupts to a halted vCPU if the
11359 * interrupt is expected to be serviced. Otherwise, the
11360 * vCPU will HLT indefinitely.
11361 */
11362 if (task_priority_class(vector) <= class) {
11363 test_basic_vid(vector, class << 4,
11364 VID_OP_SPIN_IRR, 0, false);
11365 continue;
11366 }
11367
11368 test_basic_vid(vector, class << 4, VID_OP_SPIN, 1, false);
11369 test_basic_vid(vector, class << 4, VID_OP_HLT, 1, false);
11370 }
11371 }
11372 report(true, "Posted vectors 33-25 cross TPR classes 0-0xf, running and sometimes halted\n");
11373
11374 /* Terminate the guest */
11375 args->op = VID_OP_TERMINATE;
11376 enter_guest();
11377 }
11378
11379 #define TEST(name) { #name, .v2 = name }
11380
11381 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */
11382 struct vmx_test vmx_tests[] = {
11383 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} },
11384 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} },
11385 { "preemption timer", preemption_timer_init, preemption_timer_main,
11386 preemption_timer_exit_handler, NULL, {0} },
11387 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main,
11388 test_ctrl_pat_exit_handler, NULL, {0} },
11389 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main,
11390 test_ctrl_efer_exit_handler, NULL, {0} },
11391 { "CR shadowing", NULL, cr_shadowing_main,
11392 cr_shadowing_exit_handler, NULL, {0} },
11393 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler,
11394 NULL, {0} },
11395 { "instruction intercept", insn_intercept_init, insn_intercept_main,
11396 insn_intercept_exit_handler, NULL, {0} },
11397 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} },
11398 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} },
11399 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} },
11400 { "interrupt", interrupt_init, interrupt_main,
11401 interrupt_exit_handler, NULL, {0} },
11402 { "nmi_hlt", nmi_hlt_init, nmi_hlt_main,
11403 nmi_hlt_exit_handler, NULL, {0} },
11404 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler,
11405 NULL, {0} },
11406 { "MSR switch", msr_switch_init, msr_switch_main,
11407 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure },
11408 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} },
11409 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main,
11410 disable_rdtscp_exit_handler, NULL, {0} },
11411 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main,
11412 exit_monitor_from_l2_handler, NULL, {0} },
11413 { "invalid_msr", invalid_msr_init, invalid_msr_main,
11414 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure},
11415 /* Basic V2 tests. */
11416 TEST(v2_null_test),
11417 TEST(v2_multiple_entries_test),
11418 TEST(fixture_test_case1),
11419 TEST(fixture_test_case2),
11420 /* Opcode tests. */
11421 TEST(invvpid_test),
11422 /* VM-entry tests */
11423 TEST(vmx_controls_test),
11424 TEST(vmx_host_state_area_test),
11425 TEST(vmx_guest_state_area_test),
11426 TEST(vmentry_movss_shadow_test),
11427 TEST(vmentry_unrestricted_guest_test),
11428 /* APICv tests */
11429 TEST(vmx_eoi_bitmap_ioapic_scan_test),
11430 TEST(vmx_hlt_with_rvi_test),
11431 TEST(apic_reg_virt_test),
11432 TEST(virt_x2apic_mode_test),
11433 TEST(vmx_basic_vid_test),
11434 TEST(vmx_eoi_virt_test),
11435 TEST(vmx_posted_interrupts_test),
11436 /* APIC pass-through tests */
11437 TEST(vmx_apic_passthrough_test),
11438 TEST(vmx_apic_passthrough_thread_test),
11439 TEST(vmx_apic_passthrough_tpr_threshold_test),
11440 TEST(vmx_init_signal_test),
11441 TEST(vmx_sipi_signal_test),
11442 /* VMCS Shadowing tests */
11443 TEST(vmx_vmcs_shadow_test),
11444 /* Regression tests */
11445 TEST(vmx_ldtr_test),
11446 TEST(vmx_cr_load_test),
11447 TEST(vmx_cr4_osxsave_test),
11448 TEST(vmx_no_nm_test),
11449 TEST(vmx_db_test),
11450 TEST(vmx_nmi_window_test),
11451 TEST(vmx_intr_window_test),
11452 TEST(vmx_pending_event_test),
11453 TEST(vmx_pending_event_hlt_test),
11454 TEST(vmx_store_tsc_test),
11455 TEST(vmx_preemption_timer_zero_test),
11456 TEST(vmx_preemption_timer_tf_test),
11457 TEST(vmx_preemption_timer_expiry_test),
11458 /* EPT access tests. */
11459 TEST(ept_access_test_not_present),
11460 TEST(ept_access_test_read_only),
11461 TEST(ept_access_test_write_only),
11462 TEST(ept_access_test_read_write),
11463 TEST(ept_access_test_execute_only),
11464 TEST(ept_access_test_read_execute),
11465 TEST(ept_access_test_write_execute),
11466 TEST(ept_access_test_read_write_execute),
11467 TEST(ept_access_test_reserved_bits),
11468 TEST(ept_access_test_ignored_bits),
11469 TEST(ept_access_test_paddr_not_present_ad_disabled),
11470 TEST(ept_access_test_paddr_not_present_ad_enabled),
11471 TEST(ept_access_test_paddr_read_only_ad_disabled),
11472 TEST(ept_access_test_paddr_read_only_ad_enabled),
11473 TEST(ept_access_test_paddr_read_write),
11474 TEST(ept_access_test_paddr_read_write_execute),
11475 TEST(ept_access_test_paddr_read_execute_ad_disabled),
11476 TEST(ept_access_test_paddr_read_execute_ad_enabled),
11477 TEST(ept_access_test_paddr_not_present_page_fault),
11478 TEST(ept_access_test_force_2m_page),
11479 /* Atomic MSR switch tests. */
11480 TEST(atomic_switch_max_msrs_test),
11481 TEST(atomic_switch_overflow_msrs_test),
11482 TEST(rdtsc_vmexit_diff_test),
11483 TEST(vmx_mtf_test),
11484 TEST(vmx_mtf_pdpte_test),
11485 TEST(vmx_pf_exception_test),
11486 TEST(vmx_pf_exception_forced_emulation_test),
11487 TEST(vmx_pf_no_vpid_test),
11488 TEST(vmx_pf_invvpid_test),
11489 TEST(vmx_pf_vpid_test),
11490 TEST(vmx_exception_test),
11491 TEST(vmx_canonical_test),
11492 { NULL, NULL, NULL, NULL, NULL, {0} },
11493 };
11494