1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2014-2025 MediaTek Inc.
3 
4 /*
5  * Library for MediaTek External Interrupt Support
6  *
7  * Author: Maoguang Meng <maoguang.meng@mediatek.com>
8  *	   Sean Wang <sean.wang@mediatek.com>
9  *	   Hao Chang <ot_chhao.chang@mediatek.com>
10  *	   Qingliang Li <qingliang.li@mediatek.com>
11  *
12  */
13 
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/gpio/driver.h>
17 #include <linux/io.h>
18 #include <linux/irqchip/chained_irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/module.h>
21 #include <linux/of_irq.h>
22 #include <linux/platform_device.h>
23 
24 #include "mtk-eint.h"
25 #include "pinctrl-mtk-common-v2.h"
26 
27 #define MTK_EINT_EDGE_SENSITIVE           0
28 #define MTK_EINT_LEVEL_SENSITIVE          1
29 #define MTK_EINT_DBNC_SET_DBNC_BITS	  4
30 #define MTK_EINT_DBNC_MAX		  16
31 #define MTK_EINT_DBNC_RST_BIT		  (0x1 << 1)
32 #define MTK_EINT_DBNC_SET_EN		  (0x1 << 0)
33 
34 static const struct mtk_eint_regs mtk_generic_eint_regs = {
35 	.stat      = 0x000,
36 	.ack       = 0x040,
37 	.mask      = 0x080,
38 	.mask_set  = 0x0c0,
39 	.mask_clr  = 0x100,
40 	.sens      = 0x140,
41 	.sens_set  = 0x180,
42 	.sens_clr  = 0x1c0,
43 	.soft      = 0x200,
44 	.soft_set  = 0x240,
45 	.soft_clr  = 0x280,
46 	.pol       = 0x300,
47 	.pol_set   = 0x340,
48 	.pol_clr   = 0x380,
49 	.dom_en    = 0x400,
50 	.dbnc_ctrl = 0x500,
51 	.dbnc_set  = 0x600,
52 	.dbnc_clr  = 0x700,
53 };
54 
55 const unsigned int debounce_time_mt2701[] = {
56 	500, 1000, 16000, 32000, 64000, 128000, 256000, 0
57 };
58 EXPORT_SYMBOL_GPL(debounce_time_mt2701);
59 
60 const unsigned int debounce_time_mt6765[] = {
61 	125, 250, 500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
62 };
63 EXPORT_SYMBOL_GPL(debounce_time_mt6765);
64 
65 const unsigned int debounce_time_mt6795[] = {
66 	500, 1000, 16000, 32000, 64000, 128000, 256000, 512000, 0
67 };
68 EXPORT_SYMBOL_GPL(debounce_time_mt6795);
69 
mtk_eint_get_offset(struct mtk_eint * eint,unsigned int eint_num,unsigned int offset)70 static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
71 					 unsigned int eint_num,
72 					 unsigned int offset)
73 {
74 	unsigned int idx = eint->pins[eint_num].index;
75 	unsigned int inst = eint->pins[eint_num].instance;
76 	void __iomem *reg;
77 
78 	reg = eint->base[inst] + offset + (idx / 32 * 4);
79 
80 	return reg;
81 }
82 
mtk_eint_can_en_debounce(struct mtk_eint * eint,unsigned int eint_num)83 static unsigned int mtk_eint_can_en_debounce(struct mtk_eint *eint,
84 					     unsigned int eint_num)
85 {
86 	unsigned int sens;
87 	unsigned int bit = BIT(eint->pins[eint_num].index % 32);
88 	void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
89 						eint->regs->sens);
90 
91 	if (readl(reg) & bit)
92 		sens = MTK_EINT_LEVEL_SENSITIVE;
93 	else
94 		sens = MTK_EINT_EDGE_SENSITIVE;
95 
96 	if (eint->pins[eint_num].debounce && sens != MTK_EINT_EDGE_SENSITIVE)
97 		return 1;
98 	else
99 		return 0;
100 }
101 
mtk_eint_flip_edge(struct mtk_eint * eint,int hwirq)102 static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq)
103 {
104 	int start_level, curr_level;
105 	unsigned int reg_offset;
106 	unsigned int mask = BIT(eint->pins[hwirq].index & 0x1f);
107 	unsigned int port = (eint->pins[hwirq].index >> 5) & eint->hw->port_mask;
108 	void __iomem *reg = eint->base[eint->pins[hwirq].instance] + (port << 2);
109 
110 	curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq);
111 
112 	do {
113 		start_level = curr_level;
114 		if (start_level)
115 			reg_offset = eint->regs->pol_clr;
116 		else
117 			reg_offset = eint->regs->pol_set;
118 		writel(mask, reg + reg_offset);
119 
120 		curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl,
121 							      hwirq);
122 	} while (start_level != curr_level);
123 
124 	return start_level;
125 }
126 
mtk_eint_mask(struct irq_data * d)127 static void mtk_eint_mask(struct irq_data *d)
128 {
129 	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
130 	unsigned int idx = eint->pins[d->hwirq].index;
131 	unsigned int inst = eint->pins[d->hwirq].instance;
132 	unsigned int mask = BIT(idx & 0x1f);
133 	void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
134 						eint->regs->mask_set);
135 
136 	eint->cur_mask[inst][idx >> 5] &= ~mask;
137 
138 	writel(mask, reg);
139 }
140 
mtk_eint_unmask(struct irq_data * d)141 static void mtk_eint_unmask(struct irq_data *d)
142 {
143 	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
144 	unsigned int idx = eint->pins[d->hwirq].index;
145 	unsigned int inst = eint->pins[d->hwirq].instance;
146 	unsigned int mask = BIT(idx & 0x1f);
147 	void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
148 						eint->regs->mask_clr);
149 
150 	eint->cur_mask[inst][idx >> 5] |= mask;
151 
152 	writel(mask, reg);
153 
154 	if (eint->pins[d->hwirq].dual_edge)
155 		mtk_eint_flip_edge(eint, d->hwirq);
156 }
157 
mtk_eint_get_mask(struct mtk_eint * eint,unsigned int eint_num)158 static unsigned int mtk_eint_get_mask(struct mtk_eint *eint,
159 				      unsigned int eint_num)
160 {
161 	unsigned int bit = BIT(eint->pins[eint_num].index % 32);
162 	void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
163 						eint->regs->mask);
164 
165 	return !!(readl(reg) & bit);
166 }
167 
mtk_eint_ack(struct irq_data * d)168 static void mtk_eint_ack(struct irq_data *d)
169 {
170 	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
171 	unsigned int mask = BIT(eint->pins[d->hwirq].index & 0x1f);
172 	void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
173 						eint->regs->ack);
174 
175 	writel(mask, reg);
176 }
177 
mtk_eint_set_type(struct irq_data * d,unsigned int type)178 static int mtk_eint_set_type(struct irq_data *d, unsigned int type)
179 {
180 	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
181 	bool masked;
182 	unsigned int mask = BIT(eint->pins[d->hwirq].index & 0x1f);
183 	void __iomem *reg;
184 
185 	if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
186 	    ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
187 		dev_err(eint->dev,
188 			"Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
189 			d->irq, d->hwirq, type);
190 		return -EINVAL;
191 	}
192 
193 	if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
194 		eint->pins[d->hwirq].dual_edge = 1;
195 	else
196 		eint->pins[d->hwirq].dual_edge = 0;
197 
198 	if (!mtk_eint_get_mask(eint, d->hwirq)) {
199 		mtk_eint_mask(d);
200 		masked = false;
201 	} else {
202 		masked = true;
203 	}
204 
205 	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
206 		reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr);
207 		writel(mask, reg);
208 	} else {
209 		reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_set);
210 		writel(mask, reg);
211 	}
212 
213 	if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
214 		reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr);
215 		writel(mask, reg);
216 	} else {
217 		reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_set);
218 		writel(mask, reg);
219 	}
220 
221 	mtk_eint_ack(d);
222 	if (!masked)
223 		mtk_eint_unmask(d);
224 
225 	return 0;
226 }
227 
mtk_eint_irq_set_wake(struct irq_data * d,unsigned int on)228 static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
229 {
230 	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
231 	unsigned int idx = eint->pins[d->hwirq].index;
232 	unsigned int inst = eint->pins[d->hwirq].instance;
233 	unsigned int shift = idx & 0x1f;
234 	unsigned int port = idx >> 5;
235 
236 	if (on)
237 		eint->wake_mask[inst][port] |= BIT(shift);
238 	else
239 		eint->wake_mask[inst][port] &= ~BIT(shift);
240 
241 	return 0;
242 }
243 
mtk_eint_chip_write_mask(const struct mtk_eint * eint,void __iomem * base,unsigned int ** buf)244 static void mtk_eint_chip_write_mask(const struct mtk_eint *eint,
245 				     void __iomem *base, unsigned int **buf)
246 {
247 	int inst, port, port_num;
248 	void __iomem *reg;
249 
250 	for (inst = 0; inst < eint->nbase; inst++) {
251 		port_num = DIV_ROUND_UP(eint->base_pin_num[inst], 32);
252 		for (port = 0; port < port_num; port++) {
253 			reg = eint->base[inst] + (port << 2);
254 			writel_relaxed(~buf[inst][port], reg + eint->regs->mask_set);
255 			writel_relaxed(buf[inst][port], reg + eint->regs->mask_clr);
256 		}
257 	}
258 }
259 
mtk_eint_irq_request_resources(struct irq_data * d)260 static int mtk_eint_irq_request_resources(struct irq_data *d)
261 {
262 	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
263 	struct gpio_chip *gpio_c;
264 	unsigned int gpio_n;
265 	int err;
266 
267 	err = eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq,
268 					   &gpio_n, &gpio_c);
269 	if (err < 0) {
270 		dev_err(eint->dev, "Can not find pin\n");
271 		return err;
272 	}
273 
274 	err = gpiochip_lock_as_irq(gpio_c, gpio_n);
275 	if (err < 0) {
276 		dev_err(eint->dev, "unable to lock HW IRQ %lu for IRQ\n",
277 			irqd_to_hwirq(d));
278 		return err;
279 	}
280 
281 	err = eint->gpio_xlate->set_gpio_as_eint(eint->pctl, d->hwirq);
282 	if (err < 0) {
283 		dev_err(eint->dev, "Can not eint mode\n");
284 		return err;
285 	}
286 
287 	return 0;
288 }
289 
mtk_eint_irq_release_resources(struct irq_data * d)290 static void mtk_eint_irq_release_resources(struct irq_data *d)
291 {
292 	struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
293 	struct gpio_chip *gpio_c;
294 	unsigned int gpio_n;
295 
296 	eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, &gpio_n,
297 				     &gpio_c);
298 
299 	gpiochip_unlock_as_irq(gpio_c, gpio_n);
300 }
301 
302 static struct irq_chip mtk_eint_irq_chip = {
303 	.name = "mt-eint",
304 	.irq_disable = mtk_eint_mask,
305 	.irq_mask = mtk_eint_mask,
306 	.irq_unmask = mtk_eint_unmask,
307 	.irq_ack = mtk_eint_ack,
308 	.irq_set_type = mtk_eint_set_type,
309 	.irq_set_wake = mtk_eint_irq_set_wake,
310 	.irq_request_resources = mtk_eint_irq_request_resources,
311 	.irq_release_resources = mtk_eint_irq_release_resources,
312 };
313 
mtk_eint_hw_init(struct mtk_eint * eint)314 static unsigned int mtk_eint_hw_init(struct mtk_eint *eint)
315 {
316 	void __iomem *dom_reg, *mask_reg;
317 	unsigned int i, j;
318 
319 	for (i = 0; i < eint->nbase; i++) {
320 		dom_reg = eint->base[i] + eint->regs->dom_en;
321 		mask_reg = eint->base[i] + eint->regs->mask_set;
322 		for (j = 0; j < eint->base_pin_num[i]; j += 32) {
323 			writel(0xffffffff, dom_reg);
324 			writel(0xffffffff, mask_reg);
325 			dom_reg += 4;
326 			mask_reg += 4;
327 		}
328 	}
329 
330 	return 0;
331 }
332 
333 static inline void
mtk_eint_debounce_process(struct mtk_eint * eint,int index)334 mtk_eint_debounce_process(struct mtk_eint *eint, int index)
335 {
336 	unsigned int rst, ctrl_offset;
337 	unsigned int bit, dbnc;
338 	unsigned int inst = eint->pins[index].instance;
339 	unsigned int idx = eint->pins[index].index;
340 
341 	ctrl_offset = (idx / 4) * 4 + eint->regs->dbnc_ctrl;
342 	dbnc = readl(eint->base[inst] + ctrl_offset);
343 	bit = MTK_EINT_DBNC_SET_EN << ((idx % 4) * 8);
344 	if ((bit & dbnc) > 0) {
345 		ctrl_offset = (idx / 4) * 4 + eint->regs->dbnc_set;
346 		rst = MTK_EINT_DBNC_RST_BIT << ((idx % 4) * 8);
347 		writel(rst, eint->base[inst] + ctrl_offset);
348 	}
349 }
350 
mtk_eint_irq_handler(struct irq_desc * desc)351 static void mtk_eint_irq_handler(struct irq_desc *desc)
352 {
353 	struct irq_chip *chip = irq_desc_get_chip(desc);
354 	struct mtk_eint *eint = irq_desc_get_handler_data(desc);
355 	unsigned int i, j, port, status, shift, mask, eint_num;
356 	void __iomem *reg;
357 	int dual_edge, start_level, curr_level;
358 
359 	chained_irq_enter(chip, desc);
360 	for (i = 0; i < eint->nbase; i++) {
361 		for (j = 0; j < eint->base_pin_num[i]; j += 32) {
362 			port = j >> 5;
363 			status = readl(eint->base[i] + port * 4 + eint->regs->stat);
364 			while (status) {
365 				shift = __ffs(status);
366 				status &= ~BIT(shift);
367 				mask = BIT(shift);
368 				eint_num = eint->pin_list[i][shift + j];
369 
370 				/*
371 				 * If we get an interrupt on pin that was only required
372 				 * for wake (but no real interrupt requested), mask the
373 				 * interrupt (as would mtk_eint_resume do anyway later
374 				 * in the resume sequence).
375 				 */
376 				if (eint->wake_mask[i][port] & mask &&
377 				    !(eint->cur_mask[i][port] & mask)) {
378 					reg = mtk_eint_get_offset(eint, eint_num,
379 								  eint->regs->mask_set);
380 					writel_relaxed(mask, reg);
381 				}
382 
383 				dual_edge = eint->pins[eint_num].dual_edge;
384 				if (dual_edge) {
385 					/*
386 					 * Clear soft-irq in case we raised it last
387 					 * time.
388 					 */
389 					reg = mtk_eint_get_offset(eint, eint_num,
390 								  eint->regs->soft_clr);
391 					writel(mask, reg);
392 
393 					start_level =
394 					eint->gpio_xlate->get_gpio_state(eint->pctl,
395 									 eint_num);
396 				}
397 
398 				generic_handle_domain_irq(eint->domain, eint_num);
399 
400 				if (dual_edge) {
401 					curr_level = mtk_eint_flip_edge(eint, eint_num);
402 
403 					/*
404 					 * If level changed, we might lost one edge
405 					 * interrupt, raised it through soft-irq.
406 					 */
407 					if (start_level != curr_level) {
408 						reg = mtk_eint_get_offset(eint, eint_num,
409 									  eint->regs->soft_set);
410 						writel(mask, reg);
411 					}
412 				}
413 
414 				if (eint->pins[eint_num].debounce)
415 					mtk_eint_debounce_process(eint, eint_num);
416 			}
417 		}
418 	}
419 	chained_irq_exit(chip, desc);
420 }
421 
mtk_eint_do_suspend(struct mtk_eint * eint)422 int mtk_eint_do_suspend(struct mtk_eint *eint)
423 {
424 	mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask);
425 
426 	return 0;
427 }
428 EXPORT_SYMBOL_GPL(mtk_eint_do_suspend);
429 
mtk_eint_do_resume(struct mtk_eint * eint)430 int mtk_eint_do_resume(struct mtk_eint *eint)
431 {
432 	mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask);
433 
434 	return 0;
435 }
436 EXPORT_SYMBOL_GPL(mtk_eint_do_resume);
437 
mtk_eint_set_debounce(struct mtk_eint * eint,unsigned long eint_num,unsigned int debounce)438 int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num,
439 			  unsigned int debounce)
440 {
441 	int virq, eint_offset;
442 	unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask,
443 		     dbnc;
444 	unsigned int inst = eint->pins[eint_num].instance;
445 	unsigned int idx = eint->pins[eint_num].index;
446 	struct irq_data *d;
447 
448 	if (!eint->hw->db_time)
449 		return -EOPNOTSUPP;
450 
451 	virq = irq_find_mapping(eint->domain, eint_num);
452 	eint_offset = (idx % 4) * 8;
453 	d = irq_get_irq_data(virq);
454 
455 	set_offset = (idx / 4) * 4 + eint->regs->dbnc_set;
456 	clr_offset = (idx / 4) * 4 + eint->regs->dbnc_clr;
457 
458 	if (!mtk_eint_can_en_debounce(eint, eint_num))
459 		return -EINVAL;
460 
461 	dbnc = eint->num_db_time;
462 	for (i = 0; i < eint->num_db_time; i++) {
463 		if (debounce <= eint->hw->db_time[i]) {
464 			dbnc = i;
465 			break;
466 		}
467 	}
468 
469 	if (!mtk_eint_get_mask(eint, eint_num)) {
470 		mtk_eint_mask(d);
471 		unmask = 1;
472 	} else {
473 		unmask = 0;
474 	}
475 
476 	clr_bit = 0xff << eint_offset;
477 	writel(clr_bit, eint->base[inst] + clr_offset);
478 
479 	bit = ((dbnc << MTK_EINT_DBNC_SET_DBNC_BITS) | MTK_EINT_DBNC_SET_EN) <<
480 		eint_offset;
481 	rst = MTK_EINT_DBNC_RST_BIT << eint_offset;
482 	writel(rst | bit, eint->base[inst] + set_offset);
483 
484 	/*
485 	 * Delay a while (more than 2T) to wait for hw debounce counter reset
486 	 * work correctly.
487 	 */
488 	udelay(1);
489 	if (unmask == 1)
490 		mtk_eint_unmask(d);
491 
492 	return 0;
493 }
494 EXPORT_SYMBOL_GPL(mtk_eint_set_debounce);
495 
mtk_eint_find_irq(struct mtk_eint * eint,unsigned long eint_n)496 int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
497 {
498 	int irq;
499 
500 	irq = irq_find_mapping(eint->domain, eint_n);
501 	if (!irq)
502 		return -EINVAL;
503 
504 	return irq;
505 }
506 EXPORT_SYMBOL_GPL(mtk_eint_find_irq);
507 
mtk_eint_do_init(struct mtk_eint * eint)508 int mtk_eint_do_init(struct mtk_eint *eint)
509 {
510 	unsigned int size, i, port, inst = 0;
511 	struct mtk_pinctrl *hw = (struct mtk_pinctrl *)eint->pctl;
512 
513 	/* If clients don't assign a specific regs, let's use generic one */
514 	if (!eint->regs)
515 		eint->regs = &mtk_generic_eint_regs;
516 
517 	eint->base_pin_num = devm_kmalloc_array(eint->dev, eint->nbase, sizeof(u16),
518 						GFP_KERNEL | __GFP_ZERO);
519 	if (!eint->base_pin_num)
520 		return -ENOMEM;
521 
522 	if (eint->nbase == 1) {
523 		size = eint->hw->ap_num * sizeof(struct mtk_eint_pin);
524 		eint->pins = devm_kmalloc(eint->dev, size, GFP_KERNEL);
525 		if (!eint->pins)
526 			goto err_pins;
527 
528 		eint->base_pin_num[inst] = eint->hw->ap_num;
529 		for (i = 0; i < eint->hw->ap_num; i++) {
530 			eint->pins[i].instance = inst;
531 			eint->pins[i].index = i;
532 			eint->pins[i].debounce = (i < eint->hw->db_cnt) ? 1 : 0;
533 		}
534 	}
535 
536 	if (hw && hw->soc && hw->soc->eint_pin) {
537 		eint->pins = hw->soc->eint_pin;
538 		for (i = 0; i < eint->hw->ap_num; i++) {
539 			inst = eint->pins[i].instance;
540 			if (inst >= eint->nbase)
541 				continue;
542 			eint->base_pin_num[inst]++;
543 		}
544 	}
545 
546 	eint->pin_list = devm_kmalloc(eint->dev, eint->nbase * sizeof(u16 *), GFP_KERNEL);
547 	if (!eint->pin_list)
548 		goto err_pin_list;
549 
550 	eint->wake_mask = devm_kmalloc(eint->dev, eint->nbase * sizeof(u32 *), GFP_KERNEL);
551 	if (!eint->wake_mask)
552 		goto err_wake_mask;
553 
554 	eint->cur_mask = devm_kmalloc(eint->dev, eint->nbase * sizeof(u32 *), GFP_KERNEL);
555 	if (!eint->cur_mask)
556 		goto err_cur_mask;
557 
558 	for (i = 0; i < eint->nbase; i++) {
559 		eint->pin_list[i] = devm_kzalloc(eint->dev, eint->base_pin_num[i] * sizeof(u16),
560 						 GFP_KERNEL);
561 		port = DIV_ROUND_UP(eint->base_pin_num[i], 32);
562 		eint->wake_mask[i] = devm_kzalloc(eint->dev, port * sizeof(u32), GFP_KERNEL);
563 		eint->cur_mask[i] = devm_kzalloc(eint->dev, port * sizeof(u32), GFP_KERNEL);
564 		if (!eint->pin_list[i] || !eint->wake_mask[i] || !eint->cur_mask[i])
565 			goto err_eint;
566 	}
567 
568 	eint->domain = irq_domain_add_linear(eint->dev->of_node,
569 					     eint->hw->ap_num,
570 					     &irq_domain_simple_ops, NULL);
571 	if (!eint->domain)
572 		goto err_eint;
573 
574 	if (eint->hw->db_time) {
575 		for (i = 0; i < MTK_EINT_DBNC_MAX; i++)
576 			if (eint->hw->db_time[i] == 0)
577 				break;
578 		eint->num_db_time = i;
579 	}
580 
581 	mtk_eint_hw_init(eint);
582 	for (i = 0; i < eint->hw->ap_num; i++) {
583 		inst = eint->pins[i].instance;
584 		if (inst >= eint->nbase)
585 			continue;
586 		eint->pin_list[inst][eint->pins[i].index] = i;
587 		int virq = irq_create_mapping(eint->domain, i);
588 		irq_set_chip_and_handler(virq, &mtk_eint_irq_chip,
589 					 handle_level_irq);
590 		irq_set_chip_data(virq, eint);
591 	}
592 
593 	irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler,
594 					 eint);
595 
596 	return 0;
597 
598 err_eint:
599 	for (i = 0; i < eint->nbase; i++) {
600 		if (eint->cur_mask[i])
601 			devm_kfree(eint->dev, eint->cur_mask[i]);
602 		if (eint->wake_mask[i])
603 			devm_kfree(eint->dev, eint->wake_mask[i]);
604 		if (eint->pin_list[i])
605 			devm_kfree(eint->dev, eint->pin_list[i]);
606 	}
607 	devm_kfree(eint->dev, eint->cur_mask);
608 err_cur_mask:
609 	devm_kfree(eint->dev, eint->wake_mask);
610 err_wake_mask:
611 	devm_kfree(eint->dev, eint->pin_list);
612 err_pin_list:
613 	if (eint->nbase == 1)
614 		devm_kfree(eint->dev, eint->pins);
615 err_pins:
616 	devm_kfree(eint->dev, eint->base_pin_num);
617 	return -ENOMEM;
618 }
619 EXPORT_SYMBOL_GPL(mtk_eint_do_init);
620 
621 MODULE_LICENSE("GPL v2");
622 MODULE_DESCRIPTION("MediaTek EINT Driver");
623