1 /*
2 * STM32L4X5 RCC (Reset and clock control)
3 *
4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
6 *
7 * SPDX-License-Identifier: GPL-2.0-or-later
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
11 *
12 * The reference used is the STMicroElectronics RM0351 Reference manual
13 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
14 *
15 * Inspired by the BCM2835 CPRMAN clock manager implementation by Luc Michel.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qemu/log.h"
20 #include "qemu/module.h"
21 #include "qemu/timer.h"
22 #include "qapi/error.h"
23 #include "migration/vmstate.h"
24 #include "hw/misc/stm32l4x5_rcc.h"
25 #include "hw/misc/stm32l4x5_rcc_internals.h"
26 #include "hw/clock.h"
27 #include "hw/irq.h"
28 #include "hw/qdev-clock.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
31 #include "hw/registerfields.h"
32 #include "trace.h"
33
34 #define HSE_DEFAULT_FRQ 48000000ULL
35 #define HSI_FRQ 16000000ULL
36 #define MSI_DEFAULT_FRQ 4000000ULL
37 #define LSE_FRQ 32768ULL
38 #define LSI_FRQ 32000ULL
39
40 /*
41 * Function to simply acknowledge and propagate changes in a clock mux
42 * frequency.
43 * `bypass_source` allows to bypass the period of the current source and just
44 * consider it equal to 0. This is useful during the hold phase of reset.
45 */
clock_mux_update(RccClockMuxState * mux,bool bypass_source)46 static void clock_mux_update(RccClockMuxState *mux, bool bypass_source)
47 {
48 uint64_t src_freq;
49 Clock *current_source = mux->srcs[mux->src];
50 uint32_t freq_multiplier = 0;
51 bool clk_changed = false;
52
53 /*
54 * To avoid rounding errors, we use the clock period instead of the
55 * frequency.
56 * This means that the multiplier of the mux becomes the divider of
57 * the clock and the divider of the mux becomes the multiplier of the
58 * clock.
59 */
60 if (!bypass_source && mux->enabled && mux->divider) {
61 freq_multiplier = mux->divider;
62 }
63
64 clk_changed |= clock_set_mul_div(mux->out, freq_multiplier, mux->multiplier);
65 clk_changed |= clock_set(mux->out, clock_get(current_source));
66 if (clk_changed) {
67 clock_propagate(mux->out);
68 }
69
70 src_freq = clock_get_hz(current_source);
71 /* TODO: can we simply detect if the config changed so that we reduce log spam ? */
72 trace_stm32l4x5_rcc_mux_update(mux->id, mux->src, src_freq,
73 mux->multiplier, mux->divider);
74 }
75
clock_mux_src_update(void * opaque,ClockEvent event)76 static void clock_mux_src_update(void *opaque, ClockEvent event)
77 {
78 RccClockMuxState **backref = opaque;
79 RccClockMuxState *s = *backref;
80 /*
81 * The backref value is equal to:
82 * s->backref + (sizeof(RccClockMuxState *) * update_src).
83 * By subtracting we can get back the index of the updated clock.
84 */
85 const uint32_t update_src = backref - s->backref;
86 /* Only update if the clock that was updated is the current source */
87 if (update_src == s->src) {
88 clock_mux_update(s, false);
89 }
90 }
91
clock_mux_init(Object * obj)92 static void clock_mux_init(Object *obj)
93 {
94 RccClockMuxState *s = RCC_CLOCK_MUX(obj);
95 size_t i;
96
97 for (i = 0; i < RCC_NUM_CLOCK_MUX_SRC; i++) {
98 char *name = g_strdup_printf("srcs[%zu]", i);
99 s->backref[i] = s;
100 s->srcs[i] = qdev_init_clock_in(DEVICE(s), name,
101 clock_mux_src_update,
102 &s->backref[i],
103 ClockUpdate);
104 g_free(name);
105 }
106
107 s->out = qdev_init_clock_out(DEVICE(s), "out");
108 }
109
clock_mux_reset_enter(Object * obj,ResetType type)110 static void clock_mux_reset_enter(Object *obj, ResetType type)
111 {
112 RccClockMuxState *s = RCC_CLOCK_MUX(obj);
113 set_clock_mux_init_info(s, s->id);
114 }
115
clock_mux_reset_hold(Object * obj,ResetType type)116 static void clock_mux_reset_hold(Object *obj, ResetType type)
117 {
118 RccClockMuxState *s = RCC_CLOCK_MUX(obj);
119 clock_mux_update(s, true);
120 }
121
clock_mux_reset_exit(Object * obj,ResetType type)122 static void clock_mux_reset_exit(Object *obj, ResetType type)
123 {
124 RccClockMuxState *s = RCC_CLOCK_MUX(obj);
125 clock_mux_update(s, false);
126 }
127
128 static const VMStateDescription clock_mux_vmstate = {
129 .name = TYPE_RCC_CLOCK_MUX,
130 .version_id = 1,
131 .minimum_version_id = 1,
132 .fields = (VMStateField[]) {
133 VMSTATE_UINT32(id, RccClockMuxState),
134 VMSTATE_ARRAY_CLOCK(srcs, RccClockMuxState,
135 RCC_NUM_CLOCK_MUX_SRC),
136 VMSTATE_BOOL(enabled, RccClockMuxState),
137 VMSTATE_UINT32(src, RccClockMuxState),
138 VMSTATE_UINT32(multiplier, RccClockMuxState),
139 VMSTATE_UINT32(divider, RccClockMuxState),
140 VMSTATE_END_OF_LIST()
141 }
142 };
143
clock_mux_class_init(ObjectClass * klass,const void * data)144 static void clock_mux_class_init(ObjectClass *klass, const void *data)
145 {
146 DeviceClass *dc = DEVICE_CLASS(klass);
147 ResettableClass *rc = RESETTABLE_CLASS(klass);
148
149 rc->phases.enter = clock_mux_reset_enter;
150 rc->phases.hold = clock_mux_reset_hold;
151 rc->phases.exit = clock_mux_reset_exit;
152 dc->vmsd = &clock_mux_vmstate;
153 /* Reason: Part of Stm32l4x5RccState component */
154 dc->user_creatable = false;
155 }
156
clock_mux_set_enable(RccClockMuxState * mux,bool enabled)157 static void clock_mux_set_enable(RccClockMuxState *mux, bool enabled)
158 {
159 if (mux->enabled == enabled) {
160 return;
161 }
162
163 if (enabled) {
164 trace_stm32l4x5_rcc_mux_enable(mux->id);
165 } else {
166 trace_stm32l4x5_rcc_mux_disable(mux->id);
167 }
168
169 mux->enabled = enabled;
170 clock_mux_update(mux, false);
171 }
172
clock_mux_set_factor(RccClockMuxState * mux,uint32_t multiplier,uint32_t divider)173 static void clock_mux_set_factor(RccClockMuxState *mux,
174 uint32_t multiplier, uint32_t divider)
175 {
176 if (mux->multiplier == multiplier && mux->divider == divider) {
177 return;
178 }
179 trace_stm32l4x5_rcc_mux_set_factor(mux->id,
180 mux->multiplier, multiplier, mux->divider, divider);
181
182 mux->multiplier = multiplier;
183 mux->divider = divider;
184 clock_mux_update(mux, false);
185 }
186
clock_mux_set_source(RccClockMuxState * mux,RccClockMuxSource src)187 static void clock_mux_set_source(RccClockMuxState *mux, RccClockMuxSource src)
188 {
189 if (mux->src == src) {
190 return;
191 }
192
193 trace_stm32l4x5_rcc_mux_set_src(mux->id, mux->src, src);
194 mux->src = src;
195 clock_mux_update(mux, false);
196 }
197
198 /*
199 * Acknowledge and propagate changes in a PLL frequency.
200 * `bypass_source` allows to bypass the period of the current source and just
201 * consider it equal to 0. This is useful during the hold phase of reset.
202 */
pll_update(RccPllState * pll,bool bypass_source)203 static void pll_update(RccPllState *pll, bool bypass_source)
204 {
205 uint64_t vco_freq, old_channel_freq, channel_freq;
206 int i;
207
208 /* The common PLLM factor is handled by the PLL mux */
209 vco_freq = muldiv64(clock_get_hz(pll->in), pll->vco_multiplier, 1);
210
211 for (i = 0; i < RCC_NUM_CHANNEL_PLL_OUT; i++) {
212 if (!pll->channel_exists[i]) {
213 continue;
214 }
215
216 old_channel_freq = clock_get_hz(pll->channels[i]);
217 if (bypass_source ||
218 !pll->enabled ||
219 !pll->channel_enabled[i] ||
220 !pll->channel_divider[i]) {
221 channel_freq = 0;
222 } else {
223 channel_freq = muldiv64(vco_freq,
224 1,
225 pll->channel_divider[i]);
226 }
227
228 /* No change, early continue to avoid log spam and useless propagation */
229 if (old_channel_freq == channel_freq) {
230 continue;
231 }
232
233 clock_update_hz(pll->channels[i], channel_freq);
234 trace_stm32l4x5_rcc_pll_update(pll->id, i, vco_freq,
235 old_channel_freq, channel_freq);
236 }
237 }
238
pll_src_update(void * opaque,ClockEvent event)239 static void pll_src_update(void *opaque, ClockEvent event)
240 {
241 RccPllState *s = opaque;
242 pll_update(s, false);
243 }
244
pll_init(Object * obj)245 static void pll_init(Object *obj)
246 {
247 RccPllState *s = RCC_PLL(obj);
248 size_t i;
249
250 s->in = qdev_init_clock_in(DEVICE(s), "in",
251 pll_src_update, s, ClockUpdate);
252
253 const char *names[] = {
254 "out-p", "out-q", "out-r",
255 };
256
257 for (i = 0; i < RCC_NUM_CHANNEL_PLL_OUT; i++) {
258 s->channels[i] = qdev_init_clock_out(DEVICE(s), names[i]);
259 }
260 }
261
pll_reset_enter(Object * obj,ResetType type)262 static void pll_reset_enter(Object *obj, ResetType type)
263 {
264 RccPllState *s = RCC_PLL(obj);
265 set_pll_init_info(s, s->id);
266 }
267
pll_reset_hold(Object * obj,ResetType type)268 static void pll_reset_hold(Object *obj, ResetType type)
269 {
270 RccPllState *s = RCC_PLL(obj);
271 pll_update(s, true);
272 }
273
pll_reset_exit(Object * obj,ResetType type)274 static void pll_reset_exit(Object *obj, ResetType type)
275 {
276 RccPllState *s = RCC_PLL(obj);
277 pll_update(s, false);
278 }
279
280 static const VMStateDescription pll_vmstate = {
281 .name = TYPE_RCC_PLL,
282 .version_id = 1,
283 .minimum_version_id = 1,
284 .fields = (VMStateField[]) {
285 VMSTATE_UINT32(id, RccPllState),
286 VMSTATE_CLOCK(in, RccPllState),
287 VMSTATE_ARRAY_CLOCK(channels, RccPllState,
288 RCC_NUM_CHANNEL_PLL_OUT),
289 VMSTATE_BOOL(enabled, RccPllState),
290 VMSTATE_UINT32(vco_multiplier, RccPllState),
291 VMSTATE_BOOL_ARRAY(channel_enabled, RccPllState, RCC_NUM_CHANNEL_PLL_OUT),
292 VMSTATE_BOOL_ARRAY(channel_exists, RccPllState, RCC_NUM_CHANNEL_PLL_OUT),
293 VMSTATE_UINT32_ARRAY(channel_divider, RccPllState, RCC_NUM_CHANNEL_PLL_OUT),
294 VMSTATE_END_OF_LIST()
295 }
296 };
297
pll_class_init(ObjectClass * klass,const void * data)298 static void pll_class_init(ObjectClass *klass, const void *data)
299 {
300 DeviceClass *dc = DEVICE_CLASS(klass);
301 ResettableClass *rc = RESETTABLE_CLASS(klass);
302
303 rc->phases.enter = pll_reset_enter;
304 rc->phases.hold = pll_reset_hold;
305 rc->phases.exit = pll_reset_exit;
306 dc->vmsd = &pll_vmstate;
307 /* Reason: Part of Stm32l4x5RccState component */
308 dc->user_creatable = false;
309 }
310
pll_set_vco_multiplier(RccPllState * pll,uint32_t vco_multiplier)311 static void pll_set_vco_multiplier(RccPllState *pll, uint32_t vco_multiplier)
312 {
313 if (pll->vco_multiplier == vco_multiplier) {
314 return;
315 }
316
317 if (vco_multiplier < 8 || vco_multiplier > 86) {
318 qemu_log_mask(LOG_GUEST_ERROR,
319 "%s: VCO multiplier is out of bound (%u) for PLL %u\n",
320 __func__, vco_multiplier, pll->id);
321 return;
322 }
323
324 trace_stm32l4x5_rcc_pll_set_vco_multiplier(pll->id,
325 pll->vco_multiplier, vco_multiplier);
326
327 pll->vco_multiplier = vco_multiplier;
328 pll_update(pll, false);
329 }
330
pll_set_enable(RccPllState * pll,bool enabled)331 static void pll_set_enable(RccPllState *pll, bool enabled)
332 {
333 if (pll->enabled == enabled) {
334 return;
335 }
336
337 pll->enabled = enabled;
338 pll_update(pll, false);
339 }
340
pll_set_channel_enable(RccPllState * pll,PllCommonChannels channel,bool enabled)341 static void pll_set_channel_enable(RccPllState *pll,
342 PllCommonChannels channel,
343 bool enabled)
344 {
345 if (pll->channel_enabled[channel] == enabled) {
346 return;
347 }
348
349 if (enabled) {
350 trace_stm32l4x5_rcc_pll_channel_enable(pll->id, channel);
351 } else {
352 trace_stm32l4x5_rcc_pll_channel_disable(pll->id, channel);
353 }
354
355 pll->channel_enabled[channel] = enabled;
356 pll_update(pll, false);
357 }
358
pll_set_channel_divider(RccPllState * pll,PllCommonChannels channel,uint32_t divider)359 static void pll_set_channel_divider(RccPllState *pll,
360 PllCommonChannels channel,
361 uint32_t divider)
362 {
363 if (pll->channel_divider[channel] == divider) {
364 return;
365 }
366
367 trace_stm32l4x5_rcc_pll_set_channel_divider(pll->id,
368 channel, pll->channel_divider[channel], divider);
369
370 pll->channel_divider[channel] = divider;
371 pll_update(pll, false);
372 }
373
rcc_update_irq(Stm32l4x5RccState * s)374 static void rcc_update_irq(Stm32l4x5RccState *s)
375 {
376 /*
377 * TODO: Handle LSECSSF and CSSF flags when the CSS is implemented.
378 */
379 if (s->cifr & CIFR_IRQ_MASK) {
380 qemu_irq_raise(s->irq);
381 } else {
382 qemu_irq_lower(s->irq);
383 }
384 }
385
rcc_update_msi(Stm32l4x5RccState * s,uint32_t previous_value)386 static void rcc_update_msi(Stm32l4x5RccState *s, uint32_t previous_value)
387 {
388 uint32_t val;
389
390 static const uint32_t msirange[] = {
391 100000, 200000, 400000, 800000, 1000000, 2000000,
392 4000000, 8000000, 16000000, 24000000, 32000000, 48000000
393 };
394 /* MSIRANGE and MSIRGSEL */
395 val = extract32(s->cr, R_CR_MSIRGSEL_SHIFT, R_CR_MSIRGSEL_LENGTH);
396 if (val) {
397 /* MSIRGSEL is set, use the MSIRANGE field */
398 val = extract32(s->cr, R_CR_MSIRANGE_SHIFT, R_CR_MSIRANGE_LENGTH);
399 } else {
400 /* MSIRGSEL is not set, use the MSISRANGE field */
401 val = extract32(s->csr, R_CSR_MSISRANGE_SHIFT, R_CSR_MSISRANGE_LENGTH);
402 }
403
404 if (val < ARRAY_SIZE(msirange)) {
405 clock_update_hz(s->msi_rc, msirange[val]);
406 } else {
407 /*
408 * There is a hardware write protection if the value is out of bound.
409 * Restore the previous value.
410 */
411 s->cr = (s->cr & ~R_CSR_MSISRANGE_MASK) |
412 (previous_value & R_CSR_MSISRANGE_MASK);
413 }
414 }
415
416 /*
417 * TODO: Add write-protection for all registers:
418 * DONE: CR
419 */
420
rcc_update_cr_register(Stm32l4x5RccState * s,uint32_t previous_value)421 static void rcc_update_cr_register(Stm32l4x5RccState *s, uint32_t previous_value)
422 {
423 int val;
424 const RccClockMuxSource current_pll_src =
425 CLOCK_MUX_INIT_INFO[RCC_CLOCK_MUX_PLL_INPUT].src_mapping[
426 s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT].src];
427
428 /* PLLSAI2ON and update PLLSAI2RDY */
429 val = FIELD_EX32(s->cr, CR, PLLSAI2ON);
430 pll_set_enable(&s->plls[RCC_PLL_PLLSAI2], val);
431 s->cr = (s->cr & ~R_CR_PLLSAI2RDY_MASK) |
432 (val << R_CR_PLLSAI2RDY_SHIFT);
433 if (s->cier & R_CIER_PLLSAI2RDYIE_MASK) {
434 s->cifr |= R_CIFR_PLLSAI2RDYF_MASK;
435 }
436
437 /* PLLSAI1ON and update PLLSAI1RDY */
438 val = FIELD_EX32(s->cr, CR, PLLSAI1ON);
439 pll_set_enable(&s->plls[RCC_PLL_PLLSAI1], val);
440 s->cr = (s->cr & ~R_CR_PLLSAI1RDY_MASK) |
441 (val << R_CR_PLLSAI1RDY_SHIFT);
442 if (s->cier & R_CIER_PLLSAI1RDYIE_MASK) {
443 s->cifr |= R_CIFR_PLLSAI1RDYF_MASK;
444 }
445
446 /*
447 * PLLON and update PLLRDY
448 * PLLON cannot be reset if the PLL clock is used as the system clock.
449 */
450 val = FIELD_EX32(s->cr, CR, PLLON);
451 if (FIELD_EX32(s->cfgr, CFGR, SWS) != 0b11) {
452 pll_set_enable(&s->plls[RCC_PLL_PLL], val);
453 s->cr = (s->cr & ~R_CR_PLLRDY_MASK) |
454 (val << R_CR_PLLRDY_SHIFT);
455 if (s->cier & R_CIER_PLLRDYIE_MASK) {
456 s->cifr |= R_CIFR_PLLRDYF_MASK;
457 }
458 } else {
459 s->cr |= R_CR_PLLON_MASK;
460 }
461
462 /* CSSON: TODO */
463 /* HSEBYP: TODO */
464
465 /*
466 * HSEON and update HSERDY.
467 * HSEON cannot be reset if the HSE oscillator is used directly or
468 * indirectly as the system clock.
469 */
470 val = FIELD_EX32(s->cr, CR, HSEON);
471 if (FIELD_EX32(s->cfgr, CFGR, SWS) != 0b10 &&
472 current_pll_src != RCC_CLOCK_MUX_SRC_HSE) {
473 s->cr = (s->cr & ~R_CR_HSERDY_MASK) |
474 (val << R_CR_HSERDY_SHIFT);
475 if (val) {
476 clock_update_hz(s->hse, s->hse_frequency);
477 if (s->cier & R_CIER_HSERDYIE_MASK) {
478 s->cifr |= R_CIFR_HSERDYF_MASK;
479 }
480 } else {
481 clock_update(s->hse, 0);
482 }
483 } else {
484 s->cr |= R_CR_HSEON_MASK;
485 }
486
487 /* HSIAFS: TODO*/
488 /* HSIKERON: TODO*/
489
490 /*
491 * HSION and update HSIRDY
492 * HSION is set by hardware if the HSI16 is used directly
493 * or indirectly as system clock.
494 */
495 if (FIELD_EX32(s->cfgr, CFGR, SWS) == 0b01 ||
496 current_pll_src == RCC_CLOCK_MUX_SRC_HSI) {
497 s->cr |= (R_CR_HSION_MASK | R_CR_HSIRDY_MASK);
498 clock_update_hz(s->hsi16_rc, HSI_FRQ);
499 if (s->cier & R_CIER_HSIRDYIE_MASK) {
500 s->cifr |= R_CIFR_HSIRDYF_MASK;
501 }
502 } else {
503 val = FIELD_EX32(s->cr, CR, HSION);
504 if (val) {
505 clock_update_hz(s->hsi16_rc, HSI_FRQ);
506 s->cr |= R_CR_HSIRDY_MASK;
507 if (s->cier & R_CIER_HSIRDYIE_MASK) {
508 s->cifr |= R_CIFR_HSIRDYF_MASK;
509 }
510 } else {
511 clock_update(s->hsi16_rc, 0);
512 s->cr &= ~R_CR_HSIRDY_MASK;
513 }
514 }
515
516 /* MSIPLLEN: TODO */
517
518 /*
519 * MSION and update MSIRDY
520 * Set by hardware when used directly or indirectly as system clock.
521 */
522 if (FIELD_EX32(s->cfgr, CFGR, SWS) == 0b00 ||
523 current_pll_src == RCC_CLOCK_MUX_SRC_MSI) {
524 s->cr |= (R_CR_MSION_MASK | R_CR_MSIRDY_MASK);
525 if (!(previous_value & R_CR_MSION_MASK) && (s->cier & R_CIER_MSIRDYIE_MASK)) {
526 s->cifr |= R_CIFR_MSIRDYF_MASK;
527 }
528 rcc_update_msi(s, previous_value);
529 } else {
530 val = FIELD_EX32(s->cr, CR, MSION);
531 if (val) {
532 s->cr |= R_CR_MSIRDY_MASK;
533 rcc_update_msi(s, previous_value);
534 if (s->cier & R_CIER_MSIRDYIE_MASK) {
535 s->cifr |= R_CIFR_MSIRDYF_MASK;
536 }
537 } else {
538 s->cr &= ~R_CR_MSIRDY_MASK;
539 clock_update(s->msi_rc, 0);
540 }
541 }
542 rcc_update_irq(s);
543 }
544
rcc_update_cfgr_register(Stm32l4x5RccState * s)545 static void rcc_update_cfgr_register(Stm32l4x5RccState *s)
546 {
547 uint32_t val;
548 /* MCOPRE */
549 val = FIELD_EX32(s->cfgr, CFGR, MCOPRE);
550 if (val > 0b100) {
551 qemu_log_mask(LOG_GUEST_ERROR,
552 "%s: Invalid MCOPRE value: 0x%"PRIx32"\n",
553 __func__, val);
554 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false);
555 } else {
556 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_MCO],
557 1, 1 << val);
558 }
559
560 /* MCOSEL */
561 val = FIELD_EX32(s->cfgr, CFGR, MCOSEL);
562 if (val > 0b111) {
563 qemu_log_mask(LOG_GUEST_ERROR,
564 "%s: Invalid MCOSEL value: 0x%"PRIx32"\n",
565 __func__, val);
566 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false);
567 } else {
568 if (val == 0) {
569 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], false);
570 } else {
571 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_MCO], true);
572 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_MCO],
573 val - 1);
574 }
575 }
576
577 /* STOPWUCK */
578 /* TODO */
579
580 /* PPRE2 */
581 val = FIELD_EX32(s->cfgr, CFGR, PPRE2);
582 if (val < 0b100) {
583 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK2],
584 1, 1);
585 } else {
586 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK2],
587 1, 1 << (val - 0b11));
588 }
589
590 /* PPRE1 */
591 val = FIELD_EX32(s->cfgr, CFGR, PPRE1);
592 if (val < 0b100) {
593 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK1],
594 1, 1);
595 } else {
596 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PCLK1],
597 1, 1 << (val - 0b11));
598 }
599
600 /* HPRE */
601 val = FIELD_EX32(s->cfgr, CFGR, HPRE);
602 if (val < 0b1000) {
603 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_HCLK],
604 1, 1);
605 } else {
606 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_HCLK],
607 1, 1 << (val - 0b111));
608 }
609
610 /* Update SWS */
611 val = FIELD_EX32(s->cfgr, CFGR, SW);
612 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_SYSCLK],
613 val);
614 s->cfgr &= ~R_CFGR_SWS_MASK;
615 s->cfgr |= val << R_CFGR_SWS_SHIFT;
616 }
617
rcc_update_ahb1enr(Stm32l4x5RccState * s)618 static void rcc_update_ahb1enr(Stm32l4x5RccState *s)
619 {
620 #define AHB1ENR_SET_ENABLE(_peripheral_name) \
621 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \
622 FIELD_EX32(s->ahb1enr, AHB1ENR, _peripheral_name##EN))
623
624 /* DMA2DEN: reserved for STM32L475xx */
625 AHB1ENR_SET_ENABLE(TSC);
626 AHB1ENR_SET_ENABLE(CRC);
627 AHB1ENR_SET_ENABLE(FLASH);
628 AHB1ENR_SET_ENABLE(DMA2);
629 AHB1ENR_SET_ENABLE(DMA1);
630
631 #undef AHB1ENR_SET_ENABLE
632 }
633
rcc_update_ahb2enr(Stm32l4x5RccState * s)634 static void rcc_update_ahb2enr(Stm32l4x5RccState *s)
635 {
636 #define AHB2ENR_SET_ENABLE(_peripheral_name) \
637 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \
638 FIELD_EX32(s->ahb2enr, AHB2ENR, _peripheral_name##EN))
639
640 AHB2ENR_SET_ENABLE(RNG);
641 /* HASHEN: reserved for STM32L475xx */
642 AHB2ENR_SET_ENABLE(AES);
643 /* DCMIEN: reserved for STM32L475xx */
644 AHB2ENR_SET_ENABLE(ADC);
645 AHB2ENR_SET_ENABLE(OTGFS);
646 /* GPIOIEN: reserved for STM32L475xx */
647 AHB2ENR_SET_ENABLE(GPIOA);
648 AHB2ENR_SET_ENABLE(GPIOB);
649 AHB2ENR_SET_ENABLE(GPIOC);
650 AHB2ENR_SET_ENABLE(GPIOD);
651 AHB2ENR_SET_ENABLE(GPIOE);
652 AHB2ENR_SET_ENABLE(GPIOF);
653 AHB2ENR_SET_ENABLE(GPIOG);
654 AHB2ENR_SET_ENABLE(GPIOH);
655
656 #undef AHB2ENR_SET_ENABLE
657 }
658
rcc_update_ahb3enr(Stm32l4x5RccState * s)659 static void rcc_update_ahb3enr(Stm32l4x5RccState *s)
660 {
661 #define AHB3ENR_SET_ENABLE(_peripheral_name) \
662 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \
663 FIELD_EX32(s->ahb3enr, AHB3ENR, _peripheral_name##EN))
664
665 AHB3ENR_SET_ENABLE(QSPI);
666 AHB3ENR_SET_ENABLE(FMC);
667
668 #undef AHB3ENR_SET_ENABLE
669 }
670
rcc_update_apb1enr(Stm32l4x5RccState * s)671 static void rcc_update_apb1enr(Stm32l4x5RccState *s)
672 {
673 #define APB1ENR1_SET_ENABLE(_peripheral_name) \
674 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \
675 FIELD_EX32(s->apb1enr1, APB1ENR1, _peripheral_name##EN))
676 #define APB1ENR2_SET_ENABLE(_peripheral_name) \
677 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \
678 FIELD_EX32(s->apb1enr2, APB1ENR2, _peripheral_name##EN))
679
680 /* APB1ENR1 */
681 APB1ENR1_SET_ENABLE(LPTIM1);
682 APB1ENR1_SET_ENABLE(OPAMP);
683 APB1ENR1_SET_ENABLE(DAC1);
684 APB1ENR1_SET_ENABLE(PWR);
685 /* CAN2: reserved for STM32L4x5 */
686 APB1ENR1_SET_ENABLE(CAN1);
687 /* CRSEN: reserved for STM32L4x5 */
688 APB1ENR1_SET_ENABLE(I2C3);
689 APB1ENR1_SET_ENABLE(I2C2);
690 APB1ENR1_SET_ENABLE(I2C1);
691 APB1ENR1_SET_ENABLE(UART5);
692 APB1ENR1_SET_ENABLE(UART4);
693 APB1ENR1_SET_ENABLE(USART3);
694 APB1ENR1_SET_ENABLE(USART2);
695 APB1ENR1_SET_ENABLE(SPI3);
696 APB1ENR1_SET_ENABLE(SPI2);
697 APB1ENR1_SET_ENABLE(WWDG);
698 /* RTCAPB: reserved for STM32L4x5 */
699 APB1ENR1_SET_ENABLE(LCD);
700 APB1ENR1_SET_ENABLE(TIM7);
701 APB1ENR1_SET_ENABLE(TIM6);
702 APB1ENR1_SET_ENABLE(TIM5);
703 APB1ENR1_SET_ENABLE(TIM4);
704 APB1ENR1_SET_ENABLE(TIM3);
705 APB1ENR1_SET_ENABLE(TIM2);
706
707 /* APB1ENR2 */
708 APB1ENR2_SET_ENABLE(LPTIM2);
709 APB1ENR2_SET_ENABLE(SWPMI1);
710 /* I2C4EN: reserved for STM32L4x5 */
711 APB1ENR2_SET_ENABLE(LPUART1);
712
713 #undef APB1ENR1_SET_ENABLE
714 #undef APB1ENR2_SET_ENABLE
715 }
716
rcc_update_apb2enr(Stm32l4x5RccState * s)717 static void rcc_update_apb2enr(Stm32l4x5RccState *s)
718 {
719 #define APB2ENR_SET_ENABLE(_peripheral_name) \
720 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \
721 FIELD_EX32(s->apb2enr, APB2ENR, _peripheral_name##EN))
722
723 APB2ENR_SET_ENABLE(DFSDM1);
724 APB2ENR_SET_ENABLE(SAI2);
725 APB2ENR_SET_ENABLE(SAI1);
726 APB2ENR_SET_ENABLE(TIM17);
727 APB2ENR_SET_ENABLE(TIM16);
728 APB2ENR_SET_ENABLE(TIM15);
729 APB2ENR_SET_ENABLE(USART1);
730 APB2ENR_SET_ENABLE(TIM8);
731 APB2ENR_SET_ENABLE(SPI1);
732 APB2ENR_SET_ENABLE(TIM1);
733 APB2ENR_SET_ENABLE(SDMMC1);
734 APB2ENR_SET_ENABLE(FW);
735 APB2ENR_SET_ENABLE(SYSCFG);
736
737 #undef APB2ENR_SET_ENABLE
738 }
739
740 /*
741 * The 3 PLLs share the same register layout
742 * so we can use the same function for all of them
743 * Note: no frequency bounds checking is done here.
744 */
rcc_update_pllsaixcfgr(Stm32l4x5RccState * s,RccPll pll_id)745 static void rcc_update_pllsaixcfgr(Stm32l4x5RccState *s, RccPll pll_id)
746 {
747 uint32_t reg, val;
748 switch (pll_id) {
749 case RCC_PLL_PLL:
750 reg = s->pllcfgr;
751 break;
752 case RCC_PLL_PLLSAI1:
753 reg = s->pllsai1cfgr;
754 break;
755 case RCC_PLL_PLLSAI2:
756 reg = s->pllsai2cfgr;
757 break;
758 default:
759 qemu_log_mask(LOG_GUEST_ERROR,
760 "%s: Invalid PLL ID: %u\n", __func__, pll_id);
761 return;
762 }
763
764 /* PLLPDIV */
765 val = FIELD_EX32(reg, PLLCFGR, PLLPDIV);
766 /* 1 is a reserved value */
767 if (val == 0) {
768 /* Get PLLP value */
769 val = FIELD_EX32(reg, PLLCFGR, PLLP);
770 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P,
771 (val ? 17 : 7));
772 } else if (val > 1) {
773 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P,
774 val);
775 }
776
777
778 /* PLLR */
779 val = FIELD_EX32(reg, PLLCFGR, PLLR);
780 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_R,
781 2 * (val + 1));
782
783 /* PLLREN */
784 val = FIELD_EX32(reg, PLLCFGR, PLLREN);
785 pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_R, val);
786
787 /* PLLQ */
788 val = FIELD_EX32(reg, PLLCFGR, PLLQ);
789 pll_set_channel_divider(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_Q,
790 2 * (val + 1));
791
792 /* PLLQEN */
793 val = FIELD_EX32(reg, PLLCFGR, PLLQEN);
794 pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_Q, val);
795
796 /* PLLPEN */
797 val = FIELD_EX32(reg, PLLCFGR, PLLPEN);
798 pll_set_channel_enable(&s->plls[pll_id], RCC_PLL_COMMON_CHANNEL_P, val);
799
800 /* PLLN */
801 val = FIELD_EX32(reg, PLLCFGR, PLLN);
802 pll_set_vco_multiplier(&s->plls[pll_id], val);
803 }
804
rcc_update_pllcfgr(Stm32l4x5RccState * s)805 static void rcc_update_pllcfgr(Stm32l4x5RccState *s)
806 {
807 int val;
808
809 /* Use common layout */
810 rcc_update_pllsaixcfgr(s, RCC_PLL_PLL);
811
812 /* Fetch specific fields for pllcfgr */
813
814 /* PLLM */
815 val = FIELD_EX32(s->pllcfgr, PLLCFGR, PLLM);
816 clock_mux_set_factor(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], 1, (val + 1));
817
818 /* PLLSRC */
819 val = FIELD_EX32(s->pllcfgr, PLLCFGR, PLLSRC);
820 if (val == 0) {
821 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], false);
822 } else {
823 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], val - 1);
824 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT], true);
825 }
826 }
827
rcc_update_ccipr(Stm32l4x5RccState * s)828 static void rcc_update_ccipr(Stm32l4x5RccState *s)
829 {
830 #define CCIPR_SET_SOURCE(_peripheral_name) \
831 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_##_peripheral_name], \
832 FIELD_EX32(s->ccipr, CCIPR, _peripheral_name##SEL))
833
834 CCIPR_SET_SOURCE(DFSDM1);
835 CCIPR_SET_SOURCE(SWPMI1);
836 CCIPR_SET_SOURCE(ADC);
837 CCIPR_SET_SOURCE(CLK48);
838 CCIPR_SET_SOURCE(SAI2);
839 CCIPR_SET_SOURCE(SAI1);
840 CCIPR_SET_SOURCE(LPTIM2);
841 CCIPR_SET_SOURCE(LPTIM1);
842 CCIPR_SET_SOURCE(I2C3);
843 CCIPR_SET_SOURCE(I2C2);
844 CCIPR_SET_SOURCE(I2C1);
845 CCIPR_SET_SOURCE(LPUART1);
846 CCIPR_SET_SOURCE(UART5);
847 CCIPR_SET_SOURCE(UART4);
848 CCIPR_SET_SOURCE(USART3);
849 CCIPR_SET_SOURCE(USART2);
850 CCIPR_SET_SOURCE(USART1);
851
852 #undef CCIPR_SET_SOURCE
853 }
854
rcc_update_bdcr(Stm32l4x5RccState * s)855 static void rcc_update_bdcr(Stm32l4x5RccState *s)
856 {
857 int val;
858
859 /* LSCOSEL */
860 val = FIELD_EX32(s->bdcr, BDCR, LSCOSEL);
861 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_LSCO], val);
862
863 val = FIELD_EX32(s->bdcr, BDCR, LSCOEN);
864 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_LSCO], val);
865
866 /* BDRST */
867 /*
868 * The documentation is not clear if the RTCEN flag disables the RTC and
869 * the LCD common mux or if it only affects the RTC.
870 * As the LCDEN flag exists, we assume here that it only affects the RTC.
871 */
872 val = FIELD_EX32(s->bdcr, BDCR, RTCEN);
873 clock_mux_set_enable(&s->clock_muxes[RCC_CLOCK_MUX_RTC], val);
874 /* LCD and RTC share the same clock */
875 val = FIELD_EX32(s->bdcr, BDCR, RTCSEL);
876 clock_mux_set_source(&s->clock_muxes[RCC_CLOCK_MUX_LCD_AND_RTC_COMMON], val);
877
878 /* LSECSSON */
879 /* LSEDRV[1:0] */
880 /* LSEBYP */
881
882 /* LSEON: Update LSERDY at the same time */
883 val = FIELD_EX32(s->bdcr, BDCR, LSEON);
884 if (val) {
885 clock_update_hz(s->lse_crystal, LSE_FRQ);
886 s->bdcr |= R_BDCR_LSERDY_MASK;
887 if (s->cier & R_CIER_LSERDYIE_MASK) {
888 s->cifr |= R_CIFR_LSERDYF_MASK;
889 }
890 } else {
891 clock_update(s->lse_crystal, 0);
892 s->bdcr &= ~R_BDCR_LSERDY_MASK;
893 }
894
895 rcc_update_irq(s);
896 }
897
rcc_update_csr(Stm32l4x5RccState * s)898 static void rcc_update_csr(Stm32l4x5RccState *s)
899 {
900 int val;
901
902 /* Reset flags: Not implemented */
903 /* MSISRANGE: Not implemented after reset */
904
905 /* LSION: Update LSIRDY at the same time */
906 val = FIELD_EX32(s->csr, CSR, LSION);
907 if (val) {
908 clock_update_hz(s->lsi_rc, LSI_FRQ);
909 s->csr |= R_CSR_LSIRDY_MASK;
910 if (s->cier & R_CIER_LSIRDYIE_MASK) {
911 s->cifr |= R_CIFR_LSIRDYF_MASK;
912 }
913 } else {
914 /*
915 * TODO: Handle when the LSI is set independently of LSION.
916 * E.g. when the LSI is set by the RTC.
917 * See the reference manual for more details.
918 */
919 clock_update(s->lsi_rc, 0);
920 s->csr &= ~R_CSR_LSIRDY_MASK;
921 }
922
923 rcc_update_irq(s);
924 }
925
stm32l4x5_rcc_reset_hold(Object * obj,ResetType type)926 static void stm32l4x5_rcc_reset_hold(Object *obj, ResetType type)
927 {
928 Stm32l4x5RccState *s = STM32L4X5_RCC(obj);
929 s->cr = 0x00000063;
930 /*
931 * Factory-programmed calibration data
932 * From the reference manual: 0x10XX 00XX
933 * Value taken from a real card.
934 */
935 s->icscr = 0x106E0082;
936 s->cfgr = 0x0;
937 s->pllcfgr = 0x00001000;
938 s->pllsai1cfgr = 0x00001000;
939 s->pllsai2cfgr = 0x00001000;
940 s->cier = 0x0;
941 s->cifr = 0x0;
942 s->ahb1rstr = 0x0;
943 s->ahb2rstr = 0x0;
944 s->ahb3rstr = 0x0;
945 s->apb1rstr1 = 0x0;
946 s->apb1rstr2 = 0x0;
947 s->apb2rstr = 0x0;
948 s->ahb1enr = 0x00000100;
949 s->ahb2enr = 0x0;
950 s->ahb3enr = 0x0;
951 s->apb1enr1 = 0x0;
952 s->apb1enr2 = 0x0;
953 s->apb2enr = 0x0;
954 s->ahb1smenr = 0x00011303;
955 s->ahb2smenr = 0x000532FF;
956 s->ahb3smenr = 0x00000101;
957 s->apb1smenr1 = 0xF2FECA3F;
958 s->apb1smenr2 = 0x00000025;
959 s->apb2smenr = 0x01677C01;
960 s->ccipr = 0x0;
961 s->bdcr = 0x0;
962 s->csr = 0x0C000600;
963 }
964
stm32l4x5_rcc_read(void * opaque,hwaddr addr,unsigned int size)965 static uint64_t stm32l4x5_rcc_read(void *opaque, hwaddr addr,
966 unsigned int size)
967 {
968 Stm32l4x5RccState *s = opaque;
969 uint64_t retvalue = 0;
970
971 switch (addr) {
972 case A_CR:
973 retvalue = s->cr;
974 break;
975 case A_ICSCR:
976 retvalue = s->icscr;
977 break;
978 case A_CFGR:
979 retvalue = s->cfgr;
980 break;
981 case A_PLLCFGR:
982 retvalue = s->pllcfgr;
983 break;
984 case A_PLLSAI1CFGR:
985 retvalue = s->pllsai1cfgr;
986 break;
987 case A_PLLSAI2CFGR:
988 retvalue = s->pllsai2cfgr;
989 break;
990 case A_CIER:
991 retvalue = s->cier;
992 break;
993 case A_CIFR:
994 retvalue = s->cifr;
995 break;
996 case A_CICR:
997 /* CICR is write only, return the reset value = 0 */
998 break;
999 case A_AHB1RSTR:
1000 retvalue = s->ahb1rstr;
1001 break;
1002 case A_AHB2RSTR:
1003 retvalue = s->ahb2rstr;
1004 break;
1005 case A_AHB3RSTR:
1006 retvalue = s->ahb3rstr;
1007 break;
1008 case A_APB1RSTR1:
1009 retvalue = s->apb1rstr1;
1010 break;
1011 case A_APB1RSTR2:
1012 retvalue = s->apb1rstr2;
1013 break;
1014 case A_APB2RSTR:
1015 retvalue = s->apb2rstr;
1016 break;
1017 case A_AHB1ENR:
1018 retvalue = s->ahb1enr;
1019 break;
1020 case A_AHB2ENR:
1021 retvalue = s->ahb2enr;
1022 break;
1023 case A_AHB3ENR:
1024 retvalue = s->ahb3enr;
1025 break;
1026 case A_APB1ENR1:
1027 retvalue = s->apb1enr1;
1028 break;
1029 case A_APB1ENR2:
1030 retvalue = s->apb1enr2;
1031 break;
1032 case A_APB2ENR:
1033 retvalue = s->apb2enr;
1034 break;
1035 case A_AHB1SMENR:
1036 retvalue = s->ahb1smenr;
1037 break;
1038 case A_AHB2SMENR:
1039 retvalue = s->ahb2smenr;
1040 break;
1041 case A_AHB3SMENR:
1042 retvalue = s->ahb3smenr;
1043 break;
1044 case A_APB1SMENR1:
1045 retvalue = s->apb1smenr1;
1046 break;
1047 case A_APB1SMENR2:
1048 retvalue = s->apb1smenr2;
1049 break;
1050 case A_APB2SMENR:
1051 retvalue = s->apb2smenr;
1052 break;
1053 case A_CCIPR:
1054 retvalue = s->ccipr;
1055 break;
1056 case A_BDCR:
1057 retvalue = s->bdcr;
1058 break;
1059 case A_CSR:
1060 retvalue = s->csr;
1061 break;
1062 default:
1063 qemu_log_mask(LOG_GUEST_ERROR,
1064 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
1065 break;
1066 }
1067
1068 trace_stm32l4x5_rcc_read(addr, retvalue);
1069
1070 return retvalue;
1071 }
1072
stm32l4x5_rcc_write(void * opaque,hwaddr addr,uint64_t val64,unsigned int size)1073 static void stm32l4x5_rcc_write(void *opaque, hwaddr addr,
1074 uint64_t val64, unsigned int size)
1075 {
1076 Stm32l4x5RccState *s = opaque;
1077 uint32_t previous_value = 0;
1078 const uint32_t value = val64;
1079
1080 trace_stm32l4x5_rcc_write(addr, value);
1081
1082 switch (addr) {
1083 case A_CR:
1084 previous_value = s->cr;
1085 s->cr = (s->cr & CR_READ_SET_MASK) |
1086 (value & (CR_READ_SET_MASK | ~CR_READ_ONLY_MASK));
1087 rcc_update_cr_register(s, previous_value);
1088 break;
1089 case A_ICSCR:
1090 s->icscr = value & ~ICSCR_READ_ONLY_MASK;
1091 qemu_log_mask(LOG_UNIMP,
1092 "%s: Side-effects not implemented for ICSCR\n", __func__);
1093 break;
1094 case A_CFGR:
1095 s->cfgr = value & ~CFGR_READ_ONLY_MASK;
1096 rcc_update_cfgr_register(s);
1097 break;
1098 case A_PLLCFGR:
1099 s->pllcfgr = value;
1100 rcc_update_pllcfgr(s);
1101 break;
1102 case A_PLLSAI1CFGR:
1103 s->pllsai1cfgr = value;
1104 rcc_update_pllsaixcfgr(s, RCC_PLL_PLLSAI1);
1105 break;
1106 case A_PLLSAI2CFGR:
1107 s->pllsai2cfgr = value;
1108 rcc_update_pllsaixcfgr(s, RCC_PLL_PLLSAI2);
1109 break;
1110 case A_CIER:
1111 s->cier = value;
1112 qemu_log_mask(LOG_UNIMP,
1113 "%s: Side-effects not implemented for CIER\n", __func__);
1114 break;
1115 case A_CIFR:
1116 qemu_log_mask(LOG_GUEST_ERROR,
1117 "%s: Write attempt into read-only register (CIFR) 0x%"PRIx32"\n",
1118 __func__, value);
1119 break;
1120 case A_CICR:
1121 /* Clear interrupt flags by writing a 1 to the CICR register */
1122 s->cifr &= ~value;
1123 rcc_update_irq(s);
1124 break;
1125 /* Reset behaviors are not implemented */
1126 case A_AHB1RSTR:
1127 s->ahb1rstr = value;
1128 qemu_log_mask(LOG_UNIMP,
1129 "%s: Side-effects not implemented for AHB1RSTR\n", __func__);
1130 break;
1131 case A_AHB2RSTR:
1132 s->ahb2rstr = value;
1133 qemu_log_mask(LOG_UNIMP,
1134 "%s: Side-effects not implemented for AHB2RSTR\n", __func__);
1135 break;
1136 case A_AHB3RSTR:
1137 s->ahb3rstr = value;
1138 qemu_log_mask(LOG_UNIMP,
1139 "%s: Side-effects not implemented for AHB3RSTR\n", __func__);
1140 break;
1141 case A_APB1RSTR1:
1142 s->apb1rstr1 = value;
1143 qemu_log_mask(LOG_UNIMP,
1144 "%s: Side-effects not implemented for APB1RSTR1\n", __func__);
1145 break;
1146 case A_APB1RSTR2:
1147 s->apb1rstr2 = value;
1148 qemu_log_mask(LOG_UNIMP,
1149 "%s: Side-effects not implemented for APB1RSTR2\n", __func__);
1150 break;
1151 case A_APB2RSTR:
1152 s->apb2rstr = value;
1153 qemu_log_mask(LOG_UNIMP,
1154 "%s: Side-effects not implemented for APB2RSTR\n", __func__);
1155 break;
1156 case A_AHB1ENR:
1157 s->ahb1enr = value;
1158 rcc_update_ahb1enr(s);
1159 break;
1160 case A_AHB2ENR:
1161 s->ahb2enr = value;
1162 rcc_update_ahb2enr(s);
1163 break;
1164 case A_AHB3ENR:
1165 s->ahb3enr = value;
1166 rcc_update_ahb3enr(s);
1167 break;
1168 case A_APB1ENR1:
1169 s->apb1enr1 = value;
1170 rcc_update_apb1enr(s);
1171 break;
1172 case A_APB1ENR2:
1173 s->apb1enr2 = value;
1174 rcc_update_apb1enr(s);
1175 break;
1176 case A_APB2ENR:
1177 s->apb2enr = (s->apb2enr & APB2ENR_READ_SET_MASK) | value;
1178 rcc_update_apb2enr(s);
1179 break;
1180 /* Behaviors for Sleep and Stop modes are not implemented */
1181 case A_AHB1SMENR:
1182 s->ahb1smenr = value;
1183 qemu_log_mask(LOG_UNIMP,
1184 "%s: Side-effects not implemented for AHB1SMENR\n", __func__);
1185 break;
1186 case A_AHB2SMENR:
1187 s->ahb2smenr = value;
1188 qemu_log_mask(LOG_UNIMP,
1189 "%s: Side-effects not implemented for AHB2SMENR\n", __func__);
1190 break;
1191 case A_AHB3SMENR:
1192 s->ahb3smenr = value;
1193 qemu_log_mask(LOG_UNIMP,
1194 "%s: Side-effects not implemented for AHB3SMENR\n", __func__);
1195 break;
1196 case A_APB1SMENR1:
1197 s->apb1smenr1 = value;
1198 qemu_log_mask(LOG_UNIMP,
1199 "%s: Side-effects not implemented for APB1SMENR1\n", __func__);
1200 break;
1201 case A_APB1SMENR2:
1202 s->apb1smenr2 = value;
1203 qemu_log_mask(LOG_UNIMP,
1204 "%s: Side-effects not implemented for APB1SMENR2\n", __func__);
1205 break;
1206 case A_APB2SMENR:
1207 s->apb2smenr = value;
1208 qemu_log_mask(LOG_UNIMP,
1209 "%s: Side-effects not implemented for APB2SMENR\n", __func__);
1210 break;
1211 case A_CCIPR:
1212 s->ccipr = value;
1213 rcc_update_ccipr(s);
1214 break;
1215 case A_BDCR:
1216 s->bdcr = value & ~BDCR_READ_ONLY_MASK;
1217 rcc_update_bdcr(s);
1218 break;
1219 case A_CSR:
1220 s->csr = value & ~CSR_READ_ONLY_MASK;
1221 rcc_update_csr(s);
1222 break;
1223 default:
1224 qemu_log_mask(LOG_GUEST_ERROR,
1225 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
1226 }
1227 }
1228
1229 static const MemoryRegionOps stm32l4x5_rcc_ops = {
1230 .read = stm32l4x5_rcc_read,
1231 .write = stm32l4x5_rcc_write,
1232 .endianness = DEVICE_NATIVE_ENDIAN,
1233 .valid = {
1234 .max_access_size = 4,
1235 .min_access_size = 4,
1236 .unaligned = false
1237 },
1238 .impl = {
1239 .max_access_size = 4,
1240 .min_access_size = 4,
1241 .unaligned = false
1242 },
1243 };
1244
1245 static const ClockPortInitArray stm32l4x5_rcc_clocks = {
1246 QDEV_CLOCK_IN(Stm32l4x5RccState, hsi16_rc, NULL, 0),
1247 QDEV_CLOCK_IN(Stm32l4x5RccState, msi_rc, NULL, 0),
1248 QDEV_CLOCK_IN(Stm32l4x5RccState, hse, NULL, 0),
1249 QDEV_CLOCK_IN(Stm32l4x5RccState, lsi_rc, NULL, 0),
1250 QDEV_CLOCK_IN(Stm32l4x5RccState, lse_crystal, NULL, 0),
1251 QDEV_CLOCK_IN(Stm32l4x5RccState, sai1_extclk, NULL, 0),
1252 QDEV_CLOCK_IN(Stm32l4x5RccState, sai2_extclk, NULL, 0),
1253 QDEV_CLOCK_END
1254 };
1255
1256
stm32l4x5_rcc_init(Object * obj)1257 static void stm32l4x5_rcc_init(Object *obj)
1258 {
1259 Stm32l4x5RccState *s = STM32L4X5_RCC(obj);
1260 size_t i;
1261
1262 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
1263
1264 memory_region_init_io(&s->mmio, obj, &stm32l4x5_rcc_ops, s,
1265 TYPE_STM32L4X5_RCC, 0x400);
1266 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
1267
1268 qdev_init_clocks(DEVICE(s), stm32l4x5_rcc_clocks);
1269
1270 for (i = 0; i < RCC_NUM_PLL; i++) {
1271 object_initialize_child(obj, PLL_INIT_INFO[i].name,
1272 &s->plls[i], TYPE_RCC_PLL);
1273 set_pll_init_info(&s->plls[i], i);
1274 }
1275
1276 for (i = 0; i < RCC_NUM_CLOCK_MUX; i++) {
1277 char *alias;
1278
1279 object_initialize_child(obj, CLOCK_MUX_INIT_INFO[i].name,
1280 &s->clock_muxes[i],
1281 TYPE_RCC_CLOCK_MUX);
1282 set_clock_mux_init_info(&s->clock_muxes[i], i);
1283
1284 if (!CLOCK_MUX_INIT_INFO[i].hidden) {
1285 /* Expose muxes output as RCC outputs */
1286 alias = g_strdup_printf("%s-out", CLOCK_MUX_INIT_INFO[i].name);
1287 qdev_alias_clock(DEVICE(&s->clock_muxes[i]), "out", DEVICE(obj), alias);
1288 g_free(alias);
1289 }
1290 }
1291
1292 s->gnd = clock_new(obj, "gnd");
1293 }
1294
connect_mux_sources(Stm32l4x5RccState * s,RccClockMuxState * mux,const RccClockMuxSource * clk_mapping)1295 static void connect_mux_sources(Stm32l4x5RccState *s,
1296 RccClockMuxState *mux,
1297 const RccClockMuxSource *clk_mapping)
1298 {
1299 size_t i;
1300
1301 Clock * const CLK_SRC_MAPPING[] = {
1302 [RCC_CLOCK_MUX_SRC_GND] = s->gnd,
1303 [RCC_CLOCK_MUX_SRC_HSI] = s->hsi16_rc,
1304 [RCC_CLOCK_MUX_SRC_HSE] = s->hse,
1305 [RCC_CLOCK_MUX_SRC_MSI] = s->msi_rc,
1306 [RCC_CLOCK_MUX_SRC_LSI] = s->lsi_rc,
1307 [RCC_CLOCK_MUX_SRC_LSE] = s->lse_crystal,
1308 [RCC_CLOCK_MUX_SRC_SAI1_EXTCLK] = s->sai1_extclk,
1309 [RCC_CLOCK_MUX_SRC_SAI2_EXTCLK] = s->sai2_extclk,
1310 [RCC_CLOCK_MUX_SRC_PLL] =
1311 s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLLCLK],
1312 [RCC_CLOCK_MUX_SRC_PLLSAI1] =
1313 s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLLSAI1CLK],
1314 [RCC_CLOCK_MUX_SRC_PLLSAI2] =
1315 s->plls[RCC_PLL_PLLSAI2].channels[RCC_PLLSAI2_CHANNEL_PLLSAI2CLK],
1316 [RCC_CLOCK_MUX_SRC_PLLSAI3] =
1317 s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLLSAI3CLK],
1318 [RCC_CLOCK_MUX_SRC_PLL48M1] =
1319 s->plls[RCC_PLL_PLL].channels[RCC_PLL_CHANNEL_PLL48M1CLK],
1320 [RCC_CLOCK_MUX_SRC_PLL48M2] =
1321 s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLL48M2CLK],
1322 [RCC_CLOCK_MUX_SRC_PLLADC1] =
1323 s->plls[RCC_PLL_PLLSAI1].channels[RCC_PLLSAI1_CHANNEL_PLLADC1CLK],
1324 [RCC_CLOCK_MUX_SRC_PLLADC2] =
1325 s->plls[RCC_PLL_PLLSAI2] .channels[RCC_PLLSAI2_CHANNEL_PLLADC2CLK],
1326 [RCC_CLOCK_MUX_SRC_SYSCLK] = s->clock_muxes[RCC_CLOCK_MUX_SYSCLK].out,
1327 [RCC_CLOCK_MUX_SRC_HCLK] = s->clock_muxes[RCC_CLOCK_MUX_HCLK].out,
1328 [RCC_CLOCK_MUX_SRC_PCLK1] = s->clock_muxes[RCC_CLOCK_MUX_PCLK1].out,
1329 [RCC_CLOCK_MUX_SRC_PCLK2] = s->clock_muxes[RCC_CLOCK_MUX_PCLK2].out,
1330 [RCC_CLOCK_MUX_SRC_HSE_OVER_32] = s->clock_muxes[RCC_CLOCK_MUX_HSE_OVER_32].out,
1331 [RCC_CLOCK_MUX_SRC_LCD_AND_RTC_COMMON] =
1332 s->clock_muxes[RCC_CLOCK_MUX_LCD_AND_RTC_COMMON].out,
1333 };
1334
1335 assert(ARRAY_SIZE(CLK_SRC_MAPPING) == RCC_CLOCK_MUX_SRC_NUMBER);
1336
1337 for (i = 0; i < RCC_NUM_CLOCK_MUX_SRC; i++) {
1338 RccClockMuxSource mapping = clk_mapping[i];
1339 clock_set_source(mux->srcs[i], CLK_SRC_MAPPING[mapping]);
1340 }
1341 }
1342
1343
1344 static const VMStateDescription vmstate_stm32l4x5_rcc = {
1345 .name = TYPE_STM32L4X5_RCC,
1346 .version_id = 1,
1347 .minimum_version_id = 1,
1348 .fields = (VMStateField[]) {
1349 VMSTATE_UINT32(cr, Stm32l4x5RccState),
1350 VMSTATE_UINT32(icscr, Stm32l4x5RccState),
1351 VMSTATE_UINT32(cfgr, Stm32l4x5RccState),
1352 VMSTATE_UINT32(pllcfgr, Stm32l4x5RccState),
1353 VMSTATE_UINT32(pllsai1cfgr, Stm32l4x5RccState),
1354 VMSTATE_UINT32(pllsai2cfgr, Stm32l4x5RccState),
1355 VMSTATE_UINT32(cier, Stm32l4x5RccState),
1356 VMSTATE_UINT32(cifr, Stm32l4x5RccState),
1357 VMSTATE_UINT32(ahb1rstr, Stm32l4x5RccState),
1358 VMSTATE_UINT32(ahb2rstr, Stm32l4x5RccState),
1359 VMSTATE_UINT32(ahb3rstr, Stm32l4x5RccState),
1360 VMSTATE_UINT32(apb1rstr1, Stm32l4x5RccState),
1361 VMSTATE_UINT32(apb1rstr2, Stm32l4x5RccState),
1362 VMSTATE_UINT32(apb2rstr, Stm32l4x5RccState),
1363 VMSTATE_UINT32(ahb1enr, Stm32l4x5RccState),
1364 VMSTATE_UINT32(ahb2enr, Stm32l4x5RccState),
1365 VMSTATE_UINT32(ahb3enr, Stm32l4x5RccState),
1366 VMSTATE_UINT32(apb1enr1, Stm32l4x5RccState),
1367 VMSTATE_UINT32(apb1enr2, Stm32l4x5RccState),
1368 VMSTATE_UINT32(apb2enr, Stm32l4x5RccState),
1369 VMSTATE_UINT32(ahb1smenr, Stm32l4x5RccState),
1370 VMSTATE_UINT32(ahb2smenr, Stm32l4x5RccState),
1371 VMSTATE_UINT32(ahb3smenr, Stm32l4x5RccState),
1372 VMSTATE_UINT32(apb1smenr1, Stm32l4x5RccState),
1373 VMSTATE_UINT32(apb1smenr2, Stm32l4x5RccState),
1374 VMSTATE_UINT32(apb2smenr, Stm32l4x5RccState),
1375 VMSTATE_UINT32(ccipr, Stm32l4x5RccState),
1376 VMSTATE_UINT32(bdcr, Stm32l4x5RccState),
1377 VMSTATE_UINT32(csr, Stm32l4x5RccState),
1378 VMSTATE_CLOCK(hsi16_rc, Stm32l4x5RccState),
1379 VMSTATE_CLOCK(msi_rc, Stm32l4x5RccState),
1380 VMSTATE_CLOCK(hse, Stm32l4x5RccState),
1381 VMSTATE_CLOCK(lsi_rc, Stm32l4x5RccState),
1382 VMSTATE_CLOCK(lse_crystal, Stm32l4x5RccState),
1383 VMSTATE_CLOCK(sai1_extclk, Stm32l4x5RccState),
1384 VMSTATE_CLOCK(sai2_extclk, Stm32l4x5RccState),
1385 VMSTATE_END_OF_LIST()
1386 }
1387 };
1388
1389
stm32l4x5_rcc_realize(DeviceState * dev,Error ** errp)1390 static void stm32l4x5_rcc_realize(DeviceState *dev, Error **errp)
1391 {
1392 Stm32l4x5RccState *s = STM32L4X5_RCC(dev);
1393 size_t i;
1394
1395 if (s->hse_frequency < 4000000ULL ||
1396 s->hse_frequency > 48000000ULL) {
1397 error_setg(errp,
1398 "HSE frequency is outside of the allowed [4-48]Mhz range: %" PRIx64 "",
1399 s->hse_frequency);
1400 return;
1401 }
1402
1403 for (i = 0; i < RCC_NUM_PLL; i++) {
1404 RccPllState *pll = &s->plls[i];
1405
1406 clock_set_source(pll->in, s->clock_muxes[RCC_CLOCK_MUX_PLL_INPUT].out);
1407
1408 if (!qdev_realize(DEVICE(pll), NULL, errp)) {
1409 return;
1410 }
1411 }
1412
1413 for (i = 0; i < RCC_NUM_CLOCK_MUX; i++) {
1414 RccClockMuxState *clock_mux = &s->clock_muxes[i];
1415
1416 connect_mux_sources(s, clock_mux, CLOCK_MUX_INIT_INFO[i].src_mapping);
1417
1418 if (!qdev_realize(DEVICE(clock_mux), NULL, errp)) {
1419 return;
1420 }
1421 }
1422
1423 /*
1424 * Start clocks after everything is connected
1425 * to propagate the frequencies along the tree.
1426 */
1427 clock_update_hz(s->msi_rc, MSI_DEFAULT_FRQ);
1428 clock_update_hz(s->sai1_extclk, s->sai1_extclk_frequency);
1429 clock_update_hz(s->sai2_extclk, s->sai2_extclk_frequency);
1430 clock_update(s->gnd, 0);
1431 }
1432
1433 static const Property stm32l4x5_rcc_properties[] = {
1434 DEFINE_PROP_UINT64("hse_frequency", Stm32l4x5RccState,
1435 hse_frequency, HSE_DEFAULT_FRQ),
1436 DEFINE_PROP_UINT64("sai1_extclk_frequency", Stm32l4x5RccState,
1437 sai1_extclk_frequency, 0),
1438 DEFINE_PROP_UINT64("sai2_extclk_frequency", Stm32l4x5RccState,
1439 sai2_extclk_frequency, 0),
1440 };
1441
stm32l4x5_rcc_class_init(ObjectClass * klass,const void * data)1442 static void stm32l4x5_rcc_class_init(ObjectClass *klass, const void *data)
1443 {
1444 DeviceClass *dc = DEVICE_CLASS(klass);
1445 ResettableClass *rc = RESETTABLE_CLASS(klass);
1446
1447 assert(ARRAY_SIZE(CLOCK_MUX_INIT_INFO) == RCC_NUM_CLOCK_MUX);
1448
1449 rc->phases.hold = stm32l4x5_rcc_reset_hold;
1450 device_class_set_props(dc, stm32l4x5_rcc_properties);
1451 dc->realize = stm32l4x5_rcc_realize;
1452 dc->vmsd = &vmstate_stm32l4x5_rcc;
1453 }
1454
1455 static const TypeInfo stm32l4x5_rcc_types[] = {
1456 {
1457 .name = TYPE_STM32L4X5_RCC,
1458 .parent = TYPE_SYS_BUS_DEVICE,
1459 .instance_size = sizeof(Stm32l4x5RccState),
1460 .instance_init = stm32l4x5_rcc_init,
1461 .class_init = stm32l4x5_rcc_class_init,
1462 }, {
1463 .name = TYPE_RCC_CLOCK_MUX,
1464 .parent = TYPE_DEVICE,
1465 .instance_size = sizeof(RccClockMuxState),
1466 .instance_init = clock_mux_init,
1467 .class_init = clock_mux_class_init,
1468 }, {
1469 .name = TYPE_RCC_PLL,
1470 .parent = TYPE_DEVICE,
1471 .instance_size = sizeof(RccPllState),
1472 .instance_init = pll_init,
1473 .class_init = pll_class_init,
1474 }
1475 };
1476
1477 DEFINE_TYPES(stm32l4x5_rcc_types)
1478