1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 8 #ifndef __QCOM_CLK_ALPHA_PLL_H__ 9 #define __QCOM_CLK_ALPHA_PLL_H__ 10 11 #include <linux/clk-provider.h> 12 #include "clk-regmap.h" 13 14 /* Alpha PLL types */ 15 enum { 16 CLK_ALPHA_PLL_TYPE_DEFAULT, 17 CLK_ALPHA_PLL_TYPE_HUAYRA, 18 CLK_ALPHA_PLL_TYPE_HUAYRA_APSS, 19 CLK_ALPHA_PLL_TYPE_HUAYRA_2290, 20 CLK_ALPHA_PLL_TYPE_BRAMMO, 21 CLK_ALPHA_PLL_TYPE_FABIA, 22 CLK_ALPHA_PLL_TYPE_TRION, 23 CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, 24 CLK_ALPHA_PLL_TYPE_AGERA, 25 CLK_ALPHA_PLL_TYPE_ZONDA, 26 CLK_ALPHA_PLL_TYPE_REGERA = CLK_ALPHA_PLL_TYPE_ZONDA, 27 CLK_ALPHA_PLL_TYPE_ZONDA_OLE, 28 CLK_ALPHA_PLL_TYPE_LUCID_EVO, 29 CLK_ALPHA_PLL_TYPE_LUCID_OLE, 30 CLK_ALPHA_PLL_TYPE_PONGO_ELU, 31 CLK_ALPHA_PLL_TYPE_TAYCAN_ELU, 32 CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, 33 CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, 34 CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, 35 CLK_ALPHA_PLL_TYPE_STROMER, 36 CLK_ALPHA_PLL_TYPE_STROMER_PLUS, 37 CLK_ALPHA_PLL_TYPE_NSS_HUAYRA, 38 CLK_ALPHA_PLL_TYPE_MAX, 39 }; 40 41 enum { 42 PLL_OFF_L_VAL, 43 PLL_OFF_CAL_L_VAL, 44 PLL_OFF_ALPHA_VAL, 45 PLL_OFF_ALPHA_VAL_U, 46 PLL_OFF_USER_CTL, 47 PLL_OFF_USER_CTL_U, 48 PLL_OFF_USER_CTL_U1, 49 PLL_OFF_CONFIG_CTL, 50 PLL_OFF_CONFIG_CTL_U, 51 PLL_OFF_CONFIG_CTL_U1, 52 PLL_OFF_CONFIG_CTL_U2, 53 PLL_OFF_TEST_CTL, 54 PLL_OFF_TEST_CTL_U, 55 PLL_OFF_TEST_CTL_U1, 56 PLL_OFF_TEST_CTL_U2, 57 PLL_OFF_TEST_CTL_U3, 58 PLL_OFF_STATE, 59 PLL_OFF_STATUS, 60 PLL_OFF_OPMODE, 61 PLL_OFF_FRAC, 62 PLL_OFF_CAL_VAL, 63 PLL_OFF_MAX_REGS 64 }; 65 66 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; 67 68 struct pll_vco { 69 unsigned long min_freq; 70 unsigned long max_freq; 71 u32 val; 72 }; 73 74 #define VCO(a, b, c) { \ 75 .val = a,\ 76 .min_freq = b,\ 77 .max_freq = c,\ 78 } 79 80 /** 81 * struct clk_alpha_pll - phase locked loop (PLL) 82 * @offset: base address of registers 83 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 84 * @config: array of pll settings 85 * @vco_table: array of VCO settings 86 * @num_vco: number of VCO settings in @vco_table 87 * @flags: bitmask to indicate features supported by the hardware 88 * @clkr: regmap clock handle 89 */ 90 struct clk_alpha_pll { 91 u32 offset; 92 const u8 *regs; 93 94 const struct alpha_pll_config *config; 95 const struct pll_vco *vco_table; 96 size_t num_vco; 97 #define SUPPORTS_OFFLINE_REQ BIT(0) 98 #define SUPPORTS_FSM_MODE BIT(2) 99 #define SUPPORTS_DYNAMIC_UPDATE BIT(3) 100 #define SUPPORTS_FSM_LEGACY_MODE BIT(4) 101 u8 flags; 102 103 struct clk_regmap clkr; 104 }; 105 106 /** 107 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider 108 * @offset: base address of registers 109 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 110 * @width: width of post-divider 111 * @post_div_shift: shift to differentiate between odd & even post-divider 112 * @post_div_table: table with PLL odd and even post-divider settings 113 * @num_post_div: Number of PLL post-divider settings 114 * 115 * @clkr: regmap clock handle 116 */ 117 struct clk_alpha_pll_postdiv { 118 u32 offset; 119 u8 width; 120 const u8 *regs; 121 122 struct clk_regmap clkr; 123 int post_div_shift; 124 const struct clk_div_table *post_div_table; 125 size_t num_post_div; 126 }; 127 128 struct alpha_pll_config { 129 u32 l; 130 u32 alpha; 131 u32 alpha_hi; 132 u32 config_ctl_val; 133 u32 config_ctl_hi_val; 134 u32 config_ctl_hi1_val; 135 u32 config_ctl_hi2_val; 136 u32 user_ctl_val; 137 u32 user_ctl_hi_val; 138 u32 user_ctl_hi1_val; 139 u32 test_ctl_val; 140 u32 test_ctl_mask; 141 u32 test_ctl_hi_val; 142 u32 test_ctl_hi_mask; 143 u32 test_ctl_hi1_val; 144 u32 test_ctl_hi2_val; 145 u32 test_ctl_hi3_val; 146 u32 main_output_mask; 147 u32 aux_output_mask; 148 u32 aux2_output_mask; 149 u32 early_output_mask; 150 u32 alpha_en_mask; 151 u32 alpha_mode_mask; 152 u32 pre_div_val; 153 u32 pre_div_mask; 154 u32 post_div_val; 155 u32 post_div_mask; 156 u32 vco_val; 157 u32 vco_mask; 158 u32 status_val; 159 u32 status_mask; 160 u32 lock_det; 161 }; 162 163 extern const struct clk_ops clk_alpha_pll_ops; 164 extern const struct clk_ops clk_alpha_pll_fixed_ops; 165 extern const struct clk_ops clk_alpha_pll_hwfsm_ops; 166 extern const struct clk_ops clk_alpha_pll_postdiv_ops; 167 extern const struct clk_ops clk_alpha_pll_huayra_ops; 168 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; 169 extern const struct clk_ops clk_alpha_pll_stromer_ops; 170 extern const struct clk_ops clk_alpha_pll_stromer_plus_ops; 171 172 extern const struct clk_ops clk_alpha_pll_fabia_ops; 173 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; 174 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops; 175 176 extern const struct clk_ops clk_alpha_pll_trion_ops; 177 extern const struct clk_ops clk_alpha_pll_fixed_trion_ops; 178 extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops; 179 180 extern const struct clk_ops clk_alpha_pll_lucid_ops; 181 #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops 182 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops; 183 extern const struct clk_ops clk_alpha_pll_agera_ops; 184 185 extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops; 186 extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops; 187 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; 188 189 extern const struct clk_ops clk_alpha_pll_zonda_ops; 190 #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops 191 #define clk_alpha_pll_zonda_ole_ops clk_alpha_pll_zonda_ops 192 193 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; 194 #define clk_alpha_pll_taycan_elu_ops clk_alpha_pll_lucid_evo_ops 195 extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops; 196 #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops 197 extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; 198 #define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops 199 #define clk_alpha_pll_fixed_taycan_elu_ops clk_alpha_pll_fixed_lucid_evo_ops 200 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; 201 #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops 202 #define clk_alpha_pll_postdiv_taycan_elu_ops clk_alpha_pll_postdiv_lucid_evo_ops 203 204 extern const struct clk_ops clk_alpha_pll_pongo_elu_ops; 205 extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; 206 #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops 207 208 extern const struct clk_ops clk_alpha_pll_regera_ops; 209 extern const struct clk_ops clk_alpha_pll_slew_ops; 210 211 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 212 const struct alpha_pll_config *config); 213 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 214 const struct alpha_pll_config *config); 215 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 216 const struct alpha_pll_config *config); 217 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 218 const struct alpha_pll_config *config); 219 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 220 const struct alpha_pll_config *config); 221 #define clk_lucid_pll_configure(pll, regmap, config) \ 222 clk_trion_pll_configure(pll, regmap, config) 223 224 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 225 const struct alpha_pll_config *config); 226 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 227 const struct alpha_pll_config *config); 228 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 229 const struct alpha_pll_config *config); 230 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 231 const struct alpha_pll_config *config); 232 void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 233 const struct alpha_pll_config *config); 234 #define clk_taycan_elu_pll_configure(pll, regmap, config) \ 235 clk_lucid_evo_pll_configure(pll, regmap, config) 236 237 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 238 const struct alpha_pll_config *config); 239 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 240 const struct alpha_pll_config *config); 241 void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 242 const struct alpha_pll_config *config); 243 void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap); 244 245 #endif 246