1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/export.h>
9 #include <linux/clk-provider.h>
10 #include <linux/regmap.h>
11 #include <linux/delay.h>
12
13 #include "clk-alpha-pll.h"
14 #include "common.h"
15
16 #define PLL_MODE(p) ((p)->offset + 0x0)
17 # define PLL_OUTCTRL BIT(0)
18 # define PLL_BYPASSNL BIT(1)
19 # define PLL_RESET_N BIT(2)
20 # define PLL_OFFLINE_REQ BIT(7)
21 # define PLL_LOCK_COUNT_SHIFT 8
22 # define PLL_LOCK_COUNT_MASK 0x3f
23 # define PLL_BIAS_COUNT_SHIFT 14
24 # define PLL_BIAS_COUNT_MASK 0x3f
25 # define PLL_VOTE_FSM_ENA BIT(20)
26 # define PLL_FSM_ENA BIT(20)
27 # define PLL_VOTE_FSM_RESET BIT(21)
28 # define PLL_UPDATE BIT(22)
29 # define PLL_UPDATE_BYPASS BIT(23)
30 # define PLL_FSM_LEGACY_MODE BIT(24)
31 # define PLL_OFFLINE_ACK BIT(28)
32 # define ALPHA_PLL_ACK_LATCH BIT(29)
33 # define PLL_ACTIVE_FLAG BIT(30)
34 # define PLL_LOCK_DET BIT(31)
35
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
40
41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
42 # define PLL_POST_DIV_SHIFT 8
43 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0)
44 # define PLL_ALPHA_MSB BIT(15)
45 # define PLL_ALPHA_EN BIT(24)
46 # define PLL_ALPHA_MODE BIT(25)
47 # define PLL_VCO_SHIFT 20
48 # define PLL_VCO_MASK 0x3
49
50 #define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
51 #define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
52
53 #define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
54 #define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
55 #define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
56 #define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2])
57 #define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
58 #define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
59 #define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
60 #define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
61 #define PLL_TEST_CTL_U3(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U3])
62 #define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
63 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
64 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
65
66 #define GET_PLL_TYPE(pll) (((pll)->regs - clk_alpha_pll_regs[0]) / PLL_OFF_MAX_REGS)
67
68 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
69 [CLK_ALPHA_PLL_TYPE_DEFAULT] = {
70 [PLL_OFF_L_VAL] = 0x04,
71 [PLL_OFF_ALPHA_VAL] = 0x08,
72 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
73 [PLL_OFF_USER_CTL] = 0x10,
74 [PLL_OFF_USER_CTL_U] = 0x14,
75 [PLL_OFF_CONFIG_CTL] = 0x18,
76 [PLL_OFF_TEST_CTL] = 0x1c,
77 [PLL_OFF_TEST_CTL_U] = 0x20,
78 [PLL_OFF_STATUS] = 0x24,
79 },
80 [CLK_ALPHA_PLL_TYPE_HUAYRA] = {
81 [PLL_OFF_L_VAL] = 0x04,
82 [PLL_OFF_ALPHA_VAL] = 0x08,
83 [PLL_OFF_USER_CTL] = 0x10,
84 [PLL_OFF_CONFIG_CTL] = 0x14,
85 [PLL_OFF_CONFIG_CTL_U] = 0x18,
86 [PLL_OFF_TEST_CTL] = 0x1c,
87 [PLL_OFF_TEST_CTL_U] = 0x20,
88 [PLL_OFF_STATUS] = 0x24,
89 },
90 [CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] = {
91 [PLL_OFF_L_VAL] = 0x08,
92 [PLL_OFF_ALPHA_VAL] = 0x10,
93 [PLL_OFF_USER_CTL] = 0x18,
94 [PLL_OFF_CONFIG_CTL] = 0x20,
95 [PLL_OFF_CONFIG_CTL_U] = 0x24,
96 [PLL_OFF_STATUS] = 0x28,
97 [PLL_OFF_TEST_CTL] = 0x30,
98 [PLL_OFF_TEST_CTL_U] = 0x34,
99 },
100 [CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = {
101 [PLL_OFF_L_VAL] = 0x04,
102 [PLL_OFF_ALPHA_VAL] = 0x08,
103 [PLL_OFF_USER_CTL] = 0x0c,
104 [PLL_OFF_CONFIG_CTL] = 0x10,
105 [PLL_OFF_CONFIG_CTL_U] = 0x14,
106 [PLL_OFF_CONFIG_CTL_U1] = 0x18,
107 [PLL_OFF_TEST_CTL] = 0x1c,
108 [PLL_OFF_TEST_CTL_U] = 0x20,
109 [PLL_OFF_TEST_CTL_U1] = 0x24,
110 [PLL_OFF_OPMODE] = 0x28,
111 [PLL_OFF_STATUS] = 0x38,
112 },
113 [CLK_ALPHA_PLL_TYPE_BRAMMO] = {
114 [PLL_OFF_L_VAL] = 0x04,
115 [PLL_OFF_ALPHA_VAL] = 0x08,
116 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
117 [PLL_OFF_USER_CTL] = 0x10,
118 [PLL_OFF_CONFIG_CTL] = 0x18,
119 [PLL_OFF_TEST_CTL] = 0x1c,
120 [PLL_OFF_STATUS] = 0x24,
121 },
122 [CLK_ALPHA_PLL_TYPE_FABIA] = {
123 [PLL_OFF_L_VAL] = 0x04,
124 [PLL_OFF_USER_CTL] = 0x0c,
125 [PLL_OFF_USER_CTL_U] = 0x10,
126 [PLL_OFF_CONFIG_CTL] = 0x14,
127 [PLL_OFF_CONFIG_CTL_U] = 0x18,
128 [PLL_OFF_TEST_CTL] = 0x1c,
129 [PLL_OFF_TEST_CTL_U] = 0x20,
130 [PLL_OFF_STATUS] = 0x24,
131 [PLL_OFF_OPMODE] = 0x2c,
132 [PLL_OFF_FRAC] = 0x38,
133 },
134 [CLK_ALPHA_PLL_TYPE_TRION] = {
135 [PLL_OFF_L_VAL] = 0x04,
136 [PLL_OFF_CAL_L_VAL] = 0x08,
137 [PLL_OFF_USER_CTL] = 0x0c,
138 [PLL_OFF_USER_CTL_U] = 0x10,
139 [PLL_OFF_USER_CTL_U1] = 0x14,
140 [PLL_OFF_CONFIG_CTL] = 0x18,
141 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
142 [PLL_OFF_CONFIG_CTL_U1] = 0x20,
143 [PLL_OFF_TEST_CTL] = 0x24,
144 [PLL_OFF_TEST_CTL_U] = 0x28,
145 [PLL_OFF_TEST_CTL_U1] = 0x2c,
146 [PLL_OFF_STATUS] = 0x30,
147 [PLL_OFF_OPMODE] = 0x38,
148 [PLL_OFF_ALPHA_VAL] = 0x40,
149 },
150 [CLK_ALPHA_PLL_TYPE_AGERA] = {
151 [PLL_OFF_L_VAL] = 0x04,
152 [PLL_OFF_ALPHA_VAL] = 0x08,
153 [PLL_OFF_USER_CTL] = 0x0c,
154 [PLL_OFF_CONFIG_CTL] = 0x10,
155 [PLL_OFF_CONFIG_CTL_U] = 0x14,
156 [PLL_OFF_TEST_CTL] = 0x18,
157 [PLL_OFF_TEST_CTL_U] = 0x1c,
158 [PLL_OFF_STATUS] = 0x2c,
159 },
160 [CLK_ALPHA_PLL_TYPE_ZONDA] = {
161 [PLL_OFF_L_VAL] = 0x04,
162 [PLL_OFF_ALPHA_VAL] = 0x08,
163 [PLL_OFF_USER_CTL] = 0x0c,
164 [PLL_OFF_CONFIG_CTL] = 0x10,
165 [PLL_OFF_CONFIG_CTL_U] = 0x14,
166 [PLL_OFF_CONFIG_CTL_U1] = 0x18,
167 [PLL_OFF_TEST_CTL] = 0x1c,
168 [PLL_OFF_TEST_CTL_U] = 0x20,
169 [PLL_OFF_TEST_CTL_U1] = 0x24,
170 [PLL_OFF_OPMODE] = 0x28,
171 [PLL_OFF_STATUS] = 0x38,
172 },
173 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = {
174 [PLL_OFF_OPMODE] = 0x04,
175 [PLL_OFF_STATUS] = 0x0c,
176 [PLL_OFF_L_VAL] = 0x10,
177 [PLL_OFF_ALPHA_VAL] = 0x14,
178 [PLL_OFF_USER_CTL] = 0x18,
179 [PLL_OFF_USER_CTL_U] = 0x1c,
180 [PLL_OFF_CONFIG_CTL] = 0x20,
181 [PLL_OFF_CONFIG_CTL_U] = 0x24,
182 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
183 [PLL_OFF_TEST_CTL] = 0x2c,
184 [PLL_OFF_TEST_CTL_U] = 0x30,
185 [PLL_OFF_TEST_CTL_U1] = 0x34,
186 },
187 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = {
188 [PLL_OFF_OPMODE] = 0x04,
189 [PLL_OFF_STATE] = 0x08,
190 [PLL_OFF_STATUS] = 0x0c,
191 [PLL_OFF_L_VAL] = 0x10,
192 [PLL_OFF_ALPHA_VAL] = 0x14,
193 [PLL_OFF_USER_CTL] = 0x18,
194 [PLL_OFF_USER_CTL_U] = 0x1c,
195 [PLL_OFF_CONFIG_CTL] = 0x20,
196 [PLL_OFF_CONFIG_CTL_U] = 0x24,
197 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
198 [PLL_OFF_TEST_CTL] = 0x2c,
199 [PLL_OFF_TEST_CTL_U] = 0x30,
200 [PLL_OFF_TEST_CTL_U1] = 0x34,
201 [PLL_OFF_TEST_CTL_U2] = 0x38,
202 },
203 [CLK_ALPHA_PLL_TYPE_PONGO_ELU] = {
204 [PLL_OFF_OPMODE] = 0x04,
205 [PLL_OFF_STATE] = 0x08,
206 [PLL_OFF_STATUS] = 0x0c,
207 [PLL_OFF_L_VAL] = 0x10,
208 [PLL_OFF_USER_CTL] = 0x14,
209 [PLL_OFF_USER_CTL_U] = 0x18,
210 [PLL_OFF_CONFIG_CTL] = 0x1c,
211 [PLL_OFF_CONFIG_CTL_U] = 0x20,
212 [PLL_OFF_CONFIG_CTL_U1] = 0x24,
213 [PLL_OFF_CONFIG_CTL_U2] = 0x28,
214 [PLL_OFF_TEST_CTL] = 0x2c,
215 [PLL_OFF_TEST_CTL_U] = 0x30,
216 [PLL_OFF_TEST_CTL_U1] = 0x34,
217 [PLL_OFF_TEST_CTL_U2] = 0x38,
218 [PLL_OFF_TEST_CTL_U3] = 0x3c,
219 },
220 [CLK_ALPHA_PLL_TYPE_TAYCAN_ELU] = {
221 [PLL_OFF_OPMODE] = 0x04,
222 [PLL_OFF_STATE] = 0x08,
223 [PLL_OFF_STATUS] = 0x0c,
224 [PLL_OFF_L_VAL] = 0x10,
225 [PLL_OFF_ALPHA_VAL] = 0x14,
226 [PLL_OFF_USER_CTL] = 0x18,
227 [PLL_OFF_USER_CTL_U] = 0x1c,
228 [PLL_OFF_CONFIG_CTL] = 0x20,
229 [PLL_OFF_CONFIG_CTL_U] = 0x24,
230 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
231 [PLL_OFF_TEST_CTL] = 0x2c,
232 [PLL_OFF_TEST_CTL_U] = 0x30,
233 },
234 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
235 [PLL_OFF_OPMODE] = 0x04,
236 [PLL_OFF_STATUS] = 0x0c,
237 [PLL_OFF_L_VAL] = 0x10,
238 [PLL_OFF_USER_CTL] = 0x14,
239 [PLL_OFF_USER_CTL_U] = 0x18,
240 [PLL_OFF_CONFIG_CTL] = 0x1c,
241 [PLL_OFF_CONFIG_CTL_U] = 0x20,
242 [PLL_OFF_CONFIG_CTL_U1] = 0x24,
243 [PLL_OFF_TEST_CTL] = 0x28,
244 [PLL_OFF_TEST_CTL_U] = 0x2c,
245 },
246 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = {
247 [PLL_OFF_L_VAL] = 0x04,
248 [PLL_OFF_ALPHA_VAL] = 0x08,
249 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
250 [PLL_OFF_TEST_CTL] = 0x10,
251 [PLL_OFF_TEST_CTL_U] = 0x14,
252 [PLL_OFF_USER_CTL] = 0x18,
253 [PLL_OFF_USER_CTL_U] = 0x1c,
254 [PLL_OFF_CONFIG_CTL] = 0x20,
255 [PLL_OFF_STATUS] = 0x24,
256 },
257 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = {
258 [PLL_OFF_L_VAL] = 0x04,
259 [PLL_OFF_ALPHA_VAL] = 0x08,
260 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
261 [PLL_OFF_TEST_CTL] = 0x10,
262 [PLL_OFF_TEST_CTL_U] = 0x14,
263 [PLL_OFF_USER_CTL] = 0x18,
264 [PLL_OFF_CONFIG_CTL] = 0x1C,
265 [PLL_OFF_STATUS] = 0x20,
266 },
267 [CLK_ALPHA_PLL_TYPE_STROMER] = {
268 [PLL_OFF_L_VAL] = 0x08,
269 [PLL_OFF_ALPHA_VAL] = 0x10,
270 [PLL_OFF_ALPHA_VAL_U] = 0x14,
271 [PLL_OFF_USER_CTL] = 0x18,
272 [PLL_OFF_USER_CTL_U] = 0x1c,
273 [PLL_OFF_CONFIG_CTL] = 0x20,
274 [PLL_OFF_STATUS] = 0x28,
275 [PLL_OFF_TEST_CTL] = 0x30,
276 [PLL_OFF_TEST_CTL_U] = 0x34,
277 },
278 [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
279 [PLL_OFF_L_VAL] = 0x04,
280 [PLL_OFF_USER_CTL] = 0x08,
281 [PLL_OFF_USER_CTL_U] = 0x0c,
282 [PLL_OFF_CONFIG_CTL] = 0x10,
283 [PLL_OFF_TEST_CTL] = 0x14,
284 [PLL_OFF_TEST_CTL_U] = 0x18,
285 [PLL_OFF_STATUS] = 0x1c,
286 [PLL_OFF_ALPHA_VAL] = 0x24,
287 [PLL_OFF_ALPHA_VAL_U] = 0x28,
288 },
289 [CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = {
290 [PLL_OFF_L_VAL] = 0x04,
291 [PLL_OFF_ALPHA_VAL] = 0x08,
292 [PLL_OFF_USER_CTL] = 0x0c,
293 [PLL_OFF_USER_CTL_U] = 0x10,
294 [PLL_OFF_CONFIG_CTL] = 0x14,
295 [PLL_OFF_CONFIG_CTL_U] = 0x18,
296 [PLL_OFF_CONFIG_CTL_U1] = 0x1c,
297 [PLL_OFF_CONFIG_CTL_U2] = 0x20,
298 [PLL_OFF_TEST_CTL] = 0x24,
299 [PLL_OFF_TEST_CTL_U] = 0x28,
300 [PLL_OFF_TEST_CTL_U1] = 0x2c,
301 [PLL_OFF_OPMODE] = 0x30,
302 [PLL_OFF_STATUS] = 0x3c,
303 },
304 [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = {
305 [PLL_OFF_L_VAL] = 0x04,
306 [PLL_OFF_ALPHA_VAL] = 0x08,
307 [PLL_OFF_TEST_CTL] = 0x0c,
308 [PLL_OFF_TEST_CTL_U] = 0x10,
309 [PLL_OFF_USER_CTL] = 0x14,
310 [PLL_OFF_CONFIG_CTL] = 0x18,
311 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
312 [PLL_OFF_STATUS] = 0x20,
313 },
314
315 };
316 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
317
318 /*
319 * Even though 40 bits are present, use only 32 for ease of calculation.
320 */
321 #define ALPHA_REG_BITWIDTH 40
322 #define ALPHA_REG_16BIT_WIDTH 16
323 #define ALPHA_BITWIDTH 32U
324 #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
325
326 #define ALPHA_PLL_STATUS_REG_SHIFT 8
327
328 #define PLL_HUAYRA_M_WIDTH 8
329 #define PLL_HUAYRA_M_SHIFT 8
330 #define PLL_HUAYRA_M_MASK 0xff
331 #define PLL_HUAYRA_N_SHIFT 0
332 #define PLL_HUAYRA_N_MASK 0xff
333 #define PLL_HUAYRA_ALPHA_WIDTH 16
334
335 #define PLL_STANDBY 0x0
336 #define PLL_RUN 0x1
337 #define PLL_OUT_MASK 0x7
338 #define PLL_RATE_MARGIN 500
339
340 /* TRION PLL specific settings and offsets */
341 #define TRION_PLL_CAL_VAL 0x44
342 #define TRION_PCAL_DONE BIT(26)
343
344 /* LUCID PLL specific settings and offsets */
345 #define LUCID_PCAL_DONE BIT(27)
346
347 /* LUCID 5LPE PLL specific settings and offsets */
348 #define LUCID_5LPE_PCAL_DONE BIT(11)
349 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13)
350 #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
351 #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
352
353 /* LUCID EVO PLL specific settings and offsets */
354 #define LUCID_EVO_PCAL_NOT_DONE BIT(8)
355 #define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
356 #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
357 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16
358 #define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT 24
359
360 /* PONGO ELU PLL specific setting and offsets */
361 #define PONGO_PLL_OUT_MASK GENMASK(1, 0)
362 #define PONGO_PLL_L_VAL_MASK GENMASK(11, 0)
363 #define PONGO_XO_PRESENT BIT(10)
364 #define PONGO_CLOCK_SELECT BIT(12)
365
366 /* ZONDA PLL specific */
367 #define ZONDA_PLL_OUT_MASK 0xf
368 #define ZONDA_STAY_IN_CFA BIT(16)
369 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
370
371 #define pll_alpha_width(p) \
372 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
373 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
374
375 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
376
377 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
378 struct clk_alpha_pll, clkr)
379
380 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
381 struct clk_alpha_pll_postdiv, clkr)
382
wait_for_pll(struct clk_alpha_pll * pll,u32 mask,bool inverse,const char * action)383 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
384 const char *action)
385 {
386 u32 val;
387 int count;
388 int ret;
389 const char *name = clk_hw_get_name(&pll->clkr.hw);
390
391 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
392 if (ret)
393 return ret;
394
395 /* Pongo PLLs using a 32KHz reference can take upwards of 1500us to lock. */
396 for (count = 1500; count > 0; count--) {
397 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
398 if (ret)
399 return ret;
400 if (inverse && !(val & mask))
401 return 0;
402 else if ((val & mask) == mask)
403 return 0;
404
405 udelay(1);
406 }
407
408 WARN(1, "%s failed to %s!\n", name, action);
409 return -ETIMEDOUT;
410 }
411
412 #define wait_for_pll_enable_active(pll) \
413 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
414
415 #define wait_for_pll_enable_lock(pll) \
416 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
417
418 #define wait_for_zonda_pll_freq_lock(pll) \
419 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
420
421 #define wait_for_pll_disable(pll) \
422 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
423
424 #define wait_for_pll_offline(pll) \
425 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
426
427 #define wait_for_pll_update(pll) \
428 wait_for_pll(pll, PLL_UPDATE, 1, "update")
429
430 #define wait_for_pll_update_ack_set(pll) \
431 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
432
433 #define wait_for_pll_update_ack_clear(pll) \
434 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
435
clk_alpha_pll_write_config(struct regmap * regmap,unsigned int reg,unsigned int val)436 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg,
437 unsigned int val)
438 {
439 if (val)
440 regmap_write(regmap, reg, val);
441 }
442
clk_alpha_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)443 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
444 const struct alpha_pll_config *config)
445 {
446 u32 val, mask;
447
448 regmap_write(regmap, PLL_L_VAL(pll), config->l);
449 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
450 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
451
452 if (pll_has_64bit_config(pll))
453 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
454 config->config_ctl_hi_val);
455
456 if (pll_alpha_width(pll) > 32)
457 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
458
459 val = config->main_output_mask;
460 val |= config->aux_output_mask;
461 val |= config->aux2_output_mask;
462 val |= config->early_output_mask;
463 val |= config->pre_div_val;
464 val |= config->post_div_val;
465 val |= config->vco_val;
466 val |= config->alpha_en_mask;
467 val |= config->alpha_mode_mask;
468
469 mask = config->main_output_mask;
470 mask |= config->aux_output_mask;
471 mask |= config->aux2_output_mask;
472 mask |= config->early_output_mask;
473 mask |= config->pre_div_mask;
474 mask |= config->post_div_mask;
475 mask |= config->vco_mask;
476 mask |= config->alpha_en_mask;
477 mask |= config->alpha_mode_mask;
478
479 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
480
481 if (config->test_ctl_mask)
482 regmap_update_bits(regmap, PLL_TEST_CTL(pll),
483 config->test_ctl_mask,
484 config->test_ctl_val);
485 else
486 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
487 config->test_ctl_val);
488
489 if (config->test_ctl_hi_mask)
490 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll),
491 config->test_ctl_hi_mask,
492 config->test_ctl_hi_val);
493 else
494 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
495 config->test_ctl_hi_val);
496
497 if (pll->flags & SUPPORTS_FSM_MODE)
498 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
499 }
500 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
501
clk_alpha_pll_hwfsm_enable(struct clk_hw * hw)502 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
503 {
504 int ret;
505 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
506 u32 val;
507
508 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
509 if (ret)
510 return ret;
511
512 val |= PLL_FSM_ENA;
513
514 if (pll->flags & SUPPORTS_OFFLINE_REQ)
515 val &= ~PLL_OFFLINE_REQ;
516
517 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
518 if (ret)
519 return ret;
520
521 /* Make sure enable request goes through before waiting for update */
522 mb();
523
524 return wait_for_pll_enable_active(pll);
525 }
526
clk_alpha_pll_hwfsm_disable(struct clk_hw * hw)527 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
528 {
529 int ret;
530 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
531 u32 val;
532
533 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
534 if (ret)
535 return;
536
537 if (pll->flags & SUPPORTS_OFFLINE_REQ) {
538 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
539 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
540 if (ret)
541 return;
542
543 ret = wait_for_pll_offline(pll);
544 if (ret)
545 return;
546 }
547
548 /* Disable hwfsm */
549 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
550 PLL_FSM_ENA, 0);
551 if (ret)
552 return;
553
554 wait_for_pll_disable(pll);
555 }
556
pll_is_enabled(struct clk_hw * hw,u32 mask)557 static int pll_is_enabled(struct clk_hw *hw, u32 mask)
558 {
559 int ret;
560 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
561 u32 val;
562
563 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
564 if (ret)
565 return ret;
566
567 return !!(val & mask);
568 }
569
clk_alpha_pll_hwfsm_is_enabled(struct clk_hw * hw)570 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
571 {
572 return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
573 }
574
clk_alpha_pll_is_enabled(struct clk_hw * hw)575 static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
576 {
577 return pll_is_enabled(hw, PLL_LOCK_DET);
578 }
579
clk_alpha_pll_enable(struct clk_hw * hw)580 static int clk_alpha_pll_enable(struct clk_hw *hw)
581 {
582 int ret;
583 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
584 u32 val, mask;
585
586 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
587 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
588 if (ret)
589 return ret;
590
591 /* If in FSM mode, just vote for it */
592 if (val & PLL_VOTE_FSM_ENA) {
593 ret = clk_enable_regmap(hw);
594 if (ret)
595 return ret;
596 return wait_for_pll_enable_active(pll);
597 }
598
599 /* Skip if already enabled */
600 if ((val & mask) == mask)
601 return 0;
602
603 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
604 PLL_BYPASSNL, PLL_BYPASSNL);
605 if (ret)
606 return ret;
607
608 /*
609 * H/W requires a 5us delay between disabling the bypass and
610 * de-asserting the reset.
611 */
612 mb();
613 udelay(5);
614
615 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
616 PLL_RESET_N, PLL_RESET_N);
617 if (ret)
618 return ret;
619
620 ret = wait_for_pll_enable_lock(pll);
621 if (ret)
622 return ret;
623
624 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
625 PLL_OUTCTRL, PLL_OUTCTRL);
626
627 /* Ensure that the write above goes through before returning. */
628 mb();
629 return ret;
630 }
631
clk_alpha_pll_disable(struct clk_hw * hw)632 static void clk_alpha_pll_disable(struct clk_hw *hw)
633 {
634 int ret;
635 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
636 u32 val, mask;
637
638 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
639 if (ret)
640 return;
641
642 /* If in FSM mode, just unvote it */
643 if (val & PLL_VOTE_FSM_ENA) {
644 clk_disable_regmap(hw);
645 return;
646 }
647
648 mask = PLL_OUTCTRL;
649 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
650
651 /* Delay of 2 output clock ticks required until output is disabled */
652 mb();
653 udelay(1);
654
655 mask = PLL_RESET_N | PLL_BYPASSNL;
656 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
657 }
658
659 static unsigned long
alpha_pll_calc_rate(u64 prate,u32 l,u32 a,u32 alpha_width)660 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
661 {
662 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
663 }
664
665 static unsigned long
alpha_pll_round_rate(unsigned long rate,unsigned long prate,u32 * l,u64 * a,u32 alpha_width)666 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
667 u32 alpha_width)
668 {
669 u64 remainder;
670 u64 quotient;
671
672 quotient = rate;
673 remainder = do_div(quotient, prate);
674 *l = quotient;
675
676 if (!remainder) {
677 *a = 0;
678 return rate;
679 }
680
681 /* Upper ALPHA_BITWIDTH bits of Alpha */
682 quotient = remainder << ALPHA_SHIFT(alpha_width);
683
684 remainder = do_div(quotient, prate);
685
686 if (remainder)
687 quotient++;
688
689 *a = quotient;
690 return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
691 }
692
693 static const struct pll_vco *
alpha_pll_find_vco(const struct clk_alpha_pll * pll,unsigned long rate)694 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
695 {
696 const struct pll_vco *v = pll->vco_table;
697 const struct pll_vco *end = v + pll->num_vco;
698
699 for (; v < end; v++)
700 if (rate >= v->min_freq && rate <= v->max_freq)
701 return v;
702
703 return NULL;
704 }
705
706 static unsigned long
clk_alpha_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)707 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
708 {
709 u32 l, low, high, ctl;
710 u64 a = 0, prate = parent_rate;
711 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
712 u32 alpha_width = pll_alpha_width(pll);
713
714 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
715 return 0;
716
717 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl))
718 return 0;
719
720 if (ctl & PLL_ALPHA_EN) {
721 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low))
722 return 0;
723 if (alpha_width > 32) {
724 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
725 &high))
726 return 0;
727 a = (u64)high << 32 | low;
728 } else {
729 a = low & GENMASK(alpha_width - 1, 0);
730 }
731
732 if (alpha_width > ALPHA_BITWIDTH)
733 a >>= alpha_width - ALPHA_BITWIDTH;
734 }
735
736 return alpha_pll_calc_rate(prate, l, a, alpha_width);
737 }
738
739
__clk_alpha_pll_update_latch(struct clk_alpha_pll * pll)740 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
741 {
742 int ret;
743 u32 mode;
744
745 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
746
747 /* Latch the input to the PLL */
748 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
749 PLL_UPDATE);
750
751 /* Wait for 2 reference cycle before checking ACK bit */
752 udelay(1);
753
754 /*
755 * PLL will latch the new L, Alpha and freq control word.
756 * PLL will respond by raising PLL_ACK_LATCH output when new programming
757 * has been latched in and PLL is being updated. When
758 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
759 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
760 */
761 if (mode & PLL_UPDATE_BYPASS) {
762 ret = wait_for_pll_update_ack_set(pll);
763 if (ret)
764 return ret;
765
766 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
767 } else {
768 ret = wait_for_pll_update(pll);
769 if (ret)
770 return ret;
771 }
772
773 ret = wait_for_pll_update_ack_clear(pll);
774 if (ret)
775 return ret;
776
777 /* Wait for PLL output to stabilize */
778 udelay(10);
779
780 return 0;
781 }
782
clk_alpha_pll_update_latch(struct clk_alpha_pll * pll,int (* is_enabled)(struct clk_hw *))783 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
784 int (*is_enabled)(struct clk_hw *))
785 {
786 if (!is_enabled(&pll->clkr.hw) ||
787 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
788 return 0;
789
790 return __clk_alpha_pll_update_latch(pll);
791 }
792
clk_alpha_pll_update_configs(struct clk_alpha_pll * pll,const struct pll_vco * vco,u32 l,u64 alpha,u32 alpha_width,bool alpha_en)793 static void clk_alpha_pll_update_configs(struct clk_alpha_pll *pll, const struct pll_vco *vco,
794 u32 l, u64 alpha, u32 alpha_width, bool alpha_en)
795 {
796 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
797
798 if (alpha_width > ALPHA_BITWIDTH)
799 alpha <<= alpha_width - ALPHA_BITWIDTH;
800
801 if (alpha_width > 32)
802 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), upper_32_bits(alpha));
803
804 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), lower_32_bits(alpha));
805
806 if (vco) {
807 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
808 PLL_VCO_MASK << PLL_VCO_SHIFT,
809 vco->val << PLL_VCO_SHIFT);
810 }
811
812 if (alpha_en)
813 regmap_set_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_ALPHA_EN);
814 }
815
__clk_alpha_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate,int (* is_enabled)(struct clk_hw *))816 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
817 unsigned long prate,
818 int (*is_enabled)(struct clk_hw *))
819 {
820 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
821 const struct pll_vco *vco;
822 u32 l, alpha_width = pll_alpha_width(pll);
823 u64 a;
824
825 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
826 vco = alpha_pll_find_vco(pll, rate);
827 if (pll->vco_table && !vco) {
828 pr_err("%s: alpha pll not in a valid vco range\n",
829 clk_hw_get_name(hw));
830 return -EINVAL;
831 }
832
833 clk_alpha_pll_update_configs(pll, vco, l, a, alpha_width, true);
834
835 return clk_alpha_pll_update_latch(pll, is_enabled);
836 }
837
clk_alpha_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)838 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
839 unsigned long prate)
840 {
841 return __clk_alpha_pll_set_rate(hw, rate, prate,
842 clk_alpha_pll_is_enabled);
843 }
844
clk_alpha_pll_hwfsm_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)845 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
846 unsigned long prate)
847 {
848 return __clk_alpha_pll_set_rate(hw, rate, prate,
849 clk_alpha_pll_hwfsm_is_enabled);
850 }
851
clk_alpha_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)852 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
853 unsigned long *prate)
854 {
855 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
856 u32 l, alpha_width = pll_alpha_width(pll);
857 u64 a;
858 unsigned long min_freq, max_freq;
859
860 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
861 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
862 return rate;
863
864 min_freq = pll->vco_table[0].min_freq;
865 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
866
867 return clamp(rate, min_freq, max_freq);
868 }
869
clk_huayra_2290_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)870 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
871 const struct alpha_pll_config *config)
872 {
873 u32 val;
874
875 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
876 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
877 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
878 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
879 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
880 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
881 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
882 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
883 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
884
885 /* Set PLL_BYPASSNL */
886 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
887 regmap_read(regmap, PLL_MODE(pll), &val);
888
889 /* Wait 5 us between setting BYPASS and deasserting reset */
890 udelay(5);
891
892 /* Take PLL out from reset state */
893 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
894 regmap_read(regmap, PLL_MODE(pll), &val);
895
896 /* Wait 50us for PLL_LOCK_DET bit to go high */
897 usleep_range(50, 55);
898
899 /* Enable PLL output */
900 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
901 }
902 EXPORT_SYMBOL_GPL(clk_huayra_2290_pll_configure);
903
904 static unsigned long
alpha_huayra_pll_calc_rate(u64 prate,u32 l,u32 a)905 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
906 {
907 /*
908 * a contains 16 bit alpha_val in two’s complement number in the range
909 * of [-0.5, 0.5).
910 */
911 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
912 l -= 1;
913
914 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
915 }
916
917 static unsigned long
alpha_huayra_pll_round_rate(unsigned long rate,unsigned long prate,u32 * l,u32 * a)918 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
919 u32 *l, u32 *a)
920 {
921 u64 remainder;
922 u64 quotient;
923
924 quotient = rate;
925 remainder = do_div(quotient, prate);
926 *l = quotient;
927
928 if (!remainder) {
929 *a = 0;
930 return rate;
931 }
932
933 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
934 remainder = do_div(quotient, prate);
935
936 if (remainder)
937 quotient++;
938
939 /*
940 * alpha_val should be in two’s complement number in the range
941 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
942 * since alpha value will be subtracted in this case.
943 */
944 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
945 *l += 1;
946
947 *a = quotient;
948 return alpha_huayra_pll_calc_rate(prate, *l, *a);
949 }
950
951 static unsigned long
alpha_pll_huayra_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)952 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
953 {
954 u64 rate = parent_rate, tmp;
955 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
956 u32 l, alpha = 0, ctl, alpha_m, alpha_n;
957
958 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
959 return 0;
960
961 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl))
962 return 0;
963
964 if (ctl & PLL_ALPHA_EN) {
965 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
966 /*
967 * Depending upon alpha_mode, it can be treated as M/N value or
968 * as a two’s complement number. When alpha_mode=1,
969 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
970 *
971 * Fout=FIN*(L+(M/N))
972 *
973 * M is a signed number (-128 to 127) and N is unsigned
974 * (0 to 255). M/N has to be within +/-0.5.
975 *
976 * When alpha_mode=0, it is a two’s complement number in the
977 * range [-0.5, 0.5).
978 *
979 * Fout=FIN*(L+(alpha_val)/2^16)
980 *
981 * where alpha_val is two’s complement number.
982 */
983 if (!(ctl & PLL_ALPHA_MODE))
984 return alpha_huayra_pll_calc_rate(rate, l, alpha);
985
986 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
987 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
988
989 rate *= l;
990 tmp = parent_rate;
991 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
992 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
993 tmp *= alpha_m;
994 do_div(tmp, alpha_n);
995 rate -= tmp;
996 } else {
997 tmp *= alpha_m;
998 do_div(tmp, alpha_n);
999 rate += tmp;
1000 }
1001
1002 return rate;
1003 }
1004
1005 return alpha_huayra_pll_calc_rate(rate, l, alpha);
1006 }
1007
alpha_pll_huayra_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1008 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
1009 unsigned long prate)
1010 {
1011 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1012 u32 l, a, ctl, cur_alpha = 0;
1013
1014 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
1015
1016 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1017
1018 if (ctl & PLL_ALPHA_EN)
1019 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
1020
1021 /*
1022 * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
1023 * without having to go through the power on sequence.
1024 */
1025 if (clk_alpha_pll_is_enabled(hw)) {
1026 if (cur_alpha != a) {
1027 pr_err("%s: clock needs to be gated\n",
1028 clk_hw_get_name(hw));
1029 return -EBUSY;
1030 }
1031
1032 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1033 /* Ensure that the write above goes to detect L val change. */
1034 mb();
1035 return wait_for_pll_enable_lock(pll);
1036 }
1037
1038 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1039 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1040
1041 if (a == 0)
1042 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1043 PLL_ALPHA_EN, 0x0);
1044 else
1045 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1046 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
1047
1048 return 0;
1049 }
1050
alpha_pll_huayra_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1051 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
1052 unsigned long *prate)
1053 {
1054 u32 l, a;
1055
1056 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
1057 }
1058
trion_pll_is_enabled(struct clk_alpha_pll * pll,struct regmap * regmap)1059 static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
1060 struct regmap *regmap)
1061 {
1062 u32 mode_val, opmode_val;
1063 int ret;
1064
1065 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val);
1066 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1067 if (ret)
1068 return 0;
1069
1070 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL));
1071 }
1072
clk_trion_pll_is_enabled(struct clk_hw * hw)1073 static int clk_trion_pll_is_enabled(struct clk_hw *hw)
1074 {
1075 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1076
1077 return trion_pll_is_enabled(pll, pll->clkr.regmap);
1078 }
1079
clk_trion_pll_enable(struct clk_hw * hw)1080 static int clk_trion_pll_enable(struct clk_hw *hw)
1081 {
1082 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1083 struct regmap *regmap = pll->clkr.regmap;
1084 u32 val;
1085 int ret;
1086
1087 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1088 if (ret)
1089 return ret;
1090
1091 /* If in FSM mode, just vote for it */
1092 if (val & PLL_VOTE_FSM_ENA) {
1093 ret = clk_enable_regmap(hw);
1094 if (ret)
1095 return ret;
1096 return wait_for_pll_enable_active(pll);
1097 }
1098
1099 /* Set operation mode to RUN */
1100 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1101
1102 ret = wait_for_pll_enable_lock(pll);
1103 if (ret)
1104 return ret;
1105
1106 /* Enable the PLL outputs */
1107 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1108 PLL_OUT_MASK, PLL_OUT_MASK);
1109 if (ret)
1110 return ret;
1111
1112 /* Enable the global PLL outputs */
1113 return regmap_update_bits(regmap, PLL_MODE(pll),
1114 PLL_OUTCTRL, PLL_OUTCTRL);
1115 }
1116
clk_trion_pll_disable(struct clk_hw * hw)1117 static void clk_trion_pll_disable(struct clk_hw *hw)
1118 {
1119 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1120 struct regmap *regmap = pll->clkr.regmap;
1121 u32 val;
1122 int ret;
1123
1124 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1125 if (ret)
1126 return;
1127
1128 /* If in FSM mode, just unvote it */
1129 if (val & PLL_VOTE_FSM_ENA) {
1130 clk_disable_regmap(hw);
1131 return;
1132 }
1133
1134 /* Disable the global PLL output */
1135 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1136 if (ret)
1137 return;
1138
1139 /* Disable the PLL outputs */
1140 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1141 PLL_OUT_MASK, 0);
1142 if (ret)
1143 return;
1144
1145 /* Place the PLL mode in STANDBY */
1146 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1147 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1148 }
1149
1150 static unsigned long
clk_trion_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1151 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1152 {
1153 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1154 u32 l, frac, alpha_width = pll_alpha_width(pll);
1155
1156 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
1157 return 0;
1158
1159 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac))
1160 return 0;
1161
1162 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1163 }
1164
1165 const struct clk_ops clk_alpha_pll_fixed_ops = {
1166 .enable = clk_alpha_pll_enable,
1167 .disable = clk_alpha_pll_disable,
1168 .is_enabled = clk_alpha_pll_is_enabled,
1169 .recalc_rate = clk_alpha_pll_recalc_rate,
1170 };
1171 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
1172
1173 const struct clk_ops clk_alpha_pll_ops = {
1174 .enable = clk_alpha_pll_enable,
1175 .disable = clk_alpha_pll_disable,
1176 .is_enabled = clk_alpha_pll_is_enabled,
1177 .recalc_rate = clk_alpha_pll_recalc_rate,
1178 .round_rate = clk_alpha_pll_round_rate,
1179 .set_rate = clk_alpha_pll_set_rate,
1180 };
1181 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
1182
1183 const struct clk_ops clk_alpha_pll_huayra_ops = {
1184 .enable = clk_alpha_pll_enable,
1185 .disable = clk_alpha_pll_disable,
1186 .is_enabled = clk_alpha_pll_is_enabled,
1187 .recalc_rate = alpha_pll_huayra_recalc_rate,
1188 .round_rate = alpha_pll_huayra_round_rate,
1189 .set_rate = alpha_pll_huayra_set_rate,
1190 };
1191 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
1192
1193 const struct clk_ops clk_alpha_pll_hwfsm_ops = {
1194 .enable = clk_alpha_pll_hwfsm_enable,
1195 .disable = clk_alpha_pll_hwfsm_disable,
1196 .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
1197 .recalc_rate = clk_alpha_pll_recalc_rate,
1198 .round_rate = clk_alpha_pll_round_rate,
1199 .set_rate = clk_alpha_pll_hwfsm_set_rate,
1200 };
1201 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
1202
1203 const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
1204 .enable = clk_trion_pll_enable,
1205 .disable = clk_trion_pll_disable,
1206 .is_enabled = clk_trion_pll_is_enabled,
1207 .recalc_rate = clk_trion_pll_recalc_rate,
1208 .round_rate = clk_alpha_pll_round_rate,
1209 };
1210 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
1211
1212 static unsigned long
clk_alpha_pll_postdiv_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1213 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1214 {
1215 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1216 u32 ctl;
1217
1218 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl))
1219 return 0;
1220
1221 ctl >>= PLL_POST_DIV_SHIFT;
1222 ctl &= PLL_POST_DIV_MASK(pll);
1223
1224 return parent_rate >> fls(ctl);
1225 }
1226
1227 static const struct clk_div_table clk_alpha_div_table[] = {
1228 { 0x0, 1 },
1229 { 0x1, 2 },
1230 { 0x3, 4 },
1231 { 0x7, 8 },
1232 { 0xf, 16 },
1233 { }
1234 };
1235
1236 static const struct clk_div_table clk_alpha_2bit_div_table[] = {
1237 { 0x0, 1 },
1238 { 0x1, 2 },
1239 { 0x3, 4 },
1240 { }
1241 };
1242
1243 static long
clk_alpha_pll_postdiv_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1244 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1245 unsigned long *prate)
1246 {
1247 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1248 const struct clk_div_table *table;
1249
1250 if (pll->width == 2)
1251 table = clk_alpha_2bit_div_table;
1252 else
1253 table = clk_alpha_div_table;
1254
1255 return divider_round_rate(hw, rate, prate, table,
1256 pll->width, CLK_DIVIDER_POWER_OF_TWO);
1257 }
1258
1259 static long
clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1260 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
1261 unsigned long *prate)
1262 {
1263 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1264 u32 ctl, div;
1265
1266 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1267
1268 ctl >>= PLL_POST_DIV_SHIFT;
1269 ctl &= BIT(pll->width) - 1;
1270 div = 1 << fls(ctl);
1271
1272 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
1273 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
1274
1275 return DIV_ROUND_UP_ULL((u64)*prate, div);
1276 }
1277
clk_alpha_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1278 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1279 unsigned long parent_rate)
1280 {
1281 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1282 int div;
1283
1284 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
1285 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
1286
1287 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1288 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1289 div << PLL_POST_DIV_SHIFT);
1290 }
1291
1292 const struct clk_ops clk_alpha_pll_postdiv_ops = {
1293 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1294 .round_rate = clk_alpha_pll_postdiv_round_rate,
1295 .set_rate = clk_alpha_pll_postdiv_set_rate,
1296 };
1297 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
1298
1299 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
1300 .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
1301 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1302 };
1303 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
1304
clk_fabia_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1305 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1306 const struct alpha_pll_config *config)
1307 {
1308 u32 val, mask;
1309
1310 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1311 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha);
1312 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1313 config->config_ctl_val);
1314 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1315 config->config_ctl_hi_val);
1316 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1317 config->user_ctl_val);
1318 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1319 config->user_ctl_hi_val);
1320 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1321 config->test_ctl_val);
1322 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1323 config->test_ctl_hi_val);
1324
1325 if (config->post_div_mask) {
1326 mask = config->post_div_mask;
1327 val = config->post_div_val;
1328 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
1329 }
1330
1331 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE)
1332 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE,
1333 PLL_FSM_LEGACY_MODE);
1334
1335 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1336 PLL_UPDATE_BYPASS);
1337
1338 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1339 }
1340 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
1341
alpha_pll_fabia_enable(struct clk_hw * hw)1342 static int alpha_pll_fabia_enable(struct clk_hw *hw)
1343 {
1344 int ret;
1345 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1346 u32 val, opmode_val;
1347 struct regmap *regmap = pll->clkr.regmap;
1348
1349 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1350 if (ret)
1351 return ret;
1352
1353 /* If in FSM mode, just vote for it */
1354 if (val & PLL_VOTE_FSM_ENA) {
1355 ret = clk_enable_regmap(hw);
1356 if (ret)
1357 return ret;
1358 return wait_for_pll_enable_active(pll);
1359 }
1360
1361 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1362 if (ret)
1363 return ret;
1364
1365 /* Skip If PLL is already running */
1366 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
1367 return 0;
1368
1369 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1370 if (ret)
1371 return ret;
1372
1373 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1374 if (ret)
1375 return ret;
1376
1377 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
1378 PLL_RESET_N);
1379 if (ret)
1380 return ret;
1381
1382 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1383 if (ret)
1384 return ret;
1385
1386 ret = wait_for_pll_enable_lock(pll);
1387 if (ret)
1388 return ret;
1389
1390 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1391 PLL_OUT_MASK, PLL_OUT_MASK);
1392 if (ret)
1393 return ret;
1394
1395 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
1396 PLL_OUTCTRL);
1397 }
1398
alpha_pll_fabia_disable(struct clk_hw * hw)1399 static void alpha_pll_fabia_disable(struct clk_hw *hw)
1400 {
1401 int ret;
1402 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1403 u32 val;
1404 struct regmap *regmap = pll->clkr.regmap;
1405
1406 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1407 if (ret)
1408 return;
1409
1410 /* If in FSM mode, just unvote it */
1411 if (val & PLL_FSM_ENA) {
1412 clk_disable_regmap(hw);
1413 return;
1414 }
1415
1416 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1417 if (ret)
1418 return;
1419
1420 /* Disable main outputs */
1421 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1422 if (ret)
1423 return;
1424
1425 /* Place the PLL in STANDBY */
1426 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1427 }
1428
alpha_pll_fabia_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1429 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
1430 unsigned long parent_rate)
1431 {
1432 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1433 u32 l, frac, alpha_width = pll_alpha_width(pll);
1434
1435 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
1436 return 0;
1437
1438 if (regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac))
1439 return 0;
1440
1441 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1442 }
1443
1444 /*
1445 * Due to limited number of bits for fractional rate programming, the
1446 * rounded up rate could be marginally higher than the requested rate.
1447 */
alpha_pll_check_rate_margin(struct clk_hw * hw,unsigned long rrate,unsigned long rate)1448 static int alpha_pll_check_rate_margin(struct clk_hw *hw,
1449 unsigned long rrate, unsigned long rate)
1450 {
1451 unsigned long rate_margin = rate + PLL_RATE_MARGIN;
1452
1453 if (rrate > rate_margin || rrate < rate) {
1454 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
1455 clk_hw_get_name(hw), rrate, rate, rate_margin);
1456 return -EINVAL;
1457 }
1458
1459 return 0;
1460 }
1461
alpha_pll_fabia_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1462 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
1463 unsigned long prate)
1464 {
1465 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1466 u32 l, alpha_width = pll_alpha_width(pll);
1467 unsigned long rrate;
1468 int ret;
1469 u64 a;
1470
1471 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1472
1473 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1474 if (ret < 0)
1475 return ret;
1476
1477 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1478 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1479
1480 return __clk_alpha_pll_update_latch(pll);
1481 }
1482
alpha_pll_fabia_prepare(struct clk_hw * hw)1483 static int alpha_pll_fabia_prepare(struct clk_hw *hw)
1484 {
1485 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1486 const struct pll_vco *vco;
1487 struct clk_hw *parent_hw;
1488 unsigned long cal_freq, rrate;
1489 u32 cal_l, val, alpha_width = pll_alpha_width(pll);
1490 const char *name = clk_hw_get_name(hw);
1491 u64 a;
1492 int ret;
1493
1494 /* Check if calibration needs to be done i.e. PLL is in reset */
1495 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1496 if (ret)
1497 return ret;
1498
1499 /* Return early if calibration is not needed. */
1500 if (val & PLL_RESET_N)
1501 return 0;
1502
1503 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
1504 if (!vco) {
1505 pr_err("%s: alpha pll not in a valid vco range\n", name);
1506 return -EINVAL;
1507 }
1508
1509 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq +
1510 pll->vco_table[0].max_freq) * 54, 100);
1511
1512 parent_hw = clk_hw_get_parent(hw);
1513 if (!parent_hw)
1514 return -EINVAL;
1515
1516 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw),
1517 &cal_l, &a, alpha_width);
1518
1519 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq);
1520 if (ret < 0)
1521 return ret;
1522
1523 /* Setup PLL for calibration frequency */
1524 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l);
1525
1526 /* Bringup the PLL at calibration frequency */
1527 ret = clk_alpha_pll_enable(hw);
1528 if (ret) {
1529 pr_err("%s: alpha pll calibration failed\n", name);
1530 return ret;
1531 }
1532
1533 clk_alpha_pll_disable(hw);
1534
1535 return 0;
1536 }
1537
1538 const struct clk_ops clk_alpha_pll_fabia_ops = {
1539 .prepare = alpha_pll_fabia_prepare,
1540 .enable = alpha_pll_fabia_enable,
1541 .disable = alpha_pll_fabia_disable,
1542 .is_enabled = clk_alpha_pll_is_enabled,
1543 .set_rate = alpha_pll_fabia_set_rate,
1544 .recalc_rate = alpha_pll_fabia_recalc_rate,
1545 .round_rate = clk_alpha_pll_round_rate,
1546 };
1547 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
1548
1549 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
1550 .enable = alpha_pll_fabia_enable,
1551 .disable = alpha_pll_fabia_disable,
1552 .is_enabled = clk_alpha_pll_is_enabled,
1553 .recalc_rate = alpha_pll_fabia_recalc_rate,
1554 .round_rate = clk_alpha_pll_round_rate,
1555 };
1556 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
1557
clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1558 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1559 unsigned long parent_rate)
1560 {
1561 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1562 u32 i, div = 1, val;
1563 int ret;
1564
1565 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1566 if (ret)
1567 return ret;
1568
1569 val >>= pll->post_div_shift;
1570 val &= BIT(pll->width) - 1;
1571
1572 for (i = 0; i < pll->num_post_div; i++) {
1573 if (pll->post_div_table[i].val == val) {
1574 div = pll->post_div_table[i].div;
1575 break;
1576 }
1577 }
1578
1579 return (parent_rate / div);
1580 }
1581
1582 static unsigned long
clk_trion_pll_postdiv_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1583 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1584 {
1585 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1586 struct regmap *regmap = pll->clkr.regmap;
1587 u32 i, div = 1, val;
1588
1589 if (regmap_read(regmap, PLL_USER_CTL(pll), &val))
1590 return 0;
1591
1592 val >>= pll->post_div_shift;
1593 val &= PLL_POST_DIV_MASK(pll);
1594
1595 for (i = 0; i < pll->num_post_div; i++) {
1596 if (pll->post_div_table[i].val == val) {
1597 div = pll->post_div_table[i].div;
1598 break;
1599 }
1600 }
1601
1602 return (parent_rate / div);
1603 }
1604
1605 static long
clk_trion_pll_postdiv_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1606 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1607 unsigned long *prate)
1608 {
1609 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1610
1611 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1612 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1613 };
1614
1615 static int
clk_trion_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1616 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1617 unsigned long parent_rate)
1618 {
1619 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1620 struct regmap *regmap = pll->clkr.regmap;
1621 int i, val = 0, div;
1622
1623 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1624 for (i = 0; i < pll->num_post_div; i++) {
1625 if (pll->post_div_table[i].div == div) {
1626 val = pll->post_div_table[i].val;
1627 break;
1628 }
1629 }
1630
1631 return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1632 PLL_POST_DIV_MASK(pll) << pll->post_div_shift,
1633 val << pll->post_div_shift);
1634 }
1635
1636 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
1637 .recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1638 .round_rate = clk_trion_pll_postdiv_round_rate,
1639 .set_rate = clk_trion_pll_postdiv_set_rate,
1640 };
1641 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
1642
clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1643 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1644 unsigned long rate, unsigned long *prate)
1645 {
1646 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1647
1648 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1649 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1650 }
1651
clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1652 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1653 unsigned long rate, unsigned long parent_rate)
1654 {
1655 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1656 int i, val = 0, div, ret;
1657
1658 /*
1659 * If the PLL is in FSM mode, then treat set_rate callback as a
1660 * no-operation.
1661 */
1662 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1663 if (ret)
1664 return ret;
1665
1666 if (val & PLL_VOTE_FSM_ENA)
1667 return 0;
1668
1669 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1670 for (i = 0; i < pll->num_post_div; i++) {
1671 if (pll->post_div_table[i].div == div) {
1672 val = pll->post_div_table[i].val;
1673 break;
1674 }
1675 }
1676
1677 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1678 (BIT(pll->width) - 1) << pll->post_div_shift,
1679 val << pll->post_div_shift);
1680 }
1681
1682 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
1683 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1684 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1685 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1686 };
1687 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
1688
1689 /**
1690 * clk_trion_pll_configure - configure the trion pll
1691 *
1692 * @pll: clk alpha pll
1693 * @regmap: register map
1694 * @config: configuration to apply for pll
1695 */
clk_trion_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1696 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1697 const struct alpha_pll_config *config)
1698 {
1699 /*
1700 * If the bootloader left the PLL enabled it's likely that there are
1701 * RCGs that will lock up if we disable the PLL below.
1702 */
1703 if (trion_pll_is_enabled(pll, regmap)) {
1704 pr_debug("Trion PLL is already enabled, skipping configuration\n");
1705 return;
1706 }
1707
1708 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1709 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1710 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1711 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1712 config->config_ctl_val);
1713 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1714 config->config_ctl_hi_val);
1715 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
1716 config->config_ctl_hi1_val);
1717 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1718 config->user_ctl_val);
1719 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1720 config->user_ctl_hi_val);
1721 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
1722 config->user_ctl_hi1_val);
1723 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1724 config->test_ctl_val);
1725 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1726 config->test_ctl_hi_val);
1727 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
1728 config->test_ctl_hi1_val);
1729
1730 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1731 PLL_UPDATE_BYPASS);
1732
1733 /* Disable PLL output */
1734 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1735
1736 /* Set operation mode to OFF */
1737 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1738
1739 /* Place the PLL in STANDBY mode */
1740 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1741 }
1742 EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
1743
1744 /*
1745 * The TRION PLL requires a power-on self-calibration which happens when the
1746 * PLL comes out of reset. Calibrate in case it is not completed.
1747 */
__alpha_pll_trion_prepare(struct clk_hw * hw,u32 pcal_done)1748 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
1749 {
1750 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1751 u32 val;
1752 int ret;
1753
1754 /* Return early if calibration is not needed. */
1755 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);
1756 if (val & pcal_done)
1757 return 0;
1758
1759 /* On/off to calibrate */
1760 ret = clk_trion_pll_enable(hw);
1761 if (!ret)
1762 clk_trion_pll_disable(hw);
1763
1764 return ret;
1765 }
1766
alpha_pll_trion_prepare(struct clk_hw * hw)1767 static int alpha_pll_trion_prepare(struct clk_hw *hw)
1768 {
1769 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE);
1770 }
1771
alpha_pll_lucid_prepare(struct clk_hw * hw)1772 static int alpha_pll_lucid_prepare(struct clk_hw *hw)
1773 {
1774 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);
1775 }
1776
__alpha_pll_trion_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate,u32 latch_bit,u32 latch_ack)1777 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1778 unsigned long prate, u32 latch_bit, u32 latch_ack)
1779 {
1780 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1781 unsigned long rrate;
1782 u32 val, l, alpha_width = pll_alpha_width(pll);
1783 u64 a;
1784 int ret;
1785
1786 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1787
1788 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1789 if (ret < 0)
1790 return ret;
1791
1792 regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l);
1793 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1794
1795 /* Latch the PLL input */
1796 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit);
1797 if (ret)
1798 return ret;
1799
1800 /* Wait for 2 reference cycles before checking the ACK bit. */
1801 udelay(1);
1802 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1803 if (!(val & latch_ack)) {
1804 pr_err("Lucid PLL latch failed. Output may be unstable!\n");
1805 return -EINVAL;
1806 }
1807
1808 /* Return the latch input to 0 */
1809 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0);
1810 if (ret)
1811 return ret;
1812
1813 if (clk_hw_is_enabled(hw)) {
1814 ret = wait_for_pll_enable_lock(pll);
1815 if (ret)
1816 return ret;
1817 }
1818
1819 /* Wait for PLL output to stabilize */
1820 udelay(100);
1821 return 0;
1822 }
1823
alpha_pll_trion_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1824 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1825 unsigned long prate)
1826 {
1827 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH);
1828 }
1829
1830 const struct clk_ops clk_alpha_pll_trion_ops = {
1831 .prepare = alpha_pll_trion_prepare,
1832 .enable = clk_trion_pll_enable,
1833 .disable = clk_trion_pll_disable,
1834 .is_enabled = clk_trion_pll_is_enabled,
1835 .recalc_rate = clk_trion_pll_recalc_rate,
1836 .round_rate = clk_alpha_pll_round_rate,
1837 .set_rate = alpha_pll_trion_set_rate,
1838 };
1839 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
1840
1841 const struct clk_ops clk_alpha_pll_lucid_ops = {
1842 .prepare = alpha_pll_lucid_prepare,
1843 .enable = clk_trion_pll_enable,
1844 .disable = clk_trion_pll_disable,
1845 .is_enabled = clk_trion_pll_is_enabled,
1846 .recalc_rate = clk_trion_pll_recalc_rate,
1847 .round_rate = clk_alpha_pll_round_rate,
1848 .set_rate = alpha_pll_trion_set_rate,
1849 };
1850 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
1851
1852 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
1853 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1854 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1855 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1856 };
1857 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
1858
clk_agera_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1859 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1860 const struct alpha_pll_config *config)
1861 {
1862 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1863 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1864 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1865 config->user_ctl_val);
1866 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1867 config->config_ctl_val);
1868 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1869 config->config_ctl_hi_val);
1870 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1871 config->test_ctl_val);
1872 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1873 config->test_ctl_hi_val);
1874 }
1875 EXPORT_SYMBOL_GPL(clk_agera_pll_configure);
1876
clk_alpha_pll_agera_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)1877 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate,
1878 unsigned long prate)
1879 {
1880 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1881 u32 l, alpha_width = pll_alpha_width(pll);
1882 int ret;
1883 unsigned long rrate;
1884 u64 a;
1885
1886 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1887 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1888 if (ret < 0)
1889 return ret;
1890
1891 /* change L_VAL without having to go through the power on sequence */
1892 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1893 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1894
1895 if (clk_hw_is_enabled(hw))
1896 return wait_for_pll_enable_lock(pll);
1897
1898 return 0;
1899 }
1900
1901 const struct clk_ops clk_alpha_pll_agera_ops = {
1902 .enable = clk_alpha_pll_enable,
1903 .disable = clk_alpha_pll_disable,
1904 .is_enabled = clk_alpha_pll_is_enabled,
1905 .recalc_rate = alpha_pll_fabia_recalc_rate,
1906 .round_rate = clk_alpha_pll_round_rate,
1907 .set_rate = clk_alpha_pll_agera_set_rate,
1908 };
1909 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
1910
1911 /**
1912 * clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll
1913 *
1914 * @pll: clk alpha pll
1915 * @regmap: register map
1916 * @config: configuration to apply for pll
1917 */
clk_lucid_5lpe_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)1918 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1919 const struct alpha_pll_config *config)
1920 {
1921 /*
1922 * If the bootloader left the PLL enabled it's likely that there are
1923 * RCGs that will lock up if we disable the PLL below.
1924 */
1925 if (trion_pll_is_enabled(pll, regmap)) {
1926 pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n");
1927 return;
1928 }
1929
1930 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1931 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1932 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1933 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1934 config->config_ctl_val);
1935 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1936 config->config_ctl_hi_val);
1937 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
1938 config->config_ctl_hi1_val);
1939 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1940 config->user_ctl_val);
1941 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1942 config->user_ctl_hi_val);
1943 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
1944 config->user_ctl_hi1_val);
1945 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1946 config->test_ctl_val);
1947 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1948 config->test_ctl_hi_val);
1949 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
1950 config->test_ctl_hi1_val);
1951
1952 /* Disable PLL output */
1953 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1954
1955 /* Set operation mode to OFF */
1956 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1957
1958 /* Place the PLL in STANDBY mode */
1959 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1960 }
1961 EXPORT_SYMBOL_GPL(clk_lucid_5lpe_pll_configure);
1962
alpha_pll_lucid_5lpe_enable(struct clk_hw * hw)1963 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
1964 {
1965 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1966 u32 val;
1967 int ret;
1968
1969 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1970 if (ret)
1971 return ret;
1972
1973 /* If in FSM mode, just vote for it */
1974 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1975 ret = clk_enable_regmap(hw);
1976 if (ret)
1977 return ret;
1978 return wait_for_pll_enable_lock(pll);
1979 }
1980
1981 /* Check if PLL is already enabled, return if enabled */
1982 if (trion_pll_is_enabled(pll, pll->clkr.regmap))
1983 return 0;
1984
1985 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1986 if (ret)
1987 return ret;
1988
1989 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
1990
1991 ret = wait_for_pll_enable_lock(pll);
1992 if (ret)
1993 return ret;
1994
1995 /* Enable the PLL outputs */
1996 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
1997 if (ret)
1998 return ret;
1999
2000 /* Enable the global PLL outputs */
2001 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2002 }
2003
alpha_pll_lucid_5lpe_disable(struct clk_hw * hw)2004 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
2005 {
2006 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2007 u32 val;
2008 int ret;
2009
2010 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
2011 if (ret)
2012 return;
2013
2014 /* If in FSM mode, just unvote it */
2015 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
2016 clk_disable_regmap(hw);
2017 return;
2018 }
2019
2020 /* Disable the global PLL output */
2021 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2022 if (ret)
2023 return;
2024
2025 /* Disable the PLL outputs */
2026 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
2027 if (ret)
2028 return;
2029
2030 /* Place the PLL mode in STANDBY */
2031 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
2032 }
2033
2034 /*
2035 * The Lucid 5LPE PLL requires a power-on self-calibration which happens
2036 * when the PLL comes out of reset. Calibrate in case it is not completed.
2037 */
alpha_pll_lucid_5lpe_prepare(struct clk_hw * hw)2038 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw)
2039 {
2040 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2041 struct clk_hw *p;
2042 u32 val = 0;
2043 int ret;
2044
2045 /* Return early if calibration is not needed. */
2046 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
2047 if (val & LUCID_5LPE_PCAL_DONE)
2048 return 0;
2049
2050 p = clk_hw_get_parent(hw);
2051 if (!p)
2052 return -EINVAL;
2053
2054 ret = alpha_pll_lucid_5lpe_enable(hw);
2055 if (ret)
2056 return ret;
2057
2058 alpha_pll_lucid_5lpe_disable(hw);
2059
2060 return 0;
2061 }
2062
alpha_pll_lucid_5lpe_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)2063 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
2064 unsigned long prate)
2065 {
2066 return __alpha_pll_trion_set_rate(hw, rate, prate,
2067 LUCID_5LPE_PLL_LATCH_INPUT,
2068 LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
2069 }
2070
__clk_lucid_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate,unsigned long enable_vote_run)2071 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2072 unsigned long parent_rate,
2073 unsigned long enable_vote_run)
2074 {
2075 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
2076 struct regmap *regmap = pll->clkr.regmap;
2077 int i, val, div, ret;
2078 u32 mask;
2079
2080 /*
2081 * If the PLL is in FSM mode, then treat set_rate callback as a
2082 * no-operation.
2083 */
2084 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2085 if (ret)
2086 return ret;
2087
2088 if (val & enable_vote_run)
2089 return 0;
2090
2091 if (!pll->post_div_table) {
2092 pr_err("Missing the post_div_table for the %s PLL\n",
2093 clk_hw_get_name(&pll->clkr.hw));
2094 return -EINVAL;
2095 }
2096
2097 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
2098 for (i = 0; i < pll->num_post_div; i++) {
2099 if (pll->post_div_table[i].div == div) {
2100 val = pll->post_div_table[i].val;
2101 break;
2102 }
2103 }
2104
2105 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);
2106 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2107 mask, val << pll->post_div_shift);
2108 }
2109
clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2110 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2111 unsigned long parent_rate)
2112 {
2113 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN);
2114 }
2115
2116 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
2117 .prepare = alpha_pll_lucid_5lpe_prepare,
2118 .enable = alpha_pll_lucid_5lpe_enable,
2119 .disable = alpha_pll_lucid_5lpe_disable,
2120 .is_enabled = clk_trion_pll_is_enabled,
2121 .recalc_rate = clk_trion_pll_recalc_rate,
2122 .round_rate = clk_alpha_pll_round_rate,
2123 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2124 };
2125 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);
2126
2127 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
2128 .enable = alpha_pll_lucid_5lpe_enable,
2129 .disable = alpha_pll_lucid_5lpe_disable,
2130 .is_enabled = clk_trion_pll_is_enabled,
2131 .recalc_rate = clk_trion_pll_recalc_rate,
2132 .round_rate = clk_alpha_pll_round_rate,
2133 };
2134 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);
2135
2136 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
2137 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2138 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2139 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
2140 };
2141 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
2142
clk_zonda_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2143 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2144 const struct alpha_pll_config *config)
2145 {
2146 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2147 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2148 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2149 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2150 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2151 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2152 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2153 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
2154 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2155 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2156 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2157
2158 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0);
2159
2160 /* Disable PLL output */
2161 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2162
2163 /* Set operation mode to OFF */
2164 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2165
2166 /* Place the PLL in STANDBY mode */
2167 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2168 }
2169 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure);
2170
clk_zonda_pll_enable(struct clk_hw * hw)2171 static int clk_zonda_pll_enable(struct clk_hw *hw)
2172 {
2173 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2174 struct regmap *regmap = pll->clkr.regmap;
2175 u32 val;
2176 int ret;
2177
2178 regmap_read(regmap, PLL_MODE(pll), &val);
2179
2180 /* If in FSM mode, just vote for it */
2181 if (val & PLL_VOTE_FSM_ENA) {
2182 ret = clk_enable_regmap(hw);
2183 if (ret)
2184 return ret;
2185 return wait_for_pll_enable_active(pll);
2186 }
2187
2188 /* Get the PLL out of bypass mode */
2189 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
2190
2191 /*
2192 * H/W requires a 1us delay between disabling the bypass and
2193 * de-asserting the reset.
2194 */
2195 udelay(1);
2196
2197 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2198
2199 /* Set operation mode to RUN */
2200 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2201
2202 regmap_read(regmap, PLL_TEST_CTL(pll), &val);
2203
2204 /* If cfa mode then poll for freq lock */
2205 if (val & ZONDA_STAY_IN_CFA)
2206 ret = wait_for_zonda_pll_freq_lock(pll);
2207 else
2208 ret = wait_for_pll_enable_lock(pll);
2209 if (ret)
2210 return ret;
2211
2212 /* Enable the PLL outputs */
2213 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
2214
2215 /* Enable the global PLL outputs */
2216 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2217
2218 return 0;
2219 }
2220
clk_zonda_pll_disable(struct clk_hw * hw)2221 static void clk_zonda_pll_disable(struct clk_hw *hw)
2222 {
2223 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2224 struct regmap *regmap = pll->clkr.regmap;
2225 u32 val;
2226
2227 regmap_read(regmap, PLL_MODE(pll), &val);
2228
2229 /* If in FSM mode, just unvote it */
2230 if (val & PLL_VOTE_FSM_ENA) {
2231 clk_disable_regmap(hw);
2232 return;
2233 }
2234
2235 /* Disable the global PLL output */
2236 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2237
2238 /* Disable the PLL outputs */
2239 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
2240
2241 /* Put the PLL in bypass and reset */
2242 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
2243
2244 /* Place the PLL mode in OFF state */
2245 regmap_write(regmap, PLL_OPMODE(pll), 0x0);
2246 }
2247
zonda_pll_adjust_l_val(unsigned long rate,unsigned long prate,u32 * l)2248 static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l)
2249 {
2250 u64 remainder, quotient;
2251
2252 quotient = rate;
2253 remainder = do_div(quotient, prate);
2254
2255 *l = rate + (u32)(remainder * 2 >= prate);
2256 }
2257
clk_zonda_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)2258 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
2259 unsigned long prate)
2260 {
2261 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2262 unsigned long rrate;
2263 u32 test_ctl_val;
2264 u32 l, alpha_width = pll_alpha_width(pll);
2265 u64 a;
2266 int ret;
2267
2268 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
2269
2270 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
2271 if (ret < 0)
2272 return ret;
2273
2274 if (a & PLL_ALPHA_MSB)
2275 zonda_pll_adjust_l_val(rate, prate, &l);
2276
2277 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2278 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2279
2280 if (!clk_hw_is_enabled(hw))
2281 return 0;
2282
2283 /* Wait before polling for the frequency latch */
2284 udelay(5);
2285
2286 /* Read stay in cfa mode */
2287 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
2288
2289 /* If cfa mode then poll for freq lock */
2290 if (test_ctl_val & ZONDA_STAY_IN_CFA)
2291 ret = wait_for_zonda_pll_freq_lock(pll);
2292 else
2293 ret = wait_for_pll_enable_lock(pll);
2294 if (ret)
2295 return ret;
2296
2297 /* Wait for PLL output to stabilize */
2298 udelay(100);
2299 return 0;
2300 }
2301
2302 const struct clk_ops clk_alpha_pll_zonda_ops = {
2303 .enable = clk_zonda_pll_enable,
2304 .disable = clk_zonda_pll_disable,
2305 .is_enabled = clk_trion_pll_is_enabled,
2306 .recalc_rate = clk_trion_pll_recalc_rate,
2307 .round_rate = clk_alpha_pll_round_rate,
2308 .set_rate = clk_zonda_pll_set_rate,
2309 };
2310 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
2311
clk_lucid_evo_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2312 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2313 const struct alpha_pll_config *config)
2314 {
2315 u32 lval = config->l;
2316
2317 /*
2318 * If the bootloader left the PLL enabled it's likely that there are
2319 * RCGs that will lock up if we disable the PLL below.
2320 */
2321 if (trion_pll_is_enabled(pll, regmap)) {
2322 pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n");
2323 return;
2324 }
2325
2326 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2327 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
2328 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2329 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2330 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2331 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2332 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2333 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2334 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2335 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2336 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2337 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
2338
2339 /* Disable PLL output */
2340 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2341
2342 /* Set operation mode to STANDBY and de-assert the reset */
2343 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2344 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2345 }
2346 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
2347
clk_lucid_ole_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2348 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2349 const struct alpha_pll_config *config)
2350 {
2351 u32 lval = config->l;
2352
2353 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2354 lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT;
2355 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
2356 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2357 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2358 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2359 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2360 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2361 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2362 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2363 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2364 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2365 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
2366
2367 /* Disable PLL output */
2368 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2369
2370 /* Set operation mode to STANDBY and de-assert the reset */
2371 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2372 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2373 }
2374 EXPORT_SYMBOL_GPL(clk_lucid_ole_pll_configure);
2375
alpha_pll_lucid_evo_enable(struct clk_hw * hw)2376 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
2377 {
2378 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2379 struct regmap *regmap = pll->clkr.regmap;
2380 u32 val;
2381 int ret;
2382
2383 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2384 if (ret)
2385 return ret;
2386
2387 /* If in FSM mode, just vote for it */
2388 if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2389 ret = clk_enable_regmap(hw);
2390 if (ret)
2391 return ret;
2392 return wait_for_pll_enable_lock(pll);
2393 }
2394
2395 /* Check if PLL is already enabled */
2396 if (trion_pll_is_enabled(pll, regmap))
2397 return 0;
2398
2399 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2400 if (ret)
2401 return ret;
2402
2403 /* Set operation mode to RUN */
2404 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2405
2406 ret = wait_for_pll_enable_lock(pll);
2407 if (ret)
2408 return ret;
2409
2410 /* Enable the PLL outputs */
2411 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
2412 if (ret)
2413 return ret;
2414
2415 /* Enable the global PLL outputs */
2416 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2417 if (ret)
2418 return ret;
2419
2420 /* Ensure that the write above goes through before returning. */
2421 mb();
2422 return ret;
2423 }
2424
_alpha_pll_lucid_evo_disable(struct clk_hw * hw,bool reset)2425 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset)
2426 {
2427 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2428 struct regmap *regmap = pll->clkr.regmap;
2429 u32 val;
2430 int ret;
2431
2432 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2433 if (ret)
2434 return;
2435
2436 /* If in FSM mode, just unvote it */
2437 if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2438 clk_disable_regmap(hw);
2439 return;
2440 }
2441
2442 /* Disable the global PLL output */
2443 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2444 if (ret)
2445 return;
2446
2447 /* Disable the PLL outputs */
2448 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
2449 if (ret)
2450 return;
2451
2452 /* Place the PLL mode in STANDBY */
2453 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2454
2455 if (reset)
2456 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0);
2457 }
2458
_alpha_pll_lucid_evo_prepare(struct clk_hw * hw,bool reset)2459 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset)
2460 {
2461 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2462 struct clk_hw *p;
2463 u32 val = 0;
2464 int ret;
2465
2466 /* Return early if calibration is not needed. */
2467 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
2468 if (!(val & LUCID_EVO_PCAL_NOT_DONE))
2469 return 0;
2470
2471 p = clk_hw_get_parent(hw);
2472 if (!p)
2473 return -EINVAL;
2474
2475 ret = alpha_pll_lucid_evo_enable(hw);
2476 if (ret)
2477 return ret;
2478
2479 _alpha_pll_lucid_evo_disable(hw, reset);
2480
2481 return 0;
2482 }
2483
alpha_pll_lucid_evo_disable(struct clk_hw * hw)2484 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
2485 {
2486 _alpha_pll_lucid_evo_disable(hw, false);
2487 }
2488
alpha_pll_lucid_evo_prepare(struct clk_hw * hw)2489 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
2490 {
2491 return _alpha_pll_lucid_evo_prepare(hw, false);
2492 }
2493
alpha_pll_reset_lucid_evo_disable(struct clk_hw * hw)2494 static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw)
2495 {
2496 _alpha_pll_lucid_evo_disable(hw, true);
2497 }
2498
alpha_pll_reset_lucid_evo_prepare(struct clk_hw * hw)2499 static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw)
2500 {
2501 return _alpha_pll_lucid_evo_prepare(hw, true);
2502 }
2503
alpha_pll_lucid_evo_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2504 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
2505 unsigned long parent_rate)
2506 {
2507 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2508 struct regmap *regmap = pll->clkr.regmap;
2509 u32 l, frac;
2510
2511 if (regmap_read(regmap, PLL_L_VAL(pll), &l))
2512 return 0;
2513 l &= LUCID_EVO_PLL_L_VAL_MASK;
2514
2515 if (regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac))
2516 return 0;
2517
2518 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
2519 }
2520
clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2521 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2522 unsigned long parent_rate)
2523 {
2524 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN);
2525 }
2526
2527 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
2528 .enable = alpha_pll_lucid_evo_enable,
2529 .disable = alpha_pll_lucid_evo_disable,
2530 .is_enabled = clk_trion_pll_is_enabled,
2531 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2532 .round_rate = clk_alpha_pll_round_rate,
2533 };
2534 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
2535
2536 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
2537 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2538 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2539 .set_rate = clk_lucid_evo_pll_postdiv_set_rate,
2540 };
2541 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
2542
2543 const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
2544 .prepare = alpha_pll_lucid_evo_prepare,
2545 .enable = alpha_pll_lucid_evo_enable,
2546 .disable = alpha_pll_lucid_evo_disable,
2547 .is_enabled = clk_trion_pll_is_enabled,
2548 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2549 .round_rate = clk_alpha_pll_round_rate,
2550 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2551 };
2552 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
2553
2554 const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = {
2555 .prepare = alpha_pll_reset_lucid_evo_prepare,
2556 .enable = alpha_pll_lucid_evo_enable,
2557 .disable = alpha_pll_reset_lucid_evo_disable,
2558 .is_enabled = clk_trion_pll_is_enabled,
2559 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2560 .round_rate = clk_alpha_pll_round_rate,
2561 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2562 };
2563 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);
2564
alpha_pll_pongo_elu_prepare(struct clk_hw * hw)2565 static int alpha_pll_pongo_elu_prepare(struct clk_hw *hw)
2566 {
2567 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2568 struct regmap *regmap = pll->clkr.regmap;
2569 int ret;
2570
2571 /* Enable PLL intially to one-time calibrate against XO. */
2572 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2573 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2574 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_XO_PRESENT, PONGO_XO_PRESENT);
2575
2576 /* Set regmap for wait_for_pll() */
2577 pll->clkr.regmap = regmap;
2578 ret = wait_for_pll_enable_lock(pll);
2579 if (ret) {
2580 /* Reverse calibration - disable PLL output */
2581 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2582 return ret;
2583 }
2584
2585 /* Disable PLL after one-time calibration. */
2586 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2587
2588 /* Select internally generated clock. */
2589 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_CLOCK_SELECT,
2590 PONGO_CLOCK_SELECT);
2591
2592 return 0;
2593 }
2594
alpha_pll_pongo_elu_enable(struct clk_hw * hw)2595 static int alpha_pll_pongo_elu_enable(struct clk_hw *hw)
2596 {
2597 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2598 struct regmap *regmap = pll->clkr.regmap;
2599 int ret;
2600
2601 /* Check if PLL is already enabled */
2602 if (trion_pll_is_enabled(pll, regmap))
2603 return 0;
2604
2605 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2606 if (ret)
2607 return ret;
2608
2609 /* Set operation mode to RUN */
2610 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2611
2612 ret = wait_for_pll_enable_lock(pll);
2613 if (ret)
2614 return ret;
2615
2616 /* Enable the global PLL outputs */
2617 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2618 if (ret)
2619 return ret;
2620
2621 /* Ensure that the write above goes through before returning. */
2622 mb();
2623
2624 return ret;
2625 }
2626
alpha_pll_pongo_elu_disable(struct clk_hw * hw)2627 static void alpha_pll_pongo_elu_disable(struct clk_hw *hw)
2628 {
2629 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2630 struct regmap *regmap = pll->clkr.regmap;
2631 int ret;
2632
2633 /* Disable the global PLL output */
2634 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2635 if (ret)
2636 return;
2637
2638 /* Place the PLL mode in STANDBY */
2639 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2640 }
2641
alpha_pll_pongo_elu_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2642 static unsigned long alpha_pll_pongo_elu_recalc_rate(struct clk_hw *hw,
2643 unsigned long parent_rate)
2644 {
2645 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2646 struct regmap *regmap = pll->clkr.regmap;
2647 u32 l;
2648
2649 if (regmap_read(regmap, PLL_L_VAL(pll), &l))
2650 return 0;
2651
2652 l &= PONGO_PLL_L_VAL_MASK;
2653
2654 return alpha_pll_calc_rate(parent_rate, l, 0, pll_alpha_width(pll));
2655 }
2656
2657 const struct clk_ops clk_alpha_pll_pongo_elu_ops = {
2658 .prepare = alpha_pll_pongo_elu_prepare,
2659 .enable = alpha_pll_pongo_elu_enable,
2660 .disable = alpha_pll_pongo_elu_disable,
2661 .recalc_rate = alpha_pll_pongo_elu_recalc_rate,
2662 };
2663 EXPORT_SYMBOL_GPL(clk_alpha_pll_pongo_elu_ops);
2664
clk_pongo_elu_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2665 void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll,
2666 struct regmap *regmap,
2667 const struct alpha_pll_config *config)
2668 {
2669 u32 val;
2670
2671 regmap_update_bits(regmap, PLL_USER_CTL(pll), PONGO_PLL_OUT_MASK,
2672 PONGO_PLL_OUT_MASK);
2673
2674 if (trion_pll_is_enabled(pll, regmap))
2675 return;
2676
2677 if (regmap_read(regmap, PLL_L_VAL(pll), &val))
2678 return;
2679 val &= PONGO_PLL_L_VAL_MASK;
2680 if (val)
2681 return;
2682
2683 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2684 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2685 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2686 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2687 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2688 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U2(pll), config->config_ctl_hi2_val);
2689 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
2690 config->user_ctl_val | PONGO_PLL_OUT_MASK);
2691 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2692 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2693 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2694 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2695 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
2696 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U3(pll), config->test_ctl_hi3_val);
2697
2698 /* Disable PLL output */
2699 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2700 }
2701 EXPORT_SYMBOL_GPL(clk_pongo_elu_pll_configure);
2702
clk_rivian_evo_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2703 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2704 const struct alpha_pll_config *config)
2705 {
2706 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2707 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2708 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2709 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2710 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2711 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2712 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2713 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2714
2715 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2716
2717 regmap_update_bits(regmap, PLL_MODE(pll),
2718 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL,
2719 PLL_RESET_N | PLL_BYPASSNL);
2720 }
2721 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure);
2722
clk_rivian_evo_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2723 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
2724 unsigned long parent_rate)
2725 {
2726 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2727 u32 l;
2728
2729 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l))
2730 return 0;
2731
2732 return parent_rate * l;
2733 }
2734
clk_rivian_evo_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)2735 static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
2736 unsigned long *prate)
2737 {
2738 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2739 unsigned long min_freq, max_freq;
2740 u32 l;
2741 u64 a;
2742
2743 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
2744 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
2745 return rate;
2746
2747 min_freq = pll->vco_table[0].min_freq;
2748 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
2749
2750 return clamp(rate, min_freq, max_freq);
2751 }
2752
2753 const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
2754 .enable = alpha_pll_lucid_5lpe_enable,
2755 .disable = alpha_pll_lucid_5lpe_disable,
2756 .is_enabled = clk_trion_pll_is_enabled,
2757 .recalc_rate = clk_rivian_evo_pll_recalc_rate,
2758 .round_rate = clk_rivian_evo_pll_round_rate,
2759 };
2760 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
2761
clk_stromer_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2762 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2763 const struct alpha_pll_config *config)
2764 {
2765 u32 val, val_u, mask, mask_u;
2766
2767 regmap_write(regmap, PLL_L_VAL(pll), config->l);
2768 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2769 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2770
2771 if (pll_has_64bit_config(pll))
2772 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
2773 config->config_ctl_hi_val);
2774
2775 if (pll_alpha_width(pll) > 32)
2776 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
2777
2778 val = config->main_output_mask;
2779 val |= config->aux_output_mask;
2780 val |= config->aux2_output_mask;
2781 val |= config->early_output_mask;
2782 val |= config->pre_div_val;
2783 val |= config->post_div_val;
2784 val |= config->vco_val;
2785 val |= config->alpha_en_mask;
2786 val |= config->alpha_mode_mask;
2787
2788 mask = config->main_output_mask;
2789 mask |= config->aux_output_mask;
2790 mask |= config->aux2_output_mask;
2791 mask |= config->early_output_mask;
2792 mask |= config->pre_div_mask;
2793 mask |= config->post_div_mask;
2794 mask |= config->vco_mask;
2795 mask |= config->alpha_en_mask;
2796 mask |= config->alpha_mode_mask;
2797
2798 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
2799
2800 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */
2801 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT;
2802 val_u |= config->lock_det;
2803
2804 mask_u = config->status_mask;
2805 mask_u |= config->lock_det;
2806
2807 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u);
2808 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2809 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2810
2811 if (pll->flags & SUPPORTS_FSM_MODE)
2812 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
2813 }
2814 EXPORT_SYMBOL_GPL(clk_stromer_pll_configure);
2815
clk_alpha_pll_stromer_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)2816 static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw,
2817 struct clk_rate_request *req)
2818 {
2819 u32 l;
2820 u64 a;
2821
2822 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate,
2823 &l, &a, ALPHA_REG_BITWIDTH);
2824
2825 return 0;
2826 }
2827
clk_alpha_pll_stromer_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)2828 static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
2829 unsigned long prate)
2830 {
2831 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2832 int ret;
2833 u32 l;
2834 u64 a;
2835
2836 rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH);
2837
2838 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2839
2840 a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
2841 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2842 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2843 a >> ALPHA_BITWIDTH);
2844
2845 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2846 PLL_ALPHA_EN, PLL_ALPHA_EN);
2847
2848 if (!clk_hw_is_enabled(hw))
2849 return 0;
2850
2851 /*
2852 * Stromer PLL supports Dynamic programming.
2853 * It allows the PLL frequency to be changed on-the-fly without first
2854 * execution of a shutdown procedure followed by a bring up procedure.
2855 */
2856 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
2857 PLL_UPDATE);
2858
2859 ret = wait_for_pll_update(pll);
2860 if (ret)
2861 return ret;
2862
2863 return wait_for_pll_enable_lock(pll);
2864 }
2865
2866 const struct clk_ops clk_alpha_pll_stromer_ops = {
2867 .enable = clk_alpha_pll_enable,
2868 .disable = clk_alpha_pll_disable,
2869 .is_enabled = clk_alpha_pll_is_enabled,
2870 .recalc_rate = clk_alpha_pll_recalc_rate,
2871 .determine_rate = clk_alpha_pll_stromer_determine_rate,
2872 .set_rate = clk_alpha_pll_stromer_set_rate,
2873 };
2874 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);
2875
clk_alpha_pll_stromer_plus_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long prate)2876 static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw,
2877 unsigned long rate,
2878 unsigned long prate)
2879 {
2880 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2881 u32 l, alpha_width = pll_alpha_width(pll);
2882 int ret, pll_mode;
2883 u64 a;
2884
2885 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
2886
2887 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode);
2888 if (ret)
2889 return ret;
2890
2891 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0);
2892
2893 /* Delay of 2 output clock ticks required until output is disabled */
2894 udelay(1);
2895
2896 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2897
2898 if (alpha_width > ALPHA_BITWIDTH)
2899 a <<= alpha_width - ALPHA_BITWIDTH;
2900
2901 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2902 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2903 a >> ALPHA_BITWIDTH);
2904
2905 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2906 PLL_ALPHA_EN, PLL_ALPHA_EN);
2907
2908 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);
2909
2910 /* Wait five micro seconds or more */
2911 udelay(5);
2912 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N,
2913 PLL_RESET_N);
2914
2915 /* The lock time should be less than 50 micro seconds worst case */
2916 usleep_range(50, 60);
2917
2918 ret = wait_for_pll_enable_lock(pll);
2919 if (ret) {
2920 pr_err("Wait for PLL enable lock failed [%s] %d\n",
2921 clk_hw_get_name(hw), ret);
2922 return ret;
2923 }
2924
2925 if (pll_mode & PLL_OUTCTRL)
2926 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL,
2927 PLL_OUTCTRL);
2928
2929 return 0;
2930 }
2931
2932 const struct clk_ops clk_alpha_pll_stromer_plus_ops = {
2933 .prepare = clk_alpha_pll_enable,
2934 .unprepare = clk_alpha_pll_disable,
2935 .is_enabled = clk_alpha_pll_is_enabled,
2936 .recalc_rate = clk_alpha_pll_recalc_rate,
2937 .determine_rate = clk_alpha_pll_stromer_determine_rate,
2938 .set_rate = clk_alpha_pll_stromer_plus_set_rate,
2939 };
2940 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops);
2941
clk_regera_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap,const struct alpha_pll_config * config)2942 void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2943 const struct alpha_pll_config *config)
2944 {
2945 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2946 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2947 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2948 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2949 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2950 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2951 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2952 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
2953 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2954 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2955 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2956
2957 /* Set operation mode to STANDBY */
2958 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2959 }
2960 EXPORT_SYMBOL_GPL(clk_regera_pll_configure);
2961
2962 const struct clk_ops clk_alpha_pll_regera_ops = {
2963 .enable = clk_zonda_pll_enable,
2964 .disable = clk_zonda_pll_disable,
2965 .is_enabled = clk_alpha_pll_is_enabled,
2966 .recalc_rate = clk_trion_pll_recalc_rate,
2967 .round_rate = clk_alpha_pll_round_rate,
2968 .set_rate = clk_zonda_pll_set_rate,
2969 };
2970 EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops);
2971
qcom_clk_alpha_pll_configure(struct clk_alpha_pll * pll,struct regmap * regmap)2972 void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap)
2973 {
2974 const struct clk_init_data *init = pll->clkr.hw.init;
2975
2976 switch (GET_PLL_TYPE(pll)) {
2977 case CLK_ALPHA_PLL_TYPE_LUCID_OLE:
2978 clk_lucid_ole_pll_configure(pll, regmap, pll->config);
2979 break;
2980 case CLK_ALPHA_PLL_TYPE_LUCID_EVO:
2981 clk_lucid_evo_pll_configure(pll, regmap, pll->config);
2982 break;
2983 case CLK_ALPHA_PLL_TYPE_TAYCAN_ELU:
2984 clk_taycan_elu_pll_configure(pll, regmap, pll->config);
2985 break;
2986 case CLK_ALPHA_PLL_TYPE_RIVIAN_EVO:
2987 clk_rivian_evo_pll_configure(pll, regmap, pll->config);
2988 break;
2989 case CLK_ALPHA_PLL_TYPE_TRION:
2990 clk_trion_pll_configure(pll, regmap, pll->config);
2991 break;
2992 case CLK_ALPHA_PLL_TYPE_HUAYRA_2290:
2993 clk_huayra_2290_pll_configure(pll, regmap, pll->config);
2994 break;
2995 case CLK_ALPHA_PLL_TYPE_FABIA:
2996 clk_fabia_pll_configure(pll, regmap, pll->config);
2997 break;
2998 case CLK_ALPHA_PLL_TYPE_AGERA:
2999 clk_agera_pll_configure(pll, regmap, pll->config);
3000 break;
3001 case CLK_ALPHA_PLL_TYPE_PONGO_ELU:
3002 clk_pongo_elu_pll_configure(pll, regmap, pll->config);
3003 break;
3004 case CLK_ALPHA_PLL_TYPE_ZONDA:
3005 case CLK_ALPHA_PLL_TYPE_ZONDA_OLE:
3006 clk_zonda_pll_configure(pll, regmap, pll->config);
3007 break;
3008 case CLK_ALPHA_PLL_TYPE_STROMER:
3009 case CLK_ALPHA_PLL_TYPE_STROMER_PLUS:
3010 clk_stromer_pll_configure(pll, regmap, pll->config);
3011 break;
3012 case CLK_ALPHA_PLL_TYPE_DEFAULT:
3013 case CLK_ALPHA_PLL_TYPE_DEFAULT_EVO:
3014 case CLK_ALPHA_PLL_TYPE_HUAYRA:
3015 case CLK_ALPHA_PLL_TYPE_HUAYRA_APSS:
3016 case CLK_ALPHA_PLL_TYPE_BRAMMO:
3017 case CLK_ALPHA_PLL_TYPE_BRAMMO_EVO:
3018 clk_alpha_pll_configure(pll, regmap, pll->config);
3019 break;
3020 default:
3021 WARN(1, "%s: invalid pll type\n", init->name);
3022 break;
3023 }
3024 }
3025 EXPORT_SYMBOL_GPL(qcom_clk_alpha_pll_configure);
3026
clk_alpha_pll_slew_update(struct clk_alpha_pll * pll)3027 static int clk_alpha_pll_slew_update(struct clk_alpha_pll *pll)
3028 {
3029 u32 val;
3030 int ret;
3031
3032 regmap_set_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE);
3033 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
3034
3035 ret = wait_for_pll_update(pll);
3036 if (ret)
3037 return ret;
3038 /*
3039 * Hardware programming mandates a wait of at least 570ns before polling the LOCK
3040 * detect bit. Have a delay of 1us just to be safe.
3041 */
3042 udelay(1);
3043
3044 return wait_for_pll_enable_lock(pll);
3045 }
3046
clk_alpha_pll_slew_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)3047 static int clk_alpha_pll_slew_set_rate(struct clk_hw *hw, unsigned long rate,
3048 unsigned long parent_rate)
3049 {
3050 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
3051 const struct pll_vco *curr_vco, *vco;
3052 unsigned long freq_hz;
3053 u64 a;
3054 u32 l;
3055
3056 freq_hz = alpha_pll_round_rate(rate, parent_rate, &l, &a, ALPHA_REG_BITWIDTH);
3057 if (freq_hz != rate) {
3058 pr_err("alpha_pll: Call clk_set_rate with rounded rates!\n");
3059 return -EINVAL;
3060 }
3061
3062 curr_vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
3063 if (!curr_vco) {
3064 pr_err("alpha pll: not in a valid vco range\n");
3065 return -EINVAL;
3066 }
3067
3068 vco = alpha_pll_find_vco(pll, freq_hz);
3069 if (!vco) {
3070 pr_err("alpha pll: not in a valid vco range\n");
3071 return -EINVAL;
3072 }
3073
3074 /*
3075 * Dynamic pll update will not support switching frequencies across
3076 * vco ranges. In those cases fall back to normal alpha set rate.
3077 */
3078 if (curr_vco->val != vco->val)
3079 return clk_alpha_pll_set_rate(hw, rate, parent_rate);
3080
3081 clk_alpha_pll_update_configs(pll, NULL, l, a, ALPHA_REG_BITWIDTH, false);
3082
3083 /* Ensure that the write above goes before slewing the PLL */
3084 mb();
3085
3086 if (clk_hw_is_enabled(hw))
3087 return clk_alpha_pll_slew_update(pll);
3088
3089 return 0;
3090 }
3091
3092 /*
3093 * Slewing plls should be bought up at frequency which is in the middle of the
3094 * desired VCO range. So after bringing up the pll at calibration freq, set it
3095 * back to desired frequency(that was set by previous clk_set_rate).
3096 */
clk_alpha_pll_calibrate(struct clk_hw * hw)3097 static int clk_alpha_pll_calibrate(struct clk_hw *hw)
3098 {
3099 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
3100 struct clk_hw *parent;
3101 const struct pll_vco *vco;
3102 unsigned long calibration_freq, freq_hz;
3103 u64 a;
3104 u32 l;
3105 int rc;
3106
3107 parent = clk_hw_get_parent(hw);
3108 if (!parent) {
3109 pr_err("alpha pll: no valid parent found\n");
3110 return -EINVAL;
3111 }
3112
3113 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
3114 if (!vco) {
3115 pr_err("alpha pll: not in a valid vco range\n");
3116 return -EINVAL;
3117 }
3118
3119 /*
3120 * As during slewing plls vco_sel won't be allowed to change, vco table
3121 * should have only one entry table, i.e. index = 0, find the
3122 * calibration frequency.
3123 */
3124 calibration_freq = (pll->vco_table[0].min_freq + pll->vco_table[0].max_freq) / 2;
3125
3126 freq_hz = alpha_pll_round_rate(calibration_freq, clk_hw_get_rate(parent),
3127 &l, &a, ALPHA_REG_BITWIDTH);
3128 if (freq_hz != calibration_freq) {
3129 pr_err("alpha_pll: call clk_set_rate with rounded rates!\n");
3130 return -EINVAL;
3131 }
3132
3133 clk_alpha_pll_update_configs(pll, vco, l, a, ALPHA_REG_BITWIDTH, false);
3134
3135 /* Bringup the pll at calibration frequency */
3136 rc = clk_alpha_pll_enable(hw);
3137 if (rc) {
3138 pr_err("alpha pll calibration failed\n");
3139 return rc;
3140 }
3141
3142 /*
3143 * PLL is already running at calibration frequency.
3144 * So slew pll to the previously set frequency.
3145 */
3146 freq_hz = alpha_pll_round_rate(clk_hw_get_rate(hw),
3147 clk_hw_get_rate(parent), &l, &a, ALPHA_REG_BITWIDTH);
3148
3149 pr_debug("pll %s: setting back to required rate %lu, freq_hz %ld\n",
3150 clk_hw_get_name(hw), clk_hw_get_rate(hw), freq_hz);
3151
3152 clk_alpha_pll_update_configs(pll, NULL, l, a, ALPHA_REG_BITWIDTH, true);
3153
3154 return clk_alpha_pll_slew_update(pll);
3155 }
3156
clk_alpha_pll_slew_enable(struct clk_hw * hw)3157 static int clk_alpha_pll_slew_enable(struct clk_hw *hw)
3158 {
3159 int rc;
3160
3161 rc = clk_alpha_pll_calibrate(hw);
3162 if (rc)
3163 return rc;
3164
3165 return clk_alpha_pll_enable(hw);
3166 }
3167
3168 const struct clk_ops clk_alpha_pll_slew_ops = {
3169 .enable = clk_alpha_pll_slew_enable,
3170 .disable = clk_alpha_pll_disable,
3171 .recalc_rate = clk_alpha_pll_recalc_rate,
3172 .round_rate = clk_alpha_pll_round_rate,
3173 .set_rate = clk_alpha_pll_slew_set_rate,
3174 };
3175 EXPORT_SYMBOL(clk_alpha_pll_slew_ops);
3176