1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell OcteonTx2 CGX driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/phy.h>
16 #include <linux/of.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
19
20 #include "cgx.h"
21 #include "rvu.h"
22 #include "lmac_common.h"
23
24 #define DRV_NAME "Marvell-CGX/RPM"
25 #define DRV_STRING "Marvell CGX/RPM Driver"
26
27 #define CGX_RX_STAT_GLOBAL_INDEX 9
28
29 static LIST_HEAD(cgx_list);
30
31 /* Convert firmware speed encoding to user format(Mbps) */
32 static const u32 cgx_speed_mbps[CGX_LINK_SPEED_MAX] = {
33 [CGX_LINK_NONE] = 0,
34 [CGX_LINK_10M] = 10,
35 [CGX_LINK_100M] = 100,
36 [CGX_LINK_1G] = 1000,
37 [CGX_LINK_2HG] = 2500,
38 [CGX_LINK_5G] = 5000,
39 [CGX_LINK_10G] = 10000,
40 [CGX_LINK_20G] = 20000,
41 [CGX_LINK_25G] = 25000,
42 [CGX_LINK_40G] = 40000,
43 [CGX_LINK_50G] = 50000,
44 [CGX_LINK_80G] = 80000,
45 [CGX_LINK_100G] = 100000,
46 };
47
48 /* Convert firmware lmac type encoding to string */
49 static const char *cgx_lmactype_string[LMAC_MODE_MAX] = {
50 [LMAC_MODE_SGMII] = "SGMII",
51 [LMAC_MODE_XAUI] = "XAUI",
52 [LMAC_MODE_RXAUI] = "RXAUI",
53 [LMAC_MODE_10G_R] = "10G_R",
54 [LMAC_MODE_40G_R] = "40G_R",
55 [LMAC_MODE_QSGMII] = "QSGMII",
56 [LMAC_MODE_25G_R] = "25G_R",
57 [LMAC_MODE_50G_R] = "50G_R",
58 [LMAC_MODE_100G_R] = "100G_R",
59 [LMAC_MODE_USXGMII] = "USXGMII",
60 [LMAC_MODE_USGMII] = "USGMII",
61 };
62
63 /* CGX PHY management internal APIs */
64 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool en);
65
66 /* Supported devices */
67 static const struct pci_device_id cgx_id_table[] = {
68 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) },
69 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM,
70 PCI_ANY_ID, PCI_SUBSYS_DEVID_CN10K_A) },
71 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM,
72 PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF10K_A) },
73 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM,
74 PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF10K_B) },
75 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM,
76 PCI_ANY_ID, PCI_SUBSYS_DEVID_CN10K_B) },
77 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM,
78 PCI_ANY_ID, PCI_SUBSYS_DEVID_CN20KA) },
79 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM,
80 PCI_ANY_ID, PCI_SUBSYS_DEVID_CNF20KA) },
81 { 0, } /* end of table */
82 };
83
84 MODULE_DEVICE_TABLE(pci, cgx_id_table);
85
is_dev_rpm(void * cgxd)86 static bool is_dev_rpm(void *cgxd)
87 {
88 struct cgx *cgx = cgxd;
89
90 return (cgx->pdev->device == PCI_DEVID_CN10K_RPM) ||
91 (cgx->pdev->device == PCI_DEVID_CN10KB_RPM);
92 }
93
is_lmac_valid(struct cgx * cgx,int lmac_id)94 bool is_lmac_valid(struct cgx *cgx, int lmac_id)
95 {
96 if (!cgx || lmac_id < 0 || lmac_id >= cgx->max_lmac_per_mac)
97 return false;
98 return test_bit(lmac_id, &cgx->lmac_bmap);
99 }
100
101 /* Helper function to get sequential index
102 * given the enabled LMAC of a CGX
103 */
get_sequence_id_of_lmac(struct cgx * cgx,int lmac_id)104 static int get_sequence_id_of_lmac(struct cgx *cgx, int lmac_id)
105 {
106 int tmp, id = 0;
107
108 for_each_set_bit(tmp, &cgx->lmac_bmap, cgx->max_lmac_per_mac) {
109 if (tmp == lmac_id)
110 break;
111 id++;
112 }
113
114 return id;
115 }
116
get_mac_ops(void * cgxd)117 struct mac_ops *get_mac_ops(void *cgxd)
118 {
119 if (!cgxd)
120 return cgxd;
121
122 return ((struct cgx *)cgxd)->mac_ops;
123 }
124
cgx_get_fifo_len(void * cgxd)125 u32 cgx_get_fifo_len(void *cgxd)
126 {
127 return ((struct cgx *)cgxd)->fifo_len;
128 }
129
cgx_write(struct cgx * cgx,u64 lmac,u64 offset,u64 val)130 void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val)
131 {
132 writeq(val, cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) +
133 offset);
134 }
135
cgx_read(struct cgx * cgx,u64 lmac,u64 offset)136 u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset)
137 {
138 return readq(cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) +
139 offset);
140 }
141
lmac_pdata(u8 lmac_id,struct cgx * cgx)142 struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx)
143 {
144 if (!cgx || lmac_id >= cgx->max_lmac_per_mac)
145 return NULL;
146
147 return cgx->lmac_idmap[lmac_id];
148 }
149
cgx_get_cgxcnt_max(void)150 int cgx_get_cgxcnt_max(void)
151 {
152 struct cgx *cgx_dev;
153 int idmax = -ENODEV;
154
155 list_for_each_entry(cgx_dev, &cgx_list, cgx_list)
156 if (cgx_dev->cgx_id > idmax)
157 idmax = cgx_dev->cgx_id;
158
159 if (idmax < 0)
160 return 0;
161
162 return idmax + 1;
163 }
164
cgx_get_lmac_cnt(void * cgxd)165 int cgx_get_lmac_cnt(void *cgxd)
166 {
167 struct cgx *cgx = cgxd;
168
169 if (!cgx)
170 return -ENODEV;
171
172 return cgx->lmac_count;
173 }
174
cgx_get_pdata(int cgx_id)175 void *cgx_get_pdata(int cgx_id)
176 {
177 struct cgx *cgx_dev;
178
179 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) {
180 if (cgx_dev->cgx_id == cgx_id)
181 return cgx_dev;
182 }
183 return NULL;
184 }
185
cgx_lmac_write(int cgx_id,int lmac_id,u64 offset,u64 val)186 void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val)
187 {
188 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
189
190 /* Software must not access disabled LMAC registers */
191 if (!is_lmac_valid(cgx_dev, lmac_id))
192 return;
193 cgx_write(cgx_dev, lmac_id, offset, val);
194 }
195
cgx_lmac_read(int cgx_id,int lmac_id,u64 offset)196 u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset)
197 {
198 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
199
200 /* Software must not access disabled LMAC registers */
201 if (!is_lmac_valid(cgx_dev, lmac_id))
202 return 0;
203
204 return cgx_read(cgx_dev, lmac_id, offset);
205 }
206
cgx_get_cgxid(void * cgxd)207 int cgx_get_cgxid(void *cgxd)
208 {
209 struct cgx *cgx = cgxd;
210
211 if (!cgx)
212 return -EINVAL;
213
214 return cgx->cgx_id;
215 }
216
cgx_lmac_get_p2x(int cgx_id,int lmac_id)217 u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id)
218 {
219 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
220 u64 cfg;
221
222 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_CFG);
223
224 return (cfg & CMR_P2X_SEL_MASK) >> CMR_P2X_SEL_SHIFT;
225 }
226
cgx_get_nix_resetbit(struct cgx * cgx)227 static u8 cgx_get_nix_resetbit(struct cgx *cgx)
228 {
229 int first_lmac;
230 u8 p2x;
231
232 /* non 98XX silicons supports only NIX0 block */
233 if (cgx->pdev->subsystem_device != PCI_SUBSYS_DEVID_98XX)
234 return CGX_NIX0_RESET;
235
236 first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac);
237 p2x = cgx_lmac_get_p2x(cgx->cgx_id, first_lmac);
238
239 if (p2x == CMR_P2X_SEL_NIX1)
240 return CGX_NIX1_RESET;
241 else
242 return CGX_NIX0_RESET;
243 }
244
245 /* Ensure the required lock for event queue(where asynchronous events are
246 * posted) is acquired before calling this API. Else an asynchronous event(with
247 * latest link status) can reach the destination before this function returns
248 * and could make the link status appear wrong.
249 */
cgx_get_link_info(void * cgxd,int lmac_id,struct cgx_link_user_info * linfo)250 int cgx_get_link_info(void *cgxd, int lmac_id,
251 struct cgx_link_user_info *linfo)
252 {
253 struct lmac *lmac = lmac_pdata(lmac_id, cgxd);
254
255 if (!lmac)
256 return -ENODEV;
257
258 *linfo = lmac->link_info;
259 return 0;
260 }
261
cgx_lmac_addr_set(u8 cgx_id,u8 lmac_id,u8 * mac_addr)262 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr)
263 {
264 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
265 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
266 struct mac_ops *mac_ops;
267 int index, id;
268 u64 cfg;
269
270 if (!lmac)
271 return -ENODEV;
272
273 /* access mac_ops to know csr_offset */
274 mac_ops = cgx_dev->mac_ops;
275
276 /* copy 6bytes from macaddr */
277 /* memcpy(&cfg, mac_addr, 6); */
278
279 cfg = ether_addr_to_u64(mac_addr);
280
281 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
282
283 index = id * lmac->mac_to_index_bmap.max;
284
285 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)),
286 cfg | CGX_DMAC_CAM_ADDR_ENABLE | ((u64)lmac_id << 49));
287
288 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
289 cfg |= (CGX_DMAC_CTL0_CAM_ENABLE | CGX_DMAC_BCAST_MODE |
290 CGX_DMAC_MCAST_MODE);
291 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
292
293 return 0;
294 }
295
cgx_read_dmac_ctrl(void * cgxd,int lmac_id)296 u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id)
297 {
298 struct mac_ops *mac_ops;
299 struct cgx *cgx = cgxd;
300
301 if (!cgxd || !is_lmac_valid(cgxd, lmac_id))
302 return 0;
303
304 cgx = cgxd;
305 /* Get mac_ops to know csr offset */
306 mac_ops = cgx->mac_ops;
307
308 return cgx_read(cgxd, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
309 }
310
cgx_read_dmac_entry(void * cgxd,int index)311 u64 cgx_read_dmac_entry(void *cgxd, int index)
312 {
313 struct mac_ops *mac_ops;
314 struct cgx *cgx;
315
316 if (!cgxd)
317 return 0;
318
319 cgx = cgxd;
320 mac_ops = cgx->mac_ops;
321 return cgx_read(cgx, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 8)));
322 }
323
cgx_lmac_addr_add(u8 cgx_id,u8 lmac_id,u8 * mac_addr)324 int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr)
325 {
326 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
327 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
328 struct mac_ops *mac_ops;
329 int index, idx;
330 u64 cfg = 0;
331 int id;
332
333 if (!lmac)
334 return -ENODEV;
335
336 mac_ops = cgx_dev->mac_ops;
337 /* Get available index where entry is to be installed */
338 idx = rvu_alloc_rsrc(&lmac->mac_to_index_bmap);
339 if (idx < 0)
340 return idx;
341
342 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
343
344 index = id * lmac->mac_to_index_bmap.max + idx;
345
346 cfg = ether_addr_to_u64(mac_addr);
347 cfg |= CGX_DMAC_CAM_ADDR_ENABLE;
348 cfg |= ((u64)lmac_id << 49);
349 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg);
350
351 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
352 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_CAM_ACCEPT);
353
354 if (is_multicast_ether_addr(mac_addr)) {
355 cfg &= ~GENMASK_ULL(2, 1);
356 cfg |= CGX_DMAC_MCAST_MODE_CAM;
357 lmac->mcast_filters_count++;
358 } else if (!lmac->mcast_filters_count) {
359 cfg |= CGX_DMAC_MCAST_MODE;
360 }
361
362 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
363
364 return idx;
365 }
366
cgx_lmac_addr_reset(u8 cgx_id,u8 lmac_id)367 int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id)
368 {
369 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
370 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
371 struct mac_ops *mac_ops;
372 u8 index = 0, id;
373 u64 cfg;
374
375 if (!lmac)
376 return -ENODEV;
377
378 mac_ops = cgx_dev->mac_ops;
379 /* Restore index 0 to its default init value as done during
380 * cgx_lmac_init
381 */
382 set_bit(0, lmac->mac_to_index_bmap.bmap);
383
384 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
385
386 index = id * lmac->mac_to_index_bmap.max + index;
387 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0);
388
389 /* Reset CGXX_CMRX_RX_DMAC_CTL0 register to default state */
390 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
391 cfg &= ~CGX_DMAC_CAM_ACCEPT;
392 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE);
393 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
394
395 return 0;
396 }
397
398 /* Allows caller to change macaddress associated with index
399 * in dmac filter table including index 0 reserved for
400 * interface mac address
401 */
cgx_lmac_addr_update(u8 cgx_id,u8 lmac_id,u8 * mac_addr,u8 index)402 int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index)
403 {
404 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
405 struct mac_ops *mac_ops;
406 struct lmac *lmac;
407 u64 cfg;
408 int id;
409
410 lmac = lmac_pdata(lmac_id, cgx_dev);
411 if (!lmac)
412 return -ENODEV;
413
414 mac_ops = cgx_dev->mac_ops;
415 /* Validate the index */
416 if (index >= lmac->mac_to_index_bmap.max)
417 return -EINVAL;
418
419 /* ensure index is already set */
420 if (!test_bit(index, lmac->mac_to_index_bmap.bmap))
421 return -EINVAL;
422
423 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
424
425 index = id * lmac->mac_to_index_bmap.max + index;
426
427 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)));
428 cfg &= ~CGX_RX_DMAC_ADR_MASK;
429 cfg |= ether_addr_to_u64(mac_addr);
430
431 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg);
432 return 0;
433 }
434
cgx_lmac_addr_del(u8 cgx_id,u8 lmac_id,u8 index)435 int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index)
436 {
437 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
438 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
439 struct mac_ops *mac_ops;
440 u8 mac[ETH_ALEN];
441 u64 cfg;
442 int id;
443
444 if (!lmac)
445 return -ENODEV;
446
447 mac_ops = cgx_dev->mac_ops;
448 /* Validate the index */
449 if (index >= lmac->mac_to_index_bmap.max)
450 return -EINVAL;
451
452 /* Skip deletion for reserved index i.e. index 0 */
453 if (index == 0)
454 return 0;
455
456 rvu_free_rsrc(&lmac->mac_to_index_bmap, index);
457
458 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
459
460 index = id * lmac->mac_to_index_bmap.max + index;
461
462 /* Read MAC address to check whether it is ucast or mcast */
463 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)));
464
465 u64_to_ether_addr(cfg, mac);
466 if (is_multicast_ether_addr(mac))
467 lmac->mcast_filters_count--;
468
469 if (!lmac->mcast_filters_count) {
470 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
471 cfg &= ~GENMASK_ULL(2, 1);
472 cfg |= CGX_DMAC_MCAST_MODE;
473 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
474 }
475
476 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0);
477
478 return 0;
479 }
480
cgx_lmac_addr_max_entries_get(u8 cgx_id,u8 lmac_id)481 int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id)
482 {
483 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
484 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
485
486 if (lmac)
487 return lmac->mac_to_index_bmap.max;
488
489 return 0;
490 }
491
cgx_lmac_addr_get(u8 cgx_id,u8 lmac_id)492 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id)
493 {
494 struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
495 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev);
496 struct mac_ops *mac_ops;
497 int index;
498 u64 cfg;
499 int id;
500
501 mac_ops = cgx_dev->mac_ops;
502
503 id = get_sequence_id_of_lmac(cgx_dev, lmac_id);
504
505 index = id * lmac->mac_to_index_bmap.max;
506
507 cfg = cgx_read(cgx_dev, 0, CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8);
508 return cfg & CGX_RX_DMAC_ADR_MASK;
509 }
510
cgx_set_pkind(void * cgxd,u8 lmac_id,int pkind)511 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind)
512 {
513 struct cgx *cgx = cgxd;
514
515 if (!is_lmac_valid(cgx, lmac_id))
516 return -ENODEV;
517
518 cgx_write(cgx, lmac_id, cgx->mac_ops->rxid_map_offset, (pkind & 0x3F));
519 return 0;
520 }
521
cgx_get_lmac_type(void * cgxd,int lmac_id)522 static u8 cgx_get_lmac_type(void *cgxd, int lmac_id)
523 {
524 struct cgx *cgx = cgxd;
525 u64 cfg;
526
527 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
528 return (cfg >> CGX_LMAC_TYPE_SHIFT) & CGX_LMAC_TYPE_MASK;
529 }
530
cgx_get_lmac_fifo_len(void * cgxd,int lmac_id)531 static u32 cgx_get_lmac_fifo_len(void *cgxd, int lmac_id)
532 {
533 struct cgx *cgx = cgxd;
534 u8 num_lmacs;
535 u32 fifo_len;
536
537 fifo_len = cgx->fifo_len;
538 num_lmacs = cgx->mac_ops->get_nr_lmacs(cgx);
539
540 switch (num_lmacs) {
541 case 1:
542 return fifo_len;
543 case 2:
544 return fifo_len / 2;
545 case 3:
546 /* LMAC0 gets half of the FIFO, reset 1/4th */
547 if (lmac_id == 0)
548 return fifo_len / 2;
549 return fifo_len / 4;
550 case 4:
551 default:
552 return fifo_len / 4;
553 }
554 return 0;
555 }
556
557 /* Configure CGX LMAC in internal loopback mode */
cgx_lmac_internal_loopback(void * cgxd,int lmac_id,bool enable)558 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable)
559 {
560 struct cgx *cgx = cgxd;
561 struct lmac *lmac;
562 u64 cfg;
563
564 if (!is_lmac_valid(cgx, lmac_id))
565 return -ENODEV;
566
567 lmac = lmac_pdata(lmac_id, cgx);
568 if (lmac->lmac_type == LMAC_MODE_SGMII ||
569 lmac->lmac_type == LMAC_MODE_QSGMII) {
570 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL);
571 if (enable)
572 cfg |= CGXX_GMP_PCS_MRX_CTL_LBK;
573 else
574 cfg &= ~CGXX_GMP_PCS_MRX_CTL_LBK;
575 cgx_write(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL, cfg);
576 } else {
577 cfg = cgx_read(cgx, lmac_id, CGXX_SPUX_CONTROL1);
578 if (enable)
579 cfg |= CGXX_SPUX_CONTROL1_LBK;
580 else
581 cfg &= ~CGXX_SPUX_CONTROL1_LBK;
582 cgx_write(cgx, lmac_id, CGXX_SPUX_CONTROL1, cfg);
583 }
584 return 0;
585 }
586
cgx_lmac_promisc_config(int cgx_id,int lmac_id,bool enable)587 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable)
588 {
589 struct cgx *cgx = cgx_get_pdata(cgx_id);
590 struct lmac *lmac = lmac_pdata(lmac_id, cgx);
591 struct mac_ops *mac_ops;
592 u16 max_dmac;
593 int index, i;
594 u64 cfg = 0;
595 int id;
596
597 if (!cgx || !lmac)
598 return;
599
600 max_dmac = lmac->mac_to_index_bmap.max;
601 id = get_sequence_id_of_lmac(cgx, lmac_id);
602
603 mac_ops = cgx->mac_ops;
604 if (enable) {
605 /* Enable promiscuous mode on LMAC */
606 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
607 cfg &= ~CGX_DMAC_CAM_ACCEPT;
608 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE);
609 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
610
611 for (i = 0; i < max_dmac; i++) {
612 index = id * max_dmac + i;
613 cfg = cgx_read(cgx, 0,
614 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8));
615 cfg &= ~CGX_DMAC_CAM_ADDR_ENABLE;
616 cgx_write(cgx, 0,
617 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8), cfg);
618 }
619 } else {
620 /* Disable promiscuous mode */
621 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
622 cfg |= CGX_DMAC_CAM_ACCEPT | CGX_DMAC_MCAST_MODE;
623 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
624 for (i = 0; i < max_dmac; i++) {
625 index = id * max_dmac + i;
626 cfg = cgx_read(cgx, 0,
627 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8));
628 if ((cfg & CGX_RX_DMAC_ADR_MASK) != 0) {
629 cfg |= CGX_DMAC_CAM_ADDR_ENABLE;
630 cgx_write(cgx, 0,
631 (CGXX_CMRX_RX_DMAC_CAM0 +
632 index * 0x8),
633 cfg);
634 }
635 }
636 }
637 }
638
cgx_lmac_get_pause_frm_status(void * cgxd,int lmac_id,u8 * tx_pause,u8 * rx_pause)639 static int cgx_lmac_get_pause_frm_status(void *cgxd, int lmac_id,
640 u8 *tx_pause, u8 *rx_pause)
641 {
642 struct cgx *cgx = cgxd;
643 u64 cfg;
644
645 if (is_dev_rpm(cgx))
646 return 0;
647
648 if (!is_lmac_valid(cgx, lmac_id))
649 return -ENODEV;
650
651 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
652 *rx_pause = !!(cfg & CGX_SMUX_RX_FRM_CTL_CTL_BCK);
653
654 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
655 *tx_pause = !!(cfg & CGX_SMUX_TX_CTL_L2P_BP_CONV);
656 return 0;
657 }
658
659 /* Enable or disable forwarding received pause frames to Tx block */
cgx_lmac_enadis_rx_pause_fwding(void * cgxd,int lmac_id,bool enable)660 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable)
661 {
662 struct cgx *cgx = cgxd;
663 u8 rx_pause, tx_pause;
664 bool is_pfc_enabled;
665 struct lmac *lmac;
666 u64 cfg;
667
668 if (!cgx)
669 return;
670
671 lmac = lmac_pdata(lmac_id, cgx);
672 if (!lmac)
673 return;
674
675 /* Pause frames are not enabled just return */
676 if (!bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max))
677 return;
678
679 cgx_lmac_get_pause_frm_status(cgx, lmac_id, &rx_pause, &tx_pause);
680 is_pfc_enabled = rx_pause ? false : true;
681
682 if (enable) {
683 if (!is_pfc_enabled) {
684 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
685 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
686 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
687
688 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
689 cfg |= CGX_SMUX_RX_FRM_CTL_CTL_BCK;
690 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
691 } else {
692 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
693 cfg |= CGXX_SMUX_CBFC_CTL_BCK_EN;
694 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
695 }
696 } else {
697
698 if (!is_pfc_enabled) {
699 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
700 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
701 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
702
703 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
704 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
705 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
706 } else {
707 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
708 cfg &= ~CGXX_SMUX_CBFC_CTL_BCK_EN;
709 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
710 }
711 }
712 }
713
cgx_get_rx_stats(void * cgxd,int lmac_id,int idx,u64 * rx_stat)714 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat)
715 {
716 struct cgx *cgx = cgxd;
717
718 if (!is_lmac_valid(cgx, lmac_id))
719 return -ENODEV;
720
721 /* pass lmac as 0 for CGX_CMR_RX_STAT9-12 */
722 if (idx >= CGX_RX_STAT_GLOBAL_INDEX)
723 lmac_id = 0;
724
725 *rx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_STAT0 + (idx * 8));
726 return 0;
727 }
728
cgx_get_tx_stats(void * cgxd,int lmac_id,int idx,u64 * tx_stat)729 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat)
730 {
731 struct cgx *cgx = cgxd;
732
733 if (!is_lmac_valid(cgx, lmac_id))
734 return -ENODEV;
735 *tx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (idx * 8));
736 return 0;
737 }
738
cgx_features_get(void * cgxd)739 u64 cgx_features_get(void *cgxd)
740 {
741 return ((struct cgx *)cgxd)->hw_features;
742 }
743
cgx_stats_reset(void * cgxd,int lmac_id)744 int cgx_stats_reset(void *cgxd, int lmac_id)
745 {
746 struct cgx *cgx = cgxd;
747 int stat_id;
748
749 if (!is_lmac_valid(cgx, lmac_id))
750 return -ENODEV;
751
752 for (stat_id = 0 ; stat_id < CGX_RX_STATS_COUNT; stat_id++) {
753 if (stat_id >= CGX_RX_STAT_GLOBAL_INDEX)
754 /* pass lmac as 0 for CGX_CMR_RX_STAT9-12 */
755 cgx_write(cgx, 0,
756 (CGXX_CMRX_RX_STAT0 + (stat_id * 8)), 0);
757 else
758 cgx_write(cgx, lmac_id,
759 (CGXX_CMRX_RX_STAT0 + (stat_id * 8)), 0);
760 }
761
762 for (stat_id = 0 ; stat_id < CGX_TX_STATS_COUNT; stat_id++)
763 cgx_write(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (stat_id * 8), 0);
764
765 return 0;
766 }
767
cgx_set_fec_stats_count(struct cgx_link_user_info * linfo)768 static int cgx_set_fec_stats_count(struct cgx_link_user_info *linfo)
769 {
770 if (!linfo->fec)
771 return 0;
772
773 switch (linfo->lmac_type_id) {
774 case LMAC_MODE_SGMII:
775 case LMAC_MODE_XAUI:
776 case LMAC_MODE_RXAUI:
777 case LMAC_MODE_QSGMII:
778 return 0;
779 case LMAC_MODE_10G_R:
780 case LMAC_MODE_25G_R:
781 case LMAC_MODE_100G_R:
782 case LMAC_MODE_USXGMII:
783 return 1;
784 case LMAC_MODE_40G_R:
785 return 4;
786 case LMAC_MODE_50G_R:
787 if (linfo->fec == OTX2_FEC_BASER)
788 return 2;
789 else
790 return 1;
791 default:
792 return 0;
793 }
794 }
795
cgx_get_fec_stats(void * cgxd,int lmac_id,struct cgx_fec_stats_rsp * rsp)796 int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp)
797 {
798 int stats, fec_stats_count = 0;
799 int corr_reg, uncorr_reg;
800 struct cgx *cgx = cgxd;
801
802 if (!is_lmac_valid(cgx, lmac_id))
803 return -ENODEV;
804
805 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_NONE)
806 return 0;
807
808 fec_stats_count =
809 cgx_set_fec_stats_count(&cgx->lmac_idmap[lmac_id]->link_info);
810 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_BASER) {
811 corr_reg = CGXX_SPUX_LNX_FEC_CORR_BLOCKS;
812 uncorr_reg = CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS;
813 } else {
814 corr_reg = CGXX_SPUX_RSFEC_CORR;
815 uncorr_reg = CGXX_SPUX_RSFEC_UNCORR;
816 }
817 for (stats = 0; stats < fec_stats_count; stats++) {
818 rsp->fec_corr_blks +=
819 cgx_read(cgx, lmac_id, corr_reg + (stats * 8));
820 rsp->fec_uncorr_blks +=
821 cgx_read(cgx, lmac_id, uncorr_reg + (stats * 8));
822 }
823 return 0;
824 }
825
cgx_lmac_rx_tx_enable(void * cgxd,int lmac_id,bool enable)826 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable)
827 {
828 struct cgx *cgx = cgxd;
829 u64 cfg;
830
831 if (!is_lmac_valid(cgx, lmac_id))
832 return -ENODEV;
833
834 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
835 if (enable)
836 cfg |= DATA_PKT_RX_EN | DATA_PKT_TX_EN;
837 else
838 cfg &= ~(DATA_PKT_RX_EN | DATA_PKT_TX_EN);
839 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
840 return 0;
841 }
842
cgx_lmac_tx_enable(void * cgxd,int lmac_id,bool enable)843 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable)
844 {
845 struct cgx *cgx = cgxd;
846 u64 cfg, last;
847
848 if (!is_lmac_valid(cgx, lmac_id))
849 return -ENODEV;
850
851 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
852 last = cfg;
853 if (enable)
854 cfg |= DATA_PKT_TX_EN;
855 else
856 cfg &= ~DATA_PKT_TX_EN;
857
858 if (cfg != last)
859 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
860 return !!(last & DATA_PKT_TX_EN);
861 }
862
cgx_lmac_enadis_pause_frm(void * cgxd,int lmac_id,u8 tx_pause,u8 rx_pause)863 static int cgx_lmac_enadis_pause_frm(void *cgxd, int lmac_id,
864 u8 tx_pause, u8 rx_pause)
865 {
866 struct cgx *cgx = cgxd;
867 u64 cfg;
868
869 if (is_dev_rpm(cgx))
870 return 0;
871
872 if (!is_lmac_valid(cgx, lmac_id))
873 return -ENODEV;
874
875 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
876 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
877 cfg |= rx_pause ? CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK : 0x0;
878 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
879
880 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
881 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
882 cfg |= rx_pause ? CGX_SMUX_RX_FRM_CTL_CTL_BCK : 0x0;
883 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
884
885 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
886 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV;
887 cfg |= tx_pause ? CGX_SMUX_TX_CTL_L2P_BP_CONV : 0x0;
888 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg);
889
890 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP);
891 if (tx_pause) {
892 cfg &= ~CGX_CMR_RX_OVR_BP_EN(lmac_id);
893 } else {
894 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id);
895 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id);
896 }
897 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg);
898 return 0;
899 }
900
cgx_lmac_pause_frm_config(void * cgxd,int lmac_id,bool enable)901 static void cgx_lmac_pause_frm_config(void *cgxd, int lmac_id, bool enable)
902 {
903 struct cgx *cgx = cgxd;
904 u64 cfg;
905
906 if (!is_lmac_valid(cgx, lmac_id))
907 return;
908
909 if (enable) {
910 /* Set pause time and interval */
911 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_TIME,
912 DEFAULT_PAUSE_TIME);
913 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL);
914 cfg &= ~0xFFFFULL;
915 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL,
916 cfg | (DEFAULT_PAUSE_TIME / 2));
917
918 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_TIME,
919 DEFAULT_PAUSE_TIME);
920
921 cfg = cgx_read(cgx, lmac_id,
922 CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL);
923 cfg &= ~0xFFFFULL;
924 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL,
925 cfg | (DEFAULT_PAUSE_TIME / 2));
926 }
927
928 /* ALL pause frames received are completely ignored */
929 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
930 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;
931 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
932
933 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
934 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;
935 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
936
937 /* Disable pause frames transmission */
938 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL);
939 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV;
940 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg);
941
942 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP);
943 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id);
944 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id);
945 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg);
946
947 /* Disable all PFC classes by default */
948 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
949 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg);
950 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
951 }
952
verify_lmac_fc_cfg(void * cgxd,int lmac_id,u8 tx_pause,u8 rx_pause,int pfvf_idx)953 int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,
954 int pfvf_idx)
955 {
956 struct cgx *cgx = cgxd;
957 struct lmac *lmac;
958
959 lmac = lmac_pdata(lmac_id, cgx);
960 if (!lmac)
961 return -ENODEV;
962
963 if (!rx_pause)
964 clear_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap);
965 else
966 set_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap);
967
968 if (!tx_pause)
969 clear_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap);
970 else
971 set_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap);
972
973 /* check if other pfvfs are using flow control */
974 if (!rx_pause && bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max)) {
975 dev_warn(&cgx->pdev->dev,
976 "Receive Flow control disable not permitted as its used by other PFVFs\n");
977 return -EPERM;
978 }
979
980 if (!tx_pause && bitmap_weight(lmac->tx_fc_pfvf_bmap.bmap, lmac->tx_fc_pfvf_bmap.max)) {
981 dev_warn(&cgx->pdev->dev,
982 "Transmit Flow control disable not permitted as its used by other PFVFs\n");
983 return -EPERM;
984 }
985
986 return 0;
987 }
988
cgx_lmac_pfc_config(void * cgxd,int lmac_id,u8 tx_pause,u8 rx_pause,u16 pfc_en)989 int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause,
990 u8 rx_pause, u16 pfc_en)
991 {
992 struct cgx *cgx = cgxd;
993 u64 cfg;
994
995 if (!is_lmac_valid(cgx, lmac_id))
996 return -ENODEV;
997
998 /* Return as no traffic classes are requested */
999 if (tx_pause && !pfc_en)
1000 return 0;
1001
1002 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
1003 pfc_en |= FIELD_GET(CGX_PFC_CLASS_MASK, cfg);
1004
1005 if (rx_pause) {
1006 cfg |= (CGXX_SMUX_CBFC_CTL_RX_EN |
1007 CGXX_SMUX_CBFC_CTL_BCK_EN |
1008 CGXX_SMUX_CBFC_CTL_DRP_EN);
1009 } else {
1010 cfg &= ~(CGXX_SMUX_CBFC_CTL_RX_EN |
1011 CGXX_SMUX_CBFC_CTL_BCK_EN |
1012 CGXX_SMUX_CBFC_CTL_DRP_EN);
1013 }
1014
1015 if (tx_pause) {
1016 cfg |= CGXX_SMUX_CBFC_CTL_TX_EN;
1017 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, pfc_en, cfg);
1018 } else {
1019 cfg &= ~CGXX_SMUX_CBFC_CTL_TX_EN;
1020 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg);
1021 }
1022
1023 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg);
1024
1025 /* Write source MAC address which will be filled into PFC packet */
1026 cfg = cgx_lmac_addr_get(cgx->cgx_id, lmac_id);
1027 cgx_write(cgx, lmac_id, CGXX_SMUX_SMAC, cfg);
1028
1029 return 0;
1030 }
1031
cgx_lmac_get_pfc_frm_cfg(void * cgxd,int lmac_id,u8 * tx_pause,u8 * rx_pause)1032 int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause,
1033 u8 *rx_pause)
1034 {
1035 struct cgx *cgx = cgxd;
1036 u64 cfg;
1037
1038 if (!is_lmac_valid(cgx, lmac_id))
1039 return -ENODEV;
1040
1041 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL);
1042
1043 *rx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_RX_EN);
1044 *tx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_TX_EN);
1045
1046 return 0;
1047 }
1048
cgx_lmac_ptp_config(void * cgxd,int lmac_id,bool enable)1049 void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable)
1050 {
1051 struct cgx *cgx = cgxd;
1052 u64 cfg;
1053
1054 if (!cgx)
1055 return;
1056
1057 if (enable) {
1058 /* Enable inbound PTP timestamping */
1059 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
1060 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE;
1061 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
1062
1063 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
1064 cfg |= CGX_SMUX_RX_FRM_CTL_PTP_MODE;
1065 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
1066 } else {
1067 /* Disable inbound PTP stamping */
1068 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
1069 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE;
1070 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);
1071
1072 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);
1073 cfg &= ~CGX_SMUX_RX_FRM_CTL_PTP_MODE;
1074 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg);
1075 }
1076 }
1077
1078 /* CGX Firmware interface low level support */
cgx_fwi_cmd_send(u64 req,u64 * resp,struct lmac * lmac)1079 int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac)
1080 {
1081 struct cgx *cgx = lmac->cgx;
1082 struct device *dev;
1083 int err = 0;
1084 u64 cmd;
1085
1086 /* Ensure no other command is in progress */
1087 err = mutex_lock_interruptible(&lmac->cmd_lock);
1088 if (err)
1089 return err;
1090
1091 /* Ensure command register is free */
1092 cmd = cgx_read(cgx, lmac->lmac_id, CGX_COMMAND_REG);
1093 if (FIELD_GET(CMDREG_OWN, cmd) != CGX_CMD_OWN_NS) {
1094 err = -EBUSY;
1095 goto unlock;
1096 }
1097
1098 /* Update ownership in command request */
1099 req = FIELD_SET(CMDREG_OWN, CGX_CMD_OWN_FIRMWARE, req);
1100
1101 /* Mark this lmac as pending, before we start */
1102 lmac->cmd_pend = true;
1103
1104 /* Start command in hardware */
1105 cgx_write(cgx, lmac->lmac_id, CGX_COMMAND_REG, req);
1106
1107 /* Ensure command is completed without errors */
1108 if (!wait_event_timeout(lmac->wq_cmd_cmplt, !lmac->cmd_pend,
1109 msecs_to_jiffies(CGX_CMD_TIMEOUT))) {
1110 dev = &cgx->pdev->dev;
1111 dev_err(dev, "cgx port %d:%d cmd %lld timeout\n",
1112 cgx->cgx_id, lmac->lmac_id, FIELD_GET(CMDREG_ID, req));
1113 err = LMAC_AF_ERR_CMD_TIMEOUT;
1114 goto unlock;
1115 }
1116
1117 /* we have a valid command response */
1118 smp_rmb(); /* Ensure the latest updates are visible */
1119 *resp = lmac->resp;
1120
1121 unlock:
1122 mutex_unlock(&lmac->cmd_lock);
1123
1124 return err;
1125 }
1126
cgx_fwi_cmd_generic(u64 req,u64 * resp,struct cgx * cgx,int lmac_id)1127 int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id)
1128 {
1129 struct lmac *lmac;
1130 int err;
1131
1132 lmac = lmac_pdata(lmac_id, cgx);
1133 if (!lmac)
1134 return -ENODEV;
1135
1136 err = cgx_fwi_cmd_send(req, resp, lmac);
1137
1138 /* Check for valid response */
1139 if (!err) {
1140 if (FIELD_GET(EVTREG_STAT, *resp) == CGX_STAT_FAIL)
1141 return -EIO;
1142 else
1143 return 0;
1144 }
1145
1146 return err;
1147 }
1148
cgx_link_usertable_index_map(int speed)1149 static int cgx_link_usertable_index_map(int speed)
1150 {
1151 switch (speed) {
1152 case SPEED_10:
1153 return CGX_LINK_10M;
1154 case SPEED_100:
1155 return CGX_LINK_100M;
1156 case SPEED_1000:
1157 return CGX_LINK_1G;
1158 case SPEED_2500:
1159 return CGX_LINK_2HG;
1160 case SPEED_5000:
1161 return CGX_LINK_5G;
1162 case SPEED_10000:
1163 return CGX_LINK_10G;
1164 case SPEED_20000:
1165 return CGX_LINK_20G;
1166 case SPEED_25000:
1167 return CGX_LINK_25G;
1168 case SPEED_40000:
1169 return CGX_LINK_40G;
1170 case SPEED_50000:
1171 return CGX_LINK_50G;
1172 case 80000:
1173 return CGX_LINK_80G;
1174 case SPEED_100000:
1175 return CGX_LINK_100G;
1176 case SPEED_UNKNOWN:
1177 return CGX_LINK_NONE;
1178 }
1179 return CGX_LINK_NONE;
1180 }
1181
set_mod_args(struct cgx_set_link_mode_args * args,u32 speed,u8 duplex,u8 autoneg,u64 mode)1182 static void set_mod_args(struct cgx_set_link_mode_args *args,
1183 u32 speed, u8 duplex, u8 autoneg, u64 mode)
1184 {
1185 /* Fill default values incase of user did not pass
1186 * valid parameters
1187 */
1188 if (args->duplex == DUPLEX_UNKNOWN)
1189 args->duplex = duplex;
1190 if (args->speed == SPEED_UNKNOWN)
1191 args->speed = speed;
1192 if (args->an == AUTONEG_UNKNOWN)
1193 args->an = autoneg;
1194 args->mode = mode;
1195 args->ports = 0;
1196 }
1197
otx2_map_ethtool_link_modes(u64 bitmask,struct cgx_set_link_mode_args * args)1198 static void otx2_map_ethtool_link_modes(u64 bitmask,
1199 struct cgx_set_link_mode_args *args)
1200 {
1201 switch (bitmask) {
1202 case ETHTOOL_LINK_MODE_10baseT_Half_BIT:
1203 set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII));
1204 break;
1205 case ETHTOOL_LINK_MODE_10baseT_Full_BIT:
1206 set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII));
1207 break;
1208 case ETHTOOL_LINK_MODE_100baseT_Half_BIT:
1209 set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII));
1210 break;
1211 case ETHTOOL_LINK_MODE_100baseT_Full_BIT:
1212 set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII));
1213 break;
1214 case ETHTOOL_LINK_MODE_1000baseT_Half_BIT:
1215 set_mod_args(args, 1000, 1, 1, BIT_ULL(CGX_MODE_SGMII));
1216 break;
1217 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT:
1218 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_SGMII));
1219 break;
1220 case ETHTOOL_LINK_MODE_1000baseX_Full_BIT:
1221 set_mod_args(args, 1000, 0, 0, BIT_ULL(CGX_MODE_1000_BASEX));
1222 break;
1223 case ETHTOOL_LINK_MODE_10000baseT_Full_BIT:
1224 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_QSGMII));
1225 break;
1226 case ETHTOOL_LINK_MODE_10000baseSR_Full_BIT:
1227 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2C));
1228 break;
1229 case ETHTOOL_LINK_MODE_10000baseLR_Full_BIT:
1230 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2M));
1231 break;
1232 case ETHTOOL_LINK_MODE_10000baseKR_Full_BIT:
1233 set_mod_args(args, 10000, 0, 1, BIT_ULL(CGX_MODE_10G_KR));
1234 break;
1235 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
1236 set_mod_args(args, 25000, 0, 0, BIT_ULL(CGX_MODE_25G_C2C));
1237 break;
1238 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
1239 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_CR));
1240 break;
1241 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
1242 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_KR));
1243 break;
1244 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
1245 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2C));
1246 break;
1247 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
1248 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2M));
1249 break;
1250 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
1251 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_CR4));
1252 break;
1253 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
1254 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_KR4));
1255 break;
1256 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
1257 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2C));
1258 break;
1259 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
1260 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2M));
1261 break;
1262 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
1263 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_CR));
1264 break;
1265 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
1266 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_KR));
1267 break;
1268 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
1269 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2C));
1270 break;
1271 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
1272 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2M));
1273 break;
1274 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
1275 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_CR4));
1276 break;
1277 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
1278 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_KR4));
1279 break;
1280 default:
1281 set_mod_args(args, 0, 1, 0, BIT_ULL(CGX_MODE_MAX));
1282 break;
1283 }
1284 }
1285
link_status_user_format(u64 lstat,struct cgx_link_user_info * linfo,struct cgx * cgx,u8 lmac_id)1286 static inline void link_status_user_format(u64 lstat,
1287 struct cgx_link_user_info *linfo,
1288 struct cgx *cgx, u8 lmac_id)
1289 {
1290 linfo->link_up = FIELD_GET(RESP_LINKSTAT_UP, lstat);
1291 linfo->full_duplex = FIELD_GET(RESP_LINKSTAT_FDUPLEX, lstat);
1292 linfo->speed = cgx_speed_mbps[FIELD_GET(RESP_LINKSTAT_SPEED, lstat)];
1293 linfo->an = FIELD_GET(RESP_LINKSTAT_AN, lstat);
1294 linfo->fec = FIELD_GET(RESP_LINKSTAT_FEC, lstat);
1295 linfo->lmac_type_id = FIELD_GET(RESP_LINKSTAT_LMAC_TYPE, lstat);
1296
1297 if (linfo->lmac_type_id >= LMAC_MODE_MAX) {
1298 dev_err(&cgx->pdev->dev, "Unknown lmac_type_id %d reported by firmware on cgx port%d:%d",
1299 linfo->lmac_type_id, cgx->cgx_id, lmac_id);
1300 strscpy(linfo->lmac_type, "Unknown", sizeof(linfo->lmac_type));
1301 return;
1302 }
1303
1304 strscpy(linfo->lmac_type, cgx_lmactype_string[linfo->lmac_type_id],
1305 sizeof(linfo->lmac_type));
1306 }
1307
1308 /* Hardware event handlers */
cgx_link_change_handler(u64 lstat,struct lmac * lmac)1309 static inline void cgx_link_change_handler(u64 lstat,
1310 struct lmac *lmac)
1311 {
1312 struct cgx_link_user_info *linfo;
1313 struct cgx *cgx = lmac->cgx;
1314 struct cgx_link_event event;
1315 struct device *dev;
1316 int err_type;
1317
1318 dev = &cgx->pdev->dev;
1319
1320 link_status_user_format(lstat, &event.link_uinfo, cgx, lmac->lmac_id);
1321 err_type = FIELD_GET(RESP_LINKSTAT_ERRTYPE, lstat);
1322
1323 event.cgx_id = cgx->cgx_id;
1324 event.lmac_id = lmac->lmac_id;
1325
1326 /* update the local copy of link status */
1327 lmac->link_info = event.link_uinfo;
1328 linfo = &lmac->link_info;
1329
1330 if (err_type == CGX_ERR_SPEED_CHANGE_INVALID)
1331 return;
1332
1333 /* Ensure callback doesn't get unregistered until we finish it */
1334 spin_lock(&lmac->event_cb_lock);
1335
1336 if (!lmac->event_cb.notify_link_chg) {
1337 dev_dbg(dev, "cgx port %d:%d Link change handler null",
1338 cgx->cgx_id, lmac->lmac_id);
1339 if (err_type != CGX_ERR_NONE) {
1340 dev_err(dev, "cgx port %d:%d Link error %d\n",
1341 cgx->cgx_id, lmac->lmac_id, err_type);
1342 }
1343 dev_info(dev, "cgx port %d:%d Link is %s %d Mbps\n",
1344 cgx->cgx_id, lmac->lmac_id,
1345 linfo->link_up ? "UP" : "DOWN", linfo->speed);
1346 goto err;
1347 }
1348
1349 if (lmac->event_cb.notify_link_chg(&event, lmac->event_cb.data))
1350 dev_err(dev, "event notification failure\n");
1351 err:
1352 spin_unlock(&lmac->event_cb_lock);
1353 }
1354
cgx_cmdresp_is_linkevent(u64 event)1355 static inline bool cgx_cmdresp_is_linkevent(u64 event)
1356 {
1357 u8 id;
1358
1359 id = FIELD_GET(EVTREG_ID, event);
1360 if (id == CGX_CMD_LINK_BRING_UP ||
1361 id == CGX_CMD_LINK_BRING_DOWN ||
1362 id == CGX_CMD_MODE_CHANGE)
1363 return true;
1364 else
1365 return false;
1366 }
1367
cgx_event_is_linkevent(u64 event)1368 static inline bool cgx_event_is_linkevent(u64 event)
1369 {
1370 if (FIELD_GET(EVTREG_ID, event) == CGX_EVT_LINK_CHANGE)
1371 return true;
1372 else
1373 return false;
1374 }
1375
cgx_fwi_event_handler(int irq,void * data)1376 static irqreturn_t cgx_fwi_event_handler(int irq, void *data)
1377 {
1378 u64 event, offset, clear_bit;
1379 struct lmac *lmac = data;
1380 struct cgx *cgx;
1381
1382 cgx = lmac->cgx;
1383
1384 /* Clear SW_INT for RPM and CMR_INT for CGX */
1385 offset = cgx->mac_ops->int_register;
1386 clear_bit = cgx->mac_ops->int_ena_bit;
1387
1388 event = cgx_read(cgx, lmac->lmac_id, CGX_EVENT_REG);
1389
1390 if (!FIELD_GET(EVTREG_ACK, event))
1391 return IRQ_NONE;
1392
1393 switch (FIELD_GET(EVTREG_EVT_TYPE, event)) {
1394 case CGX_EVT_CMD_RESP:
1395 /* Copy the response. Since only one command is active at a
1396 * time, there is no way a response can get overwritten
1397 */
1398 lmac->resp = event;
1399 /* Ensure response is updated before thread context starts */
1400 smp_wmb();
1401
1402 /* There wont be separate events for link change initiated from
1403 * software; Hence report the command responses as events
1404 */
1405 if (cgx_cmdresp_is_linkevent(event))
1406 cgx_link_change_handler(event, lmac);
1407
1408 /* Release thread waiting for completion */
1409 lmac->cmd_pend = false;
1410 wake_up(&lmac->wq_cmd_cmplt);
1411 break;
1412 case CGX_EVT_ASYNC:
1413 if (cgx_event_is_linkevent(event))
1414 cgx_link_change_handler(event, lmac);
1415 break;
1416 }
1417
1418 /* Any new event or command response will be posted by firmware
1419 * only after the current status is acked.
1420 * Ack the interrupt register as well.
1421 */
1422 cgx_write(lmac->cgx, lmac->lmac_id, CGX_EVENT_REG, 0);
1423 cgx_write(lmac->cgx, lmac->lmac_id, offset, clear_bit);
1424
1425 return IRQ_HANDLED;
1426 }
1427
1428 /* APIs for PHY management using CGX firmware interface */
1429
1430 /* callback registration for hardware events like link change */
cgx_lmac_evh_register(struct cgx_event_cb * cb,void * cgxd,int lmac_id)1431 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id)
1432 {
1433 struct cgx *cgx = cgxd;
1434 struct lmac *lmac;
1435
1436 lmac = lmac_pdata(lmac_id, cgx);
1437 if (!lmac)
1438 return -ENODEV;
1439
1440 lmac->event_cb = *cb;
1441
1442 return 0;
1443 }
1444
cgx_lmac_evh_unregister(void * cgxd,int lmac_id)1445 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id)
1446 {
1447 struct lmac *lmac;
1448 unsigned long flags;
1449 struct cgx *cgx = cgxd;
1450
1451 lmac = lmac_pdata(lmac_id, cgx);
1452 if (!lmac)
1453 return -ENODEV;
1454
1455 spin_lock_irqsave(&lmac->event_cb_lock, flags);
1456 lmac->event_cb.notify_link_chg = NULL;
1457 lmac->event_cb.data = NULL;
1458 spin_unlock_irqrestore(&lmac->event_cb_lock, flags);
1459
1460 return 0;
1461 }
1462
cgx_get_fwdata_base(u64 * base)1463 int cgx_get_fwdata_base(u64 *base)
1464 {
1465 u64 req = 0, resp;
1466 struct cgx *cgx;
1467 int first_lmac;
1468 int err;
1469
1470 cgx = list_first_entry_or_null(&cgx_list, struct cgx, cgx_list);
1471 if (!cgx)
1472 return -ENXIO;
1473
1474 first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac);
1475 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FWD_BASE, req);
1476 err = cgx_fwi_cmd_generic(req, &resp, cgx, first_lmac);
1477 if (!err)
1478 *base = FIELD_GET(RESP_FWD_BASE, resp);
1479
1480 return err;
1481 }
1482
cgx_set_link_mode(void * cgxd,struct cgx_set_link_mode_args args,int cgx_id,int lmac_id)1483 int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,
1484 int cgx_id, int lmac_id)
1485 {
1486 struct cgx *cgx = cgxd;
1487 u64 req = 0, resp;
1488
1489 if (!cgx)
1490 return -ENODEV;
1491
1492 if (args.mode)
1493 otx2_map_ethtool_link_modes(args.mode, &args);
1494 if (!args.speed && args.duplex && !args.an)
1495 return -EINVAL;
1496
1497 req = FIELD_SET(CMDREG_ID, CGX_CMD_MODE_CHANGE, req);
1498 req = FIELD_SET(CMDMODECHANGE_SPEED,
1499 cgx_link_usertable_index_map(args.speed), req);
1500 req = FIELD_SET(CMDMODECHANGE_DUPLEX, args.duplex, req);
1501 req = FIELD_SET(CMDMODECHANGE_AN, args.an, req);
1502 req = FIELD_SET(CMDMODECHANGE_PORT, args.ports, req);
1503 req = FIELD_SET(CMDMODECHANGE_FLAGS, args.mode, req);
1504
1505 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1506 }
cgx_set_fec(u64 fec,int cgx_id,int lmac_id)1507 int cgx_set_fec(u64 fec, int cgx_id, int lmac_id)
1508 {
1509 u64 req = 0, resp;
1510 struct cgx *cgx;
1511 int err = 0;
1512
1513 cgx = cgx_get_pdata(cgx_id);
1514 if (!cgx)
1515 return -ENXIO;
1516
1517 req = FIELD_SET(CMDREG_ID, CGX_CMD_SET_FEC, req);
1518 req = FIELD_SET(CMDSETFEC, fec, req);
1519 err = cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1520 if (err)
1521 return err;
1522
1523 cgx->lmac_idmap[lmac_id]->link_info.fec =
1524 FIELD_GET(RESP_LINKSTAT_FEC, resp);
1525 return cgx->lmac_idmap[lmac_id]->link_info.fec;
1526 }
1527
cgx_get_phy_fec_stats(void * cgxd,int lmac_id)1528 int cgx_get_phy_fec_stats(void *cgxd, int lmac_id)
1529 {
1530 struct cgx *cgx = cgxd;
1531 u64 req = 0, resp;
1532
1533 if (!cgx)
1534 return -ENODEV;
1535
1536 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_PHY_FEC_STATS, req);
1537 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1538 }
1539
cgx_fwi_link_change(struct cgx * cgx,int lmac_id,bool enable)1540 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool enable)
1541 {
1542 u64 req = 0;
1543 u64 resp;
1544
1545 if (enable) {
1546 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_UP, req);
1547 /* On CN10K firmware offloads link bring up/down operations to ECP
1548 * On Octeontx2 link operations are handled by firmware itself
1549 * which can cause mbox errors so configure maximum time firmware
1550 * poll for Link as 1000 ms
1551 */
1552 if (!is_dev_rpm(cgx))
1553 req = FIELD_SET(LINKCFG_TIMEOUT, 1000, req);
1554
1555 } else {
1556 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_DOWN, req);
1557 }
1558 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
1559 }
1560
cgx_fwi_read_version(u64 * resp,struct cgx * cgx)1561 static inline int cgx_fwi_read_version(u64 *resp, struct cgx *cgx)
1562 {
1563 int first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac);
1564 u64 req = 0;
1565
1566 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FW_VER, req);
1567 return cgx_fwi_cmd_generic(req, resp, cgx, first_lmac);
1568 }
1569
cgx_lmac_verify_fwi_version(struct cgx * cgx)1570 static int cgx_lmac_verify_fwi_version(struct cgx *cgx)
1571 {
1572 struct device *dev = &cgx->pdev->dev;
1573 int major_ver, minor_ver;
1574 u64 resp;
1575 int err;
1576
1577 if (!cgx->lmac_count)
1578 return 0;
1579
1580 err = cgx_fwi_read_version(&resp, cgx);
1581 if (err)
1582 return err;
1583
1584 major_ver = FIELD_GET(RESP_MAJOR_VER, resp);
1585 minor_ver = FIELD_GET(RESP_MINOR_VER, resp);
1586 dev_dbg(dev, "Firmware command interface version = %d.%d\n",
1587 major_ver, minor_ver);
1588 if (major_ver != CGX_FIRMWARE_MAJOR_VER)
1589 return -EIO;
1590 else
1591 return 0;
1592 }
1593
cgx_lmac_linkup_work(struct work_struct * work)1594 static void cgx_lmac_linkup_work(struct work_struct *work)
1595 {
1596 struct cgx *cgx = container_of(work, struct cgx, cgx_cmd_work);
1597 struct device *dev = &cgx->pdev->dev;
1598 int i, err;
1599
1600 /* Do Link up for all the enabled lmacs */
1601 for_each_set_bit(i, &cgx->lmac_bmap, cgx->max_lmac_per_mac) {
1602 err = cgx_fwi_link_change(cgx, i, true);
1603 if (err)
1604 dev_info(dev, "cgx port %d:%d Link up command failed\n",
1605 cgx->cgx_id, i);
1606 }
1607 }
1608
cgx_lmac_linkup_start(void * cgxd)1609 int cgx_lmac_linkup_start(void *cgxd)
1610 {
1611 struct cgx *cgx = cgxd;
1612
1613 if (!cgx)
1614 return -ENODEV;
1615
1616 queue_work(cgx->cgx_cmd_workq, &cgx->cgx_cmd_work);
1617
1618 return 0;
1619 }
1620
cgx_lmac_reset(void * cgxd,int lmac_id,u8 pf_req_flr)1621 int cgx_lmac_reset(void *cgxd, int lmac_id, u8 pf_req_flr)
1622 {
1623 struct cgx *cgx = cgxd;
1624 u64 cfg;
1625
1626 if (!is_lmac_valid(cgx, lmac_id))
1627 return -ENODEV;
1628
1629 /* Resetting PFC related CSRs */
1630 cfg = 0xff;
1631 cgx_write(cgxd, lmac_id, CGXX_CMRX_RX_LOGL_XON, cfg);
1632
1633 if (pf_req_flr)
1634 cgx_lmac_internal_loopback(cgxd, lmac_id, false);
1635 return 0;
1636 }
1637
cgx_configure_interrupt(struct cgx * cgx,struct lmac * lmac,int cnt,bool req_free)1638 static int cgx_configure_interrupt(struct cgx *cgx, struct lmac *lmac,
1639 int cnt, bool req_free)
1640 {
1641 struct mac_ops *mac_ops = cgx->mac_ops;
1642 u64 offset, ena_bit;
1643 unsigned int irq;
1644 int err;
1645
1646 irq = pci_irq_vector(cgx->pdev, mac_ops->lmac_fwi +
1647 cnt * mac_ops->irq_offset);
1648 offset = mac_ops->int_set_reg;
1649 ena_bit = mac_ops->int_ena_bit;
1650
1651 if (req_free) {
1652 free_irq(irq, lmac);
1653 return 0;
1654 }
1655
1656 err = request_irq(irq, cgx_fwi_event_handler, 0, lmac->name, lmac);
1657 if (err)
1658 return err;
1659
1660 /* Enable interrupt */
1661 cgx_write(cgx, lmac->lmac_id, offset, ena_bit);
1662 return 0;
1663 }
1664
cgx_get_nr_lmacs(void * cgxd)1665 int cgx_get_nr_lmacs(void *cgxd)
1666 {
1667 struct cgx *cgx = cgxd;
1668
1669 return cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7ULL;
1670 }
1671
cgx_get_lmacid(void * cgxd,u8 lmac_index)1672 u8 cgx_get_lmacid(void *cgxd, u8 lmac_index)
1673 {
1674 struct cgx *cgx = cgxd;
1675
1676 return cgx->lmac_idmap[lmac_index]->lmac_id;
1677 }
1678
cgx_get_lmac_bmap(void * cgxd)1679 unsigned long cgx_get_lmac_bmap(void *cgxd)
1680 {
1681 struct cgx *cgx = cgxd;
1682
1683 return cgx->lmac_bmap;
1684 }
1685
cgx_lmac_init(struct cgx * cgx)1686 static int cgx_lmac_init(struct cgx *cgx)
1687 {
1688 struct lmac *lmac;
1689 u64 lmac_list;
1690 int i, err;
1691
1692 /* lmac_list specifies which lmacs are enabled
1693 * when bit n is set to 1, LMAC[n] is enabled
1694 */
1695 if (cgx->mac_ops->non_contiguous_serdes_lane) {
1696 if (is_dev_rpm2(cgx))
1697 lmac_list =
1698 cgx_read(cgx, 0, RPM2_CMRX_RX_LMACS) & 0xFFULL;
1699 else
1700 lmac_list =
1701 cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0xFULL;
1702 }
1703
1704 if (cgx->lmac_count > cgx->max_lmac_per_mac)
1705 cgx->lmac_count = cgx->max_lmac_per_mac;
1706
1707 for (i = 0; i < cgx->lmac_count; i++) {
1708 lmac = kzalloc(sizeof(struct lmac), GFP_KERNEL);
1709 if (!lmac)
1710 return -ENOMEM;
1711 lmac->name = kcalloc(1, sizeof("cgx_fwi_xxx_yyy"), GFP_KERNEL);
1712 if (!lmac->name) {
1713 err = -ENOMEM;
1714 goto err_lmac_free;
1715 }
1716 sprintf(lmac->name, "cgx_fwi_%d_%d", cgx->cgx_id, i);
1717 if (cgx->mac_ops->non_contiguous_serdes_lane) {
1718 lmac->lmac_id = __ffs64(lmac_list);
1719 lmac_list &= ~BIT_ULL(lmac->lmac_id);
1720 } else {
1721 lmac->lmac_id = i;
1722 }
1723
1724 lmac->cgx = cgx;
1725 lmac->mac_to_index_bmap.max =
1726 cgx->mac_ops->dmac_filter_count /
1727 cgx->lmac_count;
1728
1729 err = rvu_alloc_bitmap(&lmac->mac_to_index_bmap);
1730 if (err)
1731 goto err_name_free;
1732
1733 /* Reserve first entry for default MAC address */
1734 set_bit(0, lmac->mac_to_index_bmap.bmap);
1735
1736 lmac->rx_fc_pfvf_bmap.max = 128;
1737 err = rvu_alloc_bitmap(&lmac->rx_fc_pfvf_bmap);
1738 if (err)
1739 goto err_dmac_bmap_free;
1740
1741 lmac->tx_fc_pfvf_bmap.max = 128;
1742 err = rvu_alloc_bitmap(&lmac->tx_fc_pfvf_bmap);
1743 if (err)
1744 goto err_rx_fc_bmap_free;
1745
1746 init_waitqueue_head(&lmac->wq_cmd_cmplt);
1747 mutex_init(&lmac->cmd_lock);
1748 spin_lock_init(&lmac->event_cb_lock);
1749 err = cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, false);
1750 if (err)
1751 goto err_bitmap_free;
1752
1753 /* Add reference */
1754 cgx->lmac_idmap[lmac->lmac_id] = lmac;
1755 set_bit(lmac->lmac_id, &cgx->lmac_bmap);
1756 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, true);
1757 lmac->lmac_type = cgx->mac_ops->get_lmac_type(cgx, lmac->lmac_id);
1758 }
1759
1760 /* Start X2P reset on given MAC block */
1761 cgx->mac_ops->mac_x2p_reset(cgx, true);
1762 return cgx_lmac_verify_fwi_version(cgx);
1763
1764 err_bitmap_free:
1765 rvu_free_bitmap(&lmac->tx_fc_pfvf_bmap);
1766 err_rx_fc_bmap_free:
1767 rvu_free_bitmap(&lmac->rx_fc_pfvf_bmap);
1768 err_dmac_bmap_free:
1769 rvu_free_bitmap(&lmac->mac_to_index_bmap);
1770 err_name_free:
1771 kfree(lmac->name);
1772 err_lmac_free:
1773 kfree(lmac);
1774 return err;
1775 }
1776
cgx_lmac_exit(struct cgx * cgx)1777 static int cgx_lmac_exit(struct cgx *cgx)
1778 {
1779 struct lmac *lmac;
1780 int i;
1781
1782 if (cgx->cgx_cmd_workq) {
1783 destroy_workqueue(cgx->cgx_cmd_workq);
1784 cgx->cgx_cmd_workq = NULL;
1785 }
1786
1787 /* Free all lmac related resources */
1788 for_each_set_bit(i, &cgx->lmac_bmap, cgx->max_lmac_per_mac) {
1789 lmac = cgx->lmac_idmap[i];
1790 if (!lmac)
1791 continue;
1792 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, false);
1793 cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, true);
1794 kfree(lmac->mac_to_index_bmap.bmap);
1795 kfree(lmac->name);
1796 kfree(lmac);
1797 }
1798
1799 return 0;
1800 }
1801
cgx_populate_features(struct cgx * cgx)1802 static void cgx_populate_features(struct cgx *cgx)
1803 {
1804 u64 cfg;
1805
1806 cfg = cgx_read(cgx, 0, CGX_CONST);
1807 cgx->fifo_len = FIELD_GET(CGX_CONST_RXFIFO_SIZE, cfg);
1808 cgx->max_lmac_per_mac = FIELD_GET(CGX_CONST_MAX_LMACS, cfg);
1809
1810 if (is_dev_rpm(cgx))
1811 cgx->hw_features = (RVU_LMAC_FEAT_DMACF | RVU_MAC_RPM |
1812 RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_PTP);
1813 else
1814 cgx->hw_features = (RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_HIGIG2 |
1815 RVU_LMAC_FEAT_PTP | RVU_LMAC_FEAT_DMACF);
1816 }
1817
cgx_get_rxid_mapoffset(struct cgx * cgx)1818 static u8 cgx_get_rxid_mapoffset(struct cgx *cgx)
1819 {
1820 if (cgx->pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10KB_RPM ||
1821 is_dev_rpm2(cgx))
1822 return 0x80;
1823 else
1824 return 0x60;
1825 }
1826
cgx_x2p_reset(void * cgxd,bool enable)1827 static void cgx_x2p_reset(void *cgxd, bool enable)
1828 {
1829 struct cgx *cgx = cgxd;
1830 int lmac_id;
1831 u64 cfg;
1832
1833 if (enable) {
1834 for_each_set_bit(lmac_id, &cgx->lmac_bmap, cgx->max_lmac_per_mac)
1835 cgx->mac_ops->mac_enadis_rx(cgx, lmac_id, false);
1836
1837 usleep_range(1000, 2000);
1838
1839 cfg = cgx_read(cgx, 0, CGXX_CMR_GLOBAL_CONFIG);
1840 cfg |= cgx_get_nix_resetbit(cgx) | CGX_NSCI_DROP;
1841 cgx_write(cgx, 0, CGXX_CMR_GLOBAL_CONFIG, cfg);
1842 } else {
1843 cfg = cgx_read(cgx, 0, CGXX_CMR_GLOBAL_CONFIG);
1844 cfg &= ~(cgx_get_nix_resetbit(cgx) | CGX_NSCI_DROP);
1845 cgx_write(cgx, 0, CGXX_CMR_GLOBAL_CONFIG, cfg);
1846 }
1847 }
1848
cgx_enadis_rx(void * cgxd,int lmac_id,bool enable)1849 static int cgx_enadis_rx(void *cgxd, int lmac_id, bool enable)
1850 {
1851 struct cgx *cgx = cgxd;
1852 u64 cfg;
1853
1854 if (!is_lmac_valid(cgx, lmac_id))
1855 return -ENODEV;
1856
1857 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
1858 if (enable)
1859 cfg |= DATA_PKT_RX_EN;
1860 else
1861 cfg &= ~DATA_PKT_RX_EN;
1862 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
1863 return 0;
1864 }
1865
1866 static struct mac_ops cgx_mac_ops = {
1867 .name = "cgx",
1868 .csr_offset = 0,
1869 .lmac_offset = 18,
1870 .int_register = CGXX_CMRX_INT,
1871 .int_set_reg = CGXX_CMRX_INT_ENA_W1S,
1872 .irq_offset = 9,
1873 .int_ena_bit = FW_CGX_INT,
1874 .lmac_fwi = CGX_LMAC_FWI,
1875 .non_contiguous_serdes_lane = false,
1876 .rx_stats_cnt = 9,
1877 .tx_stats_cnt = 18,
1878 .dmac_filter_count = 32,
1879 .get_nr_lmacs = cgx_get_nr_lmacs,
1880 .get_lmac_type = cgx_get_lmac_type,
1881 .lmac_fifo_len = cgx_get_lmac_fifo_len,
1882 .mac_lmac_intl_lbk = cgx_lmac_internal_loopback,
1883 .mac_get_rx_stats = cgx_get_rx_stats,
1884 .mac_get_tx_stats = cgx_get_tx_stats,
1885 .get_fec_stats = cgx_get_fec_stats,
1886 .mac_enadis_rx_pause_fwding = cgx_lmac_enadis_rx_pause_fwding,
1887 .mac_get_pause_frm_status = cgx_lmac_get_pause_frm_status,
1888 .mac_enadis_pause_frm = cgx_lmac_enadis_pause_frm,
1889 .mac_pause_frm_config = cgx_lmac_pause_frm_config,
1890 .mac_enadis_ptp_config = cgx_lmac_ptp_config,
1891 .mac_rx_tx_enable = cgx_lmac_rx_tx_enable,
1892 .mac_tx_enable = cgx_lmac_tx_enable,
1893 .pfc_config = cgx_lmac_pfc_config,
1894 .mac_get_pfc_frm_cfg = cgx_lmac_get_pfc_frm_cfg,
1895 .mac_reset = cgx_lmac_reset,
1896 .mac_stats_reset = cgx_stats_reset,
1897 .mac_x2p_reset = cgx_x2p_reset,
1898 .mac_enadis_rx = cgx_enadis_rx,
1899 };
1900
cgx_probe(struct pci_dev * pdev,const struct pci_device_id * id)1901 static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1902 {
1903 struct device *dev = &pdev->dev;
1904 struct cgx *cgx;
1905 int err, nvec;
1906
1907 cgx = devm_kzalloc(dev, sizeof(*cgx), GFP_KERNEL);
1908 if (!cgx)
1909 return -ENOMEM;
1910 cgx->pdev = pdev;
1911
1912 pci_set_drvdata(pdev, cgx);
1913
1914 /* Use mac_ops to get MAC specific features */
1915 if (is_dev_rpm(cgx))
1916 cgx->mac_ops = rpm_get_mac_ops(cgx);
1917 else
1918 cgx->mac_ops = &cgx_mac_ops;
1919
1920 cgx->mac_ops->rxid_map_offset = cgx_get_rxid_mapoffset(cgx);
1921
1922 err = pci_enable_device(pdev);
1923 if (err) {
1924 dev_err(dev, "Failed to enable PCI device\n");
1925 pci_set_drvdata(pdev, NULL);
1926 return err;
1927 }
1928
1929 err = pci_request_regions(pdev, DRV_NAME);
1930 if (err) {
1931 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1932 goto err_disable_device;
1933 }
1934
1935 /* MAP configuration registers */
1936 cgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1937 if (!cgx->reg_base) {
1938 dev_err(dev, "CGX: Cannot map CSR memory space, aborting\n");
1939 err = -ENOMEM;
1940 goto err_release_regions;
1941 }
1942
1943 cgx->lmac_count = cgx->mac_ops->get_nr_lmacs(cgx);
1944 if (!cgx->lmac_count) {
1945 dev_notice(dev, "CGX %d LMAC count is zero, skipping probe\n", cgx->cgx_id);
1946 err = -EOPNOTSUPP;
1947 goto err_release_regions;
1948 }
1949
1950 nvec = pci_msix_vec_count(cgx->pdev);
1951 err = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX);
1952 if (err < 0 || err != nvec) {
1953 dev_err(dev, "Request for %d msix vectors failed, err %d\n",
1954 nvec, err);
1955 goto err_release_regions;
1956 }
1957
1958 cgx->cgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24)
1959 & CGX_ID_MASK;
1960
1961 /* init wq for processing linkup requests */
1962 INIT_WORK(&cgx->cgx_cmd_work, cgx_lmac_linkup_work);
1963 cgx->cgx_cmd_workq = alloc_workqueue("cgx_cmd_workq", 0, 0);
1964 if (!cgx->cgx_cmd_workq) {
1965 dev_err(dev, "alloc workqueue failed for cgx cmd");
1966 err = -ENOMEM;
1967 goto err_free_irq_vectors;
1968 }
1969
1970 list_add(&cgx->cgx_list, &cgx_list);
1971
1972
1973 cgx_populate_features(cgx);
1974
1975 mutex_init(&cgx->lock);
1976
1977 err = cgx_lmac_init(cgx);
1978 if (err)
1979 goto err_release_lmac;
1980
1981 return 0;
1982
1983 err_release_lmac:
1984 cgx_lmac_exit(cgx);
1985 list_del(&cgx->cgx_list);
1986 err_free_irq_vectors:
1987 pci_free_irq_vectors(pdev);
1988 err_release_regions:
1989 pci_release_regions(pdev);
1990 err_disable_device:
1991 pci_disable_device(pdev);
1992 pci_set_drvdata(pdev, NULL);
1993 return err;
1994 }
1995
cgx_remove(struct pci_dev * pdev)1996 static void cgx_remove(struct pci_dev *pdev)
1997 {
1998 struct cgx *cgx = pci_get_drvdata(pdev);
1999
2000 if (cgx) {
2001 cgx_lmac_exit(cgx);
2002 list_del(&cgx->cgx_list);
2003 }
2004 pci_free_irq_vectors(pdev);
2005 pci_release_regions(pdev);
2006 pci_disable_device(pdev);
2007 pci_set_drvdata(pdev, NULL);
2008 }
2009
2010 struct pci_driver cgx_driver = {
2011 .name = DRV_NAME,
2012 .id_table = cgx_id_table,
2013 .probe = cgx_probe,
2014 .remove = cgx_remove,
2015 };
2016