1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Cedrus VPU driver
4 *
5 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
6 * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>
7 * Copyright (C) 2018 Bootlin
8 *
9 * Based on the vim2m driver, that is:
10 *
11 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
12 * Pawel Osciak, <pawel@osciak.com>
13 * Marek Szyprowski, <m.szyprowski@samsung.com>
14 */
15
16 #include <linux/platform_device.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/pm.h>
20
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-ioctl.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-mem2mem.h>
25
26 #include "cedrus.h"
27 #include "cedrus_video.h"
28 #include "cedrus_dec.h"
29 #include "cedrus_hw.h"
30
31 static const struct cedrus_control cedrus_controls[] = {
32 {
33 .cfg = {
34 .id = V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS,
35 },
36 .codec = CEDRUS_CODEC_MPEG2,
37 .required = true,
38 },
39 {
40 .cfg = {
41 .id = V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION,
42 },
43 .codec = CEDRUS_CODEC_MPEG2,
44 .required = false,
45 },
46 {
47 .cfg = {
48 .id = V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS,
49 },
50 .codec = CEDRUS_CODEC_H264,
51 .required = true,
52 },
53 {
54 .cfg = {
55 .id = V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS,
56 },
57 .codec = CEDRUS_CODEC_H264,
58 .required = true,
59 },
60 {
61 .cfg = {
62 .id = V4L2_CID_MPEG_VIDEO_H264_SPS,
63 },
64 .codec = CEDRUS_CODEC_H264,
65 .required = true,
66 },
67 {
68 .cfg = {
69 .id = V4L2_CID_MPEG_VIDEO_H264_PPS,
70 },
71 .codec = CEDRUS_CODEC_H264,
72 .required = true,
73 },
74 {
75 .cfg = {
76 .id = V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX,
77 },
78 .codec = CEDRUS_CODEC_H264,
79 .required = false,
80 },
81 {
82 .cfg = {
83 .id = V4L2_CID_MPEG_VIDEO_H264_PRED_WEIGHTS,
84 },
85 .codec = CEDRUS_CODEC_H264,
86 .required = false,
87 },
88 {
89 .cfg = {
90 .id = V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE,
91 .max = V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED,
92 .def = V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED,
93 },
94 .codec = CEDRUS_CODEC_H264,
95 .required = false,
96 },
97 {
98 .cfg = {
99 .id = V4L2_CID_MPEG_VIDEO_H264_START_CODE,
100 .max = V4L2_MPEG_VIDEO_H264_START_CODE_NONE,
101 .def = V4L2_MPEG_VIDEO_H264_START_CODE_NONE,
102 },
103 .codec = CEDRUS_CODEC_H264,
104 .required = false,
105 },
106 {
107 .cfg = {
108 .id = V4L2_CID_MPEG_VIDEO_HEVC_SPS,
109 },
110 .codec = CEDRUS_CODEC_H265,
111 .required = true,
112 },
113 {
114 .cfg = {
115 .id = V4L2_CID_MPEG_VIDEO_HEVC_PPS,
116 },
117 .codec = CEDRUS_CODEC_H265,
118 .required = true,
119 },
120 {
121 .cfg = {
122 .id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS,
123 },
124 .codec = CEDRUS_CODEC_H265,
125 .required = true,
126 },
127 {
128 .cfg = {
129 .id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE,
130 .max = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED,
131 .def = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED,
132 },
133 .codec = CEDRUS_CODEC_H265,
134 .required = false,
135 },
136 {
137 .cfg = {
138 .id = V4L2_CID_MPEG_VIDEO_HEVC_START_CODE,
139 .max = V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE,
140 .def = V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE,
141 },
142 .codec = CEDRUS_CODEC_H265,
143 .required = false,
144 },
145 };
146
147 #define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls)
148
cedrus_find_control_data(struct cedrus_ctx * ctx,u32 id)149 void *cedrus_find_control_data(struct cedrus_ctx *ctx, u32 id)
150 {
151 unsigned int i;
152
153 for (i = 0; ctx->ctrls[i]; i++)
154 if (ctx->ctrls[i]->id == id)
155 return ctx->ctrls[i]->p_cur.p;
156
157 return NULL;
158 }
159
cedrus_init_ctrls(struct cedrus_dev * dev,struct cedrus_ctx * ctx)160 static int cedrus_init_ctrls(struct cedrus_dev *dev, struct cedrus_ctx *ctx)
161 {
162 struct v4l2_ctrl_handler *hdl = &ctx->hdl;
163 struct v4l2_ctrl *ctrl;
164 unsigned int ctrl_size;
165 unsigned int i;
166
167 v4l2_ctrl_handler_init(hdl, CEDRUS_CONTROLS_COUNT);
168 if (hdl->error) {
169 v4l2_err(&dev->v4l2_dev,
170 "Failed to initialize control handler\n");
171 return hdl->error;
172 }
173
174 ctrl_size = sizeof(ctrl) * CEDRUS_CONTROLS_COUNT + 1;
175
176 ctx->ctrls = kzalloc(ctrl_size, GFP_KERNEL);
177 if (!ctx->ctrls)
178 return -ENOMEM;
179
180 for (i = 0; i < CEDRUS_CONTROLS_COUNT; i++) {
181 ctrl = v4l2_ctrl_new_custom(hdl, &cedrus_controls[i].cfg,
182 NULL);
183 if (hdl->error) {
184 v4l2_err(&dev->v4l2_dev,
185 "Failed to create new custom control\n");
186
187 v4l2_ctrl_handler_free(hdl);
188 kfree(ctx->ctrls);
189 return hdl->error;
190 }
191
192 ctx->ctrls[i] = ctrl;
193 }
194
195 ctx->fh.ctrl_handler = hdl;
196 v4l2_ctrl_handler_setup(hdl);
197
198 return 0;
199 }
200
cedrus_request_validate(struct media_request * req)201 static int cedrus_request_validate(struct media_request *req)
202 {
203 struct media_request_object *obj;
204 struct v4l2_ctrl_handler *parent_hdl, *hdl;
205 struct cedrus_ctx *ctx = NULL;
206 struct v4l2_ctrl *ctrl_test;
207 unsigned int count;
208 unsigned int i;
209 int ret = 0;
210
211 list_for_each_entry(obj, &req->objects, list) {
212 struct vb2_buffer *vb;
213
214 if (vb2_request_object_is_buffer(obj)) {
215 vb = container_of(obj, struct vb2_buffer, req_obj);
216 ctx = vb2_get_drv_priv(vb->vb2_queue);
217
218 break;
219 }
220 }
221
222 if (!ctx)
223 return -ENOENT;
224
225 count = vb2_request_buffer_cnt(req);
226 if (!count) {
227 v4l2_info(&ctx->dev->v4l2_dev,
228 "No buffer was provided with the request\n");
229 return -ENOENT;
230 } else if (count > 1) {
231 v4l2_info(&ctx->dev->v4l2_dev,
232 "More than one buffer was provided with the request\n");
233 return -EINVAL;
234 }
235
236 parent_hdl = &ctx->hdl;
237
238 hdl = v4l2_ctrl_request_hdl_find(req, parent_hdl);
239 if (!hdl) {
240 v4l2_info(&ctx->dev->v4l2_dev, "Missing codec control(s)\n");
241 return -ENOENT;
242 }
243
244 for (i = 0; i < CEDRUS_CONTROLS_COUNT; i++) {
245 if (cedrus_controls[i].codec != ctx->current_codec ||
246 !cedrus_controls[i].required)
247 continue;
248
249 ctrl_test = v4l2_ctrl_request_hdl_ctrl_find(hdl,
250 cedrus_controls[i].cfg.id);
251 if (!ctrl_test) {
252 v4l2_info(&ctx->dev->v4l2_dev,
253 "Missing required codec control\n");
254 ret = -ENOENT;
255 break;
256 }
257 }
258
259 v4l2_ctrl_request_hdl_put(hdl);
260
261 if (ret)
262 return ret;
263
264 return vb2_request_validate(req);
265 }
266
cedrus_open(struct file * file)267 static int cedrus_open(struct file *file)
268 {
269 struct cedrus_dev *dev = video_drvdata(file);
270 struct cedrus_ctx *ctx = NULL;
271 int ret;
272
273 if (mutex_lock_interruptible(&dev->dev_mutex))
274 return -ERESTARTSYS;
275
276 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
277 if (!ctx) {
278 mutex_unlock(&dev->dev_mutex);
279 return -ENOMEM;
280 }
281
282 v4l2_fh_init(&ctx->fh, video_devdata(file));
283 file->private_data = &ctx->fh;
284 ctx->dev = dev;
285
286 ret = cedrus_init_ctrls(dev, ctx);
287 if (ret)
288 goto err_free;
289
290 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx,
291 &cedrus_queue_init);
292 if (IS_ERR(ctx->fh.m2m_ctx)) {
293 ret = PTR_ERR(ctx->fh.m2m_ctx);
294 goto err_ctrls;
295 }
296 ctx->dst_fmt.pixelformat = V4L2_PIX_FMT_SUNXI_TILED_NV12;
297 cedrus_prepare_format(&ctx->dst_fmt);
298 ctx->src_fmt.pixelformat = V4L2_PIX_FMT_MPEG2_SLICE;
299 /*
300 * TILED_NV12 has more strict requirements, so copy the width and
301 * height to src_fmt to ensure that is matches the dst_fmt resolution.
302 */
303 ctx->src_fmt.width = ctx->dst_fmt.width;
304 ctx->src_fmt.height = ctx->dst_fmt.height;
305 cedrus_prepare_format(&ctx->src_fmt);
306
307 v4l2_fh_add(&ctx->fh);
308
309 mutex_unlock(&dev->dev_mutex);
310
311 return 0;
312
313 err_ctrls:
314 v4l2_ctrl_handler_free(&ctx->hdl);
315 err_free:
316 kfree(ctx);
317 mutex_unlock(&dev->dev_mutex);
318
319 return ret;
320 }
321
cedrus_release(struct file * file)322 static int cedrus_release(struct file *file)
323 {
324 struct cedrus_dev *dev = video_drvdata(file);
325 struct cedrus_ctx *ctx = container_of(file->private_data,
326 struct cedrus_ctx, fh);
327
328 mutex_lock(&dev->dev_mutex);
329
330 v4l2_fh_del(&ctx->fh);
331 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
332
333 v4l2_ctrl_handler_free(&ctx->hdl);
334 kfree(ctx->ctrls);
335
336 v4l2_fh_exit(&ctx->fh);
337
338 kfree(ctx);
339
340 mutex_unlock(&dev->dev_mutex);
341
342 return 0;
343 }
344
345 static const struct v4l2_file_operations cedrus_fops = {
346 .owner = THIS_MODULE,
347 .open = cedrus_open,
348 .release = cedrus_release,
349 .poll = v4l2_m2m_fop_poll,
350 .unlocked_ioctl = video_ioctl2,
351 .mmap = v4l2_m2m_fop_mmap,
352 };
353
354 static const struct video_device cedrus_video_device = {
355 .name = CEDRUS_NAME,
356 .vfl_dir = VFL_DIR_M2M,
357 .fops = &cedrus_fops,
358 .ioctl_ops = &cedrus_ioctl_ops,
359 .minor = -1,
360 .release = video_device_release_empty,
361 .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
362 };
363
364 static const struct v4l2_m2m_ops cedrus_m2m_ops = {
365 .device_run = cedrus_device_run,
366 };
367
368 static const struct media_device_ops cedrus_m2m_media_ops = {
369 .req_validate = cedrus_request_validate,
370 .req_queue = v4l2_m2m_request_queue,
371 };
372
cedrus_probe(struct platform_device * pdev)373 static int cedrus_probe(struct platform_device *pdev)
374 {
375 struct cedrus_dev *dev;
376 struct video_device *vfd;
377 int ret;
378
379 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
380 if (!dev)
381 return -ENOMEM;
382
383 dev->vfd = cedrus_video_device;
384 dev->dev = &pdev->dev;
385 dev->pdev = pdev;
386
387 ret = cedrus_hw_probe(dev);
388 if (ret) {
389 dev_err(&pdev->dev, "Failed to probe hardware\n");
390 return ret;
391 }
392
393 dev->dec_ops[CEDRUS_CODEC_MPEG2] = &cedrus_dec_ops_mpeg2;
394 dev->dec_ops[CEDRUS_CODEC_H264] = &cedrus_dec_ops_h264;
395 dev->dec_ops[CEDRUS_CODEC_H265] = &cedrus_dec_ops_h265;
396
397 mutex_init(&dev->dev_mutex);
398
399 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
400 if (ret) {
401 dev_err(&pdev->dev, "Failed to register V4L2 device\n");
402 return ret;
403 }
404
405 vfd = &dev->vfd;
406 vfd->lock = &dev->dev_mutex;
407 vfd->v4l2_dev = &dev->v4l2_dev;
408
409 snprintf(vfd->name, sizeof(vfd->name), "%s", cedrus_video_device.name);
410 video_set_drvdata(vfd, dev);
411
412 dev->m2m_dev = v4l2_m2m_init(&cedrus_m2m_ops);
413 if (IS_ERR(dev->m2m_dev)) {
414 v4l2_err(&dev->v4l2_dev,
415 "Failed to initialize V4L2 M2M device\n");
416 ret = PTR_ERR(dev->m2m_dev);
417
418 goto err_v4l2;
419 }
420
421 dev->mdev.dev = &pdev->dev;
422 strscpy(dev->mdev.model, CEDRUS_NAME, sizeof(dev->mdev.model));
423 strscpy(dev->mdev.bus_info, "platform:" CEDRUS_NAME,
424 sizeof(dev->mdev.bus_info));
425
426 media_device_init(&dev->mdev);
427 dev->mdev.ops = &cedrus_m2m_media_ops;
428 dev->v4l2_dev.mdev = &dev->mdev;
429
430 ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
431 if (ret) {
432 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
433 goto err_m2m;
434 }
435
436 v4l2_info(&dev->v4l2_dev,
437 "Device registered as /dev/video%d\n", vfd->num);
438
439 ret = v4l2_m2m_register_media_controller(dev->m2m_dev, vfd,
440 MEDIA_ENT_F_PROC_VIDEO_DECODER);
441 if (ret) {
442 v4l2_err(&dev->v4l2_dev,
443 "Failed to initialize V4L2 M2M media controller\n");
444 goto err_video;
445 }
446
447 ret = media_device_register(&dev->mdev);
448 if (ret) {
449 v4l2_err(&dev->v4l2_dev, "Failed to register media device\n");
450 goto err_m2m_mc;
451 }
452
453 platform_set_drvdata(pdev, dev);
454
455 return 0;
456
457 err_m2m_mc:
458 v4l2_m2m_unregister_media_controller(dev->m2m_dev);
459 err_video:
460 video_unregister_device(&dev->vfd);
461 err_m2m:
462 v4l2_m2m_release(dev->m2m_dev);
463 err_v4l2:
464 v4l2_device_unregister(&dev->v4l2_dev);
465
466 return ret;
467 }
468
cedrus_remove(struct platform_device * pdev)469 static int cedrus_remove(struct platform_device *pdev)
470 {
471 struct cedrus_dev *dev = platform_get_drvdata(pdev);
472
473 if (media_devnode_is_registered(dev->mdev.devnode)) {
474 media_device_unregister(&dev->mdev);
475 v4l2_m2m_unregister_media_controller(dev->m2m_dev);
476 media_device_cleanup(&dev->mdev);
477 }
478
479 v4l2_m2m_release(dev->m2m_dev);
480 video_unregister_device(&dev->vfd);
481 v4l2_device_unregister(&dev->v4l2_dev);
482
483 cedrus_hw_remove(dev);
484
485 return 0;
486 }
487
488 static const struct cedrus_variant sun4i_a10_cedrus_variant = {
489 .mod_rate = 320000000,
490 };
491
492 static const struct cedrus_variant sun5i_a13_cedrus_variant = {
493 .mod_rate = 320000000,
494 };
495
496 static const struct cedrus_variant sun7i_a20_cedrus_variant = {
497 .mod_rate = 320000000,
498 };
499
500 static const struct cedrus_variant sun8i_a33_cedrus_variant = {
501 .capabilities = CEDRUS_CAPABILITY_UNTILED,
502 .mod_rate = 320000000,
503 };
504
505 static const struct cedrus_variant sun8i_h3_cedrus_variant = {
506 .capabilities = CEDRUS_CAPABILITY_UNTILED |
507 CEDRUS_CAPABILITY_H265_DEC,
508 .mod_rate = 402000000,
509 };
510
511 static const struct cedrus_variant sun50i_a64_cedrus_variant = {
512 .capabilities = CEDRUS_CAPABILITY_UNTILED |
513 CEDRUS_CAPABILITY_H265_DEC,
514 .mod_rate = 402000000,
515 };
516
517 static const struct cedrus_variant sun50i_h5_cedrus_variant = {
518 .capabilities = CEDRUS_CAPABILITY_UNTILED |
519 CEDRUS_CAPABILITY_H265_DEC,
520 .mod_rate = 402000000,
521 };
522
523 static const struct cedrus_variant sun50i_h6_cedrus_variant = {
524 .capabilities = CEDRUS_CAPABILITY_UNTILED |
525 CEDRUS_CAPABILITY_H265_DEC,
526 .quirks = CEDRUS_QUIRK_NO_DMA_OFFSET,
527 .mod_rate = 600000000,
528 };
529
530 static const struct of_device_id cedrus_dt_match[] = {
531 {
532 .compatible = "allwinner,sun4i-a10-video-engine",
533 .data = &sun4i_a10_cedrus_variant,
534 },
535 {
536 .compatible = "allwinner,sun5i-a13-video-engine",
537 .data = &sun5i_a13_cedrus_variant,
538 },
539 {
540 .compatible = "allwinner,sun7i-a20-video-engine",
541 .data = &sun7i_a20_cedrus_variant,
542 },
543 {
544 .compatible = "allwinner,sun8i-a33-video-engine",
545 .data = &sun8i_a33_cedrus_variant,
546 },
547 {
548 .compatible = "allwinner,sun8i-h3-video-engine",
549 .data = &sun8i_h3_cedrus_variant,
550 },
551 {
552 .compatible = "allwinner,sun50i-a64-video-engine",
553 .data = &sun50i_a64_cedrus_variant,
554 },
555 {
556 .compatible = "allwinner,sun50i-h5-video-engine",
557 .data = &sun50i_h5_cedrus_variant,
558 },
559 {
560 .compatible = "allwinner,sun50i-h6-video-engine",
561 .data = &sun50i_h6_cedrus_variant,
562 },
563 { /* sentinel */ }
564 };
565 MODULE_DEVICE_TABLE(of, cedrus_dt_match);
566
567 static const struct dev_pm_ops cedrus_dev_pm_ops = {
568 SET_RUNTIME_PM_OPS(cedrus_hw_suspend,
569 cedrus_hw_resume, NULL)
570 };
571
572 static struct platform_driver cedrus_driver = {
573 .probe = cedrus_probe,
574 .remove = cedrus_remove,
575 .driver = {
576 .name = CEDRUS_NAME,
577 .of_match_table = of_match_ptr(cedrus_dt_match),
578 .pm = &cedrus_dev_pm_ops,
579 },
580 };
581 module_platform_driver(cedrus_driver);
582
583 MODULE_LICENSE("GPL v2");
584 MODULE_AUTHOR("Florent Revest <florent.revest@free-electrons.com>");
585 MODULE_AUTHOR("Paul Kocialkowski <paul.kocialkowski@bootlin.com>");
586 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@bootlin.com>");
587 MODULE_DESCRIPTION("Cedrus VPU driver");
588