1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020 Intel Corporation. All rights reserved. */
3 #ifndef __CXL_PCI_H__
4 #define __CXL_PCI_H__
5 #include <linux/pci.h>
6 #include "cxl.h"
7
8 #define CXL_MEMORY_PROGIF 0x10
9
10 /*
11 * NOTE: Currently all the functions which are enabled for CXL require their
12 * vectors to be in the first 16. Use this as the default max.
13 */
14 #define CXL_PCI_DEFAULT_MAX_VECTORS 16
15
16 /* Register Block Identifier (RBI) */
17 enum cxl_regloc_type {
18 CXL_REGLOC_RBI_EMPTY = 0,
19 CXL_REGLOC_RBI_COMPONENT,
20 CXL_REGLOC_RBI_VIRT,
21 CXL_REGLOC_RBI_MEMDEV,
22 CXL_REGLOC_RBI_PMU,
23 CXL_REGLOC_RBI_TYPES
24 };
25
26 /*
27 * Table Access DOE, CDAT Read Entry Response
28 *
29 * Spec refs:
30 *
31 * CXL 3.1 8.1.11, Table 8-14: Read Entry Response
32 * CDAT Specification 1.03: 2 CDAT Data Structures
33 */
34
35 struct cdat_header {
36 __le32 length;
37 u8 revision;
38 u8 checksum;
39 u8 reserved[6];
40 __le32 sequence;
41 } __packed;
42
43 struct cdat_entry_header {
44 u8 type;
45 u8 reserved;
46 __le16 length;
47 } __packed;
48
49 /*
50 * The DOE CDAT read response contains a CDAT read entry (either the
51 * CDAT header or a structure).
52 */
53 union cdat_data {
54 struct cdat_header header;
55 struct cdat_entry_header entry;
56 } __packed;
57
58 /* There is an additional CDAT response header of 4 bytes. */
59 struct cdat_doe_rsp {
60 __le32 doe_header;
61 u8 data[];
62 } __packed;
63
64 /*
65 * CXL v3.0 6.2.3 Table 6-4
66 * The table indicates that if PCIe Flit Mode is set, then CXL is in 256B flits
67 * mode, otherwise it's 68B flits mode.
68 */
cxl_pci_flit_256(struct pci_dev * pdev)69 static inline bool cxl_pci_flit_256(struct pci_dev *pdev)
70 {
71 u16 lnksta2;
72
73 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA2, &lnksta2);
74 return lnksta2 & PCI_EXP_LNKSTA2_FLIT;
75 }
76
77 struct cxl_dev_state;
78 void read_cdat_data(struct cxl_port *port);
79
80 #ifdef CONFIG_CXL_RAS
81 void cxl_cor_error_detected(struct pci_dev *pdev);
82 pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
83 pci_channel_state_t state);
84 void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport);
85 void devm_cxl_port_ras_setup(struct cxl_port *port);
86 #else
cxl_cor_error_detected(struct pci_dev * pdev)87 static inline void cxl_cor_error_detected(struct pci_dev *pdev) { }
88
cxl_error_detected(struct pci_dev * pdev,pci_channel_state_t state)89 static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
90 pci_channel_state_t state)
91 {
92 return PCI_ERS_RESULT_NONE;
93 }
94
devm_cxl_dport_rch_ras_setup(struct cxl_dport * dport)95 static inline void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport)
96 {
97 }
98
devm_cxl_port_ras_setup(struct cxl_port * port)99 static inline void devm_cxl_port_ras_setup(struct cxl_port *port)
100 {
101 }
102 #endif
103
104 #endif /* __CXL_PCI_H__ */
105