1 /*
2 * QEMU PowerPC pSeries Logical Partition capabilities handling
3 *
4 * Copyright (c) 2017 David Gibson, Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/error-report.h"
27 #include "qapi/error.h"
28 #include "qapi/visitor.h"
29 #include "system/hw_accel.h"
30 #include "system/ram_addr.h"
31 #include "target/ppc/cpu.h"
32 #include "target/ppc/mmu-hash64.h"
33 #include "cpu-models.h"
34 #include "kvm_ppc.h"
35 #include "migration/vmstate.h"
36 #include "system/tcg.h"
37 #include "system/hostmem.h"
38
39 #include "hw/ppc/spapr.h"
40
41 typedef struct SpaprCapPossible {
42 int num; /* size of vals array below */
43 const char *help; /* help text for vals */
44 /*
45 * Note:
46 * - because of the way compatibility is determined vals MUST be ordered
47 * such that later options are a superset of all preceding options.
48 * - the order of vals must be preserved, that is their index is important,
49 * however vals may be added to the end of the list so long as the above
50 * point is observed
51 */
52 const char *vals[];
53 } SpaprCapPossible;
54
55 typedef struct SpaprCapabilityInfo {
56 const char *name;
57 const char *description;
58 int index;
59
60 /* Getter and Setter Function Pointers */
61 ObjectPropertyAccessor *get;
62 ObjectPropertyAccessor *set;
63 const char *type;
64 /* Possible values if this is a custom string type */
65 SpaprCapPossible *possible;
66 /* Make sure the virtual hardware can support this capability */
67 void (*apply)(SpaprMachineState *spapr, uint8_t val, Error **errp);
68 void (*cpu_apply)(SpaprMachineState *spapr, PowerPCCPU *cpu,
69 uint8_t val, Error **errp);
70 bool (*migrate_needed)(void *opaque);
71 } SpaprCapabilityInfo;
72
spapr_cap_get_bool(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)73 static void spapr_cap_get_bool(Object *obj, Visitor *v, const char *name,
74 void *opaque, Error **errp)
75 {
76 SpaprCapabilityInfo *cap = opaque;
77 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
78 bool value = spapr_get_cap(spapr, cap->index) == SPAPR_CAP_ON;
79
80 visit_type_bool(v, name, &value, errp);
81 }
82
spapr_cap_set_bool(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)83 static void spapr_cap_set_bool(Object *obj, Visitor *v, const char *name,
84 void *opaque, Error **errp)
85 {
86 SpaprCapabilityInfo *cap = opaque;
87 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
88 bool value;
89
90 if (!visit_type_bool(v, name, &value, errp)) {
91 return;
92 }
93
94 spapr->cmd_line_caps[cap->index] = true;
95 spapr->eff.caps[cap->index] = value ? SPAPR_CAP_ON : SPAPR_CAP_OFF;
96 }
97
98
spapr_cap_get_string(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)99 static void spapr_cap_get_string(Object *obj, Visitor *v, const char *name,
100 void *opaque, Error **errp)
101 {
102 SpaprCapabilityInfo *cap = opaque;
103 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
104 g_autofree char *val = NULL;
105 uint8_t value = spapr_get_cap(spapr, cap->index);
106
107 if (value >= cap->possible->num) {
108 error_setg(errp, "Invalid value (%d) for cap-%s", value, cap->name);
109 return;
110 }
111
112 val = g_strdup(cap->possible->vals[value]);
113
114 visit_type_str(v, name, &val, errp);
115 }
116
spapr_cap_set_string(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)117 static void spapr_cap_set_string(Object *obj, Visitor *v, const char *name,
118 void *opaque, Error **errp)
119 {
120 SpaprCapabilityInfo *cap = opaque;
121 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
122 uint8_t i;
123 g_autofree char *val = NULL;
124
125 if (!visit_type_str(v, name, &val, errp)) {
126 return;
127 }
128
129 if (!strcmp(val, "?")) {
130 error_setg(errp, "%s", cap->possible->help);
131 return;
132 }
133 for (i = 0; i < cap->possible->num; i++) {
134 if (!strcasecmp(val, cap->possible->vals[i])) {
135 spapr->cmd_line_caps[cap->index] = true;
136 spapr->eff.caps[cap->index] = i;
137 return;
138 }
139 }
140
141 error_setg(errp, "Invalid capability mode \"%s\" for cap-%s", val,
142 cap->name);
143 }
144
spapr_cap_get_pagesize(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)145 static void spapr_cap_get_pagesize(Object *obj, Visitor *v, const char *name,
146 void *opaque, Error **errp)
147 {
148 SpaprCapabilityInfo *cap = opaque;
149 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
150 uint8_t val = spapr_get_cap(spapr, cap->index);
151 uint64_t pagesize = (1ULL << val);
152
153 visit_type_size(v, name, &pagesize, errp);
154 }
155
spapr_cap_set_pagesize(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)156 static void spapr_cap_set_pagesize(Object *obj, Visitor *v, const char *name,
157 void *opaque, Error **errp)
158 {
159 SpaprCapabilityInfo *cap = opaque;
160 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
161 uint64_t pagesize;
162 uint8_t val;
163
164 if (!visit_type_size(v, name, &pagesize, errp)) {
165 return;
166 }
167
168 if (!is_power_of_2(pagesize)) {
169 error_setg(errp, "cap-%s must be a power of 2", cap->name);
170 return;
171 }
172
173 val = ctz64(pagesize);
174 spapr->cmd_line_caps[cap->index] = true;
175 spapr->eff.caps[cap->index] = val;
176 }
177
cap_htm_apply(SpaprMachineState * spapr,uint8_t val,Error ** errp)178 static void cap_htm_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
179 {
180 ERRP_GUARD();
181 if (!val) {
182 /* TODO: We don't support disabling htm yet */
183 return;
184 }
185 if (tcg_enabled()) {
186 error_setg(errp, "No Transactional Memory support in TCG");
187 error_append_hint(errp, "Try appending -machine cap-htm=off\n");
188 } else if (kvm_enabled() && !kvmppc_has_cap_htm()) {
189 error_setg(errp,
190 "KVM implementation does not support Transactional Memory");
191 error_append_hint(errp, "Try appending -machine cap-htm=off\n");
192 }
193 }
194
cap_vsx_apply(SpaprMachineState * spapr,uint8_t val,Error ** errp)195 static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
196 {
197 ERRP_GUARD();
198 CPUPPCState *env = cpu_env(first_cpu);
199
200 if (!val) {
201 /* TODO: We don't support disabling vsx yet */
202 return;
203 }
204 /* Allowable CPUs in spapr_cpu_core.c should already have gotten
205 * rid of anything that doesn't do VMX */
206 g_assert(env->insns_flags & PPC_ALTIVEC);
207 if (!(env->insns_flags2 & PPC2_VSX)) {
208 error_setg(errp, "VSX support not available");
209 error_append_hint(errp, "Try appending -machine cap-vsx=off\n");
210 }
211 }
212
cap_dfp_apply(SpaprMachineState * spapr,uint8_t val,Error ** errp)213 static void cap_dfp_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
214 {
215 ERRP_GUARD();
216
217 if (!val) {
218 /* TODO: We don't support disabling dfp yet */
219 return;
220 }
221 if (!(cpu_env(first_cpu)->insns_flags2 & PPC2_DFP)) {
222 error_setg(errp, "DFP support not available");
223 error_append_hint(errp, "Try appending -machine cap-dfp=off\n");
224 }
225 }
226
227 SpaprCapPossible cap_cfpc_possible = {
228 .num = 3,
229 .vals = {"broken", "workaround", "fixed"},
230 .help = "broken - no protection, workaround - workaround available,"
231 " fixed - fixed in hardware",
232 };
233
cap_safe_cache_apply(SpaprMachineState * spapr,uint8_t val,Error ** errp)234 static void cap_safe_cache_apply(SpaprMachineState *spapr, uint8_t val,
235 Error **errp)
236 {
237 ERRP_GUARD();
238 uint8_t kvm_val = kvmppc_get_cap_safe_cache();
239
240 if (tcg_enabled() && val) {
241 /* TCG only supports broken, allow other values and print a warning */
242 warn_report("TCG doesn't support requested feature, cap-cfpc=%s",
243 cap_cfpc_possible.vals[val]);
244 } else if (kvm_enabled() && (val > kvm_val)) {
245 error_setg(errp,
246 "Requested safe cache capability level not supported by KVM");
247 error_append_hint(errp, "Try appending -machine cap-cfpc=%s\n",
248 cap_cfpc_possible.vals[kvm_val]);
249 }
250 }
251
252 SpaprCapPossible cap_sbbc_possible = {
253 .num = 3,
254 .vals = {"broken", "workaround", "fixed"},
255 .help = "broken - no protection, workaround - workaround available,"
256 " fixed - fixed in hardware",
257 };
258
cap_safe_bounds_check_apply(SpaprMachineState * spapr,uint8_t val,Error ** errp)259 static void cap_safe_bounds_check_apply(SpaprMachineState *spapr, uint8_t val,
260 Error **errp)
261 {
262 ERRP_GUARD();
263 uint8_t kvm_val = kvmppc_get_cap_safe_bounds_check();
264
265 if (tcg_enabled() && val) {
266 /* TCG only supports broken, allow other values and print a warning */
267 warn_report("TCG doesn't support requested feature, cap-sbbc=%s",
268 cap_sbbc_possible.vals[val]);
269 } else if (kvm_enabled() && (val > kvm_val)) {
270 error_setg(errp,
271 "Requested safe bounds check capability level not supported by KVM");
272 error_append_hint(errp, "Try appending -machine cap-sbbc=%s\n",
273 cap_sbbc_possible.vals[kvm_val]);
274 }
275 }
276
277 SpaprCapPossible cap_ibs_possible = {
278 .num = 5,
279 /* Note workaround only maintained for compatibility */
280 .vals = {"broken", "workaround", "fixed-ibs", "fixed-ccd", "fixed-na"},
281 .help = "broken - no protection, workaround - count cache flush"
282 ", fixed-ibs - indirect branch serialisation,"
283 " fixed-ccd - cache count disabled,"
284 " fixed-na - fixed in hardware (no longer applicable)",
285 };
286
cap_safe_indirect_branch_apply(SpaprMachineState * spapr,uint8_t val,Error ** errp)287 static void cap_safe_indirect_branch_apply(SpaprMachineState *spapr,
288 uint8_t val, Error **errp)
289 {
290 ERRP_GUARD();
291 uint8_t kvm_val = kvmppc_get_cap_safe_indirect_branch();
292
293 if (tcg_enabled() && val) {
294 /* TCG only supports broken, allow other values and print a warning */
295 warn_report("TCG doesn't support requested feature, cap-ibs=%s",
296 cap_ibs_possible.vals[val]);
297 } else if (kvm_enabled() && (val > kvm_val)) {
298 error_setg(errp,
299 "Requested safe indirect branch capability level not supported by KVM");
300 error_append_hint(errp, "Try appending -machine cap-ibs=%s\n",
301 cap_ibs_possible.vals[kvm_val]);
302 }
303 }
304
305 #define VALUE_DESC_TRISTATE " (broken, workaround, fixed)"
306
spapr_check_pagesize(SpaprMachineState * spapr,hwaddr pagesize,Error ** errp)307 bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize,
308 Error **errp)
309 {
310 hwaddr maxpagesize = (1ULL << spapr->eff.caps[SPAPR_CAP_HPT_MAXPAGESIZE]);
311
312 if (!kvmppc_hpt_needs_host_contiguous_pages()) {
313 return true;
314 }
315
316 if (maxpagesize > pagesize) {
317 error_setg(errp,
318 "Can't support %"HWADDR_PRIu" kiB guest pages with %"
319 HWADDR_PRIu" kiB host pages with this KVM implementation",
320 maxpagesize >> 10, pagesize >> 10);
321 return false;
322 }
323
324 return true;
325 }
326
cap_hpt_maxpagesize_apply(SpaprMachineState * spapr,uint8_t val,Error ** errp)327 static void cap_hpt_maxpagesize_apply(SpaprMachineState *spapr,
328 uint8_t val, Error **errp)
329 {
330 if (val < 12) {
331 error_setg(errp, "Require at least 4kiB hpt-max-page-size");
332 return;
333 } else if (val < 16) {
334 warn_report("Many guests require at least 64kiB hpt-max-page-size");
335 }
336
337 spapr_check_pagesize(spapr, qemu_minrampagesize(), errp);
338 }
339
cap_hpt_maxpagesize_migrate_needed(void * opaque)340 static bool cap_hpt_maxpagesize_migrate_needed(void *opaque)
341 {
342 return !SPAPR_MACHINE_GET_CLASS(opaque)->pre_4_1_migration;
343 }
344
spapr_pagesize_cb(void * opaque,uint32_t seg_pshift,uint32_t pshift)345 static bool spapr_pagesize_cb(void *opaque, uint32_t seg_pshift,
346 uint32_t pshift)
347 {
348 unsigned maxshift = *((unsigned *)opaque);
349
350 assert(pshift >= seg_pshift);
351
352 /* Don't allow the guest to use pages bigger than the configured
353 * maximum size */
354 if (pshift > maxshift) {
355 return false;
356 }
357
358 /* For whatever reason, KVM doesn't allow multiple pagesizes
359 * within a segment, *except* for the case of 16M pages in a 4k or
360 * 64k segment. Always exclude other cases, so that TCG and KVM
361 * guests see a consistent environment */
362 if ((pshift != seg_pshift) && (pshift != 24)) {
363 return false;
364 }
365
366 return true;
367 }
368
ppc_hash64_filter_pagesizes(PowerPCCPU * cpu,bool (* cb)(void *,uint32_t,uint32_t),void * opaque)369 static void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
370 bool (*cb)(void *, uint32_t, uint32_t),
371 void *opaque)
372 {
373 PPCHash64Options *opts = cpu->hash64_opts;
374 int i;
375 int n = 0;
376 bool ci_largepage = false;
377
378 assert(opts);
379
380 n = 0;
381 for (i = 0; i < ARRAY_SIZE(opts->sps); i++) {
382 PPCHash64SegmentPageSizes *sps = &opts->sps[i];
383 int j;
384 int m = 0;
385
386 assert(n <= i);
387
388 if (!sps->page_shift) {
389 break;
390 }
391
392 for (j = 0; j < ARRAY_SIZE(sps->enc); j++) {
393 PPCHash64PageSize *ps = &sps->enc[j];
394
395 assert(m <= j);
396 if (!ps->page_shift) {
397 break;
398 }
399
400 if (cb(opaque, sps->page_shift, ps->page_shift)) {
401 if (ps->page_shift >= 16) {
402 ci_largepage = true;
403 }
404 sps->enc[m++] = *ps;
405 }
406 }
407
408 /* Clear rest of the row */
409 for (j = m; j < ARRAY_SIZE(sps->enc); j++) {
410 memset(&sps->enc[j], 0, sizeof(sps->enc[j]));
411 }
412
413 if (m) {
414 n++;
415 }
416 }
417
418 /* Clear the rest of the table */
419 for (i = n; i < ARRAY_SIZE(opts->sps); i++) {
420 memset(&opts->sps[i], 0, sizeof(opts->sps[i]));
421 }
422
423 if (!ci_largepage) {
424 opts->flags &= ~PPC_HASH64_CI_LARGEPAGE;
425 }
426 }
427
cap_hpt_maxpagesize_cpu_apply(SpaprMachineState * spapr,PowerPCCPU * cpu,uint8_t val,Error ** errp)428 static void cap_hpt_maxpagesize_cpu_apply(SpaprMachineState *spapr,
429 PowerPCCPU *cpu,
430 uint8_t val, Error **errp)
431 {
432 unsigned maxshift = val;
433
434 ppc_hash64_filter_pagesizes(cpu, spapr_pagesize_cb, &maxshift);
435 }
436
cap_nested_kvm_hv_apply(SpaprMachineState * spapr,uint8_t val,Error ** errp)437 static void cap_nested_kvm_hv_apply(SpaprMachineState *spapr,
438 uint8_t val, Error **errp)
439 {
440 ERRP_GUARD();
441 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
442 CPUPPCState *env = &cpu->env;
443
444 if (!val) {
445 /* capability disabled by default */
446 return;
447 }
448
449 if (!(env->insns_flags2 & PPC2_ISA300)) {
450 error_setg(errp, "Nested-HV only supported on POWER9 and later");
451 error_append_hint(errp, "Try appending -machine cap-nested-hv=off\n");
452 return;
453 }
454
455 if (kvm_enabled()) {
456 if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0,
457 spapr->max_compat_pvr)) {
458 error_setg(errp, "Nested-HV only supported on POWER9 and later");
459 error_append_hint(errp,
460 "Try appending -machine max-cpu-compat=power9\n");
461 return;
462 }
463
464 if (!kvmppc_has_cap_nested_kvm_hv()) {
465 error_setg(errp,
466 "KVM implementation does not support Nested-HV");
467 error_append_hint(errp,
468 "Try appending -machine cap-nested-hv=off\n");
469 } else if (kvmppc_set_cap_nested_kvm_hv(val) < 0) {
470 error_setg(errp, "Error enabling cap-nested-hv with KVM");
471 error_append_hint(errp,
472 "Try appending -machine cap-nested-hv=off\n");
473 }
474 } else if (tcg_enabled()) {
475 MachineState *ms = MACHINE(spapr);
476 unsigned int smp_threads = ms->smp.threads;
477
478 /*
479 * Nested-HV vCPU env state to L2, so SMT-shared SPR updates, for
480 * example, do not necessarily update the correct SPR value on sibling
481 * threads that are in a different guest/host context.
482 */
483 if (smp_threads > 1) {
484 error_setg(errp, "TCG does not support nested-HV with SMT");
485 error_append_hint(errp, "Try appending -machine cap-nested-hv=off "
486 "or use threads=1 with -smp\n");
487 }
488 if (spapr_nested_api(spapr) &&
489 spapr_nested_api(spapr) != NESTED_API_KVM_HV) {
490 error_setg(errp, "Nested-HV APIs are mutually exclusive");
491 error_append_hint(errp, "Please use either cap-nested-hv or "
492 "cap-nested-papr to proceed.\n");
493 return;
494 } else {
495 spapr->nested.api = NESTED_API_KVM_HV;
496 }
497 }
498 }
499
cap_nested_papr_apply(SpaprMachineState * spapr,uint8_t val,Error ** errp)500 static void cap_nested_papr_apply(SpaprMachineState *spapr,
501 uint8_t val, Error **errp)
502 {
503 ERRP_GUARD();
504 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
505 CPUPPCState *env = &cpu->env;
506
507 if (!val) {
508 /* capability disabled by default */
509 return;
510 }
511
512 if (tcg_enabled()) {
513 if (!(env->insns_flags2 & PPC2_ISA300)) {
514 error_setg(errp, "Nested-PAPR only supported on POWER9 and later");
515 error_append_hint(errp,
516 "Try appending -machine cap-nested-papr=off\n");
517 return;
518 }
519 if (spapr_nested_api(spapr) &&
520 spapr_nested_api(spapr) != NESTED_API_PAPR) {
521 error_setg(errp, "Nested-HV APIs are mutually exclusive");
522 error_append_hint(errp, "Please use either cap-nested-hv or "
523 "cap-nested-papr to proceed.\n");
524 return;
525 } else {
526 spapr->nested.api = NESTED_API_PAPR;
527 }
528 } else if (kvm_enabled()) {
529 error_setg(errp, "KVM implementation does not support Nested-PAPR");
530 error_append_hint(errp,
531 "Try appending -machine cap-nested-papr=off\n");
532 }
533 }
534
cap_large_decr_apply(SpaprMachineState * spapr,uint8_t val,Error ** errp)535 static void cap_large_decr_apply(SpaprMachineState *spapr,
536 uint8_t val, Error **errp)
537 {
538 ERRP_GUARD();
539 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
540 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
541
542 if (!val) {
543 return; /* Disabled by default */
544 }
545
546 if (tcg_enabled()) {
547 if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0,
548 spapr->max_compat_pvr)) {
549 error_setg(errp, "Large decrementer only supported on POWER9");
550 error_append_hint(errp, "Try -cpu POWER9\n");
551 return;
552 }
553 } else if (kvm_enabled()) {
554 int kvm_nr_bits = kvmppc_get_cap_large_decr();
555
556 if (!kvm_nr_bits) {
557 error_setg(errp, "No large decrementer support");
558 error_append_hint(errp,
559 "Try appending -machine cap-large-decr=off\n");
560 } else if (pcc->lrg_decr_bits != kvm_nr_bits) {
561 error_setg(errp,
562 "KVM large decrementer size (%d) differs to model (%d)",
563 kvm_nr_bits, pcc->lrg_decr_bits);
564 error_append_hint(errp,
565 "Try appending -machine cap-large-decr=off\n");
566 }
567 }
568 }
569
cap_large_decr_cpu_apply(SpaprMachineState * spapr,PowerPCCPU * cpu,uint8_t val,Error ** errp)570 static void cap_large_decr_cpu_apply(SpaprMachineState *spapr,
571 PowerPCCPU *cpu,
572 uint8_t val, Error **errp)
573 {
574 ERRP_GUARD();
575 CPUPPCState *env = &cpu->env;
576 target_ulong lpcr = env->spr[SPR_LPCR];
577
578 if (kvm_enabled()) {
579 if (kvmppc_enable_cap_large_decr(cpu, val)) {
580 error_setg(errp, "No large decrementer support");
581 error_append_hint(errp,
582 "Try appending -machine cap-large-decr=off\n");
583 }
584 }
585
586 if (val) {
587 lpcr |= LPCR_LD;
588 } else {
589 lpcr &= ~LPCR_LD;
590 }
591 ppc_store_lpcr(cpu, lpcr);
592 }
593
cap_ccf_assist_apply(SpaprMachineState * spapr,uint8_t val,Error ** errp)594 static void cap_ccf_assist_apply(SpaprMachineState *spapr, uint8_t val,
595 Error **errp)
596 {
597 ERRP_GUARD();
598 uint8_t kvm_val = kvmppc_get_cap_count_cache_flush_assist();
599
600 if (tcg_enabled() && val) {
601 /* TCG doesn't implement anything here, but allow with a warning */
602 warn_report("TCG doesn't support requested feature, cap-ccf-assist=on");
603 } else if (kvm_enabled() && (val > kvm_val)) {
604 uint8_t kvm_ibs = kvmppc_get_cap_safe_indirect_branch();
605
606 if (kvm_ibs == SPAPR_CAP_FIXED_CCD) {
607 /*
608 * If we don't have CCF assist on the host, the assist
609 * instruction is a harmless no-op. It won't correctly
610 * implement the cache count flush *but* if we have
611 * count-cache-disabled in the host, that flush is
612 * unnecessary. So, specifically allow this case. This
613 * allows us to have better performance on POWER9 DD2.3,
614 * while still working on POWER9 DD2.2 and POWER8 host
615 * cpus.
616 */
617 return;
618 }
619 error_setg(errp,
620 "Requested count cache flush assist capability level not supported by KVM");
621 error_append_hint(errp, "Try appending -machine cap-ccf-assist=off\n");
622 }
623 }
624
cap_fwnmi_apply(SpaprMachineState * spapr,uint8_t val,Error ** errp)625 static void cap_fwnmi_apply(SpaprMachineState *spapr, uint8_t val,
626 Error **errp)
627 {
628 ERRP_GUARD();
629 if (!val) {
630 return; /* Disabled by default */
631 }
632
633 if (kvm_enabled()) {
634 if (!kvmppc_get_fwnmi()) {
635 error_setg(errp,
636 "Firmware Assisted Non-Maskable Interrupts(FWNMI) not supported by KVM.");
637 error_append_hint(errp, "Try appending -machine cap-fwnmi=off\n");
638 }
639 }
640 }
641
cap_rpt_invalidate_apply(SpaprMachineState * spapr,uint8_t val,Error ** errp)642 static void cap_rpt_invalidate_apply(SpaprMachineState *spapr,
643 uint8_t val, Error **errp)
644 {
645 ERRP_GUARD();
646
647 if (!val) {
648 /* capability disabled by default */
649 return;
650 }
651
652 if (tcg_enabled()) {
653 error_setg(errp, "No H_RPT_INVALIDATE support in TCG");
654 error_append_hint(errp,
655 "Try appending -machine cap-rpt-invalidate=off\n");
656 } else if (kvm_enabled()) {
657 if (!kvmppc_has_cap_mmu_radix()) {
658 error_setg(errp, "H_RPT_INVALIDATE only supported on Radix");
659 return;
660 }
661
662 if (!kvmppc_has_cap_rpt_invalidate()) {
663 error_setg(errp,
664 "KVM implementation does not support H_RPT_INVALIDATE");
665 error_append_hint(errp,
666 "Try appending -machine cap-rpt-invalidate=off\n");
667 } else {
668 kvmppc_enable_h_rpt_invalidate();
669 }
670 }
671 }
672
cap_ail_mode_3_apply(SpaprMachineState * spapr,uint8_t val,Error ** errp)673 static void cap_ail_mode_3_apply(SpaprMachineState *spapr,
674 uint8_t val, Error **errp)
675 {
676 ERRP_GUARD();
677 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
678 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
679
680 if (!val) {
681 return;
682 }
683
684 if (tcg_enabled()) {
685 /* AIL-3 is only supported on POWER8 and above CPUs. */
686 if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
687 error_setg(errp, "TCG only supports cap-ail-mode-3 on POWER8 and later CPUs");
688 error_append_hint(errp, "Try appending -machine cap-ail-mode-3=off\n");
689 return;
690 }
691 } else if (kvm_enabled()) {
692 if (!kvmppc_supports_ail_3()) {
693 error_setg(errp, "KVM implementation does not support cap-ail-mode-3");
694 error_append_hint(errp, "Try appending -machine cap-ail-mode-3=off\n");
695 return;
696 }
697 }
698 }
699
cap_dawr1_apply(SpaprMachineState * spapr,uint8_t val,Error ** errp)700 static void cap_dawr1_apply(SpaprMachineState *spapr, uint8_t val,
701 Error **errp)
702 {
703 ERRP_GUARD();
704
705 if (!val) {
706 return; /* Disable by default */
707 }
708
709 if (!ppc_type_check_compat(MACHINE(spapr)->cpu_type,
710 CPU_POWERPC_LOGICAL_3_10, 0,
711 spapr->max_compat_pvr)) {
712 error_setg(errp, "DAWR1 supported only on POWER10 and later CPUs");
713 error_append_hint(errp, "Try appending -machine cap-dawr1=off\n");
714 return;
715 }
716
717 if (kvm_enabled()) {
718 if (!kvmppc_has_cap_dawr1()) {
719 error_setg(errp, "DAWR1 not supported by KVM.");
720 error_append_hint(errp, "Try appending -machine cap-dawr1=off");
721 } else if (kvmppc_set_cap_dawr1(val) < 0) {
722 error_setg(errp, "Error enabling cap-dawr1 with KVM.");
723 error_append_hint(errp, "Try appending -machine cap-dawr1=off");
724 }
725 }
726 }
727
728 SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
729 [SPAPR_CAP_HTM] = {
730 .name = "htm",
731 .description = "Allow Hardware Transactional Memory (HTM)",
732 .index = SPAPR_CAP_HTM,
733 .get = spapr_cap_get_bool,
734 .set = spapr_cap_set_bool,
735 .type = "bool",
736 .apply = cap_htm_apply,
737 },
738 [SPAPR_CAP_VSX] = {
739 .name = "vsx",
740 .description = "Allow Vector Scalar Extensions (VSX)",
741 .index = SPAPR_CAP_VSX,
742 .get = spapr_cap_get_bool,
743 .set = spapr_cap_set_bool,
744 .type = "bool",
745 .apply = cap_vsx_apply,
746 },
747 [SPAPR_CAP_DFP] = {
748 .name = "dfp",
749 .description = "Allow Decimal Floating Point (DFP)",
750 .index = SPAPR_CAP_DFP,
751 .get = spapr_cap_get_bool,
752 .set = spapr_cap_set_bool,
753 .type = "bool",
754 .apply = cap_dfp_apply,
755 },
756 [SPAPR_CAP_CFPC] = {
757 .name = "cfpc",
758 .description = "Cache Flush on Privilege Change" VALUE_DESC_TRISTATE,
759 .index = SPAPR_CAP_CFPC,
760 .get = spapr_cap_get_string,
761 .set = spapr_cap_set_string,
762 .type = "string",
763 .possible = &cap_cfpc_possible,
764 .apply = cap_safe_cache_apply,
765 },
766 [SPAPR_CAP_SBBC] = {
767 .name = "sbbc",
768 .description = "Speculation Barrier Bounds Checking" VALUE_DESC_TRISTATE,
769 .index = SPAPR_CAP_SBBC,
770 .get = spapr_cap_get_string,
771 .set = spapr_cap_set_string,
772 .type = "string",
773 .possible = &cap_sbbc_possible,
774 .apply = cap_safe_bounds_check_apply,
775 },
776 [SPAPR_CAP_IBS] = {
777 .name = "ibs",
778 .description =
779 "Indirect Branch Speculation (broken, workaround, fixed-ibs,"
780 "fixed-ccd, fixed-na)",
781 .index = SPAPR_CAP_IBS,
782 .get = spapr_cap_get_string,
783 .set = spapr_cap_set_string,
784 .type = "string",
785 .possible = &cap_ibs_possible,
786 .apply = cap_safe_indirect_branch_apply,
787 },
788 [SPAPR_CAP_HPT_MAXPAGESIZE] = {
789 .name = "hpt-max-page-size",
790 .description = "Maximum page size for Hash Page Table guests",
791 .index = SPAPR_CAP_HPT_MAXPAGESIZE,
792 .get = spapr_cap_get_pagesize,
793 .set = spapr_cap_set_pagesize,
794 .type = "int",
795 .apply = cap_hpt_maxpagesize_apply,
796 .cpu_apply = cap_hpt_maxpagesize_cpu_apply,
797 .migrate_needed = cap_hpt_maxpagesize_migrate_needed,
798 },
799 [SPAPR_CAP_NESTED_KVM_HV] = {
800 .name = "nested-hv",
801 .description = "Allow Nested KVM-HV",
802 .index = SPAPR_CAP_NESTED_KVM_HV,
803 .get = spapr_cap_get_bool,
804 .set = spapr_cap_set_bool,
805 .type = "bool",
806 .apply = cap_nested_kvm_hv_apply,
807 },
808 [SPAPR_CAP_NESTED_PAPR] = {
809 .name = "nested-papr",
810 .description = "Allow Nested HV (PAPR API)",
811 .index = SPAPR_CAP_NESTED_PAPR,
812 .get = spapr_cap_get_bool,
813 .set = spapr_cap_set_bool,
814 .type = "bool",
815 .apply = cap_nested_papr_apply,
816 },
817 [SPAPR_CAP_LARGE_DECREMENTER] = {
818 .name = "large-decr",
819 .description = "Allow Large Decrementer",
820 .index = SPAPR_CAP_LARGE_DECREMENTER,
821 .get = spapr_cap_get_bool,
822 .set = spapr_cap_set_bool,
823 .type = "bool",
824 .apply = cap_large_decr_apply,
825 .cpu_apply = cap_large_decr_cpu_apply,
826 },
827 [SPAPR_CAP_CCF_ASSIST] = {
828 .name = "ccf-assist",
829 .description = "Count Cache Flush Assist via HW Instruction",
830 .index = SPAPR_CAP_CCF_ASSIST,
831 .get = spapr_cap_get_bool,
832 .set = spapr_cap_set_bool,
833 .type = "bool",
834 .apply = cap_ccf_assist_apply,
835 },
836 [SPAPR_CAP_FWNMI] = {
837 .name = "fwnmi",
838 .description = "Implements PAPR FWNMI option",
839 .index = SPAPR_CAP_FWNMI,
840 .get = spapr_cap_get_bool,
841 .set = spapr_cap_set_bool,
842 .type = "bool",
843 .apply = cap_fwnmi_apply,
844 },
845 [SPAPR_CAP_RPT_INVALIDATE] = {
846 .name = "rpt-invalidate",
847 .description = "Allow H_RPT_INVALIDATE",
848 .index = SPAPR_CAP_RPT_INVALIDATE,
849 .get = spapr_cap_get_bool,
850 .set = spapr_cap_set_bool,
851 .type = "bool",
852 .apply = cap_rpt_invalidate_apply,
853 },
854 [SPAPR_CAP_AIL_MODE_3] = {
855 .name = "ail-mode-3",
856 .description = "Alternate Interrupt Location (AIL) mode 3 support",
857 .index = SPAPR_CAP_AIL_MODE_3,
858 .get = spapr_cap_get_bool,
859 .set = spapr_cap_set_bool,
860 .type = "bool",
861 .apply = cap_ail_mode_3_apply,
862 },
863 [SPAPR_CAP_DAWR1] = {
864 .name = "dawr1",
865 .description = "Allow 2nd Data Address Watchpoint Register (DAWR1)",
866 .index = SPAPR_CAP_DAWR1,
867 .get = spapr_cap_get_bool,
868 .set = spapr_cap_set_bool,
869 .type = "bool",
870 .apply = cap_dawr1_apply,
871 },
872 };
873
default_caps_with_cpu(SpaprMachineState * spapr,const char * cputype)874 static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr,
875 const char *cputype)
876 {
877 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
878 SpaprCapabilities caps;
879
880 caps = smc->default_caps;
881
882 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_3_10,
883 0, spapr->max_compat_pvr)) {
884 caps.caps[SPAPR_CAP_DAWR1] = SPAPR_CAP_OFF;
885 }
886
887 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_3_00,
888 0, spapr->max_compat_pvr)) {
889 caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF;
890 }
891
892 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_07,
893 0, spapr->max_compat_pvr)) {
894 caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
895 caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
896 caps.caps[SPAPR_CAP_AIL_MODE_3] = SPAPR_CAP_OFF;
897 }
898
899 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_06_PLUS,
900 0, spapr->max_compat_pvr)) {
901 caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
902 }
903
904 if (!ppc_type_check_compat(cputype, CPU_POWERPC_LOGICAL_2_06,
905 0, spapr->max_compat_pvr)) {
906 caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_OFF;
907 caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_OFF;
908 caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
909 }
910
911 /* This is for pseries-2.12 and older */
912 if (smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] == 0) {
913 uint8_t mps;
914
915 if (kvmppc_hpt_needs_host_contiguous_pages()) {
916 mps = ctz64(qemu_minrampagesize());
917 } else {
918 mps = 34; /* allow everything up to 16GiB, i.e. everything */
919 }
920
921 caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = mps;
922 }
923
924 return caps;
925 }
926
spapr_caps_pre_load(void * opaque)927 int spapr_caps_pre_load(void *opaque)
928 {
929 SpaprMachineState *spapr = opaque;
930
931 /* Set to default so we can tell if this came in with the migration */
932 spapr->mig = spapr->def;
933 return 0;
934 }
935
spapr_caps_pre_save(void * opaque)936 int spapr_caps_pre_save(void *opaque)
937 {
938 SpaprMachineState *spapr = opaque;
939
940 spapr->mig = spapr->eff;
941 return 0;
942 }
943
944 /* This has to be called from the top-level spapr post_load, not the
945 * caps specific one. Otherwise it wouldn't be called when the source
946 * caps are all defaults, which could still conflict with overridden
947 * caps on the destination */
spapr_caps_post_migration(SpaprMachineState * spapr)948 int spapr_caps_post_migration(SpaprMachineState *spapr)
949 {
950 int i;
951 bool ok = true;
952 SpaprCapabilities dstcaps = spapr->eff;
953 SpaprCapabilities srccaps;
954
955 srccaps = default_caps_with_cpu(spapr, MACHINE(spapr)->cpu_type);
956 for (i = 0; i < SPAPR_CAP_NUM; i++) {
957 /* If not default value then assume came in with the migration */
958 if (spapr->mig.caps[i] != spapr->def.caps[i]) {
959 srccaps.caps[i] = spapr->mig.caps[i];
960 }
961 }
962
963 for (i = 0; i < SPAPR_CAP_NUM; i++) {
964 SpaprCapabilityInfo *info = &capability_table[i];
965
966 if (srccaps.caps[i] > dstcaps.caps[i]) {
967 error_report("cap-%s higher level (%d) in incoming stream than on destination (%d)",
968 info->name, srccaps.caps[i], dstcaps.caps[i]);
969 ok = false;
970 }
971
972 if (srccaps.caps[i] < dstcaps.caps[i]) {
973 warn_report("cap-%s lower level (%d) in incoming stream than on destination (%d)",
974 info->name, srccaps.caps[i], dstcaps.caps[i]);
975 }
976 }
977
978 return ok ? 0 : -EINVAL;
979 }
980
981 /* Used to generate the migration field and needed function for a spapr cap */
982 #define SPAPR_CAP_MIG_STATE(sname, cap) \
983 static bool spapr_cap_##sname##_needed(void *opaque) \
984 { \
985 SpaprMachineState *spapr = opaque; \
986 bool (*needed)(void *opaque) = \
987 capability_table[cap].migrate_needed; \
988 \
989 return needed ? needed(opaque) : true && \
990 spapr->cmd_line_caps[cap] && \
991 (spapr->eff.caps[cap] != \
992 spapr->def.caps[cap]); \
993 } \
994 \
995 const VMStateDescription vmstate_spapr_cap_##sname = { \
996 .name = "spapr/cap/" #sname, \
997 .version_id = 1, \
998 .minimum_version_id = 1, \
999 .needed = spapr_cap_##sname##_needed, \
1000 .fields = (const VMStateField[]) { \
1001 VMSTATE_UINT8(mig.caps[cap], \
1002 SpaprMachineState), \
1003 VMSTATE_END_OF_LIST() \
1004 }, \
1005 }
1006
1007 SPAPR_CAP_MIG_STATE(htm, SPAPR_CAP_HTM);
1008 SPAPR_CAP_MIG_STATE(vsx, SPAPR_CAP_VSX);
1009 SPAPR_CAP_MIG_STATE(dfp, SPAPR_CAP_DFP);
1010 SPAPR_CAP_MIG_STATE(cfpc, SPAPR_CAP_CFPC);
1011 SPAPR_CAP_MIG_STATE(sbbc, SPAPR_CAP_SBBC);
1012 SPAPR_CAP_MIG_STATE(ibs, SPAPR_CAP_IBS);
1013 SPAPR_CAP_MIG_STATE(hpt_maxpagesize, SPAPR_CAP_HPT_MAXPAGESIZE);
1014 SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV);
1015 SPAPR_CAP_MIG_STATE(nested_papr, SPAPR_CAP_NESTED_PAPR);
1016 SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER);
1017 SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST);
1018 SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI);
1019 SPAPR_CAP_MIG_STATE(rpt_invalidate, SPAPR_CAP_RPT_INVALIDATE);
1020 SPAPR_CAP_MIG_STATE(ail_mode_3, SPAPR_CAP_AIL_MODE_3);
1021 SPAPR_CAP_MIG_STATE(dawr1, SPAPR_CAP_DAWR1);
1022
spapr_caps_init(SpaprMachineState * spapr)1023 void spapr_caps_init(SpaprMachineState *spapr)
1024 {
1025 SpaprCapabilities default_caps;
1026 int i;
1027
1028 /* Compute the actual set of caps we should run with */
1029 default_caps = default_caps_with_cpu(spapr, MACHINE(spapr)->cpu_type);
1030
1031 for (i = 0; i < SPAPR_CAP_NUM; i++) {
1032 /* Store the defaults */
1033 spapr->def.caps[i] = default_caps.caps[i];
1034 /* If not set on the command line then apply the default value */
1035 if (!spapr->cmd_line_caps[i]) {
1036 spapr->eff.caps[i] = default_caps.caps[i];
1037 }
1038 }
1039 }
1040
spapr_caps_apply(SpaprMachineState * spapr)1041 void spapr_caps_apply(SpaprMachineState *spapr)
1042 {
1043 int i;
1044
1045 for (i = 0; i < SPAPR_CAP_NUM; i++) {
1046 SpaprCapabilityInfo *info = &capability_table[i];
1047
1048 /*
1049 * If the apply function can't set the desired level and thinks it's
1050 * fatal, it should cause that.
1051 */
1052 info->apply(spapr, spapr->eff.caps[i], &error_fatal);
1053 }
1054 }
1055
spapr_caps_cpu_apply(SpaprMachineState * spapr,PowerPCCPU * cpu)1056 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu)
1057 {
1058 int i;
1059
1060 for (i = 0; i < SPAPR_CAP_NUM; i++) {
1061 SpaprCapabilityInfo *info = &capability_table[i];
1062
1063 /*
1064 * If the apply function can't set the desired level and thinks it's
1065 * fatal, it should cause that.
1066 */
1067 if (info->cpu_apply) {
1068 info->cpu_apply(spapr, cpu, spapr->eff.caps[i], &error_fatal);
1069 }
1070 }
1071 }
1072
spapr_caps_add_properties(SpaprMachineClass * smc)1073 void spapr_caps_add_properties(SpaprMachineClass *smc)
1074 {
1075 ObjectClass *klass = OBJECT_CLASS(smc);
1076 int i;
1077
1078 for (i = 0; i < ARRAY_SIZE(capability_table); i++) {
1079 SpaprCapabilityInfo *cap = &capability_table[i];
1080 g_autofree char *name = g_strdup_printf("cap-%s", cap->name);
1081 g_autofree char *desc = g_strdup(cap->description);
1082
1083 object_class_property_add(klass, name, cap->type,
1084 cap->get, cap->set,
1085 NULL, cap);
1086
1087 object_class_property_set_description(klass, name, desc);
1088 }
1089 }
1090