1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2019 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef AMDGPU_DM_AMDGPU_DM_HDCP_H_ 28 #define AMDGPU_DM_AMDGPU_DM_HDCP_H_ 29 30 #include "mod_hdcp.h" 31 #include "hdcp.h" 32 #include "dc.h" 33 #include "dm_cp_psp.h" 34 #include "amdgpu.h" 35 36 struct mod_hdcp; 37 struct mod_hdcp_link; 38 struct mod_hdcp_display; 39 struct cp_psp; 40 41 struct hdcp_workqueue { 42 struct work_struct cpirq_work; 43 struct work_struct property_update_work; 44 struct delayed_work callback_dwork; 45 struct delayed_work watchdog_timer_dwork; 46 struct delayed_work property_validate_dwork; 47 struct amdgpu_dm_connector *aconnector[AMDGPU_DM_MAX_DISPLAY_INDEX]; 48 struct mutex mutex; 49 50 struct mod_hdcp hdcp; 51 struct mod_hdcp_output output; 52 struct mod_hdcp_display display; 53 struct mod_hdcp_link link; 54 55 enum mod_hdcp_encryption_status encryption_status[AMDGPU_DM_MAX_DISPLAY_INDEX]; 56 /* when display is unplugged from mst hub, connctor will be 57 * destroyed within dm_dp_mst_connector_destroy. connector 58 * hdcp perperties, like type, undesired, desired, enabled, 59 * will be lost. So, save hdcp properties into hdcp_work within 60 * amdgpu_dm_atomic_commit_tail. if the same display is 61 * plugged back with same display index, its hdcp properties 62 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 63 */ 64 /* un-desired, desired, enabled */ 65 unsigned int content_protection[AMDGPU_DM_MAX_DISPLAY_INDEX]; 66 /* hdcp1.x, hdcp2.x */ 67 unsigned int hdcp_content_type[AMDGPU_DM_MAX_DISPLAY_INDEX]; 68 69 uint8_t max_link; 70 71 uint8_t *srm; 72 uint8_t *srm_temp; 73 uint32_t srm_version; 74 uint32_t srm_size; 75 struct bin_attribute attr; 76 }; 77 78 void hdcp_update_display(struct hdcp_workqueue *hdcp_work, 79 unsigned int link_index, 80 struct amdgpu_dm_connector *aconnector, 81 uint8_t content_type, 82 bool enable_encryption); 83 84 void hdcp_reset_display(struct hdcp_workqueue *work, unsigned int link_index); 85 void hdcp_handle_cpirq(struct hdcp_workqueue *work, unsigned int link_index); 86 void hdcp_destroy(struct kobject *kobj, struct hdcp_workqueue *work); 87 88 struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct cp_psp *cp_psp, struct dc *dc); 89 90 #endif /* AMDGPU_DM_AMDGPU_DM_HDCP_H_ */ 91