1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4 
5 #ifndef __DML2_CORE_SHARED_TYPES_H__
6 #define __DML2_CORE_SHARED_TYPES_H__
7 
8 #include "dml2_external_lib_deps.h"
9 #include "dml_top_display_cfg_types.h"
10 #include "dml_top_types.h"
11 
12 #define __DML_VBA_DEBUG__
13 #define __DML2_CALCS_MAX_VRATIO_PRE_OTO__ 4.0 //<brief max vratio for one-to-one prefetch bw scheduling
14 #define __DML2_CALCS_MAX_VRATIO_PRE_EQU__ 6.0 //<brief max vratio for equalized prefetch bw scheduling
15 #define __DML2_CALCS_MAX_VRATIO_PRE__ 8.0 //<brief max prefetch vratio register limit
16 
17 #define __DML2_CALCS_DPP_INVALID__ 0
18 #define __DML2_CALCS_DCFCLK_FACTOR__ 1.15 //<brief fudge factor for min dcfclk calclation
19 #define __DML2_CALCS_PIPE_NO_PLANE__ 99
20 
21 struct dml2_core_ip_params {
22 	unsigned int vblank_nom_default_us;
23 	unsigned int remote_iommu_outstanding_translations;
24 	unsigned int rob_buffer_size_kbytes;
25 	unsigned int config_return_buffer_size_in_kbytes;
26 	unsigned int config_return_buffer_segment_size_in_kbytes;
27 	unsigned int compressed_buffer_segment_size_in_kbytes;
28 	unsigned int meta_fifo_size_in_kentries;
29 	unsigned int dpte_buffer_size_in_pte_reqs_luma;
30 	unsigned int dpte_buffer_size_in_pte_reqs_chroma;
31 	unsigned int pixel_chunk_size_kbytes;
32 	unsigned int alpha_pixel_chunk_size_kbytes;
33 	unsigned int min_pixel_chunk_size_bytes;
34 	unsigned int writeback_chunk_size_kbytes;
35 	unsigned int line_buffer_size_bits;
36 	unsigned int max_line_buffer_lines;
37 	unsigned int writeback_interface_buffer_size_kbytes;
38 	unsigned int max_num_dpp;
39 	unsigned int max_num_otg;
40 	unsigned int max_num_wb;
41 	unsigned int max_dchub_pscl_bw_pix_per_clk;
42 	unsigned int max_pscl_lb_bw_pix_per_clk;
43 	unsigned int max_lb_vscl_bw_pix_per_clk;
44 	unsigned int max_vscl_hscl_bw_pix_per_clk;
45 	double max_hscl_ratio;
46 	double max_vscl_ratio;
47 	unsigned int max_hscl_taps;
48 	unsigned int max_vscl_taps;
49 	unsigned int num_dsc;
50 	unsigned int maximum_dsc_bits_per_component;
51 	unsigned int maximum_pixels_per_line_per_dsc_unit;
52 	bool dsc422_native_support;
53 	bool cursor_64bpp_support;
54 	double dispclk_ramp_margin_percent;
55 	unsigned int dppclk_delay_subtotal;
56 	unsigned int dppclk_delay_scl;
57 	unsigned int dppclk_delay_scl_lb_only;
58 	unsigned int dppclk_delay_cnvc_formatter;
59 	unsigned int dppclk_delay_cnvc_cursor;
60 	unsigned int cursor_buffer_size;
61 	unsigned int cursor_chunk_size;
62 	unsigned int dispclk_delay_subtotal;
63 	bool dynamic_metadata_vm_enabled;
64 	unsigned int max_inter_dcn_tile_repeaters;
65 	unsigned int max_num_hdmi_frl_outputs;
66 	unsigned int max_num_dp2p0_outputs;
67 	unsigned int max_num_dp2p0_streams;
68 	bool dcc_supported;
69 	bool ptoi_supported;
70 	double writeback_max_hscl_ratio;
71 	double writeback_max_vscl_ratio;
72 	double writeback_min_hscl_ratio;
73 	double writeback_min_vscl_ratio;
74 	unsigned int writeback_max_hscl_taps;
75 	unsigned int writeback_max_vscl_taps;
76 	unsigned int writeback_line_buffer_buffer_size;
77 
78 	unsigned int words_per_channel;
79 	bool imall_supported;
80 	unsigned int max_flip_time_us;
81 	unsigned int max_flip_time_lines;
82 	unsigned int subvp_swath_height_margin_lines;
83 	unsigned int subvp_fw_processing_delay_us;
84 	unsigned int subvp_pstate_allow_width_us;
85 
86 	// MRQ
87 	bool dcn_mrq_present;
88 	unsigned int zero_size_buffer_entries;
89 	unsigned int compbuf_reserved_space_zs;
90 	unsigned int dcc_meta_buffer_size_bytes;
91 	unsigned int meta_chunk_size_kbytes;
92 	unsigned int min_meta_chunk_size_bytes;
93 
94 	unsigned int dchub_arb_to_ret_delay; // num of dcfclk
95 	unsigned int hostvm_mode;
96 };
97 
98 struct dml2_core_internal_DmlPipe {
99 	double Dppclk;
100 	double Dispclk;
101 	double PixelClock;
102 	double DCFClkDeepSleep;
103 	unsigned int DPPPerSurface;
104 	bool ScalerEnabled;
105 	enum dml2_rotation_angle RotationAngle;
106 	bool mirrored;
107 	unsigned int ViewportHeight;
108 	unsigned int ViewportHeightC;
109 	unsigned int BlockWidth256BytesY;
110 	unsigned int BlockHeight256BytesY;
111 	unsigned int BlockWidth256BytesC;
112 	unsigned int BlockHeight256BytesC;
113 	unsigned int BlockWidthY;
114 	unsigned int BlockHeightY;
115 	unsigned int BlockWidthC;
116 	unsigned int BlockHeightC;
117 	unsigned int InterlaceEnable;
118 	unsigned int NumberOfCursors;
119 	unsigned int VBlank;
120 	unsigned int HTotal;
121 	unsigned int HActive;
122 	bool DCCEnable;
123 	enum dml2_odm_mode ODMMode;
124 	enum dml2_source_format_class SourcePixelFormat;
125 	enum dml2_swizzle_mode SurfaceTiling;
126 	unsigned int BytePerPixelY;
127 	unsigned int BytePerPixelC;
128 	bool ProgressiveToInterlaceUnitInOPP;
129 	double VRatio;
130 	double VRatioChroma;
131 	unsigned int VTaps;
132 	unsigned int VTapsChroma;
133 	unsigned int PitchY;
134 	unsigned int PitchC;
135 	bool ViewportStationary;
136 	unsigned int ViewportXStart;
137 	unsigned int ViewportYStart;
138 	unsigned int ViewportXStartC;
139 	unsigned int ViewportYStartC;
140 	bool FORCE_ONE_ROW_FOR_FRAME;
141 	unsigned int SwathHeightY;
142 	unsigned int SwathHeightC;
143 
144 	unsigned int DCCMetaPitchY;
145 	unsigned int DCCMetaPitchC;
146 };
147 
148 enum dml2_core_internal_request_type {
149 	dml2_core_internal_request_type_256_bytes = 0,
150 	dml2_core_internal_request_type_128_bytes_non_contiguous = 1,
151 	dml2_core_internal_request_type_128_bytes_contiguous = 2,
152 	dml2_core_internal_request_type_na = 3
153 };
154 enum dml2_core_internal_bw_type {
155 	dml2_core_internal_bw_sdp = 0,
156 	dml2_core_internal_bw_dram = 1,
157 	dml2_core_internal_bw_max
158 };
159 
160 enum dml2_core_internal_soc_state_type {
161 	dml2_core_internal_soc_state_sys_active = 0,
162 	dml2_core_internal_soc_state_svp_prefetch = 1,
163 	dml2_core_internal_soc_state_sys_idle = 2,
164 	dml2_core_internal_soc_state_max
165 };
166 
167 enum dml2_core_internal_output_type {
168 	dml2_core_internal_output_type_unknown = 0,
169 	dml2_core_internal_output_type_dp = 1,
170 	dml2_core_internal_output_type_edp = 2,
171 	dml2_core_internal_output_type_dp2p0 = 3,
172 	dml2_core_internal_output_type_hdmi = 4,
173 	dml2_core_internal_output_type_hdmifrl = 5
174 };
175 
176 enum dml2_core_internal_output_type_rate {
177 	dml2_core_internal_output_rate_unknown = 0,
178 	dml2_core_internal_output_rate_dp_rate_hbr = 1,
179 	dml2_core_internal_output_rate_dp_rate_hbr2 = 2,
180 	dml2_core_internal_output_rate_dp_rate_hbr3 = 3,
181 	dml2_core_internal_output_rate_dp_rate_uhbr10 = 4,
182 	dml2_core_internal_output_rate_dp_rate_uhbr13p5 = 5,
183 	dml2_core_internal_output_rate_dp_rate_uhbr20 = 6,
184 	dml2_core_internal_output_rate_hdmi_rate_3x3 = 7,
185 	dml2_core_internal_output_rate_hdmi_rate_6x3 = 8,
186 	dml2_core_internal_output_rate_hdmi_rate_6x4 = 9,
187 	dml2_core_internal_output_rate_hdmi_rate_8x4 = 10,
188 	dml2_core_internal_output_rate_hdmi_rate_10x4 = 11,
189 	dml2_core_internal_output_rate_hdmi_rate_12x4 = 12
190 };
191 
192 struct dml2_core_internal_watermarks {
193 	double UrgentWatermark;
194 	double WritebackUrgentWatermark;
195 	double DRAMClockChangeWatermark;
196 	double FCLKChangeWatermark;
197 	double WritebackDRAMClockChangeWatermark;
198 	double WritebackFCLKChangeWatermark;
199 	double StutterExitWatermark;
200 	double StutterEnterPlusExitWatermark;
201 	double Z8StutterExitWatermark;
202 	double Z8StutterEnterPlusExitWatermark;
203 	double USRRetrainingWatermark;
204 	double temp_read_or_ppt_watermark_us;
205 };
206 
207 struct dml2_core_internal_mode_support_info {
208 	//-----------------
209 	// Mode Support Information
210 	//-----------------
211 	bool ImmediateFlipSupport; //<brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming
212 
213 	// Mode Support Reason/
214 	bool WritebackLatencySupport;
215 	bool ScaleRatioAndTapsSupport;
216 	bool SourceFormatPixelAndScanSupport;
217 	bool P2IWith420;
218 	bool DSCSlicesODMModeSupported;
219 	bool DSCOnlyIfNecessaryWithBPP;
220 	bool DSC422NativeNotSupported;
221 	bool LinkRateDoesNotMatchDPVersion;
222 	bool LinkRateForMultistreamNotIndicated;
223 	bool BPPForMultistreamNotIndicated;
224 	bool MultistreamWithHDMIOreDP;
225 	bool MSOOrODMSplitWithNonDPLink;
226 	bool NotEnoughLanesForMSO;
227 	bool NumberOfOTGSupport;
228 	bool NumberOfHDMIFRLSupport;
229 	bool NumberOfDP2p0Support;
230 	bool WritebackScaleRatioAndTapsSupport;
231 	bool CursorSupport;
232 	bool PitchSupport;
233 	bool ViewportExceedsSurface;
234 	//bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
235 	bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
236 	bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;
237 	bool InvalidCombinationOfMALLUseForPState;
238 	bool ExceededMALLSize;
239 	bool EnoughWritebackUnits;
240 
241 	bool ExceededMultistreamSlots;
242 	bool NotEnoughDSCUnits;
243 	bool NotEnoughDSCSlices;
244 	bool PixelsPerLinePerDSCUnitSupport;
245 	bool DSCCLKRequiredMoreThanSupported;
246 	bool DTBCLKRequiredMoreThanSupported;
247 	bool LinkCapacitySupport;
248 
249 	bool ROBSupport;
250 	bool OutstandingRequestsSupport;
251 	bool OutstandingRequestsUrgencyAvoidance;
252 
253 	bool PTEBufferSizeNotExceeded;
254 	bool DCCMetaBufferSizeNotExceeded;
255 	enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES];
256 	enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES];
257 	bool global_dram_clock_change_supported;
258 	bool global_fclk_change_supported;
259 	bool USRRetrainingSupport;
260 	bool AvgBandwidthSupport;
261 	bool UrgVactiveBandwidthSupport;
262 	bool EnoughUrgentLatencyHidingSupport;
263 	bool PrefetchSupported;
264 	bool PrefetchBandwidthSupported;
265 	bool DynamicMetadataSupported;
266 	bool VRatioInPrefetchSupported;
267 	bool DISPCLK_DPPCLK_Support;
268 	bool TotalAvailablePipesSupport;
269 	bool ModeSupport;
270 	bool ViewportSizeSupport;
271 
272 	bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting
273 	enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage
274 	unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4.
275 	bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mode_programming
276 	bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required
277 	unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to support the given mode
278 
279 	double OutputBpp[DML2_MAX_PLANES];
280 	enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES];
281 	enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES];
282 
283 	unsigned int AlignedYPitch[DML2_MAX_PLANES];
284 	unsigned int AlignedCPitch[DML2_MAX_PLANES];
285 
286 	unsigned int AlignedDCCMetaPitchY[DML2_MAX_PLANES];
287 	unsigned int AlignedDCCMetaPitchC[DML2_MAX_PLANES];
288 
289 	unsigned int request_size_bytes_luma[DML2_MAX_PLANES];
290 	unsigned int request_size_bytes_chroma[DML2_MAX_PLANES];
291 	enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES];
292 	enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES];
293 
294 	unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES];
295 	unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES];
296 	unsigned int DCCYIndependentBlock[DML2_MAX_PLANES];
297 	unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES];
298 	unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES];
299 	unsigned int DCCCIndependentBlock[DML2_MAX_PLANES];
300 
301 	double avg_bandwidth_available_min[dml2_core_internal_soc_state_max];
302 	double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
303 	double urg_bandwidth_available_min_latency[dml2_core_internal_soc_state_max]; // min between SDP and DRAM, for latency evaluation
304 	double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM
305 	double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
306 	double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm etc.
307 	double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc.
308 
309 	double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
310 	double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor
311 	double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor
312 	double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw
313 	double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip
314 
315 	double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor
316 	double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
317 
318 	bool avg_bandwidth_support_ok[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
319 
320 	double max_urgent_latency_us;
321 	double max_non_urgent_latency_us;
322 	double avg_non_urgent_latency_us;
323 	double avg_urgent_latency_us;
324 	double df_response_time_us;
325 
326 	bool incorrect_imall_usage;
327 
328 	bool g6_temp_read_support;
329 	bool temp_read_or_ppt_support;
330 
331 	struct dml2_core_internal_watermarks watermarks;
332 };
333 
334 struct dml2_core_internal_mode_support {
335 	// Physical info; only using for programming
336 	unsigned int state_idx; // <brief min clk state table index for mode support call
337 	unsigned int qos_param_index; // to access the uclk dependent qos_parameters table
338 	unsigned int active_min_uclk_dpm_index; // to access the min_clk table
339 	unsigned int num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg
340 
341 	// Calculated Clocks
342 	double RequiredDISPCLK; /// <brief Required DISPCLK; depends on pixel rate; odm mode etc.
343 	double RequiredDPPCLK[DML2_MAX_PLANES];
344 	double RequiredDISPCLKPerSurface[DML2_MAX_PLANES];
345 	double RequiredDTBCLK[DML2_MAX_PLANES];
346 
347 	double required_dscclk_freq_mhz[DML2_MAX_PLANES];
348 
349 	double FabricClock; /// <brief Basically just the clock freq at the min (or given) state
350 	double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state
351 	double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting
352 	double GlobalDPPCLK; /// <brief the Max DPPCLK freq out of all pipes
353 	double uclk_freq_mhz;
354 	double dram_bw_mbps;
355 	double max_dram_bw_mbps;
356 
357 	double MaxFabricClock; /// <brief Basically just the clock freq at the min (or given) state
358 	double MaxDCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting
359 	double max_dispclk_freq_mhz;
360 	double max_dppclk_freq_mhz;
361 	double max_dscclk_freq_mhz;
362 
363 	bool NoTimeForPrefetch[DML2_MAX_PLANES];
364 	bool NoTimeForDynamicMetadata[DML2_MAX_PLANES];
365 
366 	// ----------------------------------
367 	// Mode Support Info and fail reason
368 	// ----------------------------------
369 	struct dml2_core_internal_mode_support_info support;
370 
371 	// These are calculated before the ModeSupport and ModeProgram step
372 	// They represent the bound for the return buffer sizing
373 	unsigned int MaxTotalDETInKByte;
374 	unsigned int NomDETInKByte;
375 	unsigned int MinCompressedBufferSizeInKByte;
376 
377 	// Info obtained at the end of mode support calculations
378 	// The reported info is at the "optimal" state and combine setting
379 	unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value.
380 	unsigned int DETBufferSizeY[DML2_MAX_PLANES];
381 	unsigned int DETBufferSizeC[DML2_MAX_PLANES];
382 	unsigned int SwathHeightY[DML2_MAX_PLANES];
383 	unsigned int SwathHeightC[DML2_MAX_PLANES];
384 	unsigned int SwathWidthY[DML2_MAX_PLANES]; // per-pipe
385 	unsigned int SwathWidthC[DML2_MAX_PLANES]; // per-pipe
386 
387 	// ----------------------------------
388 	// Intermediates/Informational
389 	// ----------------------------------
390 	unsigned int TotImmediateFlipBytes;
391 	bool DCCEnabledInAnySurface;
392 	double WritebackRequiredDISPCLK;
393 	double TimeCalc;
394 	double TWait[DML2_MAX_PLANES];
395 
396 	bool UnboundedRequestEnabled;
397 	unsigned int CompressedBufferSizeInkByte;
398 	double VRatioPreY[DML2_MAX_PLANES];
399 	double VRatioPreC[DML2_MAX_PLANES];
400 	unsigned int swath_width_luma_ub[DML2_MAX_PLANES];
401 	unsigned int swath_width_chroma_ub[DML2_MAX_PLANES];
402 	unsigned int RequiredSlots[DML2_MAX_PLANES];
403 	unsigned int vm_bytes[DML2_MAX_PLANES];
404 	unsigned int DPTEBytesPerRow[DML2_MAX_PLANES];
405 	unsigned int PrefetchLinesY[DML2_MAX_PLANES];
406 	unsigned int PrefetchLinesC[DML2_MAX_PLANES];
407 	unsigned int MaxNumSwathY[DML2_MAX_PLANES]; /// <brief Max number of swath for prefetch
408 	unsigned int MaxNumSwathC[DML2_MAX_PLANES]; /// <brief Max number of swath for prefetch
409 	unsigned int PrefillY[DML2_MAX_PLANES];
410 	unsigned int PrefillC[DML2_MAX_PLANES];
411 	unsigned int full_swath_bytes_l[DML2_MAX_PLANES];
412 	unsigned int full_swath_bytes_c[DML2_MAX_PLANES];
413 
414 	bool use_one_row_for_frame[DML2_MAX_PLANES];
415 	bool use_one_row_for_frame_flip[DML2_MAX_PLANES];
416 
417 	double dst_y_prefetch[DML2_MAX_PLANES];
418 	double LinesForVM[DML2_MAX_PLANES];
419 	double LinesForDPTERow[DML2_MAX_PLANES];
420 	double SwathWidthYSingleDPP[DML2_MAX_PLANES];
421 	double SwathWidthCSingleDPP[DML2_MAX_PLANES];
422 	unsigned int BytePerPixelY[DML2_MAX_PLANES];
423 	unsigned int BytePerPixelC[DML2_MAX_PLANES];
424 	double BytePerPixelInDETY[DML2_MAX_PLANES];
425 	double BytePerPixelInDETC[DML2_MAX_PLANES];
426 
427 	unsigned int Read256BlockHeightY[DML2_MAX_PLANES];
428 	unsigned int Read256BlockWidthY[DML2_MAX_PLANES];
429 	unsigned int Read256BlockHeightC[DML2_MAX_PLANES];
430 	unsigned int Read256BlockWidthC[DML2_MAX_PLANES];
431 	unsigned int MacroTileHeightY[DML2_MAX_PLANES];
432 	unsigned int MacroTileHeightC[DML2_MAX_PLANES];
433 	unsigned int MacroTileWidthY[DML2_MAX_PLANES];
434 	unsigned int MacroTileWidthC[DML2_MAX_PLANES];
435 
436 	bool surf_linear128_l[DML2_MAX_PLANES];
437 	bool surf_linear128_c[DML2_MAX_PLANES];
438 
439 	double PSCL_FACTOR[DML2_MAX_PLANES];
440 	double PSCL_FACTOR_CHROMA[DML2_MAX_PLANES];
441 	double MaximumSwathWidthLuma[DML2_MAX_PLANES];
442 	double MaximumSwathWidthChroma[DML2_MAX_PLANES];
443 	double Tno_bw[DML2_MAX_PLANES];
444 	double Tno_bw_flip[DML2_MAX_PLANES];
445 	double dst_y_per_vm_flip[DML2_MAX_PLANES];
446 	double dst_y_per_row_flip[DML2_MAX_PLANES];
447 	double WritebackDelayTime[DML2_MAX_PLANES];
448 	unsigned int dpte_group_bytes[DML2_MAX_PLANES];
449 	unsigned int dpte_row_height[DML2_MAX_PLANES];
450 	unsigned int dpte_row_height_chroma[DML2_MAX_PLANES];
451 	double UrgLatency;
452 	double TripToMemory;
453 	double UrgentBurstFactorCursor[DML2_MAX_PLANES];
454 	double UrgentBurstFactorCursorPre[DML2_MAX_PLANES];
455 	double UrgentBurstFactorLuma[DML2_MAX_PLANES];
456 	double UrgentBurstFactorLumaPre[DML2_MAX_PLANES];
457 	double UrgentBurstFactorChroma[DML2_MAX_PLANES];
458 	double UrgentBurstFactorChromaPre[DML2_MAX_PLANES];
459 	double MaximumSwathWidthInLineBufferLuma;
460 	double MaximumSwathWidthInLineBufferChroma;
461 	double ExtraLatency;
462 	double ExtraLatency_sr;
463 	double ExtraLatencyPrefetch;
464 
465 	double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta
466 	double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES];
467 	double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta
468 	double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES];
469 	double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES]; // overhead to the imall or phantom pipe
470 	double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES];
471 
472 	// Backend
473 	bool RequiresDSC[DML2_MAX_PLANES];
474 	bool RequiresFEC[DML2_MAX_PLANES];
475 	double OutputBpp[DML2_MAX_PLANES];
476 	unsigned int DSCDelay[DML2_MAX_PLANES];
477 	enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES];
478 	enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES];
479 
480 	// Bandwidth Related Info
481 	double BandwidthAvailableForImmediateFlip;
482 	double vactive_sw_bw_l[DML2_MAX_PLANES]; // no dcc overhead, for the plane
483 	double vactive_sw_bw_c[DML2_MAX_PLANES];
484 	double WriteBandwidth[DML2_MAX_PLANES][DML2_MAX_WRITEBACK];
485 	double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES];
486 	double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES];
487 	/* oto bw should also be considered when calculating peak urgent bw to avoid situations oto/equ mismatches between ms and mp */
488 	double RequiredPrefetchBWOTO[DML2_MAX_PLANES];
489 	double cursor_bw[DML2_MAX_PLANES];
490 	double prefetch_cursor_bw[DML2_MAX_PLANES];
491 	double prefetch_vmrow_bw[DML2_MAX_PLANES];
492 	double final_flip_bw[DML2_MAX_PLANES];
493 	double meta_row_bw[DML2_MAX_PLANES];
494 	unsigned int meta_row_bytes[DML2_MAX_PLANES];
495 	double dpte_row_bw[DML2_MAX_PLANES];
496 	double excess_vactive_fill_bw_l[DML2_MAX_PLANES];
497 	double excess_vactive_fill_bw_c[DML2_MAX_PLANES];
498 	double surface_avg_vactive_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];
499 	double surface_peak_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];
500 
501 	// Something that should be feedback to caller
502 	enum dml2_odm_mode ODMMode[DML2_MAX_PLANES];
503 	unsigned int SurfaceSizeInMALL[DML2_MAX_PLANES];
504 	unsigned int NoOfDPP[DML2_MAX_PLANES];
505 	bool MPCCombine[DML2_MAX_PLANES];
506 	double dcfclk_deepsleep;
507 	double MinDPPCLKUsingSingleDPP[DML2_MAX_PLANES];
508 	bool SingleDPPViewportSizeSupportPerSurface[DML2_MAX_PLANES];
509 	bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES];
510 	bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES];
511 	bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES];
512 	bool PTEBufferSizeNotExceeded[DML2_MAX_PLANES];
513 	bool DCCMetaBufferSizeNotExceeded[DML2_MAX_PLANES];
514 	unsigned int TotalNumberOfActiveDPP;
515 	unsigned int TotalNumberOfSingleDPPSurfaces;
516 	unsigned int TotalNumberOfDCCActiveDPP;
517 	unsigned int Total3dlutActive;
518 
519 	unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES];
520 	double VActiveLatencyHidingMargin[DML2_MAX_PLANES];
521 	double VActiveLatencyHidingUs[DML2_MAX_PLANES];
522 	unsigned int MaxVStartupLines[DML2_MAX_PLANES];
523 	double dram_change_vactive_det_fill_delay_us[DML2_MAX_PLANES];
524 
525 	unsigned int num_mcaches_l[DML2_MAX_PLANES];
526 	unsigned int mcache_row_bytes_l[DML2_MAX_PLANES];
527 	unsigned int mcache_row_bytes_per_channel_l[DML2_MAX_PLANES];
528 	unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];
529 	unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES];
530 
531 	unsigned int num_mcaches_c[DML2_MAX_PLANES];
532 	unsigned int mcache_row_bytes_c[DML2_MAX_PLANES];
533 	unsigned int mcache_row_bytes_per_channel_c[DML2_MAX_PLANES];
534 	unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];
535 	unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES];
536 
537 	bool mall_comb_mcache_l[DML2_MAX_PLANES];
538 	bool mall_comb_mcache_c[DML2_MAX_PLANES];
539 	bool lc_comb_mcache[DML2_MAX_PLANES];
540 
541 
542 };
543 
544 /// @brief A mega structure that houses various info for model programming step.
545 struct dml2_core_internal_mode_program {
546 	unsigned int qos_param_index; // to access the uclk dependent dpm table
547 	unsigned int active_min_uclk_dpm_index; // to access the min_clk table
548 	double FabricClock; /// <brief Basically just the clock freq at the min (or given) state
549 	//double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting
550 	double dram_bw_mbps;
551 	double uclk_freq_mhz;
552 	unsigned int NoOfDPP[DML2_MAX_PLANES];
553 	enum dml2_odm_mode ODMMode[DML2_MAX_PLANES];
554 
555 	//-------------
556 	// Intermediate/Informational
557 	//-------------
558 	double UrgentLatency;
559 	double TripToMemory;
560 	double MetaTripToMemory;
561 	unsigned int VInitPreFillY[DML2_MAX_PLANES];
562 	unsigned int VInitPreFillC[DML2_MAX_PLANES];
563 	unsigned int MaxNumSwathY[DML2_MAX_PLANES];
564 	unsigned int MaxNumSwathC[DML2_MAX_PLANES];
565 	unsigned int full_swath_bytes_l[DML2_MAX_PLANES];
566 	unsigned int full_swath_bytes_c[DML2_MAX_PLANES];
567 
568 	double BytePerPixelInDETY[DML2_MAX_PLANES];
569 	double BytePerPixelInDETC[DML2_MAX_PLANES];
570 	unsigned int BytePerPixelY[DML2_MAX_PLANES];
571 	unsigned int BytePerPixelC[DML2_MAX_PLANES];
572 	unsigned int SwathWidthY[DML2_MAX_PLANES]; // per-pipe
573 	unsigned int SwathWidthC[DML2_MAX_PLANES]; // per-pipe
574 	unsigned int req_per_swath_ub_l[DML2_MAX_PLANES];
575 	unsigned int req_per_swath_ub_c[DML2_MAX_PLANES];
576 	unsigned int SwathWidthSingleDPPY[DML2_MAX_PLANES];
577 	unsigned int SwathWidthSingleDPPC[DML2_MAX_PLANES];
578 	double vactive_sw_bw_l[DML2_MAX_PLANES];
579 	double vactive_sw_bw_c[DML2_MAX_PLANES];
580 	double excess_vactive_fill_bw_l[DML2_MAX_PLANES];
581 	double excess_vactive_fill_bw_c[DML2_MAX_PLANES];
582 
583 	unsigned int PixelPTEBytesPerRow[DML2_MAX_PLANES];
584 	unsigned int vm_bytes[DML2_MAX_PLANES];
585 	unsigned int PrefetchSourceLinesY[DML2_MAX_PLANES];
586 	double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES];
587 	double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES];
588 	unsigned int PrefetchSourceLinesC[DML2_MAX_PLANES];
589 	double PSCL_THROUGHPUT[DML2_MAX_PLANES];
590 	double PSCL_THROUGHPUT_CHROMA[DML2_MAX_PLANES];
591 	unsigned int DSCDelay[DML2_MAX_PLANES];
592 	double DPPCLKUsingSingleDPP[DML2_MAX_PLANES];
593 
594 	unsigned int Read256BlockHeightY[DML2_MAX_PLANES];
595 	unsigned int Read256BlockWidthY[DML2_MAX_PLANES];
596 	unsigned int Read256BlockHeightC[DML2_MAX_PLANES];
597 	unsigned int Read256BlockWidthC[DML2_MAX_PLANES];
598 	unsigned int MacroTileHeightY[DML2_MAX_PLANES];
599 	unsigned int MacroTileHeightC[DML2_MAX_PLANES];
600 	unsigned int MacroTileWidthY[DML2_MAX_PLANES];
601 	unsigned int MacroTileWidthC[DML2_MAX_PLANES];
602 
603 	bool surf_linear128_l[DML2_MAX_PLANES];
604 	bool surf_linear128_c[DML2_MAX_PLANES];
605 
606 	unsigned int SurfaceSizeInTheMALL[DML2_MAX_PLANES];
607 	double VRatioPrefetchY[DML2_MAX_PLANES];
608 	double VRatioPrefetchC[DML2_MAX_PLANES];
609 	double Tno_bw[DML2_MAX_PLANES];
610 	double Tno_bw_flip[DML2_MAX_PLANES];
611 	double final_flip_bw[DML2_MAX_PLANES];
612 	double prefetch_vmrow_bw[DML2_MAX_PLANES];
613 	double cursor_bw[DML2_MAX_PLANES];
614 	double prefetch_cursor_bw[DML2_MAX_PLANES];
615 	double WritebackDelay[DML2_MAX_PLANES];
616 	unsigned int dpte_row_height[DML2_MAX_PLANES];
617 	unsigned int dpte_row_height_linear[DML2_MAX_PLANES];
618 	unsigned int dpte_row_width_luma_ub[DML2_MAX_PLANES];
619 	unsigned int dpte_row_width_chroma_ub[DML2_MAX_PLANES];
620 	unsigned int dpte_row_height_chroma[DML2_MAX_PLANES];
621 	unsigned int dpte_row_height_linear_chroma[DML2_MAX_PLANES];
622 	unsigned int vm_group_bytes[DML2_MAX_PLANES];
623 	unsigned int dpte_group_bytes[DML2_MAX_PLANES];
624 
625 	double dpte_row_bw[DML2_MAX_PLANES];
626 	double time_per_tdlut_group[DML2_MAX_PLANES];
627 	double UrgentBurstFactorCursor[DML2_MAX_PLANES];
628 	double UrgentBurstFactorCursorPre[DML2_MAX_PLANES];
629 	double UrgentBurstFactorLuma[DML2_MAX_PLANES];
630 	double UrgentBurstFactorLumaPre[DML2_MAX_PLANES];
631 	double UrgentBurstFactorChroma[DML2_MAX_PLANES];
632 	double UrgentBurstFactorChromaPre[DML2_MAX_PLANES];
633 
634 	double meta_row_bw[DML2_MAX_PLANES];
635 	unsigned int meta_row_bytes[DML2_MAX_PLANES];
636 	unsigned int meta_req_width[DML2_MAX_PLANES];
637 	unsigned int meta_req_height[DML2_MAX_PLANES];
638 	unsigned int meta_row_width[DML2_MAX_PLANES];
639 	unsigned int meta_row_height[DML2_MAX_PLANES];
640 	unsigned int meta_req_width_chroma[DML2_MAX_PLANES];
641 	unsigned int meta_row_height_chroma[DML2_MAX_PLANES];
642 	unsigned int meta_row_width_chroma[DML2_MAX_PLANES];
643 	unsigned int meta_req_height_chroma[DML2_MAX_PLANES];
644 
645 	unsigned int swath_width_luma_ub[DML2_MAX_PLANES];
646 	unsigned int swath_width_chroma_ub[DML2_MAX_PLANES];
647 	unsigned int PixelPTEReqWidthY[DML2_MAX_PLANES];
648 	unsigned int PixelPTEReqHeightY[DML2_MAX_PLANES];
649 	unsigned int PTERequestSizeY[DML2_MAX_PLANES];
650 	unsigned int PixelPTEReqWidthC[DML2_MAX_PLANES];
651 	unsigned int PixelPTEReqHeightC[DML2_MAX_PLANES];
652 	unsigned int PTERequestSizeC[DML2_MAX_PLANES];
653 
654 	double TWait[DML2_MAX_PLANES];
655 	double Tdmdl_vm[DML2_MAX_PLANES];
656 	double Tdmdl[DML2_MAX_PLANES];
657 	double TSetup[DML2_MAX_PLANES];
658 	unsigned int dpde0_bytes_per_frame_ub_l[DML2_MAX_PLANES];
659 	unsigned int dpde0_bytes_per_frame_ub_c[DML2_MAX_PLANES];
660 
661 	unsigned int meta_pte_bytes_per_frame_ub_l[DML2_MAX_PLANES];
662 	unsigned int meta_pte_bytes_per_frame_ub_c[DML2_MAX_PLANES];
663 
664 	bool UnboundedRequestEnabled;
665 	unsigned int CompressedBufferSizeInkByte;
666 	unsigned int compbuf_reserved_space_64b;
667 	bool hw_debug5;
668 	unsigned int dcfclk_deep_sleep_hysteresis;
669 	unsigned int min_return_latency_in_dcfclk;
670 
671 	bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES];
672 	bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES];
673 	double ExtraLatency;
674 	double ExtraLatency_sr;
675 	double ExtraLatencyPrefetch;
676 	bool PrefetchAndImmediateFlipSupported;
677 	double TotalDataReadBandwidth;
678 	double BandwidthAvailableForImmediateFlip;
679 	bool NotEnoughTimeForDynamicMetadata[DML2_MAX_PLANES];
680 
681 	bool use_one_row_for_frame[DML2_MAX_PLANES];
682 	bool use_one_row_for_frame_flip[DML2_MAX_PLANES];
683 
684 	double TCalc;
685 	unsigned int TotImmediateFlipBytes;
686 
687 	// -------------------
688 	// Output
689 	// -------------------
690 	unsigned int pipe_plane[DML2_MAX_PLANES]; // <brief used mainly by dv to map the pipe inst to plane index within DML core; the plane idx of a pipe
691 	unsigned int num_active_pipes;
692 
693 	bool NoTimeToPrefetch[DML2_MAX_PLANES]; // <brief Prefetch schedule calculation result
694 
695 	// Support
696 	bool UrgVactiveBandwidthSupport;
697 	bool PrefetchModeSupported; // <brief Is the prefetch mode (bandwidth and latency) supported
698 	bool ImmediateFlipSupported;
699 	bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES];
700 
701 	// Clock
702 	double Dcfclk;
703 	double Dispclk; // <brief dispclk being used in mode programming
704 	double Dppclk[DML2_MAX_PLANES]; // <brief dppclk being used in mode programming
705 	double GlobalDPPCLK;
706 
707 	double DSCCLK[DML2_MAX_PLANES]; //< brief Required DSCCLK freq. Backend; not used in any subsequent calculations for now
708 	double DCFCLKDeepSleep;
709 
710 	// ARB reg
711 	bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
712 	struct dml2_core_internal_watermarks Watermark;
713 
714 	// DCC compression control
715 	unsigned int request_size_bytes_luma[DML2_MAX_PLANES];
716 	unsigned int request_size_bytes_chroma[DML2_MAX_PLANES];
717 	enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES];
718 	enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES];
719 	unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES];
720 	unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES];
721 	unsigned int DCCYIndependentBlock[DML2_MAX_PLANES];
722 	unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES];
723 	unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES];
724 	unsigned int DCCCIndependentBlock[DML2_MAX_PLANES];
725 
726 	// Stutter Efficiency
727 	double StutterEfficiency;
728 	double StutterEfficiencyNotIncludingVBlank;
729 	unsigned int NumberOfStutterBurstsPerFrame;
730 	double Z8StutterEfficiency;
731 	unsigned int Z8NumberOfStutterBurstsPerFrame;
732 	double Z8StutterEfficiencyNotIncludingVBlank;
733 	double StutterPeriod;
734 	double Z8StutterEfficiencyBestCase;
735 	unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;
736 	double Z8StutterEfficiencyNotIncludingVBlankBestCase;
737 	double StutterPeriodBestCase;
738 
739 	// DLG TTU reg
740 	double MIN_DST_Y_NEXT_START[DML2_MAX_PLANES];
741 	bool VREADY_AT_OR_AFTER_VSYNC[DML2_MAX_PLANES];
742 	unsigned int DSTYAfterScaler[DML2_MAX_PLANES];
743 	unsigned int DSTXAfterScaler[DML2_MAX_PLANES];
744 	double dst_y_prefetch[DML2_MAX_PLANES];
745 	double dst_y_per_vm_vblank[DML2_MAX_PLANES];
746 	double dst_y_per_row_vblank[DML2_MAX_PLANES];
747 	double dst_y_per_vm_flip[DML2_MAX_PLANES];
748 	double dst_y_per_row_flip[DML2_MAX_PLANES];
749 	double MinTTUVBlank[DML2_MAX_PLANES];
750 	double DisplayPipeLineDeliveryTimeLuma[DML2_MAX_PLANES];
751 	double DisplayPipeLineDeliveryTimeChroma[DML2_MAX_PLANES];
752 	double DisplayPipeLineDeliveryTimeLumaPrefetch[DML2_MAX_PLANES];
753 	double DisplayPipeLineDeliveryTimeChromaPrefetch[DML2_MAX_PLANES];
754 	double DisplayPipeRequestDeliveryTimeLuma[DML2_MAX_PLANES];
755 	double DisplayPipeRequestDeliveryTimeChroma[DML2_MAX_PLANES];
756 	double DisplayPipeRequestDeliveryTimeLumaPrefetch[DML2_MAX_PLANES];
757 	double DisplayPipeRequestDeliveryTimeChromaPrefetch[DML2_MAX_PLANES];
758 	unsigned int CursorDstXOffset[DML2_MAX_PLANES];
759 	unsigned int CursorDstYOffset[DML2_MAX_PLANES];
760 	unsigned int CursorChunkHDLAdjust[DML2_MAX_PLANES];
761 
762 	double DST_Y_PER_PTE_ROW_NOM_L[DML2_MAX_PLANES];
763 	double DST_Y_PER_PTE_ROW_NOM_C[DML2_MAX_PLANES];
764 	double time_per_pte_group_nom_luma[DML2_MAX_PLANES];
765 	double time_per_pte_group_nom_chroma[DML2_MAX_PLANES];
766 	double time_per_pte_group_vblank_luma[DML2_MAX_PLANES];
767 	double time_per_pte_group_vblank_chroma[DML2_MAX_PLANES];
768 	double time_per_pte_group_flip_luma[DML2_MAX_PLANES];
769 	double time_per_pte_group_flip_chroma[DML2_MAX_PLANES];
770 	double TimePerVMGroupVBlank[DML2_MAX_PLANES];
771 	double TimePerVMGroupFlip[DML2_MAX_PLANES];
772 	double TimePerVMRequestVBlank[DML2_MAX_PLANES];
773 	double TimePerVMRequestFlip[DML2_MAX_PLANES];
774 
775 	double DST_Y_PER_META_ROW_NOM_L[DML2_MAX_PLANES];
776 	double DST_Y_PER_META_ROW_NOM_C[DML2_MAX_PLANES];
777 	double TimePerMetaChunkNominal[DML2_MAX_PLANES];
778 	double TimePerChromaMetaChunkNominal[DML2_MAX_PLANES];
779 	double TimePerMetaChunkVBlank[DML2_MAX_PLANES];
780 	double TimePerChromaMetaChunkVBlank[DML2_MAX_PLANES];
781 	double TimePerMetaChunkFlip[DML2_MAX_PLANES];
782 	double TimePerChromaMetaChunkFlip[DML2_MAX_PLANES];
783 
784 	double FractionOfUrgentBandwidth;
785 	double FractionOfUrgentBandwidthImmediateFlip;
786 	double FractionOfUrgentBandwidthMALL;
787 
788 	// RQ registers
789 	bool PTE_BUFFER_MODE[DML2_MAX_PLANES];
790 	unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES];
791 
792 	unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES];
793 	bool is_using_mall_for_ss[DML2_MAX_PLANES];
794 
795 	// OTG
796 	unsigned int VStartupMin[DML2_MAX_PLANES]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos.
797 	unsigned int VStartup[DML2_MAX_PLANES]; /// <brief The vstartup value for OTG programming (will set to max vstartup; but now bounded by min(vblank_nom. actual vblank))
798 	unsigned int VUpdateOffsetPix[DML2_MAX_PLANES];
799 	unsigned int VUpdateWidthPix[DML2_MAX_PLANES];
800 	unsigned int VReadyOffsetPix[DML2_MAX_PLANES];
801 	unsigned int pstate_keepout_dst_lines[DML2_MAX_PLANES];
802 
803 	// Latency and Support
804 	double MaxActiveFCLKChangeLatencySupported;
805 	bool USRRetrainingSupport;
806 	bool g6_temp_read_support;
807 	bool temp_read_or_ppt_support;
808 	enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES];
809 	enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES];
810 	bool global_dram_clock_change_supported;
811 	bool global_fclk_change_supported;
812 	double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES];
813 	double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES];
814 	double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES];
815 
816 	// buffer sizing
817 	unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value.
818 	unsigned int DETBufferSizeY[DML2_MAX_PLANES];
819 	unsigned int DETBufferSizeC[DML2_MAX_PLANES];
820 	unsigned int SwathHeightY[DML2_MAX_PLANES];
821 	unsigned int SwathHeightC[DML2_MAX_PLANES];
822 
823 	double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor
824 	double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor
825 	double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw
826 	double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip
827 	double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor
828 	double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
829 
830 	double avg_bandwidth_available_min[dml2_core_internal_soc_state_max];
831 	double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
832 	double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM
833 	double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
834 	double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm traffic etc.
835 	double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc.
836 
837 	double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES];
838 	double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES];
839 	double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES];
840 	double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES];
841 	double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES];
842 	double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES];
843 
844 	unsigned int num_mcaches_l[DML2_MAX_PLANES];
845 	unsigned int mcache_row_bytes_l[DML2_MAX_PLANES];
846 	unsigned int mcache_row_bytes_per_channel_l[DML2_MAX_PLANES];
847 	unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];
848 	unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES];
849 
850 	unsigned int num_mcaches_c[DML2_MAX_PLANES];
851 	unsigned int mcache_row_bytes_c[DML2_MAX_PLANES];
852 	unsigned int mcache_row_bytes_per_channel_c[DML2_MAX_PLANES];
853 	unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];
854 	unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES];
855 
856 	bool mall_comb_mcache_l[DML2_MAX_PLANES];
857 	bool mall_comb_mcache_c[DML2_MAX_PLANES];
858 	bool lc_comb_mcache[DML2_MAX_PLANES];
859 
860 	double impacted_prefetch_margin_us[DML2_MAX_PLANES];
861 };
862 
863 struct dml2_core_internal_SOCParametersList {
864 	double UrgentLatency;
865 	double ExtraLatency_sr;
866 	double ExtraLatency;
867 	double WritebackLatency;
868 	double DRAMClockChangeLatency;
869 	double FCLKChangeLatency;
870 	double SRExitTime;
871 	double SREnterPlusExitTime;
872 	double SRExitZ8Time;
873 	double SREnterPlusExitZ8Time;
874 	double USRRetrainingLatency;
875 	double SMNLatency;
876 	double g6_temp_read_blackout_us;
877 	double temp_read_or_ppt_blackout_us;
878 	double max_urgent_latency_us;
879 	double df_response_time_us;
880 	enum dml2_qos_param_type qos_type;
881 };
882 
883 struct dml2_core_calcs_mode_support_locals {
884 	double PixelClockBackEnd[DML2_MAX_PLANES];
885 	double OutputBpp[DML2_MAX_PLANES];
886 
887 	unsigned int meta_row_height_luma[DML2_MAX_PLANES];
888 	unsigned int meta_row_height_chroma[DML2_MAX_PLANES];
889 	unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];
890 	unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];
891 	unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];
892 	unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];
893 
894 	bool dummy_boolean[3];
895 	unsigned int dummy_integer[3];
896 	unsigned int dummy_integer_array[36][DML2_MAX_PLANES];
897 	enum dml2_odm_mode dummy_odm_mode[DML2_MAX_PLANES];
898 	bool dummy_boolean_array[2][DML2_MAX_PLANES];
899 	double dummy_single[3];
900 	double dummy_single_array[DML2_MAX_PLANES];
901 	struct dml2_core_internal_watermarks dummy_watermark;
902 	double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
903 	double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];
904 
905 	unsigned int MaximumVStartup[DML2_MAX_PLANES];
906 	unsigned int DSTYAfterScaler[DML2_MAX_PLANES];
907 	unsigned int DSTXAfterScaler[DML2_MAX_PLANES];
908 	struct dml2_core_internal_SOCParametersList mSOCParameters;
909 	struct dml2_core_internal_DmlPipe myPipe;
910 	struct dml2_core_internal_DmlPipe SurfParameters[DML2_MAX_PLANES];
911 	unsigned int TotalNumberOfActiveWriteback;
912 	unsigned int MaximumSwathWidthSupportLuma;
913 	unsigned int MaximumSwathWidthSupportChroma;
914 	bool MPCCombineMethodAsNeededForPStateChangeAndVoltage;
915 	bool MPCCombineMethodAsPossible;
916 	bool TotalAvailablePipesSupportNoDSC;
917 	unsigned int NumberOfDPPNoDSC;
918 	enum dml2_odm_mode ODMModeNoDSC;
919 	double RequiredDISPCLKPerSurfaceNoDSC;
920 	bool TotalAvailablePipesSupportDSC;
921 	unsigned int NumberOfDPPDSC;
922 	enum dml2_odm_mode ODMModeDSC;
923 	double RequiredDISPCLKPerSurfaceDSC;
924 	double BWOfNonCombinedSurfaceOfMaximumBandwidth;
925 	unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth;
926 	unsigned int TotalNumberOfActiveOTG;
927 	unsigned int TotalNumberOfActiveHDMIFRL;
928 	unsigned int TotalNumberOfActiveDP2p0;
929 	unsigned int TotalNumberOfActiveDP2p0Outputs;
930 	unsigned int TotalSlots;
931 	unsigned int DSCFormatFactor;
932 	unsigned int TotalDSCUnitsRequired;
933 	unsigned int ReorderingBytes;
934 	bool ImmediateFlipRequired;
935 	bool FullFrameMALLPStateMethod;
936 	bool SubViewportMALLPStateMethod;
937 	bool PhantomPipeMALLPStateMethod;
938 	bool SubViewportMALLRefreshGreaterThan120Hz;
939 
940 	double HostVMInefficiencyFactor;
941 	double HostVMInefficiencyFactorPrefetch;
942 	unsigned int MaxVStartup;
943 	double PixelClockBackEndFactor;
944 	unsigned int NumDSCUnitRequired;
945 
946 	double Tvm_trips[DML2_MAX_PLANES];
947 	double Tr0_trips[DML2_MAX_PLANES];
948 	double Tvm_trips_flip[DML2_MAX_PLANES];
949 	double Tr0_trips_flip[DML2_MAX_PLANES];
950 	double Tvm_trips_flip_rounded[DML2_MAX_PLANES];
951 	double Tr0_trips_flip_rounded[DML2_MAX_PLANES];
952 	unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES];
953 
954 	unsigned int vmpg_width_y[DML2_MAX_PLANES];
955 	unsigned int vmpg_height_y[DML2_MAX_PLANES];
956 	unsigned int vmpg_width_c[DML2_MAX_PLANES];
957 	unsigned int vmpg_height_c[DML2_MAX_PLANES];
958 	unsigned int full_swath_bytes_l[DML2_MAX_PLANES];
959 	unsigned int full_swath_bytes_c[DML2_MAX_PLANES];
960 
961 	unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES];
962 	unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES];
963 	unsigned int tdlut_row_bytes[DML2_MAX_PLANES];
964 	unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES];
965 	double tdlut_opt_time[DML2_MAX_PLANES];
966 	double tdlut_drain_time[DML2_MAX_PLANES];
967 	unsigned int tdlut_bytes_to_deliver[DML2_MAX_PLANES];
968 	unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES];
969 
970 	unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES];
971 	unsigned int cursor_bytes_per_line[DML2_MAX_PLANES];
972 	unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES];
973 	unsigned int cursor_bytes[DML2_MAX_PLANES];
974 	bool stream_visited[DML2_MAX_PLANES];
975 
976 	unsigned int pstate_bytes_required_l[DML2_MAX_PLANES];
977 	unsigned int pstate_bytes_required_c[DML2_MAX_PLANES];
978 
979 	double prefetch_sw_bytes[DML2_MAX_PLANES];
980 	double Tpre_rounded[DML2_MAX_PLANES];
981 	double Tpre_oto[DML2_MAX_PLANES];
982 	bool recalc_prefetch_schedule;
983 	bool recalc_prefetch_done;
984 	double impacted_dst_y_pre[DML2_MAX_PLANES];
985 	double line_times[DML2_MAX_PLANES];
986 	enum dml2_source_format_class pixel_format[DML2_MAX_PLANES];
987 	unsigned int lb_source_lines_l[DML2_MAX_PLANES];
988 	unsigned int lb_source_lines_c[DML2_MAX_PLANES];
989 	double prefetch_swath_time_us[DML2_MAX_PLANES];
990 };
991 
992 struct dml2_core_calcs_mode_programming_locals {
993 	double PixelClockBackEnd[DML2_MAX_PLANES];
994 	double OutputBpp[DML2_MAX_PLANES];
995 	unsigned int num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg
996 	unsigned int MaxTotalDETInKByte;
997 	unsigned int NomDETInKByte;
998 	unsigned int MinCompressedBufferSizeInKByte;
999 	double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state
1000 
1001 	double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
1002 	double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];
1003 	double surface_dummy_bw0[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];
1004 	unsigned int dummy_integer_array[2][DML2_MAX_PLANES];
1005 	enum dml2_output_encoder_class dummy_output_encoder_array[DML2_MAX_PLANES];
1006 	double dummy_single_array[2][DML2_MAX_PLANES];
1007 	unsigned int dummy_long_array[4][DML2_MAX_PLANES];
1008 	bool dummy_boolean_array[2][DML2_MAX_PLANES];
1009 	bool dummy_boolean[2];
1010 	double dummy_single[2];
1011 	struct dml2_core_internal_watermarks dummy_watermark;
1012 
1013 	unsigned int DSCFormatFactor;
1014 	struct dml2_core_internal_DmlPipe SurfaceParameters[DML2_MAX_PLANES];
1015 	unsigned int ReorderingBytes;
1016 	double HostVMInefficiencyFactor;
1017 	double HostVMInefficiencyFactorPrefetch;
1018 	unsigned int TotalDCCActiveDPP;
1019 	unsigned int TotalActiveDPP;
1020 	unsigned int Total3dlutActive;
1021 	unsigned int MaxVStartupLines[DML2_MAX_PLANES]; /// <brief more like vblank for the plane's OTG
1022 	bool immediate_flip_required; // any pipes need immediate flip
1023 	bool DestinationLineTimesForPrefetchLessThan2;
1024 	bool VRatioPrefetchMoreThanMax;
1025 	double MaxTotalRDBandwidthNotIncludingMALLPrefetch;
1026 	struct dml2_core_internal_SOCParametersList mmSOCParameters;
1027 	double Tvstartup_margin;
1028 	double dlg_vblank_start;
1029 	double LSetup;
1030 	double blank_lines_remaining;
1031 	double TotalWRBandwidth;
1032 	double WRBandwidth;
1033 	struct dml2_core_internal_DmlPipe myPipe;
1034 	double PixelClockBackEndFactor;
1035 	unsigned int vmpg_width_y[DML2_MAX_PLANES];
1036 	unsigned int vmpg_height_y[DML2_MAX_PLANES];
1037 	unsigned int vmpg_width_c[DML2_MAX_PLANES];
1038 	unsigned int vmpg_height_c[DML2_MAX_PLANES];
1039 	unsigned int full_swath_bytes_l[DML2_MAX_PLANES];
1040 	unsigned int full_swath_bytes_c[DML2_MAX_PLANES];
1041 
1042 	unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];
1043 	unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];
1044 	unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];
1045 	unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];
1046 
1047 	unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES];
1048 	unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES];
1049 	unsigned int tdlut_row_bytes[DML2_MAX_PLANES];
1050 	unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES];
1051 	double tdlut_opt_time[DML2_MAX_PLANES];
1052 	double tdlut_drain_time[DML2_MAX_PLANES];
1053 	unsigned int tdlut_bytes_to_deliver[DML2_MAX_PLANES];
1054 	unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES];
1055 
1056 	unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES];
1057 	unsigned int cursor_bytes_per_line[DML2_MAX_PLANES];
1058 	unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES];
1059 	unsigned int cursor_bytes[DML2_MAX_PLANES];
1060 
1061 	double Tvm_trips[DML2_MAX_PLANES];
1062 	double Tr0_trips[DML2_MAX_PLANES];
1063 	double Tvm_trips_flip[DML2_MAX_PLANES];
1064 	double Tr0_trips_flip[DML2_MAX_PLANES];
1065 	double Tvm_trips_flip_rounded[DML2_MAX_PLANES];
1066 	double Tr0_trips_flip_rounded[DML2_MAX_PLANES];
1067 	unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES];
1068 
1069 	unsigned int pstate_bytes_required_l[DML2_MAX_PLANES];
1070 	unsigned int pstate_bytes_required_c[DML2_MAX_PLANES];
1071 
1072 	double prefetch_sw_bytes[DML2_MAX_PLANES];
1073 	double Tpre_rounded[DML2_MAX_PLANES];
1074 	double Tpre_oto[DML2_MAX_PLANES];
1075 	bool recalc_prefetch_schedule;
1076 	double impacted_dst_y_pre[DML2_MAX_PLANES];
1077 	double line_times[DML2_MAX_PLANES];
1078 	enum dml2_source_format_class pixel_format[DML2_MAX_PLANES];
1079 	unsigned int lb_source_lines_l[DML2_MAX_PLANES];
1080 	unsigned int lb_source_lines_c[DML2_MAX_PLANES];
1081 };
1082 
1083 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals {
1084 	double ActiveDRAMClockChangeLatencyMargin[DML2_MAX_PLANES];
1085 	double ActiveFCLKChangeLatencyMargin[DML2_MAX_PLANES];
1086 	double USRRetrainingLatencyMargin[DML2_MAX_PLANES];
1087 	double g6_temp_read_latency_margin[DML2_MAX_PLANES];
1088 	double temp_read_or_ppt_latency_margin[DML2_MAX_PLANES];
1089 
1090 	double EffectiveLBLatencyHidingY;
1091 	double EffectiveLBLatencyHidingC;
1092 	double LinesInDETY[DML2_MAX_PLANES];
1093 	double LinesInDETC[DML2_MAX_PLANES];
1094 	unsigned int LinesInDETYRoundedDownToSwath[DML2_MAX_PLANES];
1095 	unsigned int LinesInDETCRoundedDownToSwath[DML2_MAX_PLANES];
1096 	double FullDETBufferingTimeY;
1097 	double FullDETBufferingTimeC;
1098 	double WritebackDRAMClockChangeLatencyMargin;
1099 	double WritebackFCLKChangeLatencyMargin;
1100 	double WritebackLatencyHiding;
1101 
1102 	unsigned int TotalActiveWriteback;
1103 	unsigned int LBLatencyHidingSourceLinesY[DML2_MAX_PLANES];
1104 	unsigned int LBLatencyHidingSourceLinesC[DML2_MAX_PLANES];
1105 	double TotalPixelBW;
1106 	double EffectiveDETBufferSizeY;
1107 	double ActiveClockChangeLatencyHidingY;
1108 	double ActiveClockChangeLatencyHidingC;
1109 	double ActiveClockChangeLatencyHiding;
1110 	unsigned int dst_y_pstate;
1111 	unsigned int src_y_pstate_l;
1112 	unsigned int src_y_pstate_c;
1113 	unsigned int src_y_ahead_l;
1114 	unsigned int src_y_ahead_c;
1115 	unsigned int sub_vp_lines_l;
1116 	unsigned int sub_vp_lines_c;
1117 
1118 };
1119 
1120 struct dml2_core_calcs_CalculateVMRowAndSwath_locals {
1121 	unsigned int PTEBufferSizeInRequestsForLuma[DML2_MAX_PLANES];
1122 	unsigned int PTEBufferSizeInRequestsForChroma[DML2_MAX_PLANES];
1123 	unsigned int vm_bytes_l;
1124 	unsigned int vm_bytes_c;
1125 	unsigned int PixelPTEBytesPerRowY[DML2_MAX_PLANES];
1126 	unsigned int PixelPTEBytesPerRowC[DML2_MAX_PLANES];
1127 	unsigned int PixelPTEBytesPerRowStorageY[DML2_MAX_PLANES];
1128 	unsigned int PixelPTEBytesPerRowStorageC[DML2_MAX_PLANES];
1129 	unsigned int PixelPTEBytesPerRowY_one_row_per_frame[DML2_MAX_PLANES];
1130 	unsigned int PixelPTEBytesPerRowC_one_row_per_frame[DML2_MAX_PLANES];
1131 	unsigned int dpte_row_width_luma_ub_one_row_per_frame[DML2_MAX_PLANES];
1132 	unsigned int dpte_row_height_luma_one_row_per_frame[DML2_MAX_PLANES];
1133 	unsigned int dpte_row_width_chroma_ub_one_row_per_frame[DML2_MAX_PLANES];
1134 	unsigned int dpte_row_height_chroma_one_row_per_frame[DML2_MAX_PLANES];
1135 	bool one_row_per_frame_fits_in_buffer[DML2_MAX_PLANES];
1136 	unsigned int HostVMDynamicLevels;
1137 	unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];
1138 	unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];
1139 };
1140 
1141 struct dml2_core_calcs_CalculateVMRowAndSwath_params {
1142 	const struct dml2_display_cfg *display_cfg;
1143 	unsigned int NumberOfActiveSurfaces;
1144 	struct dml2_core_internal_DmlPipe *myPipe;
1145 	unsigned int *SurfaceSizeInMALL;
1146 	unsigned int PTEBufferSizeInRequestsLuma;
1147 	unsigned int PTEBufferSizeInRequestsChroma;
1148 	unsigned int MALLAllocatedForDCN;
1149 	unsigned int *SwathWidthY;
1150 	unsigned int *SwathWidthC;
1151 	unsigned int HostVMMinPageSize;
1152 	unsigned int DCCMetaBufferSizeBytes;
1153 	bool mrq_present;
1154 
1155 	// Output
1156 	bool *PTEBufferSizeNotExceeded;
1157 	bool *DCCMetaBufferSizeNotExceeded;
1158 
1159 	unsigned int *dpte_row_width_luma_ub;
1160 	unsigned int *dpte_row_width_chroma_ub;
1161 	unsigned int *dpte_row_height_luma;
1162 	unsigned int *dpte_row_height_chroma;
1163 	unsigned int *dpte_row_height_linear_luma; // VBA_DELTA
1164 	unsigned int *dpte_row_height_linear_chroma; // VBA_DELTA
1165 
1166 	unsigned int *vm_group_bytes;
1167 	unsigned int *dpte_group_bytes;
1168 	unsigned int *PixelPTEReqWidthY;
1169 	unsigned int *PixelPTEReqHeightY;
1170 	unsigned int *PTERequestSizeY;
1171 	unsigned int *vmpg_width_y;
1172 	unsigned int *vmpg_height_y;
1173 
1174 	unsigned int *PixelPTEReqWidthC;
1175 	unsigned int *PixelPTEReqHeightC;
1176 	unsigned int *PTERequestSizeC;
1177 	unsigned int *vmpg_width_c;
1178 	unsigned int *vmpg_height_c;
1179 
1180 	unsigned int *dpde0_bytes_per_frame_ub_l;
1181 	unsigned int *dpde0_bytes_per_frame_ub_c;
1182 
1183 	unsigned int *PrefetchSourceLinesY;
1184 	unsigned int *PrefetchSourceLinesC;
1185 	unsigned int *VInitPreFillY;
1186 	unsigned int *VInitPreFillC;
1187 	unsigned int *MaxNumSwathY;
1188 	unsigned int *MaxNumSwathC;
1189 	double *dpte_row_bw;
1190 	unsigned int *PixelPTEBytesPerRow;
1191 	unsigned int *dpte_row_bytes_per_row_l;
1192 	unsigned int *dpte_row_bytes_per_row_c;
1193 	unsigned int *vm_bytes;
1194 	bool *use_one_row_for_frame;
1195 	bool *use_one_row_for_frame_flip;
1196 	bool *is_using_mall_for_ss;
1197 	bool *PTE_BUFFER_MODE;
1198 	unsigned int *BIGK_FRAGMENT_SIZE;
1199 
1200 	// MRQ
1201 	unsigned int *meta_req_width_luma;
1202 	unsigned int *meta_req_height_luma;
1203 	unsigned int *meta_row_width_luma;
1204 	unsigned int *meta_row_height_luma;
1205 	unsigned int *meta_pte_bytes_per_frame_ub_l;
1206 
1207 	unsigned int *meta_req_width_chroma;
1208 	unsigned int *meta_req_height_chroma;
1209 	unsigned int *meta_row_width_chroma;
1210 	unsigned int *meta_row_height_chroma;
1211 	unsigned int *meta_pte_bytes_per_frame_ub_c;
1212 	double *meta_row_bw;
1213 	unsigned int *meta_row_bytes;
1214 	unsigned int *meta_row_bytes_per_row_ub_l;
1215 	unsigned int *meta_row_bytes_per_row_ub_c;
1216 };
1217 
1218 struct dml2_core_calcs_CalculatePrefetchSchedule_locals {
1219 	bool NoTimeToPrefetch;
1220 	unsigned int DPPCycles;
1221 	unsigned int DISPCLKCycles;
1222 	double DSTTotalPixelsAfterScaler;
1223 	double LineTime;
1224 	double dst_y_prefetch_equ;
1225 	double prefetch_bw_oto;
1226 	double per_pipe_vactive_sw_bw;
1227 	double Tvm_oto;
1228 	double Tr0_oto;
1229 	double Tvm_oto_lines;
1230 	double Tr0_oto_lines;
1231 	double dst_y_prefetch_oto;
1232 	double TimeForFetchingVM;
1233 	double TimeForFetchingRowInVBlank;
1234 	double LinesToRequestPrefetchPixelData;
1235 	unsigned int HostVMDynamicLevelsTrips;
1236 	double trip_to_mem;
1237 	double Tvm_trips_rounded;
1238 	double Tr0_trips_rounded;
1239 	double max_Tsw;
1240 	double Lsw_oto;
1241 	double prefetch_bw_equ;
1242 	double Tvm_equ;
1243 	double Tr0_equ;
1244 	double Tdmbf;
1245 	double Tdmec;
1246 	double Tdmsks;
1247 	double total_row_bytes;
1248 	double prefetch_bw_pr;
1249 	double bytes_pp;
1250 	double dep_bytes;
1251 	double min_Lsw_oto;
1252 	double min_Lsw_equ;
1253 	double Tsw_est1;
1254 	double Tsw_est2;
1255 	double Tsw_est3;
1256 	double prefetch_bw1;
1257 	double prefetch_bw2;
1258 	double prefetch_bw3;
1259 	double prefetch_bw4;
1260 	double dst_y_prefetch_equ_impacted;
1261 
1262 	double TWait_p;
1263 	unsigned int cursor_prefetch_bytes;
1264 };
1265 
1266 struct dml2_core_shared_calculate_det_buffer_size_params {
1267 	const struct dml2_display_cfg *display_cfg;
1268 	bool ForceSingleDPP;
1269 	unsigned int NumberOfActiveSurfaces;
1270 	bool UnboundedRequestEnabled;
1271 	unsigned int nomDETInKByte;
1272 	unsigned int MaxTotalDETInKByte;
1273 	unsigned int ConfigReturnBufferSizeInKByte;
1274 	unsigned int MinCompressedBufferSizeInKByte;
1275 	unsigned int ConfigReturnBufferSegmentSizeInkByte;
1276 	unsigned int CompressedBufferSegmentSizeInkByte;
1277 	double *ReadBandwidthLuma;
1278 	double *ReadBandwidthChroma;
1279 	unsigned int *full_swath_bytes_l;
1280 	unsigned int *full_swath_bytes_c;
1281 	unsigned int *swath_time_value_us;
1282 	unsigned int *DPPPerSurface;
1283 	bool TryToAllocateForWriteLatency;
1284 	unsigned int bestEffortMinActiveLatencyHidingUs;
1285 
1286 	// Output
1287 	unsigned int *DETBufferSizeInKByte;
1288 	unsigned int *CompressedBufferSizeInkByte;
1289 };
1290 
1291 struct dml2_core_shared_calculate_vm_and_row_bytes_params {
1292 	bool ViewportStationary;
1293 	bool DCCEnable;
1294 	unsigned int NumberOfDPPs;
1295 	unsigned int BlockHeight256Bytes;
1296 	unsigned int BlockWidth256Bytes;
1297 	enum dml2_source_format_class SourcePixelFormat;
1298 	unsigned int SurfaceTiling;
1299 	unsigned int BytePerPixel;
1300 	enum dml2_rotation_angle RotationAngle;
1301 	unsigned int SwathWidth; // per pipe
1302 	unsigned int ViewportHeight;
1303 	unsigned int ViewportXStart;
1304 	unsigned int ViewportYStart;
1305 	bool GPUVMEnable;
1306 	unsigned int GPUVMMaxPageTableLevels;
1307 	unsigned int GPUVMMinPageSizeKBytes;
1308 	unsigned int PTEBufferSizeInRequests;
1309 	unsigned int Pitch;
1310 	unsigned int MacroTileWidth;
1311 	unsigned int MacroTileHeight;
1312 	bool is_phantom;
1313 	unsigned int DCCMetaPitch;
1314 	bool mrq_present;
1315 
1316 	// Output
1317 	unsigned int *PixelPTEBytesPerRow; // for bandwidth calculation
1318 	unsigned int *PixelPTEBytesPerRowStorage; // for PTE buffer size check
1319 	unsigned int *dpte_row_width_ub;
1320 	unsigned int *dpte_row_height;
1321 	unsigned int *dpte_row_height_linear;
1322 	unsigned int *PixelPTEBytesPerRow_one_row_per_frame;
1323 	unsigned int *dpte_row_width_ub_one_row_per_frame;
1324 	unsigned int *dpte_row_height_one_row_per_frame;
1325 	unsigned int *vmpg_width;
1326 	unsigned int *vmpg_height;
1327 	unsigned int *PixelPTEReqWidth;
1328 	unsigned int *PixelPTEReqHeight;
1329 	unsigned int *PTERequestSize;
1330 	unsigned int *dpde0_bytes_per_frame_ub;
1331 
1332 	unsigned int *meta_row_bytes;
1333 	unsigned int *MetaRequestWidth;
1334 	unsigned int *MetaRequestHeight;
1335 	unsigned int *meta_row_width;
1336 	unsigned int *meta_row_height;
1337 	unsigned int *meta_pte_bytes_per_frame_ub;
1338 };
1339 
1340 struct dml2_core_shared_CalculateSwathAndDETConfiguration_locals {
1341 	unsigned int MaximumSwathHeightY[DML2_MAX_PLANES];
1342 	unsigned int MaximumSwathHeightC[DML2_MAX_PLANES];
1343 	unsigned int RoundedUpSwathSizeBytesY[DML2_MAX_PLANES];
1344 	unsigned int RoundedUpSwathSizeBytesC[DML2_MAX_PLANES];
1345 	unsigned int SwathWidthSingleDPP[DML2_MAX_PLANES];
1346 	unsigned int SwathWidthSingleDPPChroma[DML2_MAX_PLANES];
1347 	unsigned int SwathTimeValueUs[DML2_MAX_PLANES];
1348 
1349 	struct dml2_core_shared_calculate_det_buffer_size_params calculate_det_buffer_size_params;
1350 };
1351 
1352 struct dml2_core_shared_TruncToValidBPP_locals {
1353 };
1354 
1355 struct dml2_core_shared_CalculateDETBufferSize_locals {
1356 	unsigned int DETBufferSizePoolInKByte;
1357 	unsigned int NextDETBufferPieceInKByte;
1358 	unsigned int NextSurfaceToAssignDETPiece;
1359 	double TotalBandwidth;
1360 	double BandwidthOfSurfacesNotAssignedDETPiece;
1361 	unsigned int max_minDET;
1362 	unsigned int minDET;
1363 	unsigned int minDET_pipe;
1364 	unsigned int TotalBandwidthPerStream[DML2_MAX_PLANES];
1365 	unsigned int TotalPixelRate;
1366 	unsigned int DETBudgetPerStream[DML2_MAX_PLANES];
1367 	unsigned int RemainingDETBudgetPerStream[DML2_MAX_PLANES];
1368 	unsigned int IdealDETBudget, DeltaDETBudget;
1369 	unsigned int ResidualDETAfterRounding;
1370 };
1371 
1372 struct dml2_core_shared_get_urgent_bandwidth_required_locals {
1373 	double required_bandwidth_mbps;
1374 	double required_bandwidth_mbps_this_surface;
1375 	double adj_factor_p0;
1376 	double adj_factor_p1;
1377 	double adj_factor_cur;
1378 	double adj_factor_p0_pre;
1379 	double adj_factor_p1_pre;
1380 	double adj_factor_cur_pre;
1381 	double per_plane_flip_bw[DML2_MAX_PLANES];
1382 	double mall_svp_prefetch_factor;
1383 	double tmp_nom_adj_factor_p0;
1384 	double tmp_nom_adj_factor_p1;
1385 	double tmp_pref_adj_factor_p0;
1386 	double tmp_pref_adj_factor_p1;
1387 	double vm_row_bw;
1388 	double flip_and_active_bw;
1389 	double flip_and_prefetch_bw;
1390 	double flip_and_prefetch_bw_oto;
1391 	double active_and_excess_bw;
1392 };
1393 
1394 struct dml2_core_shared_calculate_peak_bandwidth_required_locals {
1395 	double unity_array[DML2_MAX_PLANES];
1396 	double zero_array[DML2_MAX_PLANES];
1397 	double surface_dummy_bw[DML2_MAX_PLANES];
1398 };
1399 
1400 struct dml2_core_shared_CalculateFlipSchedule_locals {
1401 	double min_row_time;
1402 	double Tvm_flip;
1403 	double Tr0_flip;
1404 	double ImmediateFlipBW;
1405 	double dpte_row_bytes;
1406 	double min_row_height;
1407 	double min_row_height_chroma;
1408 	double max_flip_time;
1409 	double lb_flip_bw;
1410 	double hvm_scaled_vm_bytes;
1411 	double num_rows;
1412 	double hvm_scaled_row_bytes;
1413 	double hvm_scaled_vm_row_bytes;
1414 	bool dual_plane;
1415 };
1416 
1417 struct dml2_core_shared_rq_dlg_get_dlg_reg_locals {
1418 	unsigned int plane_idx;
1419 	enum dml2_source_format_class source_format;
1420 	const struct dml2_timing_cfg *timing;
1421 	bool dual_plane;
1422 	enum dml2_odm_mode odm_mode;
1423 
1424 	unsigned int htotal;
1425 	unsigned int hactive;
1426 	unsigned int hblank_end;
1427 	unsigned int vblank_end;
1428 	bool interlaced;
1429 	double pclk_freq_in_mhz;
1430 	double refclk_freq_in_mhz;
1431 	double ref_freq_to_pix_freq;
1432 
1433 	unsigned int num_active_pipes;
1434 	unsigned int first_pipe_idx_in_plane;
1435 	unsigned int pipe_idx_in_combine;
1436 	unsigned int odm_combine_factor;
1437 
1438 	double min_ttu_vblank;
1439 	unsigned int min_dst_y_next_start;
1440 
1441 	unsigned int vready_after_vcount0;
1442 
1443 	unsigned int dst_x_after_scaler;
1444 	unsigned int dst_y_after_scaler;
1445 
1446 	double dst_y_prefetch;
1447 	double dst_y_per_vm_vblank;
1448 	double dst_y_per_row_vblank;
1449 	double dst_y_per_vm_flip;
1450 	double dst_y_per_row_flip;
1451 
1452 	double max_dst_y_per_vm_vblank;
1453 	double max_dst_y_per_row_vblank;
1454 
1455 	double vratio_pre_l;
1456 	double vratio_pre_c;
1457 
1458 	double refcyc_per_line_delivery_pre_l;
1459 	double refcyc_per_line_delivery_l;
1460 
1461 	double refcyc_per_line_delivery_pre_c;
1462 	double refcyc_per_line_delivery_c;
1463 
1464 	double refcyc_per_req_delivery_pre_l;
1465 	double refcyc_per_req_delivery_l;
1466 
1467 	double refcyc_per_req_delivery_pre_c;
1468 	double refcyc_per_req_delivery_c;
1469 
1470 	double dst_y_per_pte_row_nom_l;
1471 	double dst_y_per_pte_row_nom_c;
1472 	double refcyc_per_pte_group_nom_l;
1473 	double refcyc_per_pte_group_nom_c;
1474 	double refcyc_per_pte_group_vblank_l;
1475 	double refcyc_per_pte_group_vblank_c;
1476 	double refcyc_per_pte_group_flip_l;
1477 	double refcyc_per_pte_group_flip_c;
1478 	double refcyc_per_tdlut_group;
1479 
1480 	double dst_y_per_meta_row_nom_l;
1481 	double dst_y_per_meta_row_nom_c;
1482 	double refcyc_per_meta_chunk_nom_l;
1483 	double refcyc_per_meta_chunk_nom_c;
1484 	double refcyc_per_meta_chunk_vblank_l;
1485 	double refcyc_per_meta_chunk_vblank_c;
1486 	double refcyc_per_meta_chunk_flip_l;
1487 	double refcyc_per_meta_chunk_flip_c;
1488 };
1489 
1490 struct dml2_core_shared_CalculateMetaAndPTETimes_params {
1491 	struct dml2_core_internal_scratch *scratch;
1492 	const struct dml2_display_cfg *display_cfg;
1493 	unsigned int NumberOfActiveSurfaces;
1494 	bool *use_one_row_for_frame;
1495 	double *dst_y_per_row_vblank;
1496 	double *dst_y_per_row_flip;
1497 	unsigned int *BytePerPixelY;
1498 	unsigned int *BytePerPixelC;
1499 	unsigned int *dpte_row_height;
1500 	unsigned int *dpte_row_height_chroma;
1501 	unsigned int *dpte_group_bytes;
1502 	unsigned int *PTERequestSizeY;
1503 	unsigned int *PTERequestSizeC;
1504 	unsigned int *PixelPTEReqWidthY;
1505 	unsigned int *PixelPTEReqHeightY;
1506 	unsigned int *PixelPTEReqWidthC;
1507 	unsigned int *PixelPTEReqHeightC;
1508 	unsigned int *dpte_row_width_luma_ub;
1509 	unsigned int *dpte_row_width_chroma_ub;
1510 	unsigned int *tdlut_groups_per_2row_ub;
1511 	bool mrq_present;
1512 	unsigned int MetaChunkSize;
1513 	unsigned int MinMetaChunkSizeBytes;
1514 	unsigned int *meta_row_width;
1515 	unsigned int *meta_row_width_chroma;
1516 	unsigned int *meta_row_height;
1517 	unsigned int *meta_row_height_chroma;
1518 	unsigned int *meta_req_width;
1519 	unsigned int *meta_req_width_chroma;
1520 	unsigned int *meta_req_height;
1521 	unsigned int *meta_req_height_chroma;
1522 
1523 	// Output
1524 	double *time_per_tdlut_group;
1525 	double *DST_Y_PER_PTE_ROW_NOM_L;
1526 	double *DST_Y_PER_PTE_ROW_NOM_C;
1527 	double *time_per_pte_group_nom_luma;
1528 	double *time_per_pte_group_vblank_luma;
1529 	double *time_per_pte_group_flip_luma;
1530 	double *time_per_pte_group_nom_chroma;
1531 	double *time_per_pte_group_vblank_chroma;
1532 	double *time_per_pte_group_flip_chroma;
1533 
1534 	double *DST_Y_PER_META_ROW_NOM_L;
1535 	double *DST_Y_PER_META_ROW_NOM_C;
1536 
1537 	double *TimePerMetaChunkNominal;
1538 	double *TimePerChromaMetaChunkNominal;
1539 	double *TimePerMetaChunkVBlank;
1540 	double *TimePerChromaMetaChunkVBlank;
1541 	double *TimePerMetaChunkFlip;
1542 	double *TimePerChromaMetaChunkFlip;
1543 };
1544 
1545 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params {
1546 	const struct dml2_display_cfg *display_cfg;
1547 	bool USRRetrainingRequired;
1548 	unsigned int NumberOfActiveSurfaces;
1549 	unsigned int MaxLineBufferLines;
1550 	unsigned int LineBufferSize;
1551 	unsigned int WritebackInterfaceBufferSize;
1552 	double DCFCLK;
1553 	double ReturnBW;
1554 	bool SynchronizeTimings;
1555 	bool SynchronizeDRRDisplaysForUCLKPStateChange;
1556 	unsigned int *dpte_group_bytes;
1557 	struct dml2_core_internal_SOCParametersList mmSOCParameters;
1558 	unsigned int WritebackChunkSize;
1559 	double SOCCLK;
1560 	double DCFClkDeepSleep;
1561 	unsigned int *DETBufferSizeY;
1562 	unsigned int *DETBufferSizeC;
1563 	unsigned int *SwathHeightY;
1564 	unsigned int *SwathHeightC;
1565 	unsigned int *SwathWidthY;
1566 	unsigned int *SwathWidthC;
1567 	unsigned int *DPPPerSurface;
1568 	double *BytePerPixelDETY;
1569 	double *BytePerPixelDETC;
1570 	unsigned int *DSTXAfterScaler;
1571 	unsigned int *DSTYAfterScaler;
1572 	bool UnboundedRequestEnabled;
1573 	unsigned int CompressedBufferSizeInkByte;
1574 	bool max_outstanding_when_urgent_expected;
1575 	unsigned int max_outstanding_requests;
1576 	unsigned int max_request_size_bytes;
1577 	unsigned int *meta_row_height_l;
1578 	unsigned int *meta_row_height_c;
1579 
1580 	// Output
1581 	struct dml2_core_internal_watermarks *Watermark;
1582 	enum dml2_pstate_change_support *DRAMClockChangeSupport;
1583 	bool *global_dram_clock_change_supported;
1584 	double *MaxActiveDRAMClockChangeLatencySupported;
1585 	unsigned int *SubViewportLinesNeededInMALL;
1586 	enum dml2_pstate_change_support *FCLKChangeSupport;
1587 	bool *global_fclk_change_supported;
1588 	double *MaxActiveFCLKChangeLatencySupported;
1589 	bool *USRRetrainingSupport;
1590 	double *VActiveLatencyHidingMargin;
1591 	double *VActiveLatencyHidingUs;
1592 	bool *g6_temp_read_support;
1593 	bool *temp_read_or_ppt_support;
1594 };
1595 
1596 
1597 struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params {
1598 	const struct dml2_display_cfg *display_cfg;
1599 	unsigned int ConfigReturnBufferSizeInKByte;
1600 	unsigned int MaxTotalDETInKByte;
1601 	unsigned int MinCompressedBufferSizeInKByte;
1602 	unsigned int rob_buffer_size_kbytes;
1603 	unsigned int pixel_chunk_size_kbytes;
1604 	bool ForceSingleDPP;
1605 	unsigned int NumberOfActiveSurfaces;
1606 	unsigned int nomDETInKByte;
1607 	unsigned int ConfigReturnBufferSegmentSizeInkByte;
1608 	unsigned int CompressedBufferSegmentSizeInkByte;
1609 	double *ReadBandwidthLuma;
1610 	double *ReadBandwidthChroma;
1611 	double *MaximumSwathWidthLuma;
1612 	double *MaximumSwathWidthChroma;
1613 	unsigned int *Read256BytesBlockHeightY;
1614 	unsigned int *Read256BytesBlockHeightC;
1615 	unsigned int *Read256BytesBlockWidthY;
1616 	unsigned int *Read256BytesBlockWidthC;
1617 	bool *surf_linear128_l;
1618 	bool *surf_linear128_c;
1619 	enum dml2_odm_mode *ODMMode;
1620 	unsigned int *BytePerPixY;
1621 	unsigned int *BytePerPixC;
1622 	double *BytePerPixDETY;
1623 	double *BytePerPixDETC;
1624 	unsigned int *DPPPerSurface;
1625 	bool mrq_present;
1626 
1627 	// output
1628 	unsigned int *req_per_swath_ub_l;
1629 	unsigned int *req_per_swath_ub_c;
1630 	unsigned int *swath_width_luma_ub;
1631 	unsigned int *swath_width_chroma_ub;
1632 	unsigned int *SwathWidth;
1633 	unsigned int *SwathWidthChroma;
1634 	unsigned int *SwathHeightY;
1635 	unsigned int *SwathHeightC;
1636 	unsigned int *request_size_bytes_luma;
1637 	unsigned int *request_size_bytes_chroma;
1638 	unsigned int *DETBufferSizeInKByte;
1639 	unsigned int *DETBufferSizeY;
1640 	unsigned int *DETBufferSizeC;
1641 	unsigned int *full_swath_bytes_l;
1642 	unsigned int *full_swath_bytes_c;
1643 	bool *UnboundedRequestEnabled;
1644 	unsigned int *compbuf_reserved_space_64b;
1645 	unsigned int *CompressedBufferSizeInkByte;
1646 	bool *ViewportSizeSupportPerSurface;
1647 	bool *ViewportSizeSupport;
1648 	bool *hw_debug5;
1649 
1650 	struct dml2_core_shared_calculation_funcs *funcs;
1651 };
1652 
1653 struct dml2_core_calcs_CalculateStutterEfficiency_locals {
1654 	double DETBufferingTimeY;
1655 	double SwathWidthYCriticalSurface;
1656 	double SwathHeightYCriticalSurface;
1657 	double VActiveTimeCriticalSurface;
1658 	double FrameTimeCriticalSurface;
1659 	unsigned int BytePerPixelYCriticalSurface;
1660 	unsigned int DETBufferSizeYCriticalSurface;
1661 	double MinTTUVBlankCriticalSurface;
1662 	unsigned int BlockWidth256BytesYCriticalSurface;
1663 	bool SinglePlaneCriticalSurface;
1664 	bool SinglePipeCriticalSurface;
1665 	double TotalCompressedReadBandwidth;
1666 	double TotalRowReadBandwidth;
1667 	double AverageDCCCompressionRate;
1668 	double EffectiveCompressedBufferSize;
1669 	double PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer;
1670 	double StutterBurstTime;
1671 	unsigned int TotalActiveWriteback;
1672 	double LinesInDETY;
1673 	double LinesInDETYRoundedDownToSwath;
1674 	double MaximumEffectiveCompressionLuma;
1675 	double MaximumEffectiveCompressionChroma;
1676 	double TotalZeroSizeRequestReadBandwidth;
1677 	double TotalZeroSizeCompressedReadBandwidth;
1678 	double AverageDCCZeroSizeFraction;
1679 	double AverageZeroSizeCompressionRate;
1680 	bool stream_visited[DML2_MAX_PLANES];
1681 };
1682 
1683 struct dml2_core_calcs_CalculateStutterEfficiency_params {
1684 	const struct dml2_display_cfg *display_cfg;
1685 	unsigned int CompressedBufferSizeInkByte;
1686 	bool UnboundedRequestEnabled;
1687 	unsigned int MetaFIFOSizeInKEntries;
1688 	unsigned int ZeroSizeBufferEntries;
1689 	unsigned int PixelChunkSizeInKByte;
1690 	unsigned int NumberOfActiveSurfaces;
1691 	unsigned int ROBBufferSizeInKByte;
1692 	double TotalDataReadBandwidth;
1693 	double DCFCLK;
1694 	double ReturnBW;
1695 	unsigned int CompbufReservedSpace64B;
1696 	unsigned int CompbufReservedSpaceZs;
1697 	bool hw_debug5;
1698 	double SRExitTime;
1699 	double SRExitZ8Time;
1700 	bool SynchronizeTimings;
1701 	double StutterEnterPlusExitWatermark;
1702 	double Z8StutterEnterPlusExitWatermark;
1703 	bool ProgressiveToInterlaceUnitInOPP;
1704 	double *MinTTUVBlank;
1705 	unsigned int *DPPPerSurface;
1706 	unsigned int *DETBufferSizeY;
1707 	unsigned int *BytePerPixelY;
1708 	double *BytePerPixelDETY;
1709 	unsigned int *SwathWidthY;
1710 	unsigned int *SwathHeightY;
1711 	unsigned int *SwathHeightC;
1712 	unsigned int *BlockHeight256BytesY;
1713 	unsigned int *BlockWidth256BytesY;
1714 	unsigned int *BlockHeight256BytesC;
1715 	unsigned int *BlockWidth256BytesC;
1716 	unsigned int *DCCYMaxUncompressedBlock;
1717 	unsigned int *DCCCMaxUncompressedBlock;
1718 	double *ReadBandwidthSurfaceLuma;
1719 	double *ReadBandwidthSurfaceChroma;
1720 	double *meta_row_bw;
1721 	double *dpte_row_bw;
1722 	bool rob_alloc_compressed;
1723 
1724 	// output
1725 	double *StutterEfficiencyNotIncludingVBlank;
1726 	double *StutterEfficiency;
1727 	unsigned int *NumberOfStutterBurstsPerFrame;
1728 	double *Z8StutterEfficiencyNotIncludingVBlank;
1729 	double *Z8StutterEfficiency;
1730 	unsigned int *Z8NumberOfStutterBurstsPerFrame;
1731 	double *StutterPeriod;
1732 	bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
1733 };
1734 
1735 struct dml2_core_calcs_CalculatePrefetchSchedule_params {
1736 	const struct dml2_display_cfg *display_cfg;
1737 	double HostVMInefficiencyFactor;
1738 	struct dml2_core_internal_DmlPipe *myPipe;
1739 	unsigned int DSCDelay;
1740 	double DPPCLKDelaySubtotalPlusCNVCFormater;
1741 	double DPPCLKDelaySCL;
1742 	double DPPCLKDelaySCLLBOnly;
1743 	double DPPCLKDelayCNVCCursor;
1744 	double DISPCLKDelaySubtotal;
1745 	unsigned int DPP_RECOUT_WIDTH;
1746 	enum dml2_output_format_class OutputFormat;
1747 	unsigned int MaxInterDCNTileRepeaters;
1748 	unsigned int VStartup;
1749 	unsigned int HostVMMinPageSize;
1750 	bool DynamicMetadataEnable;
1751 	bool DynamicMetadataVMEnabled;
1752 	unsigned int DynamicMetadataLinesBeforeActiveRequired;
1753 	unsigned int DynamicMetadataTransmittedBytes;
1754 	double UrgentLatency;
1755 	double ExtraLatencyPrefetch;
1756 	double TCalc;
1757 	unsigned int vm_bytes;
1758 	unsigned int PixelPTEBytesPerRow;
1759 	double PrefetchSourceLinesY;
1760 	unsigned int VInitPreFillY;
1761 	unsigned int MaxNumSwathY;
1762 	double PrefetchSourceLinesC;
1763 	unsigned int VInitPreFillC;
1764 	unsigned int MaxNumSwathC;
1765 	unsigned int swath_width_luma_ub;  // per-pipe
1766 	unsigned int swath_width_chroma_ub; // per-pipe
1767 	unsigned int SwathHeightY;
1768 	unsigned int SwathHeightC;
1769 	double TWait;
1770 	double Ttrip;
1771 	double Turg;
1772 	bool setup_for_tdlut;
1773 	unsigned int tdlut_pte_bytes_per_frame;
1774 	unsigned int tdlut_bytes_per_frame;
1775 	double tdlut_opt_time;
1776 	double tdlut_drain_time;
1777 
1778 	unsigned int num_cursors;
1779 	unsigned int cursor_bytes_per_chunk;
1780 	unsigned int cursor_bytes_per_line;
1781 
1782 	// MRQ
1783 	bool dcc_enable;
1784 	bool mrq_present;
1785 	unsigned int meta_row_bytes;
1786 	double mall_prefetch_sdp_overhead_factor;
1787 
1788 	double impacted_dst_y_pre;
1789 	double vactive_sw_bw_l; // per surface bw
1790 	double vactive_sw_bw_c; // per surface bw
1791 
1792 	// output
1793 	unsigned int *DSTXAfterScaler;
1794 	unsigned int *DSTYAfterScaler;
1795 	double *dst_y_prefetch;
1796 	double *dst_y_per_vm_vblank;
1797 	double *dst_y_per_row_vblank;
1798 	double *VRatioPrefetchY;
1799 	double *VRatioPrefetchC;
1800 	double *RequiredPrefetchPixelDataBWLuma;
1801 	double *RequiredPrefetchPixelDataBWChroma;
1802 	double *RequiredPrefetchBWOTO;
1803 	bool *NotEnoughTimeForDynamicMetadata;
1804 	double *Tno_bw;
1805 	double *Tno_bw_flip;
1806 	double *prefetch_vmrow_bw;
1807 	double *Tdmdl_vm;
1808 	double *Tdmdl;
1809 	double *TSetup;
1810 	double *Tpre_rounded;
1811 	double *Tpre_oto;
1812 	double *Tvm_trips;
1813 	double *Tr0_trips;
1814 	double *Tvm_trips_flip;
1815 	double *Tr0_trips_flip;
1816 	double *Tvm_trips_flip_rounded;
1817 	double *Tr0_trips_flip_rounded;
1818 	unsigned int *VUpdateOffsetPix;
1819 	unsigned int *VUpdateWidthPix;
1820 	unsigned int *VReadyOffsetPix;
1821 	double *prefetch_cursor_bw;
1822 	double *prefetch_sw_bytes;
1823 	double *prefetch_swath_time_us;
1824 };
1825 
1826 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params {
1827 	unsigned int num_active_planes;
1828 	enum dml2_source_format_class *pixel_format;
1829 	unsigned int rob_buffer_size_kbytes;
1830 	unsigned int compressed_buffer_size_kbytes;
1831 	unsigned int chunk_bytes_l; // same for all planes
1832 	unsigned int chunk_bytes_c;
1833 	unsigned int *detile_buffer_size_bytes_l;
1834 	unsigned int *detile_buffer_size_bytes_c;
1835 	unsigned int *full_swath_bytes_l;
1836 	unsigned int *full_swath_bytes_c;
1837 	unsigned int *lb_source_lines_l;
1838 	unsigned int *lb_source_lines_c;
1839 	unsigned int *swath_height_l;
1840 	unsigned int *swath_height_c;
1841 	double *prefetch_sw_bytes;
1842 	double *Tpre_rounded;
1843 	double *Tpre_oto;
1844 	double estimated_dcfclk_mhz;
1845 	double estimated_urg_bandwidth_required_mbps;
1846 	double *line_time;
1847 	double *dst_y_prefetch;
1848 
1849 	// output
1850 	bool *recalc_prefetch_schedule;
1851 	double *impacted_dst_y_pre;
1852 };
1853 
1854 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals {
1855 	unsigned int max_Trpd_dcfclk_cycles;
1856 	unsigned int burst_bytes_to_fill_det;
1857 	double time_to_fill_det_us;
1858 	unsigned int accumulated_return_path_dcfclk_cycles[DML2_MAX_PLANES];
1859 	bool prefetch_global_check_passed;
1860 	unsigned int src_swath_bytes_l[DML2_MAX_PLANES];
1861 	unsigned int src_swath_bytes_c[DML2_MAX_PLANES];
1862 	unsigned int src_detile_buf_size_bytes_l[DML2_MAX_PLANES];
1863 	unsigned int src_detile_buf_size_bytes_c[DML2_MAX_PLANES];
1864 };
1865 
1866 struct dml2_core_calcs_calculate_mcache_row_bytes_params {
1867 	unsigned int num_chans;
1868 	unsigned int mem_word_bytes;
1869 	unsigned int mcache_size_bytes;
1870 	unsigned int mcache_line_size_bytes;
1871 	unsigned int gpuvm_enable;
1872 	unsigned int gpuvm_page_size_kbytes;
1873 
1874 	//enum dml_rotation_angle rotation_angle;
1875 	bool surf_vert;
1876 	unsigned int vp_stationary;
1877 	unsigned int tiling_mode;
1878 	bool imall_enable;
1879 
1880 	unsigned int vp_start_x;
1881 	unsigned int vp_start_y;
1882 	unsigned int full_vp_width;
1883 	unsigned int full_vp_height;
1884 	unsigned int blk_width;
1885 	unsigned int blk_height;
1886 	unsigned int vmpg_width;
1887 	unsigned int vmpg_height;
1888 	unsigned int full_swath_bytes;
1889 	unsigned int bytes_per_pixel;
1890 
1891 	// output
1892 	unsigned int *num_mcaches;
1893 	unsigned int *mcache_row_bytes;
1894 	unsigned int *mcache_row_bytes_per_channel;
1895 	unsigned int *meta_row_width_ub;
1896 	double *dcc_dram_bw_nom_overhead_factor;
1897 	double *dcc_dram_bw_pref_overhead_factor;
1898 	unsigned int *mvmpg_width;
1899 	unsigned int *mvmpg_height;
1900 	unsigned int *full_vp_access_width_mvmpg_aligned;
1901 	unsigned int *mvmpg_per_mcache_lb;
1902 };
1903 
1904 struct dml2_core_shared_calculate_mcache_setting_locals {
1905 	struct dml2_core_calcs_calculate_mcache_row_bytes_params l_p;
1906 	struct dml2_core_calcs_calculate_mcache_row_bytes_params c_p;
1907 
1908 	bool is_dual_plane;
1909 	unsigned int mvmpg_width_l;
1910 	unsigned int mvmpg_height_l;
1911 	unsigned int full_vp_access_width_mvmpg_aligned_l;
1912 	unsigned int mvmpg_per_mcache_lb_l;
1913 	unsigned int meta_row_width_l;
1914 
1915 	unsigned int mvmpg_width_c;
1916 	unsigned int mvmpg_height_c;
1917 	unsigned int full_vp_access_width_mvmpg_aligned_c;
1918 	unsigned int mvmpg_per_mcache_lb_c;
1919 	unsigned int meta_row_width_c;
1920 
1921 	unsigned int lc_comb_last_mcache_size;
1922 	double luma_time_factor;
1923 	double mcache_remainder_l;
1924 	double mcache_remainder_c;
1925 	unsigned int mvmpg_access_width_l;
1926 	unsigned int mvmpg_access_width_c;
1927 	unsigned int avg_mcache_element_size_l;
1928 	unsigned int avg_mcache_element_size_c;
1929 
1930 	unsigned int full_vp_access_width_l;
1931 	unsigned int full_vp_access_width_c;
1932 };
1933 
1934 struct dml2_core_calcs_calculate_mcache_setting_params {
1935 	bool dcc_enable;
1936 	unsigned int num_chans;
1937 	unsigned int mem_word_bytes;
1938 	unsigned int mcache_size_bytes;
1939 	unsigned int mcache_line_size_bytes;
1940 	unsigned int gpuvm_enable;
1941 	unsigned int gpuvm_page_size_kbytes;
1942 
1943 	enum dml2_source_format_class source_format;
1944 	bool surf_vert;
1945 	unsigned int vp_stationary;
1946 	unsigned int tiling_mode;
1947 	bool imall_enable;
1948 
1949 	unsigned int vp_start_x_l;
1950 	unsigned int vp_start_y_l;
1951 	unsigned int full_vp_width_l;
1952 	unsigned int full_vp_height_l;
1953 	unsigned int blk_width_l;
1954 	unsigned int blk_height_l;
1955 	unsigned int vmpg_width_l;
1956 	unsigned int vmpg_height_l;
1957 	unsigned int full_swath_bytes_l;
1958 	unsigned int bytes_per_pixel_l;
1959 
1960 	unsigned int vp_start_x_c;
1961 	unsigned int vp_start_y_c;
1962 	unsigned int full_vp_width_c;
1963 	unsigned int full_vp_height_c;
1964 	unsigned int blk_width_c;
1965 	unsigned int blk_height_c;
1966 	unsigned int vmpg_width_c;
1967 	unsigned int vmpg_height_c;
1968 	unsigned int full_swath_bytes_c;
1969 	unsigned int bytes_per_pixel_c;
1970 
1971 	// output
1972 	unsigned int *num_mcaches_l;
1973 	unsigned int *mcache_row_bytes_l;
1974 	unsigned int *mcache_row_bytes_per_channel_l;
1975 	unsigned int *mcache_offsets_l;
1976 	unsigned int *mcache_shift_granularity_l;
1977 	double *dcc_dram_bw_nom_overhead_factor_l;
1978 	double *dcc_dram_bw_pref_overhead_factor_l;
1979 
1980 	unsigned int *num_mcaches_c;
1981 	unsigned int *mcache_row_bytes_c;
1982 	unsigned int *mcache_row_bytes_per_channel_c;
1983 	unsigned int *mcache_offsets_c;
1984 	unsigned int *mcache_shift_granularity_c;
1985 	double *dcc_dram_bw_nom_overhead_factor_c;
1986 	double *dcc_dram_bw_pref_overhead_factor_c;
1987 
1988 	bool *mall_comb_mcache_l;
1989 	bool *mall_comb_mcache_c;
1990 	bool *lc_comb_mcache;
1991 };
1992 
1993 struct dml2_core_calcs_calculate_tdlut_setting_params {
1994 	// input params
1995 	double dispclk_mhz;
1996 	bool setup_for_tdlut;
1997 	enum dml2_tdlut_width_mode tdlut_width_mode;
1998 	enum dml2_tdlut_addressing_mode tdlut_addressing_mode;
1999 	unsigned int cursor_buffer_size;
2000 	bool gpuvm_enable;
2001 	unsigned int gpuvm_page_size_kbytes;
2002 	bool is_gfx11;
2003 	bool tdlut_mpc_width_flag;
2004 
2005 	// output param
2006 	unsigned int *tdlut_pte_bytes_per_frame;
2007 	unsigned int *tdlut_bytes_per_frame;
2008 	unsigned int *tdlut_groups_per_2row_ub;
2009 	double *tdlut_opt_time;
2010 	double *tdlut_drain_time;
2011 	unsigned int *tdlut_bytes_to_deliver;
2012 	unsigned int *tdlut_bytes_per_group;
2013 };
2014 
2015 struct dml2_core_calcs_calculate_peak_bandwidth_required_params {
2016 	// output
2017 	double (*urg_vactive_bandwidth_required)[dml2_core_internal_bw_max];
2018 	double (*urg_bandwidth_required)[dml2_core_internal_bw_max];
2019 	double (*urg_bandwidth_required_qual)[dml2_core_internal_bw_max];
2020 	double (*non_urg_bandwidth_required)[dml2_core_internal_bw_max];
2021 	double (*surface_avg_vactive_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES];
2022 	double (*surface_peak_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES];
2023 
2024 	// input
2025 	const struct dml2_display_cfg *display_cfg;
2026 	bool inc_flip_bw;
2027 	unsigned int num_active_planes;
2028 	unsigned int *num_of_dpp;
2029 	double *dcc_dram_bw_nom_overhead_factor_p0;
2030 	double *dcc_dram_bw_nom_overhead_factor_p1;
2031 	double *dcc_dram_bw_pref_overhead_factor_p0;
2032 	double *dcc_dram_bw_pref_overhead_factor_p1;
2033 	double *mall_prefetch_sdp_overhead_factor;
2034 	double *mall_prefetch_dram_overhead_factor;
2035 	double *surface_read_bandwidth_l;
2036 	double *surface_read_bandwidth_c;
2037 	double *prefetch_bandwidth_l;
2038 	double *prefetch_bandwidth_c;
2039 	double *prefetch_bandwidth_oto;
2040 	double *excess_vactive_fill_bw_l;
2041 	double *excess_vactive_fill_bw_c;
2042 	double *cursor_bw;
2043 	double *dpte_row_bw;
2044 	double *meta_row_bw;
2045 	double *prefetch_cursor_bw;
2046 	double *prefetch_vmrow_bw;
2047 	double *flip_bw;
2048 	double *urgent_burst_factor_l;
2049 	double *urgent_burst_factor_c;
2050 	double *urgent_burst_factor_cursor;
2051 	double *urgent_burst_factor_prefetch_l;
2052 	double *urgent_burst_factor_prefetch_c;
2053 	double *urgent_burst_factor_prefetch_cursor;
2054 };
2055 
2056 struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params {
2057 	/* inputs */
2058 	const struct dml2_display_cfg *display_cfg;
2059 	bool mrq_present;
2060 	unsigned int num_active_planes;
2061 	unsigned int *num_of_dpp;
2062 	unsigned int *meta_row_height_l;
2063 	unsigned int *meta_row_height_c;
2064 	unsigned int *meta_row_bytes_per_row_ub_l;
2065 	unsigned int *meta_row_bytes_per_row_ub_c;
2066 	unsigned int *dpte_row_height_l;
2067 	unsigned int *dpte_row_height_c;
2068 	unsigned int *dpte_bytes_per_row_l;
2069 	unsigned int *dpte_bytes_per_row_c;
2070 	unsigned int *byte_per_pix_l;
2071 	unsigned int *byte_per_pix_c;
2072 	unsigned int *swath_width_l;
2073 	unsigned int *swath_width_c;
2074 	unsigned int *swath_height_l;
2075 	unsigned int *swath_height_c;
2076 	double latency_to_hide_us;
2077 
2078 	/* outputs */
2079 	unsigned int *bytes_required_l;
2080 	unsigned int *bytes_required_c;
2081 };
2082 
2083 // A list of overridable function pointers in the core
2084 // shared calculation library.
2085 struct dml2_core_shared_calculation_funcs {
2086 	void (*calculate_det_buffer_size)(struct dml2_core_shared_calculate_det_buffer_size_params *p);
2087 };
2088 
2089 struct dml2_core_internal_scratch {
2090 	// Scratch space for function locals
2091 	struct dml2_core_calcs_mode_support_locals dml_core_mode_support_locals;
2092 	struct dml2_core_calcs_mode_programming_locals dml_core_mode_programming_locals;
2093 	struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals;
2094 	struct dml2_core_calcs_CalculateVMRowAndSwath_locals CalculateVMRowAndSwath_locals;
2095 	struct dml2_core_calcs_CalculatePrefetchSchedule_locals CalculatePrefetchSchedule_locals;
2096 	struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals CheckGlobalPrefetchAdmissibility_locals;
2097 	struct dml2_core_shared_CalculateSwathAndDETConfiguration_locals CalculateSwathAndDETConfiguration_locals;
2098 	struct dml2_core_shared_TruncToValidBPP_locals TruncToValidBPP_locals;
2099 	struct dml2_core_shared_CalculateDETBufferSize_locals CalculateDETBufferSize_locals;
2100 	struct dml2_core_shared_get_urgent_bandwidth_required_locals get_urgent_bandwidth_required_locals;
2101 	struct dml2_core_shared_calculate_peak_bandwidth_required_locals calculate_peak_bandwidth_required_locals;
2102 	struct dml2_core_shared_CalculateFlipSchedule_locals CalculateFlipSchedule_locals;
2103 	struct dml2_core_shared_rq_dlg_get_dlg_reg_locals rq_dlg_get_dlg_reg_locals;
2104 	struct dml2_core_calcs_CalculateStutterEfficiency_locals CalculateStutterEfficiency_locals;
2105 
2106 	// Scratch space for function params
2107 	struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params;
2108 	struct dml2_core_calcs_CalculateVMRowAndSwath_params CalculateVMRowAndSwath_params;
2109 	struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params CalculateSwathAndDETConfiguration_params;
2110 	struct dml2_core_calcs_CalculateStutterEfficiency_params CalculateStutterEfficiency_params;
2111 	struct dml2_core_calcs_CalculatePrefetchSchedule_params CalculatePrefetchSchedule_params;
2112 	struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params CheckGlobalPrefetchAdmissibility_params;
2113 	struct dml2_core_calcs_calculate_mcache_setting_params calculate_mcache_setting_params;
2114 	struct dml2_core_calcs_calculate_tdlut_setting_params calculate_tdlut_setting_params;
2115 	struct dml2_core_shared_calculate_vm_and_row_bytes_params calculate_vm_and_row_bytes_params;
2116 	struct dml2_core_shared_calculate_mcache_setting_locals calculate_mcache_setting_locals;
2117 	struct dml2_core_shared_CalculateMetaAndPTETimes_params CalculateMetaAndPTETimes_params;
2118 	struct dml2_core_calcs_calculate_peak_bandwidth_required_params calculate_peak_bandwidth_params;
2119 	struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params calculate_bytes_to_fetch_required_to_hide_latency_params;
2120 };
2121 
2122 //struct dml2_svp_mode_override;
2123 struct dml2_core_internal_display_mode_lib {
2124 	struct dml2_core_ip_params ip;
2125 	struct dml2_soc_bb soc;
2126 	struct dml2_ip_capabilities ip_caps;
2127 
2128 	//@brief Mode Support and Mode programming struct
2129 	// Used to hold input; intermediate and output of the calculations
2130 	struct dml2_core_internal_mode_support ms; // struct for mode support
2131 	struct dml2_core_internal_mode_program mp; // struct for mode programming
2132 	// Available overridable calculators for core_shared.
2133 	// if null, core_shared will use default calculators.
2134 	struct dml2_core_shared_calculation_funcs funcs;
2135 
2136 	struct dml2_core_internal_scratch scratch;
2137 };
2138 
2139 struct dml2_core_calcs_mode_support_ex {
2140 	struct dml2_core_internal_display_mode_lib *mode_lib;
2141 	const struct dml2_display_cfg *in_display_cfg;
2142 	const struct dml2_mcg_min_clock_table *min_clk_table;
2143 	int min_clk_index;
2144 	//unsigned int in_state_index;
2145 	struct dml2_core_internal_mode_support_info *out_evaluation_info;
2146 };
2147 
2148 struct core_display_cfg_support_info;
2149 
2150 struct dml2_core_calcs_mode_programming_ex {
2151 	struct dml2_core_internal_display_mode_lib *mode_lib;
2152 	const struct dml2_display_cfg *in_display_cfg;
2153 	const struct dml2_mcg_min_clock_table *min_clk_table;
2154 	const struct core_display_cfg_support_info *cfg_support_info;
2155 	int min_clk_index;
2156 	struct dml2_display_cfg_programming *programming;
2157 };
2158 
2159 #endif
2160