1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML2_INTERNAL_SHARED_TYPES_H__ 6 #define __DML2_INTERNAL_SHARED_TYPES_H__ 7 8 #include "dml2_external_lib_deps.h" 9 #include "dml_top_types.h" 10 #include "dml2_core_shared_types.h" 11 /* 12 * DML2 MCG Types and Interfaces 13 */ 14 15 #define DML_MCG_MAX_CLK_TABLE_SIZE 20 16 17 struct dram_bw_to_min_clk_table_entry { 18 unsigned long long pre_derate_dram_bw_kbps; 19 unsigned long min_fclk_khz; 20 unsigned long min_dcfclk_khz; 21 }; 22 23 struct dml2_mcg_dram_bw_to_min_clk_table { 24 struct dram_bw_to_min_clk_table_entry entries[DML_MCG_MAX_CLK_TABLE_SIZE]; 25 26 unsigned int num_entries; 27 }; 28 29 struct dml2_mcg_min_clock_table { 30 struct { 31 unsigned int dispclk; 32 unsigned int dppclk; 33 unsigned int dscclk; 34 unsigned int dtbclk; 35 unsigned int phyclk; 36 unsigned int fclk; 37 unsigned int dcfclk; 38 } max_clocks_khz; 39 40 struct { 41 unsigned int dprefclk; 42 unsigned int xtalclk; 43 unsigned int pcierefclk; 44 unsigned int dchubrefclk; 45 unsigned int amclk; 46 } fixed_clocks_khz; 47 48 struct dml2_mcg_dram_bw_to_min_clk_table dram_bw_table; 49 }; 50 51 struct dml2_mcg_build_min_clock_table_params_in_out { 52 /* 53 * Input 54 */ 55 struct dml2_soc_bb *soc_bb; 56 struct { 57 bool perform_pseudo_build; 58 } clean_me_up; 59 60 /* 61 * Output 62 */ 63 struct dml2_mcg_min_clock_table *min_clk_table; 64 }; 65 struct dml2_mcg_instance { 66 bool (*build_min_clock_table)(struct dml2_mcg_build_min_clock_table_params_in_out *in_out); 67 }; 68 69 /* 70 * DML2 DPMM Types and Interfaces 71 */ 72 73 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out { 74 /* 75 * Input 76 */ 77 struct dml2_core_ip_params *ip; 78 struct dml2_soc_bb *soc_bb; 79 struct dml2_mcg_min_clock_table *min_clk_table; 80 const struct display_configuation_with_meta *display_cfg; 81 struct { 82 bool perform_pseudo_map; 83 struct dml2_core_internal_soc_bb *soc_bb; 84 } clean_me_up; 85 86 /* 87 * Output 88 */ 89 struct dml2_display_cfg_programming *programming; 90 }; 91 92 struct dml2_dpmm_map_watermarks_params_in_out { 93 /* 94 * Input 95 */ 96 const struct display_configuation_with_meta *display_cfg; 97 const struct dml2_core_instance *core; 98 99 /* 100 * Output 101 */ 102 struct dml2_display_cfg_programming *programming; 103 }; 104 105 struct dml2_dpmm_scratch { 106 struct dml2_display_cfg_programming programming; 107 }; 108 109 struct dml2_dpmm_instance { 110 bool (*map_mode_to_soc_dpm)(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out); 111 bool (*map_watermarks)(struct dml2_dpmm_map_watermarks_params_in_out *in_out); 112 113 struct dml2_dpmm_scratch dpmm_scratch; 114 }; 115 116 /* 117 * DML2 Core Types and Interfaces 118 */ 119 120 struct dml2_core_initialize_in_out { 121 enum dml2_project_id project_id; 122 struct dml2_core_instance *instance; 123 struct dml2_soc_bb *soc_bb; 124 struct dml2_ip_capabilities *ip_caps; 125 126 struct dml2_mcg_min_clock_table *minimum_clock_table; 127 128 void *explicit_ip_bb; 129 unsigned int explicit_ip_bb_size; 130 131 // FIXME_STAGE2 can remove but dcn3 version still need this 132 struct { 133 struct soc_bounding_box_st *soc_bb; 134 struct soc_states_st *soc_states; 135 } legacy; 136 }; 137 138 struct core_bandwidth_requirements { 139 int urgent_bandwidth_kbytes_per_sec; 140 int average_bandwidth_kbytes_per_sec; 141 }; 142 143 struct core_plane_support_info { 144 int dpps_used; 145 int dram_change_latency_hiding_margin_in_active; 146 int active_latency_hiding_us; 147 int mall_svp_size_requirement_ways; 148 int nominal_vblank_pstate_latency_hiding_us; 149 unsigned int dram_change_vactive_det_fill_delay_us; 150 }; 151 152 struct core_stream_support_info { 153 unsigned int odms_used; 154 unsigned int num_odm_output_segments; // for odm split mode (e.g. a value of 2 for odm_mode_mso_1to2) 155 156 /* FAMS2 SubVP support info */ 157 unsigned int phantom_min_v_active; 158 unsigned int phantom_v_startup; 159 160 unsigned int phantom_v_active; 161 unsigned int phantom_v_total; 162 int vblank_reserved_time_us; 163 int num_dsc_slices; 164 bool dsc_enable; 165 }; 166 167 struct core_display_cfg_support_info { 168 bool is_supported; 169 170 struct core_stream_support_info stream_support_info[DML2_MAX_PLANES]; 171 struct core_plane_support_info plane_support_info[DML2_MAX_PLANES]; 172 173 struct { 174 struct dml2_core_internal_mode_support_info support_info; 175 } clean_me_up; 176 }; 177 178 struct dml2_core_mode_support_result { 179 struct { 180 struct { 181 unsigned long urgent_bw_sdp_kbps; 182 unsigned long average_bw_sdp_kbps; 183 unsigned long urgent_bw_dram_kbps; 184 unsigned long average_bw_dram_kbps; 185 unsigned long dcfclk_khz; 186 unsigned long fclk_khz; 187 } svp_prefetch; 188 189 struct { 190 unsigned long urgent_bw_sdp_kbps; 191 unsigned long average_bw_sdp_kbps; 192 unsigned long urgent_bw_dram_kbps; 193 unsigned long average_bw_dram_kbps; 194 unsigned long dcfclk_khz; 195 unsigned long fclk_khz; 196 } active; 197 198 unsigned int dispclk_khz; 199 unsigned int dcfclk_deepsleep_khz; 200 unsigned int socclk_khz; 201 202 unsigned int uclk_pstate_supported; 203 unsigned int fclk_pstate_supported; 204 } global; 205 206 struct { 207 unsigned int dscclk_khz; 208 unsigned int dtbclk_khz; 209 unsigned int phyclk_khz; 210 } per_stream[DML2_MAX_PLANES]; 211 212 struct { 213 unsigned int dppclk_khz; 214 unsigned int mall_svp_allocation_mblks; 215 unsigned int mall_full_frame_allocation_mblks; 216 } per_plane[DML2_MAX_PLANES]; 217 218 struct core_display_cfg_support_info cfg_support_info; 219 }; 220 221 struct dml2_optimization_stage1_state { 222 bool performed; 223 bool success; 224 225 int min_clk_index_for_latency; 226 }; 227 228 struct dml2_optimization_stage2_state { 229 bool performed; 230 bool success; 231 232 // Whether or not each plane supports mcache 233 // The number of valid elements == display_cfg.num_planes 234 // The indexing of pstate_switch_modes matches plane_descriptors[] 235 bool per_plane_mcache_support[DML2_MAX_PLANES]; 236 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; 237 }; 238 239 #define DML2_PMO_LEGACY_PREFETCH_MAX_TWAIT_OPTIONS 8 240 #define DML2_PMO_PSTATE_CANDIDATE_LIST_SIZE 10 241 #define DML2_PMO_STUTTER_CANDIDATE_LIST_SIZE 3 242 243 struct dml2_implicit_svp_meta { 244 bool valid; 245 unsigned long v_active; 246 unsigned long v_total; 247 unsigned long v_front_porch; 248 }; 249 250 struct dml2_fams2_per_method_common_meta { 251 /* generic params */ 252 unsigned int allow_start_otg_vline; 253 unsigned int allow_end_otg_vline; 254 /* scheduling params */ 255 double allow_time_us; 256 double disallow_time_us; 257 double period_us; 258 }; 259 260 struct dml2_fams2_meta { 261 bool valid; 262 double otg_vline_time_us; 263 unsigned int scheduling_delay_otg_vlines; 264 unsigned int vertical_interrupt_ack_delay_otg_vlines; 265 unsigned int allow_to_target_delay_otg_vlines; 266 unsigned int contention_delay_otg_vlines; 267 unsigned int min_allow_width_otg_vlines; 268 unsigned int nom_vtotal; 269 unsigned int vblank_start; 270 double nom_refresh_rate_hz; 271 double nom_frame_time_us; 272 unsigned int max_vtotal; 273 double min_refresh_rate_hz; 274 double max_frame_time_us; 275 unsigned int dram_clk_change_blackout_otg_vlines; 276 struct { 277 double max_vactive_det_fill_delay_us; 278 unsigned int max_vactive_det_fill_delay_otg_vlines; 279 struct dml2_fams2_per_method_common_meta common; 280 } method_vactive; 281 struct { 282 struct dml2_fams2_per_method_common_meta common; 283 } method_vblank; 284 struct { 285 unsigned int programming_delay_otg_vlines; 286 unsigned int df_throttle_delay_otg_vlines; 287 unsigned int prefetch_to_mall_delay_otg_vlines; 288 unsigned long phantom_vactive; 289 unsigned long phantom_vfp; 290 unsigned long phantom_vtotal; 291 struct dml2_fams2_per_method_common_meta common; 292 } method_subvp; 293 struct { 294 unsigned int programming_delay_otg_vlines; 295 unsigned int stretched_vtotal; 296 struct dml2_fams2_per_method_common_meta common; 297 } method_drr; 298 }; 299 300 struct dml2_optimization_stage3_state { 301 bool performed; 302 bool success; 303 304 // The pstate support mode for each plane 305 // The number of valid elements == display_cfg.num_planes 306 // The indexing of pstate_switch_modes matches plane_descriptors[] 307 enum dml2_pstate_method pstate_switch_modes[DML2_MAX_PLANES]; 308 309 // Meta-data for implicit SVP generation, indexed by stream index 310 struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES]; 311 312 // Meta-data for FAMS2 313 bool fams2_required; 314 struct dml2_fams2_meta stream_fams2_meta[DML2_MAX_PLANES]; 315 316 int min_clk_index_for_latency; 317 }; 318 319 struct dml2_optimization_stage4_state { 320 bool performed; 321 bool success; 322 bool unoptimizable_streams[DML2_MAX_DCN_PIPES]; 323 }; 324 325 struct dml2_optimization_stage5_state { 326 bool performed; 327 bool success; 328 329 bool optimal_reserved_time_in_vblank_us; 330 bool vblank_includes_z8_optimization; 331 }; 332 333 struct display_configuation_with_meta { 334 struct dml2_display_cfg display_config; 335 336 struct dml2_core_mode_support_result mode_support_result; 337 338 // Stage 1 = Min Clocks for Latency 339 struct dml2_optimization_stage1_state stage1; 340 341 // Stage 2 = MCache 342 struct dml2_optimization_stage2_state stage2; 343 344 // Stage 3 = UCLK PState 345 struct dml2_optimization_stage3_state stage3; 346 347 // Stage 4 = Vmin 348 struct dml2_optimization_stage4_state stage4; 349 350 // Stage 5 = Stutter 351 struct dml2_optimization_stage5_state stage5; 352 }; 353 354 struct dml2_pmo_pstate_strategy { 355 enum dml2_pstate_method per_stream_pstate_method[DML2_MAX_PLANES]; 356 bool allow_state_increase; 357 }; 358 struct dml2_core_mode_support_in_out { 359 /* 360 * Inputs 361 */ 362 struct dml2_core_instance *instance; 363 const struct display_configuation_with_meta *display_cfg; 364 365 struct dml2_mcg_min_clock_table *min_clk_table; 366 int min_clk_index; 367 /* 368 * Outputs 369 */ 370 struct dml2_core_mode_support_result mode_support_result; 371 372 struct { 373 // Inputs 374 struct dml_display_cfg_st *display_cfg; 375 376 // Outputs 377 struct dml_mode_support_info_st *support_info; 378 unsigned int out_lowest_state_idx; 379 unsigned int min_fclk_khz; 380 unsigned int min_dcfclk_khz; 381 unsigned int min_dram_speed_mts; 382 unsigned int min_socclk_khz; 383 unsigned int min_dscclk_khz; 384 unsigned int min_dtbclk_khz; 385 unsigned int min_phyclk_khz; 386 } legacy; 387 }; 388 389 struct dml2_core_mode_programming_in_out { 390 /* 391 * Inputs 392 */ 393 struct dml2_core_instance *instance; 394 const struct display_configuation_with_meta *display_cfg; 395 const struct core_display_cfg_support_info *cfg_support_info; 396 /* 397 * Outputs (also Input the clk freq are also from programming struct) 398 */ 399 struct dml2_display_cfg_programming *programming; 400 401 }; 402 403 struct dml2_core_populate_informative_in_out { 404 /* 405 * Inputs 406 */ 407 struct dml2_core_instance *instance; 408 409 // If this is set, then the mode was supported, and mode programming 410 // was successfully run. 411 // Otherwise, mode programming was not run, because mode support failed. 412 bool mode_is_supported; 413 414 /* 415 * Outputs 416 */ 417 struct dml2_display_cfg_programming *programming; 418 }; 419 420 struct dml2_calculate_mcache_allocation_in_out { 421 /* 422 * Inputs 423 */ 424 struct dml2_core_instance *instance; 425 const struct dml2_plane_parameters *plane_descriptor; 426 unsigned int plane_index; 427 428 /* 429 * Outputs 430 */ 431 struct dml2_mcache_surface_allocation *mcache_allocation; 432 }; 433 434 struct dml2_core_internal_state_inputs { 435 unsigned int dummy; 436 }; 437 438 struct dml2_core_internal_state_intermediates { 439 unsigned int dummy; 440 }; 441 442 struct dml2_core_mode_support_locals { 443 struct dml2_core_calcs_mode_support_ex mode_support_ex_params; 444 struct dml2_display_cfg svp_expanded_display_cfg; 445 struct dml2_calculate_mcache_allocation_in_out calc_mcache_allocation_params; 446 }; 447 448 struct dml2_core_mode_programming_locals { 449 struct dml2_core_calcs_mode_programming_ex mode_programming_ex_params; 450 struct dml2_display_cfg svp_expanded_display_cfg; 451 }; 452 453 struct dml2_core_scratch { 454 struct dml2_core_mode_support_locals mode_support_locals; 455 struct dml2_core_mode_programming_locals mode_programming_locals; 456 int main_stream_index_from_svp_stream_index[DML2_MAX_PLANES]; 457 int svp_stream_index_from_main_stream_index[DML2_MAX_PLANES]; 458 int main_plane_index_to_phantom_plane_index[DML2_MAX_PLANES]; 459 int phantom_plane_index_to_main_plane_index[DML2_MAX_PLANES]; 460 }; 461 462 struct dml2_core_instance { 463 struct dml2_mcg_min_clock_table *minimum_clock_table; 464 struct dml2_core_internal_state_inputs inputs; 465 struct dml2_core_internal_state_intermediates intermediates; 466 467 struct dml2_core_scratch scratch; 468 469 bool (*initialize)(struct dml2_core_initialize_in_out *in_out); 470 bool (*mode_support)(struct dml2_core_mode_support_in_out *in_out); 471 bool (*mode_programming)(struct dml2_core_mode_programming_in_out *in_out); 472 bool (*populate_informative)(struct dml2_core_populate_informative_in_out *in_out); 473 bool (*calculate_mcache_allocation)(struct dml2_calculate_mcache_allocation_in_out *in_out); 474 475 struct { 476 struct dml2_core_internal_display_mode_lib mode_lib; 477 } clean_me_up; 478 }; 479 480 /* 481 * DML2 PMO Types and Interfaces 482 */ 483 484 struct dml2_pmo_initialize_in_out { 485 /* 486 * Input 487 */ 488 struct dml2_pmo_instance *instance; 489 struct dml2_soc_bb *soc_bb; 490 struct dml2_ip_capabilities *ip_caps; 491 struct dml2_pmo_options *options; 492 int mcg_clock_table_size; 493 }; 494 495 struct dml2_pmo_optimize_dcc_mcache_in_out { 496 /* 497 * Input 498 */ 499 struct dml2_pmo_instance *instance; 500 const struct dml2_display_cfg *display_config; 501 bool *dcc_mcache_supported; 502 struct core_display_cfg_support_info *cfg_support_info; 503 504 /* 505 * Output 506 */ 507 struct dml2_display_cfg *optimized_display_cfg; 508 }; 509 510 struct dml2_pmo_init_for_vmin_in_out { 511 /* 512 * Input 513 */ 514 struct dml2_pmo_instance *instance; 515 struct display_configuation_with_meta *base_display_config; 516 }; 517 518 struct dml2_pmo_test_for_vmin_in_out { 519 /* 520 * Input 521 */ 522 struct dml2_pmo_instance *instance; 523 const struct display_configuation_with_meta *display_config; 524 const struct dml2_soc_vmin_clock_limits *vmin_limits; 525 }; 526 527 struct dml2_pmo_optimize_for_vmin_in_out { 528 /* 529 * Input 530 */ 531 struct dml2_pmo_instance *instance; 532 struct display_configuation_with_meta *base_display_config; 533 534 /* 535 * Output 536 */ 537 struct display_configuation_with_meta *optimized_display_config; 538 }; 539 540 struct dml2_pmo_init_for_pstate_support_in_out { 541 /* 542 * Input 543 */ 544 struct dml2_pmo_instance *instance; 545 struct display_configuation_with_meta *base_display_config; 546 }; 547 548 struct dml2_pmo_test_for_pstate_support_in_out { 549 /* 550 * Input 551 */ 552 struct dml2_pmo_instance *instance; 553 struct display_configuation_with_meta *base_display_config; 554 }; 555 556 struct dml2_pmo_optimize_for_pstate_support_in_out { 557 /* 558 * Input 559 */ 560 struct dml2_pmo_instance *instance; 561 struct display_configuation_with_meta *base_display_config; 562 bool last_candidate_failed; 563 564 /* 565 * Output 566 */ 567 struct display_configuation_with_meta *optimized_display_config; 568 }; 569 570 struct dml2_pmo_init_for_stutter_in_out { 571 /* 572 * Input 573 */ 574 struct dml2_pmo_instance *instance; 575 struct display_configuation_with_meta *base_display_config; 576 }; 577 578 struct dml2_pmo_test_for_stutter_in_out { 579 /* 580 * Input 581 */ 582 struct dml2_pmo_instance *instance; 583 struct display_configuation_with_meta *base_display_config; 584 }; 585 586 struct dml2_pmo_optimize_for_stutter_in_out { 587 /* 588 * Input 589 */ 590 struct dml2_pmo_instance *instance; 591 struct display_configuation_with_meta *base_display_config; 592 bool last_candidate_failed; 593 594 /* 595 * Output 596 */ 597 struct display_configuation_with_meta *optimized_display_config; 598 }; 599 600 #define PMO_NO_DRR_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw - dml2_pstate_method_na + 1)) - 1) << dml2_pstate_method_na) 601 #define PMO_DRR_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_vactive_drr + 1)) - 1) << dml2_pstate_method_fw_vactive_drr) 602 #define PMO_DRR_CLAMPED_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_clamped - dml2_pstate_method_fw_vactive_drr + 1)) - 1) << dml2_pstate_method_fw_vactive_drr) 603 #define PMO_DRR_VAR_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_drr + 1)) - 1) << dml2_pstate_method_fw_drr) 604 #define PMO_FW_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_svp + 1)) - 1) << dml2_pstate_method_fw_svp) 605 606 #define PMO_DCN4_MAX_DISPLAYS 4 607 #define PMO_DCN4_MAX_NUM_VARIANTS 2 608 #define PMO_DCN4_MAX_BASE_STRATEGIES 10 609 610 struct dml2_pmo_scratch { 611 union { 612 struct { 613 double reserved_time_candidates[DML2_MAX_PLANES][DML2_PMO_LEGACY_PREFETCH_MAX_TWAIT_OPTIONS]; 614 int reserved_time_candidates_count[DML2_MAX_PLANES]; 615 int current_candidate[DML2_MAX_PLANES]; 616 int min_latency_index; 617 int max_latency_index; 618 int cur_latency_index; 619 int stream_mask; 620 } pmo_dcn3; 621 struct { 622 struct dml2_pmo_pstate_strategy expanded_override_strategy_list[2 * 2 * 2 * 2]; 623 unsigned int num_expanded_override_strategies; 624 struct dml2_pmo_pstate_strategy pstate_strategy_candidates[DML2_PMO_PSTATE_CANDIDATE_LIST_SIZE]; 625 int num_pstate_candidates; 626 int cur_pstate_candidate; 627 628 unsigned int stream_plane_mask[DML2_MAX_PLANES]; 629 630 unsigned int stream_vactive_capability_mask; 631 632 int min_latency_index; 633 int max_latency_index; 634 int cur_latency_index; 635 636 // Stores all the implicit SVP meta information indexed by stream index of the display 637 // configuration under inspection, built at optimization stage init 638 struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES]; 639 struct dml2_fams2_meta stream_fams2_meta[DML2_MAX_PLANES]; 640 641 unsigned int optimal_vblank_reserved_time_for_stutter_us[DML2_PMO_STUTTER_CANDIDATE_LIST_SIZE]; 642 unsigned int num_stutter_candidates; 643 unsigned int cur_stutter_candidate; 644 bool z8_vblank_optimizable; 645 646 /* mask of synchronized timings by stream index */ 647 unsigned int num_timing_groups; 648 unsigned int synchronized_timing_group_masks[DML2_MAX_PLANES]; 649 bool group_is_drr_enabled[DML2_MAX_PLANES]; 650 bool group_is_drr_active[DML2_MAX_PLANES]; 651 double group_line_time_us[DML2_MAX_PLANES]; 652 653 /* scheduling check locals */ 654 struct dml2_fams2_per_method_common_meta group_common_fams2_meta[DML2_MAX_PLANES]; 655 unsigned int sorted_group_gtl_disallow_index[DML2_MAX_PLANES]; 656 unsigned int sorted_group_gtl_period_index[DML2_MAX_PLANES]; 657 double group_phase_offset[DML2_MAX_PLANES]; 658 } pmo_dcn4; 659 }; 660 }; 661 662 struct dml2_pmo_init_data { 663 union { 664 struct { 665 /* populated once during initialization */ 666 struct dml2_pmo_pstate_strategy expanded_strategy_list_1_display[PMO_DCN4_MAX_BASE_STRATEGIES * 2]; 667 struct dml2_pmo_pstate_strategy expanded_strategy_list_2_display[PMO_DCN4_MAX_BASE_STRATEGIES * 4 * 4]; 668 struct dml2_pmo_pstate_strategy expanded_strategy_list_3_display[PMO_DCN4_MAX_BASE_STRATEGIES * 6 * 6 * 6]; 669 struct dml2_pmo_pstate_strategy expanded_strategy_list_4_display[PMO_DCN4_MAX_BASE_STRATEGIES * 8 * 8 * 8 * 8]; 670 unsigned int num_expanded_strategies_per_list[PMO_DCN4_MAX_DISPLAYS]; 671 } pmo_dcn4; 672 }; 673 }; 674 675 struct dml2_pmo_instance { 676 struct dml2_soc_bb *soc_bb; 677 struct dml2_ip_capabilities *ip_caps; 678 679 struct dml2_pmo_options *options; 680 681 int disp_clk_vmin_threshold; 682 int mpc_combine_limit; 683 int odm_combine_limit; 684 int mcg_clock_table_size; 685 union { 686 struct { 687 struct { 688 int prefetch_end_to_mall_start_us; 689 int fw_processing_delay_us; 690 int refresh_rate_limit_min; 691 int refresh_rate_limit_max; 692 } subvp; 693 } v1; 694 struct { 695 struct { 696 int refresh_rate_limit_min; 697 int refresh_rate_limit_max; 698 } subvp; 699 struct { 700 int refresh_rate_limit_min; 701 int refresh_rate_limit_max; 702 } drr; 703 } v2; 704 } fams_params; 705 706 bool (*initialize)(struct dml2_pmo_initialize_in_out *in_out); 707 bool (*optimize_dcc_mcache)(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out); 708 709 bool (*init_for_vmin)(struct dml2_pmo_init_for_vmin_in_out *in_out); 710 bool (*test_for_vmin)(struct dml2_pmo_test_for_vmin_in_out *in_out); 711 bool (*optimize_for_vmin)(struct dml2_pmo_optimize_for_vmin_in_out *in_out); 712 713 bool (*init_for_uclk_pstate)(struct dml2_pmo_init_for_pstate_support_in_out *in_out); 714 bool (*test_for_uclk_pstate)(struct dml2_pmo_test_for_pstate_support_in_out *in_out); 715 bool (*optimize_for_uclk_pstate)(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out); 716 717 bool (*init_for_stutter)(struct dml2_pmo_init_for_stutter_in_out *in_out); 718 bool (*test_for_stutter)(struct dml2_pmo_test_for_stutter_in_out *in_out); 719 bool (*optimize_for_stutter)(struct dml2_pmo_optimize_for_stutter_in_out *in_out); 720 721 struct dml2_pmo_init_data init_data; 722 struct dml2_pmo_scratch scratch; 723 }; 724 725 /* 726 * DML2 MCache Types 727 */ 728 729 struct top_mcache_validate_admissability_in_out { 730 struct dml2_instance *dml2_instance; 731 732 const struct dml2_display_cfg *display_cfg; 733 const struct core_display_cfg_support_info *cfg_support_info; 734 struct dml2_mcache_surface_allocation *mcache_allocations; 735 736 bool per_plane_status[DML2_MAX_PLANES]; 737 738 struct { 739 const struct dml_mode_support_info_st *mode_support_info; 740 } legacy; 741 }; 742 743 struct top_mcache_assign_ids_in_out { 744 /* 745 * Input 746 */ 747 const struct dml2_mcache_surface_allocation *mcache_allocations; 748 int plane_count; 749 750 int per_pipe_viewport_x_start[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; 751 int per_pipe_viewport_x_end[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; 752 int pipe_count_per_plane[DML2_MAX_PLANES]; 753 754 struct dml2_display_mcache_regs *current_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pipe/hubp 755 756 /* 757 * Output 758 */ 759 struct dml2_display_mcache_regs mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pipe/hubp 760 struct dml2_build_mcache_programming_in_out *mcache_programming; 761 }; 762 763 struct top_mcache_calc_mcache_count_and_offsets_in_out { 764 /* 765 * Inputs 766 */ 767 struct dml2_instance *dml2_instance; 768 const struct dml2_display_cfg *display_config; 769 770 /* 771 * Outputs 772 */ 773 struct dml2_mcache_surface_allocation *mcache_allocations; 774 }; 775 776 struct top_mcache_assign_global_mcache_ids_in_out { 777 /* 778 * Inputs/Outputs 779 */ 780 struct dml2_mcache_surface_allocation *allocations; 781 int num_allocations; 782 }; 783 784 /* 785 * DML2 Top Types 786 */ 787 788 struct dml2_initialize_instance_locals { 789 int dummy; 790 }; 791 792 struct dml2_optimization_init_function_locals { 793 union { 794 struct { 795 struct dml2_pmo_init_for_pstate_support_in_out init_params; 796 } uclk_pstate; 797 struct { 798 struct dml2_pmo_init_for_stutter_in_out stutter_params; 799 } stutter; 800 struct { 801 struct dml2_pmo_init_for_vmin_in_out init_params; 802 } vmin; 803 }; 804 }; 805 806 struct dml2_optimization_test_function_locals { 807 union { 808 struct { 809 struct top_mcache_calc_mcache_count_and_offsets_in_out calc_mcache_count_params; 810 struct top_mcache_assign_global_mcache_ids_in_out assign_global_mcache_ids_params; 811 struct top_mcache_validate_admissability_in_out validate_admissibility_params; 812 } test_mcache; 813 struct { 814 struct dml2_pmo_test_for_vmin_in_out pmo_test_vmin_params; 815 } test_vmin; 816 struct { 817 struct dml2_pmo_test_for_pstate_support_in_out test_params; 818 } uclk_pstate; 819 struct { 820 struct dml2_pmo_test_for_stutter_in_out stutter_params; 821 } stutter; 822 }; 823 }; 824 825 struct dml2_optimization_optimize_function_locals { 826 union { 827 struct { 828 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 829 } optimize_mcache; 830 struct { 831 struct dml2_pmo_optimize_for_vmin_in_out pmo_optimize_vmin_params; 832 } optimize_vmin; 833 struct { 834 struct dml2_pmo_optimize_for_pstate_support_in_out optimize_params; 835 } uclk_pstate; 836 struct { 837 struct dml2_pmo_optimize_for_stutter_in_out stutter_params; 838 } stutter; 839 }; 840 }; 841 842 struct dml2_optimization_phase_locals { 843 struct display_configuation_with_meta cur_candidate_display_cfg; 844 struct display_configuation_with_meta next_candidate_display_cfg; 845 struct dml2_core_mode_support_in_out mode_support_params; 846 struct dml2_optimization_init_function_locals init_function_locals; 847 struct dml2_optimization_test_function_locals test_function_locals; 848 struct dml2_optimization_optimize_function_locals optimize_function_locals; 849 }; 850 851 struct dml2_check_mode_supported_locals { 852 struct dml2_display_cfg display_cfg_working_copy; 853 struct dml2_core_mode_support_in_out mode_support_params; 854 struct dml2_optimization_phase_locals optimization_phase_locals; 855 struct display_configuation_with_meta base_display_config_with_meta; 856 struct display_configuation_with_meta optimized_display_config_with_meta; 857 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out dppm_map_mode_params; 858 }; 859 860 struct optimization_init_function_params { 861 struct dml2_optimization_init_function_locals *locals; 862 struct dml2_instance *dml; 863 struct display_configuation_with_meta *display_config; 864 }; 865 866 struct optimization_test_function_params { 867 struct dml2_optimization_test_function_locals *locals; 868 struct dml2_instance *dml; 869 struct display_configuation_with_meta *display_config; 870 }; 871 872 struct optimization_optimize_function_params { 873 bool last_candidate_supported; 874 struct dml2_optimization_optimize_function_locals *locals; 875 struct dml2_instance *dml; 876 struct display_configuation_with_meta *display_config; 877 struct display_configuation_with_meta *optimized_display_config; 878 }; 879 880 struct optimization_phase_params { 881 struct dml2_instance *dml; 882 const struct display_configuation_with_meta *display_config; // Initial Display Configuration 883 bool (*init_function)(const struct optimization_init_function_params *params); // Test function to determine optimization is complete 884 bool (*test_function)(const struct optimization_test_function_params *params); // Test function to determine optimization is complete 885 bool (*optimize_function)(const struct optimization_optimize_function_params *params); // Function which produces a more optimized display configuration 886 struct display_configuation_with_meta *optimized_display_config; // The optimized display configuration 887 888 bool all_or_nothing; 889 }; 890 891 struct dml2_build_mode_programming_locals { 892 struct dml2_core_mode_support_in_out mode_support_params; 893 struct dml2_core_mode_programming_in_out mode_programming_params; 894 struct dml2_core_populate_informative_in_out informative_params; 895 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 896 struct display_configuation_with_meta base_display_config_with_meta; 897 struct display_configuation_with_meta optimized_display_config_with_meta; 898 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out dppm_map_mode_params; 899 struct dml2_dpmm_map_watermarks_params_in_out dppm_map_watermarks_params; 900 struct dml2_optimization_phase_locals optimization_phase_locals; 901 struct optimization_phase_params min_clock_for_latency_phase; 902 struct optimization_phase_params mcache_phase; 903 struct optimization_phase_params uclk_pstate_phase; 904 struct optimization_phase_params vmin_phase; 905 struct optimization_phase_params stutter_phase; 906 }; 907 908 struct dml2_legacy_core_build_mode_programming_wrapper_locals { 909 struct dml2_core_mode_support_in_out mode_support_params; 910 struct dml2_core_mode_programming_in_out mode_programming_params; 911 struct dml2_core_populate_informative_in_out informative_params; 912 struct top_mcache_calc_mcache_count_and_offsets_in_out calc_mcache_count_params; 913 struct top_mcache_validate_admissability_in_out validate_admissibility_params; 914 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; 915 struct top_mcache_assign_global_mcache_ids_in_out assign_global_mcache_ids_params; 916 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 917 struct dml2_display_cfg optimized_display_cfg; 918 struct core_display_cfg_support_info core_support_info; 919 }; 920 921 struct dml2_top_mcache_verify_mcache_size_locals { 922 struct dml2_calculate_mcache_allocation_in_out calc_mcache_params; 923 }; 924 925 struct dml2_top_mcache_validate_admissability_locals { 926 struct { 927 int pipe_vp_startx[DML2_MAX_DCN_PIPES]; 928 int pipe_vp_endx[DML2_MAX_DCN_PIPES]; 929 } plane0; 930 struct { 931 int pipe_vp_startx[DML2_MAX_DCN_PIPES]; 932 int pipe_vp_endx[DML2_MAX_DCN_PIPES]; 933 } plane1; 934 }; 935 936 struct dml2_top_display_cfg_support_info { 937 const struct dml2_display_cfg *display_config; 938 struct core_display_cfg_support_info core_info; 939 }; 940 941 struct dml2_top_funcs { 942 bool (*check_mode_supported)(struct dml2_check_mode_supported_in_out *in_out); 943 bool (*build_mode_programming)(struct dml2_build_mode_programming_in_out *in_out); 944 bool (*build_mcache_programming)(struct dml2_build_mcache_programming_in_out *in_out); 945 }; 946 947 struct dml2_instance { 948 enum dml2_project_id project_id; 949 950 struct dml2_core_instance core_instance; 951 struct dml2_mcg_instance mcg_instance; 952 struct dml2_dpmm_instance dpmm_instance; 953 struct dml2_pmo_instance pmo_instance; 954 955 struct dml2_soc_bb soc_bbox; 956 struct dml2_ip_capabilities ip_caps; 957 958 struct dml2_mcg_min_clock_table min_clk_table; 959 struct dml2_pmo_options pmo_options; 960 struct dml2_top_funcs funcs; 961 962 struct { 963 struct dml2_initialize_instance_locals initialize_instance_locals; 964 struct dml2_top_mcache_verify_mcache_size_locals mcache_verify_mcache_size_locals; 965 struct dml2_top_mcache_validate_admissability_locals mcache_validate_admissability_locals; 966 struct dml2_check_mode_supported_locals check_mode_supported_locals; 967 struct dml2_build_mode_programming_locals build_mode_programming_locals; 968 } scratch; 969 970 struct { 971 struct { 972 struct dml2_legacy_core_build_mode_programming_wrapper_locals legacy_core_build_mode_programming_wrapper_locals; 973 } scratch; 974 } legacy; 975 }; 976 #endif 977