1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * This contains the functions to handle the descriptors for DesignWare databook
4 * 4.xx.
5 *
6 * Copyright (C) 2015 STMicroelectronics Ltd
7 *
8 * Author: Alexandre Torgue <alexandre.torgue@st.com>
9 */
10
11 #include <linux/stmmac.h>
12 #include "common.h"
13 #include "dwmac4.h"
14 #include "dwmac4_descs.h"
15
dwmac4_wrback_get_tx_status(struct stmmac_extra_stats * x,struct dma_desc * p,void __iomem * ioaddr)16 static int dwmac4_wrback_get_tx_status(struct stmmac_extra_stats *x,
17 struct dma_desc *p,
18 void __iomem *ioaddr)
19 {
20 u32 tdes3 = le32_to_cpu(p->des3);
21 int ret = tx_done;
22
23 /* Get tx owner first */
24 if (unlikely(tdes3 & TDES3_OWN))
25 return tx_dma_own;
26
27 /* Verify tx error by looking at the last segment. */
28 if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR)))
29 return tx_not_ls;
30
31 if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) {
32 ret = tx_err;
33
34 if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT))
35 x->tx_jabber++;
36 if (unlikely(tdes3 & TDES3_PACKET_FLUSHED))
37 x->tx_frame_flushed++;
38 if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) {
39 x->tx_losscarrier++;
40 }
41 if (unlikely(tdes3 & TDES3_NO_CARRIER)) {
42 x->tx_carrier++;
43 }
44 if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||
45 (tdes3 & TDES3_EXCESSIVE_COLLISION)))
46 x->tx_collision +=
47 FIELD_GET(TDES3_COLLISION_COUNT_MASK, tdes3);
48
49 if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
50 x->tx_deferred++;
51
52 if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR)) {
53 x->tx_underflow++;
54 ret |= tx_err_bump_tc;
55 }
56
57 if (unlikely(tdes3 & TDES3_IP_HDR_ERROR))
58 x->tx_ip_header_error++;
59
60 if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR))
61 x->tx_payload_error++;
62 }
63
64 if (unlikely(tdes3 & TDES3_DEFERRED))
65 x->tx_deferred++;
66
67 return ret;
68 }
69
dwmac4_wrback_get_rx_status(struct stmmac_extra_stats * x,struct dma_desc * p)70 static int dwmac4_wrback_get_rx_status(struct stmmac_extra_stats *x,
71 struct dma_desc *p)
72 {
73 u32 rdes1 = le32_to_cpu(p->des1);
74 u32 rdes2 = le32_to_cpu(p->des2);
75 u32 rdes3 = le32_to_cpu(p->des3);
76 int message_type;
77 int ret = good_frame;
78
79 if (unlikely(rdes3 & RDES3_OWN))
80 return dma_own;
81
82 if (unlikely(rdes3 & RDES3_CONTEXT_DESCRIPTOR))
83 return discard_frame;
84 if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
85 return rx_not_ls;
86
87 if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {
88 if (unlikely(rdes3 & RDES3_GIANT_PACKET))
89 x->rx_length++;
90 if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR))
91 x->rx_gmac_overflow++;
92
93 if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG))
94 x->rx_watchdog++;
95
96 if (unlikely(rdes3 & RDES3_RECEIVE_ERROR))
97 x->rx_mii++;
98
99 if (unlikely(rdes3 & RDES3_CRC_ERROR))
100 x->rx_crc_errors++;
101
102 if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR))
103 x->dribbling_bit++;
104
105 ret = discard_frame;
106 }
107
108 message_type = FIELD_GET(RDES1_PTP_MSG_TYPE_MASK, rdes1);
109
110 if (rdes1 & RDES1_IP_HDR_ERROR) {
111 x->ip_hdr_err++;
112 ret |= csum_none;
113 }
114 if (rdes1 & RDES1_IP_CSUM_BYPASSED)
115 x->ip_csum_bypassed++;
116 if (rdes1 & RDES1_IPV4_HEADER)
117 x->ipv4_pkt_rcvd++;
118 if (rdes1 & RDES1_IPV6_HEADER)
119 x->ipv6_pkt_rcvd++;
120 if (rdes1 & RDES1_IP_PAYLOAD_ERROR) {
121 x->ip_payload_err++;
122 ret |= csum_none;
123 }
124
125 if (message_type == RDES_EXT_NO_PTP)
126 x->no_ptp_rx_msg_type_ext++;
127 else if (message_type == RDES_EXT_SYNC)
128 x->ptp_rx_msg_type_sync++;
129 else if (message_type == RDES_EXT_FOLLOW_UP)
130 x->ptp_rx_msg_type_follow_up++;
131 else if (message_type == RDES_EXT_DELAY_REQ)
132 x->ptp_rx_msg_type_delay_req++;
133 else if (message_type == RDES_EXT_DELAY_RESP)
134 x->ptp_rx_msg_type_delay_resp++;
135 else if (message_type == RDES_EXT_PDELAY_REQ)
136 x->ptp_rx_msg_type_pdelay_req++;
137 else if (message_type == RDES_EXT_PDELAY_RESP)
138 x->ptp_rx_msg_type_pdelay_resp++;
139 else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
140 x->ptp_rx_msg_type_pdelay_follow_up++;
141 else if (message_type == RDES_PTP_ANNOUNCE)
142 x->ptp_rx_msg_type_announce++;
143 else if (message_type == RDES_PTP_MANAGEMENT)
144 x->ptp_rx_msg_type_management++;
145 else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
146 x->ptp_rx_msg_pkt_reserved_type++;
147
148 if (rdes1 & RDES1_PTP_PACKET_TYPE)
149 x->ptp_frame_type++;
150 if (rdes1 & RDES1_PTP_VER)
151 x->ptp_ver++;
152 if (rdes1 & RDES1_TIMESTAMP_DROPPED)
153 x->timestamp_dropped++;
154
155 if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) {
156 x->sa_rx_filter_fail++;
157 ret = discard_frame;
158 }
159 if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) {
160 x->da_rx_filter_fail++;
161 ret = discard_frame;
162 }
163
164 if (rdes2 & RDES2_L3_FILTER_MATCH)
165 x->l3_filter_match++;
166 if (rdes2 & RDES2_L4_FILTER_MATCH)
167 x->l4_filter_match++;
168 if (rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
169 x->l3_l4_filter_no_match++;
170
171 return ret;
172 }
173
dwmac4_rd_get_tx_len(struct dma_desc * p)174 static int dwmac4_rd_get_tx_len(struct dma_desc *p)
175 {
176 return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
177 }
178
dwmac4_get_tx_owner(struct dma_desc * p)179 static int dwmac4_get_tx_owner(struct dma_desc *p)
180 {
181 return (le32_to_cpu(p->des3) & TDES3_OWN) >> TDES3_OWN_SHIFT;
182 }
183
dwmac4_set_tx_owner(struct dma_desc * p)184 static void dwmac4_set_tx_owner(struct dma_desc *p)
185 {
186 p->des3 |= cpu_to_le32(TDES3_OWN);
187 }
188
dwmac4_set_rx_owner(struct dma_desc * p,int disable_rx_ic)189 static void dwmac4_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
190 {
191 u32 flags = (RDES3_OWN | RDES3_BUFFER1_VALID_ADDR);
192
193 if (!disable_rx_ic)
194 flags |= RDES3_INT_ON_COMPLETION_EN;
195
196 p->des3 |= cpu_to_le32(flags);
197 }
198
dwmac4_get_tx_ls(struct dma_desc * p)199 static int dwmac4_get_tx_ls(struct dma_desc *p)
200 {
201 return (le32_to_cpu(p->des3) & TDES3_LAST_DESCRIPTOR)
202 >> TDES3_LAST_DESCRIPTOR_SHIFT;
203 }
204
dwmac4_wrback_get_rx_vlan_tci(struct dma_desc * p)205 static u16 dwmac4_wrback_get_rx_vlan_tci(struct dma_desc *p)
206 {
207 return (le32_to_cpu(p->des0) & RDES0_VLAN_TAG_MASK);
208 }
209
dwmac4_wrback_get_rx_vlan_valid(struct dma_desc * p)210 static bool dwmac4_wrback_get_rx_vlan_valid(struct dma_desc *p)
211 {
212 return ((le32_to_cpu(p->des3) & RDES3_LAST_DESCRIPTOR) &&
213 (le32_to_cpu(p->des3) & RDES3_RDES0_VALID));
214 }
215
dwmac4_wrback_get_rx_frame_len(struct dma_desc * p,int rx_coe)216 static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)
217 {
218 return (le32_to_cpu(p->des3) & RDES3_PACKET_SIZE_MASK);
219 }
220
dwmac4_rd_enable_tx_timestamp(struct dma_desc * p)221 static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)
222 {
223 p->des2 |= cpu_to_le32(TDES2_TIMESTAMP_ENABLE);
224 }
225
dwmac4_wrback_get_tx_timestamp_status(struct dma_desc * p)226 static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)
227 {
228 /* Context type from W/B descriptor must be zero */
229 if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE)
230 return 0;
231
232 /* Tx Timestamp Status is 1 so des0 and des1'll have valid values */
233 if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)
234 return 1;
235
236 return 0;
237 }
238
dwmac4_get_timestamp(void * desc,u32 ats,u64 * ts)239 static inline void dwmac4_get_timestamp(void *desc, u32 ats, u64 *ts)
240 {
241 struct dma_desc *p = (struct dma_desc *)desc;
242 u64 ns;
243
244 ns = le32_to_cpu(p->des0);
245 /* convert high/sec time stamp value to nanosecond */
246 ns += le32_to_cpu(p->des1) * 1000000000ULL;
247
248 *ts = ns;
249 }
250
dwmac4_rx_check_timestamp(void * desc)251 static int dwmac4_rx_check_timestamp(void *desc)
252 {
253 struct dma_desc *p = (struct dma_desc *)desc;
254 u32 rdes0 = le32_to_cpu(p->des0);
255 u32 rdes1 = le32_to_cpu(p->des1);
256 u32 rdes3 = le32_to_cpu(p->des3);
257 bool own, ctxt;
258 int ret = 1;
259
260 own = rdes3 & RDES3_OWN;
261 ctxt = rdes3 & RDES3_CONTEXT_DESCRIPTOR;
262
263 if (likely(!own && ctxt)) {
264 if ((rdes0 == 0xffffffff) && (rdes1 == 0xffffffff))
265 /* Corrupted value */
266 ret = -EINVAL;
267 else
268 /* A valid Timestamp is ready to be read */
269 ret = 0;
270 }
271
272 /* Timestamp not ready */
273 return ret;
274 }
275
dwmac4_wrback_get_rx_timestamp_status(void * desc,void * next_desc,u32 ats)276 static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
277 u32 ats)
278 {
279 struct dma_desc *p = (struct dma_desc *)desc;
280 int ret = -EINVAL;
281
282 /* Get the status from normal w/b descriptor */
283 if (likely(le32_to_cpu(p->des3) & RDES3_RDES1_VALID)) {
284 if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) {
285 int i = 0;
286
287 /* Check if timestamp is OK from context descriptor */
288 do {
289 ret = dwmac4_rx_check_timestamp(next_desc);
290 if (ret < 0)
291 goto exit;
292 i++;
293
294 } while ((ret == 1) && (i < 10));
295
296 if (i == 10)
297 ret = -EBUSY;
298 }
299 }
300 exit:
301 if (likely(ret == 0))
302 return 1;
303
304 return 0;
305 }
306
dwmac4_rd_init_rx_desc(struct dma_desc * p,int disable_rx_ic,int mode,int end,int bfsize)307 static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
308 int mode, int end, int bfsize)
309 {
310 dwmac4_set_rx_owner(p, disable_rx_ic);
311 }
312
dwmac4_rd_init_tx_desc(struct dma_desc * p,int mode,int end)313 static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
314 {
315 p->des0 = 0;
316 p->des1 = 0;
317 p->des2 = 0;
318 p->des3 = 0;
319 }
320
dwmac4_rd_prepare_tx_desc(struct dma_desc * p,int is_fs,int len,bool csum_flag,int mode,bool tx_own,bool ls,unsigned int tot_pkt_len)321 static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
322 bool csum_flag, int mode, bool tx_own,
323 bool ls, unsigned int tot_pkt_len)
324 {
325 u32 tdes3 = le32_to_cpu(p->des3);
326
327 p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK);
328
329 tdes3 |= tot_pkt_len & TDES3_PACKET_SIZE_MASK;
330 if (is_fs)
331 tdes3 |= TDES3_FIRST_DESCRIPTOR;
332 else
333 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
334
335 tdes3 = u32_replace_bits(tdes3, csum_flag ? TX_CIC_FULL : 0,
336 TDES3_CHECKSUM_INSERTION_MASK);
337
338 if (ls)
339 tdes3 |= TDES3_LAST_DESCRIPTOR;
340 else
341 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
342
343 /* Finally set the OWN bit. Later the DMA will start! */
344 if (tx_own)
345 tdes3 |= TDES3_OWN;
346
347 if (is_fs && tx_own)
348 /* When the own bit, for the first frame, has to be set, all
349 * descriptors for the same frame has to be set before, to
350 * avoid race condition.
351 */
352 dma_wmb();
353
354 p->des3 = cpu_to_le32(tdes3);
355 }
356
dwmac4_rd_prepare_tso_tx_desc(struct dma_desc * p,int is_fs,int len1,int len2,bool tx_own,bool ls,unsigned int tcphdrlen,unsigned int tcppayloadlen)357 static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
358 int len1, int len2, bool tx_own,
359 bool ls, unsigned int tcphdrlen,
360 unsigned int tcppayloadlen)
361 {
362 u32 tdes3 = le32_to_cpu(p->des3);
363
364 if (len1)
365 p->des2 |= cpu_to_le32(FIELD_PREP(TDES2_BUFFER1_SIZE_MASK,
366 len1));
367
368 if (len2)
369 p->des2 |= cpu_to_le32(FIELD_PREP(TDES2_BUFFER2_SIZE_MASK,
370 len2));
371
372 if (is_fs) {
373 tdes3 |= TDES3_FIRST_DESCRIPTOR |
374 TDES3_TCP_SEGMENTATION_ENABLE |
375 FIELD_PREP(TDES3_SLOT_NUMBER_MASK, tcphdrlen) |
376 FIELD_PREP(TDES3_TCP_PKT_PAYLOAD_MASK, tcppayloadlen);
377 } else {
378 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
379 }
380
381 if (ls)
382 tdes3 |= TDES3_LAST_DESCRIPTOR;
383 else
384 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
385
386 /* Finally set the OWN bit. Later the DMA will start! */
387 if (tx_own)
388 tdes3 |= TDES3_OWN;
389
390 if (is_fs && tx_own)
391 /* When the own bit, for the first frame, has to be set, all
392 * descriptors for the same frame has to be set before, to
393 * avoid race condition.
394 */
395 dma_wmb();
396
397 p->des3 = cpu_to_le32(tdes3);
398 }
399
dwmac4_release_tx_desc(struct dma_desc * p,int mode)400 static void dwmac4_release_tx_desc(struct dma_desc *p, int mode)
401 {
402 p->des0 = 0;
403 p->des1 = 0;
404 p->des2 = 0;
405 p->des3 = 0;
406 }
407
dwmac4_rd_set_tx_ic(struct dma_desc * p)408 static void dwmac4_rd_set_tx_ic(struct dma_desc *p)
409 {
410 p->des2 |= cpu_to_le32(TDES2_INTERRUPT_ON_COMPLETION);
411 }
412
dwmac4_display_ring(void * head,unsigned int size,bool rx,dma_addr_t dma_rx_phy,unsigned int desc_size)413 static void dwmac4_display_ring(void *head, unsigned int size, bool rx,
414 dma_addr_t dma_rx_phy, unsigned int desc_size)
415 {
416 dma_addr_t dma_addr;
417 int i;
418
419 pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
420
421 if (desc_size == sizeof(struct dma_desc)) {
422 struct dma_desc *p = (struct dma_desc *)head;
423
424 for (i = 0; i < size; i++) {
425 dma_addr = dma_rx_phy + i * sizeof(*p);
426 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
427 i, &dma_addr,
428 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
429 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
430 p++;
431 }
432 } else if (desc_size == sizeof(struct dma_extended_desc)) {
433 struct dma_extended_desc *extp = (struct dma_extended_desc *)head;
434
435 for (i = 0; i < size; i++) {
436 dma_addr = dma_rx_phy + i * sizeof(*extp);
437 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
438 i, &dma_addr,
439 le32_to_cpu(extp->basic.des0), le32_to_cpu(extp->basic.des1),
440 le32_to_cpu(extp->basic.des2), le32_to_cpu(extp->basic.des3),
441 le32_to_cpu(extp->des4), le32_to_cpu(extp->des5),
442 le32_to_cpu(extp->des6), le32_to_cpu(extp->des7));
443 extp++;
444 }
445 } else if (desc_size == sizeof(struct dma_edesc)) {
446 struct dma_edesc *ep = (struct dma_edesc *)head;
447
448 for (i = 0; i < size; i++) {
449 dma_addr = dma_rx_phy + i * sizeof(*ep);
450 pr_info("%03d [%pad]: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
451 i, &dma_addr,
452 le32_to_cpu(ep->des4), le32_to_cpu(ep->des5),
453 le32_to_cpu(ep->des6), le32_to_cpu(ep->des7),
454 le32_to_cpu(ep->basic.des0), le32_to_cpu(ep->basic.des1),
455 le32_to_cpu(ep->basic.des2), le32_to_cpu(ep->basic.des3));
456 ep++;
457 }
458 } else {
459 pr_err("unsupported descriptor!");
460 }
461 }
462
dwmac4_set_mss_ctxt(struct dma_desc * p,unsigned int mss)463 static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
464 {
465 p->des0 = 0;
466 p->des1 = 0;
467 p->des2 = cpu_to_le32(mss);
468 p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);
469 }
470
dwmac4_set_addr(struct dma_desc * p,dma_addr_t addr)471 static void dwmac4_set_addr(struct dma_desc *p, dma_addr_t addr)
472 {
473 p->des0 = cpu_to_le32(lower_32_bits(addr));
474 p->des1 = cpu_to_le32(upper_32_bits(addr));
475 }
476
dwmac4_clear(struct dma_desc * p)477 static void dwmac4_clear(struct dma_desc *p)
478 {
479 p->des0 = 0;
480 p->des1 = 0;
481 p->des2 = 0;
482 p->des3 = 0;
483 }
484
dwmac4_set_sarc(struct dma_desc * p,u32 sarc_type)485 static void dwmac4_set_sarc(struct dma_desc *p, u32 sarc_type)
486 {
487 p->des3 |= cpu_to_le32(FIELD_PREP(TDES3_SA_INSERT_CTRL_MASK,
488 sarc_type));
489 }
490
set_16kib_bfsize(int mtu)491 static int set_16kib_bfsize(int mtu)
492 {
493 int ret = 0;
494
495 if (unlikely(mtu >= BUF_SIZE_8KiB))
496 ret = BUF_SIZE_16KiB;
497 return ret;
498 }
499
dwmac4_set_vlan_tag(struct dma_desc * p,u16 tag,u16 inner_tag,u32 inner_type)500 static void dwmac4_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
501 u32 inner_type)
502 {
503 p->des0 = 0;
504 p->des1 = 0;
505 p->des2 = 0;
506 p->des3 = 0;
507
508 /* Inner VLAN */
509 if (inner_type) {
510 p->des2 = cpu_to_le32(FIELD_PREP(TDES2_IVT_MASK, inner_tag));
511 p->des3 = cpu_to_le32(FIELD_PREP(TDES3_IVTIR_MASK, inner_type) |
512 TDES3_IVLTV);
513 }
514
515 /* Outer VLAN */
516 p->des3 |= cpu_to_le32(tag & TDES3_VLAN_TAG);
517 p->des3 |= cpu_to_le32(TDES3_VLTV);
518
519 p->des3 |= cpu_to_le32(TDES3_CONTEXT_TYPE);
520 }
521
dwmac4_set_vlan(struct dma_desc * p,u32 type)522 static void dwmac4_set_vlan(struct dma_desc *p, u32 type)
523 {
524 p->des2 |= cpu_to_le32(FIELD_PREP(TDES2_VLAN_TAG_MASK, type));
525 }
526
dwmac4_get_rx_header_len(struct dma_desc * p,unsigned int * len)527 static void dwmac4_get_rx_header_len(struct dma_desc *p, unsigned int *len)
528 {
529 *len = le32_to_cpu(p->des2) & RDES2_HL;
530 }
531
dwmac4_set_sec_addr(struct dma_desc * p,dma_addr_t addr,bool buf2_valid)532 static void dwmac4_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool buf2_valid)
533 {
534 p->des2 = cpu_to_le32(lower_32_bits(addr));
535 p->des3 = cpu_to_le32(upper_32_bits(addr));
536
537 if (buf2_valid)
538 p->des3 |= cpu_to_le32(RDES3_BUFFER2_VALID_ADDR);
539 else
540 p->des3 &= cpu_to_le32(~RDES3_BUFFER2_VALID_ADDR);
541 }
542
dwmac4_set_tbs(struct dma_edesc * p,u32 sec,u32 nsec)543 static void dwmac4_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)
544 {
545 p->des4 = cpu_to_le32((sec & TDES4_LT) | TDES4_LTV);
546 p->des5 = cpu_to_le32(nsec & TDES5_LT);
547 p->des6 = 0;
548 p->des7 = 0;
549 }
550
551 const struct stmmac_desc_ops dwmac4_desc_ops = {
552 .tx_status = dwmac4_wrback_get_tx_status,
553 .rx_status = dwmac4_wrback_get_rx_status,
554 .get_tx_len = dwmac4_rd_get_tx_len,
555 .get_tx_owner = dwmac4_get_tx_owner,
556 .set_tx_owner = dwmac4_set_tx_owner,
557 .set_rx_owner = dwmac4_set_rx_owner,
558 .get_tx_ls = dwmac4_get_tx_ls,
559 .get_rx_vlan_tci = dwmac4_wrback_get_rx_vlan_tci,
560 .get_rx_vlan_valid = dwmac4_wrback_get_rx_vlan_valid,
561 .get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
562 .enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,
563 .get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,
564 .get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status,
565 .get_timestamp = dwmac4_get_timestamp,
566 .set_tx_ic = dwmac4_rd_set_tx_ic,
567 .prepare_tx_desc = dwmac4_rd_prepare_tx_desc,
568 .prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,
569 .release_tx_desc = dwmac4_release_tx_desc,
570 .init_rx_desc = dwmac4_rd_init_rx_desc,
571 .init_tx_desc = dwmac4_rd_init_tx_desc,
572 .display_ring = dwmac4_display_ring,
573 .set_mss = dwmac4_set_mss_ctxt,
574 .set_addr = dwmac4_set_addr,
575 .clear = dwmac4_clear,
576 .set_sarc = dwmac4_set_sarc,
577 .set_vlan_tag = dwmac4_set_vlan_tag,
578 .set_vlan = dwmac4_set_vlan,
579 .get_rx_header_len = dwmac4_get_rx_header_len,
580 .set_sec_addr = dwmac4_set_sec_addr,
581 .set_tbs = dwmac4_set_tbs,
582 };
583
584 const struct stmmac_mode_ops dwmac4_ring_mode_ops = {
585 .set_16kib_bfsize = set_16kib_bfsize,
586 };
587