1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef _XE_BO_TYPES_H_ 7 #define _XE_BO_TYPES_H_ 8 9 #include <linux/iosys-map.h> 10 11 #include <drm/drm_gpusvm.h> 12 #include <drm/drm_pagemap.h> 13 #include <drm/ttm/ttm_bo.h> 14 #include <drm/ttm/ttm_device.h> 15 #include <drm/ttm/ttm_placement.h> 16 17 #include "xe_device_types.h" 18 #include "xe_ggtt_types.h" 19 20 struct xe_device; 21 struct xe_vm; 22 23 #define XE_BO_MAX_PLACEMENTS 3 24 25 /* TODO: To be selected with VM_MADVISE */ 26 #define XE_BO_PRIORITY_NORMAL 1 27 28 /** 29 * struct xe_bo - Xe buffer object 30 */ 31 struct xe_bo { 32 /** @ttm: TTM base buffer object */ 33 struct ttm_buffer_object ttm; 34 /** @backup_obj: The backup object when pinned and suspended (vram only) */ 35 struct xe_bo *backup_obj; 36 /** @parent_obj: Ref to parent bo if this a backup_obj */ 37 struct xe_bo *parent_obj; 38 /** @flags: flags for this buffer object */ 39 u32 flags; 40 /** @vm: VM this BO is attached to, for extobj this will be NULL */ 41 struct xe_vm *vm; 42 /** @tile: Tile this BO is attached to (kernel BO only) */ 43 struct xe_tile *tile; 44 /** @placements: valid placements for this BO */ 45 struct ttm_place placements[XE_BO_MAX_PLACEMENTS]; 46 /** @placement: current placement for this BO */ 47 struct ttm_placement placement; 48 /** @ggtt_node: Array of GGTT nodes if this BO is mapped in the GGTTs */ 49 struct xe_ggtt_node *ggtt_node[XE_MAX_TILES_PER_DEVICE]; 50 /** @vmap: iosys map of this buffer */ 51 struct iosys_map vmap; 52 /** @kmap: TTM bo kmap object for internal use only. Keep off. */ 53 struct ttm_bo_kmap_obj kmap; 54 /** @pinned_link: link to present / evicted list of pinned BO */ 55 struct list_head pinned_link; 56 #ifdef CONFIG_PROC_FS 57 /** 58 * @client: @xe_drm_client which created the bo 59 */ 60 struct xe_drm_client *client; 61 /** 62 * @client_link: Link into @xe_drm_client.objects_list 63 */ 64 struct list_head client_link; 65 #endif 66 /** @attr: User controlled attributes for bo */ 67 struct { 68 /** 69 * @atomic_access: type of atomic access bo needs 70 * protected by bo dma-resv lock 71 */ 72 u32 atomic_access; 73 } attr; 74 /** 75 * @pxp_key_instance: PXP key instance this BO was created against. A 76 * 0 in this variable indicates that the BO does not use PXP encryption. 77 */ 78 u32 pxp_key_instance; 79 80 /** @freed: List node for delayed put. */ 81 struct llist_node freed; 82 /** @update_index: Update index if PT BO */ 83 int update_index; 84 /** @created: Whether the bo has passed initial creation */ 85 bool created; 86 87 /** @ccs_cleared: true means that CCS region of BO is already cleared */ 88 bool ccs_cleared; 89 90 /** @bb_ccs: BB instructions of CCS read/write. Valid only for VF */ 91 struct xe_bb *bb_ccs[XE_SRIOV_VF_CCS_CTX_COUNT]; 92 93 /** 94 * @cpu_caching: CPU caching mode. Currently only used for userspace 95 * objects. Exceptions are system memory on DGFX, which is always 96 * WB. 97 */ 98 u16 cpu_caching; 99 100 /** @devmem_allocation: SVM device memory allocation */ 101 struct drm_pagemap_devmem devmem_allocation; 102 103 /** @vram_userfault_link: Link into @mem_access.vram_userfault.list */ 104 struct list_head vram_userfault_link; 105 106 /** 107 * @min_align: minimum alignment needed for this BO if different 108 * from default 109 */ 110 u64 min_align; 111 }; 112 113 #endif 114