1 /*-
2 * Copyright (c) 2016 Ganbold Tsagaankhuu <ganbold@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 /*
28 * Allwinner Consumer IR controller
29 */
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/rman.h>
37 #include <sys/sysctl.h>
38 #include <machine/bus.h>
39
40 #include <dev/ofw/openfirm.h>
41 #include <dev/ofw/ofw_bus.h>
42 #include <dev/ofw/ofw_bus_subr.h>
43 #include <dev/clk/clk.h>
44 #include <dev/hwreset/hwreset.h>
45
46 #include <dev/evdev/input.h>
47 #include <dev/evdev/evdev.h>
48
49 #define READ(_sc, _r) bus_read_4((_sc)->res[0], (_r))
50 #define WRITE(_sc, _r, _v) bus_write_4((_sc)->res[0], (_r), (_v))
51
52 /* IR Control */
53 #define AW_IR_CTL 0x00
54 /* Global Enable */
55 #define AW_IR_CTL_GEN (1 << 0)
56 /* RX enable */
57 #define AW_IR_CTL_RXEN (1 << 1)
58 /* CIR mode enable */
59 #define AW_IR_CTL_MD (1 << 4) | (1 << 5)
60
61 /* RX Config Reg */
62 #define AW_IR_RXCTL 0x10
63 /* Pulse Polarity Invert flag */
64 #define AW_IR_RXCTL_RPPI (1 << 2)
65
66 /* RX Data */
67 #define AW_IR_RXFIFO 0x20
68
69 /* RX Interrupt Control */
70 #define AW_IR_RXINT 0x2C
71 /* RX FIFO Overflow */
72 #define AW_IR_RXINT_ROI_EN (1 << 0)
73 /* RX Packet End */
74 #define AW_IR_RXINT_RPEI_EN (1 << 1)
75 /* RX FIFO Data Available */
76 #define AW_IR_RXINT_RAI_EN (1 << 4)
77 /* RX FIFO available byte level */
78 #define AW_IR_RXINT_RAL(val) ((val) << 8)
79
80 /* RX Interrupt Status Reg */
81 #define AW_IR_RXSTA 0x30
82 /* RX FIFO Get Available Counter */
83 #define AW_IR_RXSTA_COUNTER(val) (((val) >> 8) & (sc->fifo_size * 2 - 1))
84 /* Clear all interrupt status */
85 #define AW_IR_RXSTA_CLEARALL 0xff
86
87 /* IR Sample Configure Reg */
88 #define AW_IR_CIR 0x34
89
90 /*
91 * Frequency sample: 23437.5Hz (Cycle: 42.7us)
92 * Pulse of NEC Remote > 560us
93 */
94 /* Filter Threshold = 8 * 42.7 = ~341us < 500us */
95 #define AW_IR_RXFILT_VAL (((8) & 0x3f) << 2)
96 /* Idle Threshold = (2 + 1) * 128 * 42.7 = ~16.4ms > 9ms */
97 #define AW_IR_RXIDLE_VAL (((2) & 0xff) << 8)
98
99 /* Bit 15 - value (pulse/space) */
100 #define VAL_MASK 0x80
101 /* Bits 0:14 - sample duration */
102 #define PERIOD_MASK 0x7f
103
104 /* Clock rate for IR0 or IR1 clock in CIR mode */
105 #define AW_IR_BASE_CLK 3000000
106 /* Frequency sample 3MHz/64 = 46875Hz (21.3us) */
107 #define AW_IR_SAMPLE_64 (0 << 0)
108 /* Frequency sample 3MHz/128 = 23437.5Hz (42.7us) */
109 #define AW_IR_SAMPLE_128 (1 << 0)
110
111 #define AW_IR_ERROR_CODE 0xffffffff
112 #define AW_IR_REPEAT_CODE 0x0
113
114 /* 80 * 42.7 = ~3.4ms, Lead1(4.5ms) > AW_IR_L1_MIN */
115 #define AW_IR_L1_MIN 80
116 /* 40 * 42.7 = ~1.7ms, Lead0(4.5ms) Lead0R(2.25ms) > AW_IR_L0_MIN */
117 #define AW_IR_L0_MIN 40
118 /* 26 * 42.7 = ~1109us ~= 561 * 2, Pulse < AW_IR_PMAX */
119 #define AW_IR_PMAX 26
120 /* 26 * 42.7 = ~1109us ~= 561 * 2, D1 > AW_IR_DMID, D0 <= AW_IR_DMID */
121 #define AW_IR_DMID 26
122 /* 53 * 42.7 = ~2263us ~= 561 * 4, D < AW_IR_DMAX */
123 #define AW_IR_DMAX 53
124
125 /* Active Thresholds */
126 #define AW_IR_ACTIVE_T_VAL AW_IR_L1_MIN
127 #define AW_IR_ACTIVE_T (((AW_IR_ACTIVE_T_VAL - 1) & 0xff) << 16)
128 #define AW_IR_ACTIVE_T_C_VAL 0
129 #define AW_IR_ACTIVE_T_C ((AW_IR_ACTIVE_T_C_VAL & 0xff) << 23)
130
131 /* Code masks */
132 #define CODE_MASK 0x00ff00ff
133 #define INV_CODE_MASK 0xff00ff00
134 #define VALID_CODE_MASK 0x00ff0000
135
136 enum {
137 A10_IR = 1,
138 A13_IR,
139 A31_IR,
140 H616_IR,
141 };
142
143 #define AW_IR_RAW_BUF_SIZE 128
144
145 SYSCTL_NODE(_hw, OID_AUTO, aw_cir, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
146 "aw_cir driver");
147
148 static int aw_cir_debug = 0;
149 SYSCTL_INT(_hw_aw_cir, OID_AUTO, debug, CTLFLAG_RWTUN, &aw_cir_debug, 0,
150 "Debug 1=on 0=off");
151
152 struct aw_ir_softc {
153 device_t dev;
154 struct resource *res[2];
155 void * intrhand;
156 int fifo_size;
157 int dcnt; /* Packet Count */
158 unsigned char buf[AW_IR_RAW_BUF_SIZE];
159 struct evdev_dev *sc_evdev;
160 };
161
162 static struct resource_spec aw_ir_spec[] = {
163 { SYS_RES_MEMORY, 0, RF_ACTIVE },
164 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
165 { -1, 0 }
166 };
167
168 static struct ofw_compat_data compat_data[] = {
169 { "allwinner,sun4i-a10-ir", A10_IR },
170 { "allwinner,sun5i-a13-ir", A13_IR },
171 { "allwinner,sun6i-a31-ir", A31_IR },
172 { "allwinner,sun6i-h616-ir", H616_IR },
173 { NULL, 0 }
174 };
175
176 static void
aw_ir_buf_reset(struct aw_ir_softc * sc)177 aw_ir_buf_reset(struct aw_ir_softc *sc)
178 {
179
180 sc->dcnt = 0;
181 }
182
183 static void
aw_ir_buf_write(struct aw_ir_softc * sc,unsigned char data)184 aw_ir_buf_write(struct aw_ir_softc *sc, unsigned char data)
185 {
186
187 if (sc->dcnt < AW_IR_RAW_BUF_SIZE)
188 sc->buf[sc->dcnt++] = data;
189 else
190 if (bootverbose)
191 device_printf(sc->dev, "IR RX Buffer Full!\n");
192 }
193
194 static int
aw_ir_buf_full(struct aw_ir_softc * sc)195 aw_ir_buf_full(struct aw_ir_softc *sc)
196 {
197
198 return (sc->dcnt >= AW_IR_RAW_BUF_SIZE);
199 }
200
201 static unsigned char
aw_ir_read_data(struct aw_ir_softc * sc)202 aw_ir_read_data(struct aw_ir_softc *sc)
203 {
204
205 return (unsigned char)(READ(sc, AW_IR_RXFIFO) & 0xff);
206 }
207
208 static unsigned long
aw_ir_decode_packets(struct aw_ir_softc * sc)209 aw_ir_decode_packets(struct aw_ir_softc *sc)
210 {
211 unsigned int len, code;
212 unsigned int active_delay;
213 unsigned char val, last;
214 int i, bitcount;
215
216 if (bootverbose && __predict_false(aw_cir_debug) != 0)
217 device_printf(sc->dev, "sc->dcnt = %d\n", sc->dcnt);
218
219 /* Find Lead 1 (bit separator) */
220 active_delay = AW_IR_ACTIVE_T_VAL *
221 (AW_IR_ACTIVE_T_C_VAL != 0 ? 128 : 1);
222 len = active_delay;
223 if (bootverbose && __predict_false(aw_cir_debug) != 0)
224 device_printf(sc->dev, "Initial len: %d\n", len);
225 for (i = 0; i < sc->dcnt; i++) {
226 val = sc->buf[i];
227 if (val & VAL_MASK)
228 len += (val & PERIOD_MASK) + 1;
229 else {
230 if (len > AW_IR_L1_MIN)
231 break;
232 len = 0;
233 }
234 }
235 if (bootverbose && __predict_false(aw_cir_debug) != 0)
236 device_printf(sc->dev, "len = %d\n", len);
237 if ((val & VAL_MASK) || (len <= AW_IR_L1_MIN)) {
238 if (bootverbose && __predict_false(aw_cir_debug) != 0)
239 device_printf(sc->dev, "Bit separator error\n");
240 goto error_code;
241 }
242
243 /* Find Lead 0 (bit length) */
244 len = 0;
245 for (; i < sc->dcnt; i++) {
246 val = sc->buf[i];
247 if (val & VAL_MASK) {
248 if(len > AW_IR_L0_MIN)
249 break;
250 len = 0;
251 } else
252 len += (val & PERIOD_MASK) + 1;
253 }
254 if ((!(val & VAL_MASK)) || (len <= AW_IR_L0_MIN)) {
255 if (bootverbose && __predict_false(aw_cir_debug) != 0)
256 device_printf(sc->dev, "Bit length error\n");
257 goto error_code;
258 }
259
260 /* Start decoding */
261 code = 0;
262 bitcount = 0;
263 last = 1;
264 len = 0;
265 for (; i < sc->dcnt; i++) {
266 val = sc->buf[i];
267 if (last) {
268 if (val & VAL_MASK)
269 len += (val & PERIOD_MASK) + 1;
270 else {
271 if (len > AW_IR_PMAX) {
272 if (bootverbose)
273 device_printf(sc->dev,
274 "Pulse error, len=%d\n",
275 len);
276 goto error_code;
277 }
278 last = 0;
279 len = (val & PERIOD_MASK) + 1;
280 }
281 } else {
282 if (val & VAL_MASK) {
283 if (len > AW_IR_DMAX) {
284 if (bootverbose)
285 device_printf(sc->dev,
286 "Distance error, len=%d\n",
287 len);
288 goto error_code;
289 } else {
290 if (len > AW_IR_DMID) {
291 /* Decode */
292 code |= 1 << bitcount;
293 }
294 bitcount++;
295 if (bitcount == 32)
296 break; /* Finish decoding */
297 }
298 last = 1;
299 len = (val & PERIOD_MASK) + 1;
300 } else
301 len += (val & PERIOD_MASK) + 1;
302 }
303 }
304 return (code);
305
306 error_code:
307
308 return (AW_IR_ERROR_CODE);
309 }
310
311 static int
aw_ir_validate_code(unsigned long code)312 aw_ir_validate_code(unsigned long code)
313 {
314 unsigned long v1, v2;
315
316 /* Don't check address */
317 v1 = code & CODE_MASK;
318 v2 = (code & INV_CODE_MASK) >> 8;
319
320 if (((v1 ^ v2) & VALID_CODE_MASK) == VALID_CODE_MASK)
321 return (0); /* valid */
322 else
323 return (1); /* invalid */
324 }
325
326 static void
aw_ir_intr(void * arg)327 aw_ir_intr(void *arg)
328 {
329 struct aw_ir_softc *sc;
330 uint32_t val;
331 int i, dcnt;
332 unsigned long ir_code;
333 int stat;
334
335 sc = (struct aw_ir_softc *)arg;
336
337 /* Read RX interrupt status */
338 val = READ(sc, AW_IR_RXSTA);
339 if (bootverbose && __predict_false(aw_cir_debug) != 0)
340 device_printf(sc->dev, "RX interrupt status: %x\n", val);
341
342 /* Clean all pending interrupt statuses */
343 WRITE(sc, AW_IR_RXSTA, val | AW_IR_RXSTA_CLEARALL);
344
345 /* When Rx FIFO Data available or Packet end */
346 if (val & (AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RPEI_EN)) {
347 if (bootverbose && __predict_false(aw_cir_debug) != 0)
348 device_printf(sc->dev,
349 "RX FIFO Data available or Packet end\n");
350 /* Get available message count in RX FIFO */
351 dcnt = AW_IR_RXSTA_COUNTER(val);
352 /* Read FIFO */
353 for (i = 0; i < dcnt; i++) {
354 if (aw_ir_buf_full(sc)) {
355 if (bootverbose)
356 device_printf(sc->dev,
357 "raw buffer full\n");
358 break;
359 } else
360 aw_ir_buf_write(sc, aw_ir_read_data(sc));
361 }
362 }
363
364 if (val & AW_IR_RXINT_RPEI_EN) {
365 /* RX Packet end */
366 if (bootverbose && __predict_false(aw_cir_debug) != 0)
367 device_printf(sc->dev, "RX Packet end\n");
368 ir_code = aw_ir_decode_packets(sc);
369 stat = aw_ir_validate_code(ir_code);
370 if (stat == 0) {
371 evdev_push_event(sc->sc_evdev,
372 EV_MSC, MSC_SCAN, ir_code);
373 evdev_sync(sc->sc_evdev);
374 }
375 if (bootverbose && __predict_false(aw_cir_debug) != 0) {
376 device_printf(sc->dev, "Final IR code: %lx\n",
377 ir_code);
378 device_printf(sc->dev, "IR code status: %d\n",
379 stat);
380 }
381 aw_ir_buf_reset(sc);
382 }
383 if (val & AW_IR_RXINT_ROI_EN) {
384 /* RX FIFO overflow */
385 if (bootverbose)
386 device_printf(sc->dev, "RX FIFO overflow\n");
387 /* Flush raw buffer */
388 aw_ir_buf_reset(sc);
389 }
390 }
391
392 static int
aw_ir_probe(device_t dev)393 aw_ir_probe(device_t dev)
394 {
395
396 if (!ofw_bus_status_okay(dev))
397 return (ENXIO);
398
399 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
400 return (ENXIO);
401
402 device_set_desc(dev, "Allwinner CIR controller");
403 return (BUS_PROBE_DEFAULT);
404 }
405
406 static int
aw_ir_attach(device_t dev)407 aw_ir_attach(device_t dev)
408 {
409 struct aw_ir_softc *sc;
410 hwreset_t rst_apb;
411 clk_t clk_ir, clk_gate;
412 int err;
413 uint32_t val = 0;
414
415 clk_ir = clk_gate = NULL;
416 rst_apb = NULL;
417
418 sc = device_get_softc(dev);
419 sc->dev = dev;
420
421 if (bus_alloc_resources(dev, aw_ir_spec, sc->res) != 0) {
422 device_printf(dev, "could not allocate memory resource\n");
423 return (ENXIO);
424 }
425
426 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
427 case A10_IR:
428 sc->fifo_size = 16;
429 break;
430 case A13_IR:
431 case A31_IR:
432 case H616_IR:
433 sc->fifo_size = 64;
434 break;
435 }
436
437 /* De-assert reset */
438 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst_apb) == 0) {
439 err = hwreset_deassert(rst_apb);
440 if (err != 0) {
441 device_printf(dev, "cannot de-assert reset\n");
442 goto error;
443 }
444 }
445
446 /* Reset buffer */
447 aw_ir_buf_reset(sc);
448
449 /* Get clocks and enable them */
450 err = clk_get_by_ofw_name(dev, 0, "apb", &clk_gate);
451 if (err != 0) {
452 device_printf(dev, "Cannot get gate clock\n");
453 goto error;
454 }
455 err = clk_get_by_ofw_name(dev, 0, "ir", &clk_ir);
456 if (err != 0) {
457 device_printf(dev, "Cannot get IR clock\n");
458 goto error;
459 }
460 /* Set clock rate */
461 err = clk_set_freq(clk_ir, AW_IR_BASE_CLK, 0);
462 if (err != 0) {
463 device_printf(dev, "cannot set IR clock rate\n");
464 goto error;
465 }
466 /* Enable clocks */
467 err = clk_enable(clk_gate);
468 if (err != 0) {
469 device_printf(dev, "Cannot enable clk gate\n");
470 goto error;
471 }
472 err = clk_enable(clk_ir);
473 if (err != 0) {
474 device_printf(dev, "Cannot enable IR clock\n");
475 goto error;
476 }
477
478 if (bus_setup_intr(dev, sc->res[1],
479 INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_ir_intr, sc,
480 &sc->intrhand)) {
481 bus_release_resources(dev, aw_ir_spec, sc->res);
482 device_printf(dev, "cannot setup interrupt handler\n");
483 err = ENXIO;
484 goto error;
485 }
486
487 /* Enable CIR Mode */
488 WRITE(sc, AW_IR_CTL, AW_IR_CTL_MD);
489
490 /*
491 * Set clock sample, filter, idle thresholds.
492 * Frequency sample = 3MHz/128 = 23437.5Hz (42.7us)
493 */
494 val = AW_IR_SAMPLE_128;
495 val |= (AW_IR_RXFILT_VAL | AW_IR_RXIDLE_VAL);
496 val |= (AW_IR_ACTIVE_T | AW_IR_ACTIVE_T_C);
497 WRITE(sc, AW_IR_CIR, val);
498
499 /* Invert Input Signal */
500 WRITE(sc, AW_IR_RXCTL, AW_IR_RXCTL_RPPI);
501
502 /* Clear All RX Interrupt Status */
503 WRITE(sc, AW_IR_RXSTA, AW_IR_RXSTA_CLEARALL);
504
505 /*
506 * Enable RX interrupt in case of overflow, packet end
507 * and FIFO available.
508 * RX FIFO Threshold = FIFO size / 2
509 */
510 WRITE(sc, AW_IR_RXINT, AW_IR_RXINT_ROI_EN | AW_IR_RXINT_RPEI_EN |
511 AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RAL((sc->fifo_size >> 1) - 1));
512
513 /* Enable IR Module */
514 val = READ(sc, AW_IR_CTL);
515 WRITE(sc, AW_IR_CTL, val | AW_IR_CTL_GEN | AW_IR_CTL_RXEN);
516
517 sc->sc_evdev = evdev_alloc();
518 evdev_set_name(sc->sc_evdev, device_get_desc(sc->dev));
519 evdev_set_phys(sc->sc_evdev, device_get_nameunit(sc->dev));
520 evdev_set_id(sc->sc_evdev, BUS_HOST, 0, 0, 0);
521 evdev_support_event(sc->sc_evdev, EV_SYN);
522 evdev_support_event(sc->sc_evdev, EV_MSC);
523 evdev_support_msc(sc->sc_evdev, MSC_SCAN);
524
525 err = evdev_register(sc->sc_evdev);
526 if (err) {
527 device_printf(dev,
528 "failed to register evdev: error=%d\n", err);
529 goto error;
530 }
531
532 return (0);
533 error:
534 if (clk_gate != NULL)
535 clk_release(clk_gate);
536 if (clk_ir != NULL)
537 clk_release(clk_ir);
538 if (rst_apb != NULL)
539 hwreset_release(rst_apb);
540 evdev_free(sc->sc_evdev);
541 sc->sc_evdev = NULL; /* Avoid double free */
542
543 bus_release_resources(dev, aw_ir_spec, sc->res);
544 return (ENXIO);
545 }
546
547 static device_method_t aw_ir_methods[] = {
548 DEVMETHOD(device_probe, aw_ir_probe),
549 DEVMETHOD(device_attach, aw_ir_attach),
550
551 DEVMETHOD_END
552 };
553
554 static driver_t aw_ir_driver = {
555 "aw_ir",
556 aw_ir_methods,
557 sizeof(struct aw_ir_softc),
558 };
559
560 DRIVER_MODULE(aw_ir, simplebus, aw_ir_driver, 0, 0);
561 MODULE_DEPEND(aw_ir, evdev, 1, 1, 1);
562