1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Support for Medifield PNW Camera Imaging ISP subsystem.
4 *
5 * Copyright (c) 2010-2017 Intel Corporation. All Rights Reserved.
6 *
7 * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License version
11 * 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 *
19 */
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/pm_domain.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm_qos.h>
25 #include <linux/timer.h>
26 #include <linux/delay.h>
27 #include <linux/dmi.h>
28 #include <linux/interrupt.h>
29 #include <linux/bits.h>
30 #include <media/v4l2-fwnode.h>
31
32 #include <asm/iosf_mbi.h>
33
34 #include "../../include/linux/atomisp_gmin_platform.h"
35
36 #include "atomisp_cmd.h"
37 #include "atomisp_common.h"
38 #include "atomisp_fops.h"
39 #include "atomisp_ioctl.h"
40 #include "atomisp_internal.h"
41 #include "atomisp-regs.h"
42 #include "atomisp_dfs_tables.h"
43 #include "atomisp_drvfs.h"
44 #include "hmm/hmm.h"
45 #include "atomisp_trace_event.h"
46
47 #include "sh_css_firmware.h"
48
49 #include "device_access.h"
50
51 /* Timeouts to wait for all subdevs to be registered */
52 #define SUBDEV_WAIT_TIMEOUT 50 /* ms */
53 #define SUBDEV_WAIT_TIMEOUT_MAX_COUNT 40 /* up to 2 seconds */
54
55 /* G-Min addition: pull this in from intel_mid_pm.h */
56 #define CSTATE_EXIT_LATENCY_C1 1
57
58 static uint skip_fwload;
59 module_param(skip_fwload, uint, 0644);
60 MODULE_PARM_DESC(skip_fwload, "Skip atomisp firmware load");
61
62 /* cross componnet debug message flag */
63 int dbg_level;
64 module_param(dbg_level, int, 0644);
65 MODULE_PARM_DESC(dbg_level, "debug message level (default:0)");
66
67 /* log function switch */
68 int dbg_func = 1;
69 module_param(dbg_func, int, 0644);
70 MODULE_PARM_DESC(dbg_func,
71 "log function switch non/printk (default:printk)");
72
73 int mipicsi_flag;
74 module_param(mipicsi_flag, int, 0644);
75 MODULE_PARM_DESC(mipicsi_flag, "mipi csi compression predictor algorithm");
76
77 static char firmware_name[256];
78 module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0);
79 MODULE_PARM_DESC(firmware_name, "Firmware file name. Allows overriding the default firmware name.");
80
81 /*set to 16x16 since this is the amount of lines and pixels the sensor
82 exports extra. If these are kept at the 10x8 that they were on, in yuv
83 downscaling modes incorrect resolutions where requested to the sensor
84 driver with strange outcomes as a result. The proper way tot do this
85 would be to have a list of tables the specify the sensor res, mipi rec,
86 output res, and isp output res. however since we do not have this yet,
87 the chosen solution is the next best thing. */
88 int pad_w = 16;
89 module_param(pad_w, int, 0644);
90 MODULE_PARM_DESC(pad_w, "extra data for ISP processing");
91
92 int pad_h = 16;
93 module_param(pad_h, int, 0644);
94 MODULE_PARM_DESC(pad_h, "extra data for ISP processing");
95
96 /*
97 * FIXME: this is a hack to make easier to support ISP2401 variant.
98 * As a given system will either be ISP2401 or not, we can just use
99 * a boolean, in order to replace existing #ifdef ISP2401 everywhere.
100 *
101 * Once this driver gets into a better shape, however, the best would
102 * be to replace this to something stored inside atomisp allocated
103 * structures.
104 */
105
106 struct device *atomisp_dev;
107
108 static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = {
109 {
110 .width = ISP_FREQ_RULE_ANY,
111 .height = ISP_FREQ_RULE_ANY,
112 .fps = ISP_FREQ_RULE_ANY,
113 .isp_freq = ISP_FREQ_400MHZ,
114 .run_mode = ATOMISP_RUN_MODE_VIDEO,
115 },
116 {
117 .width = ISP_FREQ_RULE_ANY,
118 .height = ISP_FREQ_RULE_ANY,
119 .fps = ISP_FREQ_RULE_ANY,
120 .isp_freq = ISP_FREQ_400MHZ,
121 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
122 },
123 {
124 .width = ISP_FREQ_RULE_ANY,
125 .height = ISP_FREQ_RULE_ANY,
126 .fps = ISP_FREQ_RULE_ANY,
127 .isp_freq = ISP_FREQ_400MHZ,
128 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
129 },
130 };
131
132 /* Merrifield and Moorefield DFS rules */
133 static const struct atomisp_dfs_config dfs_config_merr = {
134 .lowest_freq = ISP_FREQ_200MHZ,
135 .max_freq_at_vmin = ISP_FREQ_400MHZ,
136 .highest_freq = ISP_FREQ_457MHZ,
137 .dfs_table = dfs_rules_merr,
138 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr),
139 };
140
141 static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = {
142 {
143 .width = ISP_FREQ_RULE_ANY,
144 .height = ISP_FREQ_RULE_ANY,
145 .fps = ISP_FREQ_RULE_ANY,
146 .isp_freq = ISP_FREQ_400MHZ,
147 .run_mode = ATOMISP_RUN_MODE_VIDEO,
148 },
149 {
150 .width = ISP_FREQ_RULE_ANY,
151 .height = ISP_FREQ_RULE_ANY,
152 .fps = ISP_FREQ_RULE_ANY,
153 .isp_freq = ISP_FREQ_400MHZ,
154 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
155 },
156 {
157 .width = ISP_FREQ_RULE_ANY,
158 .height = ISP_FREQ_RULE_ANY,
159 .fps = ISP_FREQ_RULE_ANY,
160 .isp_freq = ISP_FREQ_400MHZ,
161 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
162 },
163 };
164
165 static const struct atomisp_dfs_config dfs_config_merr_1179 = {
166 .lowest_freq = ISP_FREQ_200MHZ,
167 .max_freq_at_vmin = ISP_FREQ_400MHZ,
168 .highest_freq = ISP_FREQ_400MHZ,
169 .dfs_table = dfs_rules_merr_1179,
170 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179),
171 };
172
173 static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = {
174 {
175 .width = 1920,
176 .height = 1080,
177 .fps = 30,
178 .isp_freq = ISP_FREQ_266MHZ,
179 .run_mode = ATOMISP_RUN_MODE_VIDEO,
180 },
181 {
182 .width = 1080,
183 .height = 1920,
184 .fps = 30,
185 .isp_freq = ISP_FREQ_266MHZ,
186 .run_mode = ATOMISP_RUN_MODE_VIDEO,
187 },
188 {
189 .width = 1920,
190 .height = 1080,
191 .fps = 45,
192 .isp_freq = ISP_FREQ_320MHZ,
193 .run_mode = ATOMISP_RUN_MODE_VIDEO,
194 },
195 {
196 .width = 1080,
197 .height = 1920,
198 .fps = 45,
199 .isp_freq = ISP_FREQ_320MHZ,
200 .run_mode = ATOMISP_RUN_MODE_VIDEO,
201 },
202 {
203 .width = ISP_FREQ_RULE_ANY,
204 .height = ISP_FREQ_RULE_ANY,
205 .fps = 60,
206 .isp_freq = ISP_FREQ_356MHZ,
207 .run_mode = ATOMISP_RUN_MODE_VIDEO,
208 },
209 {
210 .width = ISP_FREQ_RULE_ANY,
211 .height = ISP_FREQ_RULE_ANY,
212 .fps = ISP_FREQ_RULE_ANY,
213 .isp_freq = ISP_FREQ_200MHZ,
214 .run_mode = ATOMISP_RUN_MODE_VIDEO,
215 },
216 {
217 .width = ISP_FREQ_RULE_ANY,
218 .height = ISP_FREQ_RULE_ANY,
219 .fps = ISP_FREQ_RULE_ANY,
220 .isp_freq = ISP_FREQ_400MHZ,
221 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
222 },
223 {
224 .width = ISP_FREQ_RULE_ANY,
225 .height = ISP_FREQ_RULE_ANY,
226 .fps = ISP_FREQ_RULE_ANY,
227 .isp_freq = ISP_FREQ_200MHZ,
228 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
229 },
230 };
231
232 static struct atomisp_dfs_config dfs_config_merr_117a = {
233 .lowest_freq = ISP_FREQ_200MHZ,
234 .max_freq_at_vmin = ISP_FREQ_200MHZ,
235 .highest_freq = ISP_FREQ_400MHZ,
236 .dfs_table = dfs_rules_merr_117a,
237 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a),
238 };
239
240 static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = {
241 {
242 .width = ISP_FREQ_RULE_ANY,
243 .height = ISP_FREQ_RULE_ANY,
244 .fps = ISP_FREQ_RULE_ANY,
245 .isp_freq = ISP_FREQ_400MHZ,
246 .run_mode = ATOMISP_RUN_MODE_VIDEO,
247 },
248 {
249 .width = ISP_FREQ_RULE_ANY,
250 .height = ISP_FREQ_RULE_ANY,
251 .fps = ISP_FREQ_RULE_ANY,
252 .isp_freq = ISP_FREQ_400MHZ,
253 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
254 },
255 {
256 .width = ISP_FREQ_RULE_ANY,
257 .height = ISP_FREQ_RULE_ANY,
258 .fps = ISP_FREQ_RULE_ANY,
259 .isp_freq = ISP_FREQ_400MHZ,
260 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
261 },
262 };
263
264 static const struct atomisp_dfs_config dfs_config_byt = {
265 .lowest_freq = ISP_FREQ_200MHZ,
266 .max_freq_at_vmin = ISP_FREQ_400MHZ,
267 .highest_freq = ISP_FREQ_400MHZ,
268 .dfs_table = dfs_rules_byt,
269 .dfs_table_size = ARRAY_SIZE(dfs_rules_byt),
270 };
271
272 static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = {
273 {
274 .width = ISP_FREQ_RULE_ANY,
275 .height = ISP_FREQ_RULE_ANY,
276 .fps = ISP_FREQ_RULE_ANY,
277 .isp_freq = ISP_FREQ_320MHZ,
278 .run_mode = ATOMISP_RUN_MODE_VIDEO,
279 },
280 {
281 .width = ISP_FREQ_RULE_ANY,
282 .height = ISP_FREQ_RULE_ANY,
283 .fps = ISP_FREQ_RULE_ANY,
284 .isp_freq = ISP_FREQ_356MHZ,
285 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
286 },
287 {
288 .width = ISP_FREQ_RULE_ANY,
289 .height = ISP_FREQ_RULE_ANY,
290 .fps = ISP_FREQ_RULE_ANY,
291 .isp_freq = ISP_FREQ_320MHZ,
292 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
293 },
294 };
295
296 static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = {
297 {
298 .width = ISP_FREQ_RULE_ANY,
299 .height = ISP_FREQ_RULE_ANY,
300 .fps = ISP_FREQ_RULE_ANY,
301 .isp_freq = ISP_FREQ_356MHZ,
302 .run_mode = ATOMISP_RUN_MODE_VIDEO,
303 },
304 {
305 .width = ISP_FREQ_RULE_ANY,
306 .height = ISP_FREQ_RULE_ANY,
307 .fps = ISP_FREQ_RULE_ANY,
308 .isp_freq = ISP_FREQ_356MHZ,
309 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
310 },
311 {
312 .width = ISP_FREQ_RULE_ANY,
313 .height = ISP_FREQ_RULE_ANY,
314 .fps = ISP_FREQ_RULE_ANY,
315 .isp_freq = ISP_FREQ_320MHZ,
316 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
317 },
318 };
319
320 static const struct atomisp_dfs_config dfs_config_cht = {
321 .lowest_freq = ISP_FREQ_100MHZ,
322 .max_freq_at_vmin = ISP_FREQ_356MHZ,
323 .highest_freq = ISP_FREQ_356MHZ,
324 .dfs_table = dfs_rules_cht,
325 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht),
326 };
327
328 /* This one should be visible also by atomisp_cmd.c */
329 const struct atomisp_dfs_config dfs_config_cht_soc = {
330 .lowest_freq = ISP_FREQ_100MHZ,
331 .max_freq_at_vmin = ISP_FREQ_356MHZ,
332 .highest_freq = ISP_FREQ_356MHZ,
333 .dfs_table = dfs_rules_cht_soc,
334 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc),
335 };
336
atomisp_video_init(struct atomisp_video_pipe * video)337 int atomisp_video_init(struct atomisp_video_pipe *video)
338 {
339 int ret;
340
341 video->pad.flags = MEDIA_PAD_FL_SINK;
342 ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad);
343 if (ret < 0)
344 return ret;
345
346 /* Initialize the video device. */
347 strscpy(video->vdev.name, "ATOMISP video output", sizeof(video->vdev.name));
348 video->vdev.fops = &atomisp_fops;
349 video->vdev.ioctl_ops = &atomisp_ioctl_ops;
350 video->vdev.lock = &video->isp->mutex;
351 video->vdev.release = video_device_release_empty;
352 video_set_drvdata(&video->vdev, video->isp);
353
354 return 0;
355 }
356
atomisp_video_unregister(struct atomisp_video_pipe * video)357 void atomisp_video_unregister(struct atomisp_video_pipe *video)
358 {
359 if (video_is_registered(&video->vdev)) {
360 media_entity_cleanup(&video->vdev.entity);
361 video_unregister_device(&video->vdev);
362 }
363 }
364
atomisp_save_iunit_reg(struct atomisp_device * isp)365 static int atomisp_save_iunit_reg(struct atomisp_device *isp)
366 {
367 struct pci_dev *pdev = to_pci_dev(isp->dev);
368
369 dev_dbg(isp->dev, "%s\n", __func__);
370
371 pci_read_config_word(pdev, PCI_COMMAND, &isp->saved_regs.pcicmdsts);
372 /* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */
373 pci_read_config_dword(pdev, PCI_MSI_CAPID, &isp->saved_regs.msicap);
374 pci_read_config_dword(pdev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr);
375 pci_read_config_word(pdev, PCI_MSI_DATA, &isp->saved_regs.msi_data);
376 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr);
377 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &isp->saved_regs.interrupt_control);
378
379 pci_read_config_dword(pdev, MRFLD_PCI_PMCS, &isp->saved_regs.pmcs);
380 /* Ensure read/write combining is enabled. */
381 pci_read_config_dword(pdev, PCI_I_CONTROL, &isp->saved_regs.i_control);
382 isp->saved_regs.i_control |=
383 MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING |
384 MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING;
385 pci_read_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
386 &isp->saved_regs.csi_access_viol);
387 pci_read_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
388 &isp->saved_regs.csi_rcomp_config);
389 /*
390 * Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE.
391 * ANN/CHV: RCOMP updates do not happen when using CSI2+ path
392 * and sensor sending "continuous clock".
393 * TNG/ANN/CHV: MIPI packets are lost if the HS entry sequence
394 * is missed, and IUNIT can hang.
395 * For both issues, setting this bit is a workaround.
396 */
397 isp->saved_regs.csi_rcomp_config |= MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE;
398 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
399 &isp->saved_regs.csi_afe_dly);
400 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
401 &isp->saved_regs.csi_control);
402 if (isp->media_dev.hw_revision >=
403 (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT))
404 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_PARPATHEN;
405 /*
406 * On CHT CSI_READY bit should be enabled before stream on
407 */
408 if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 <<
409 ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)))
410 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_CSI_READY;
411 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
412 &isp->saved_regs.csi_afe_rcomp_config);
413 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
414 &isp->saved_regs.csi_afe_hs_control);
415 pci_read_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
416 &isp->saved_regs.csi_deadline_control);
417 return 0;
418 }
419
atomisp_restore_iunit_reg(struct atomisp_device * isp)420 static int atomisp_restore_iunit_reg(struct atomisp_device *isp)
421 {
422 struct pci_dev *pdev = to_pci_dev(isp->dev);
423
424 dev_dbg(isp->dev, "%s\n", __func__);
425
426 pci_write_config_word(pdev, PCI_COMMAND, isp->saved_regs.pcicmdsts);
427 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, isp->saved_regs.ispmmadr);
428 pci_write_config_dword(pdev, PCI_MSI_CAPID, isp->saved_regs.msicap);
429 pci_write_config_dword(pdev, PCI_MSI_ADDR, isp->saved_regs.msi_addr);
430 pci_write_config_word(pdev, PCI_MSI_DATA, isp->saved_regs.msi_data);
431 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, isp->saved_regs.intr);
432 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, isp->saved_regs.interrupt_control);
433 pci_write_config_dword(pdev, PCI_I_CONTROL, isp->saved_regs.i_control);
434
435 pci_write_config_dword(pdev, MRFLD_PCI_PMCS, isp->saved_regs.pmcs);
436 pci_write_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
437 isp->saved_regs.csi_access_viol);
438 pci_write_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
439 isp->saved_regs.csi_rcomp_config);
440 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
441 isp->saved_regs.csi_afe_dly);
442 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
443 isp->saved_regs.csi_control);
444 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
445 isp->saved_regs.csi_afe_rcomp_config);
446 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
447 isp->saved_regs.csi_afe_hs_control);
448 pci_write_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
449 isp->saved_regs.csi_deadline_control);
450
451 /*
452 * for MRFLD, Software/firmware needs to write a 1 to bit0
453 * of the register at CSI_RECEIVER_SELECTION_REG to enable
454 * SH CSI backend write 0 will enable Arasan CSI backend,
455 * which has bugs(like sighting:4567697 and 4567699) and
456 * will be removed in B0
457 */
458 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
459 return 0;
460 }
461
atomisp_mrfld_pre_power_down(struct atomisp_device * isp)462 static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp)
463 {
464 struct pci_dev *pdev = to_pci_dev(isp->dev);
465 u32 irq;
466 unsigned long flags;
467
468 spin_lock_irqsave(&isp->lock, flags);
469
470 /*
471 * MRFLD HAS requirement: cannot power off i-unit if
472 * ISP has IRQ not serviced.
473 * So, here we need to check if there is any pending
474 * IRQ, if so, waiting for it to be served
475 */
476 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
477 irq &= BIT(INTR_IIR);
478 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
479
480 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
481 if (!(irq & BIT(INTR_IIR)))
482 goto done;
483
484 atomisp_css2_hw_store_32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF);
485 atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq);
486 if (irq != 0) {
487 dev_err(isp->dev,
488 "%s: fail to clear isp interrupt status reg=0x%x\n",
489 __func__, irq);
490 spin_unlock_irqrestore(&isp->lock, flags);
491 return -EAGAIN;
492 } else {
493 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
494 irq &= BIT(INTR_IIR);
495 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
496
497 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
498 if (!(irq & BIT(INTR_IIR))) {
499 atomisp_css2_hw_store_32(MRFLD_INTR_ENABLE_REG, 0x0);
500 goto done;
501 }
502 dev_err(isp->dev,
503 "%s: error in iunit interrupt. status reg=0x%x\n",
504 __func__, irq);
505 spin_unlock_irqrestore(&isp->lock, flags);
506 return -EAGAIN;
507 }
508 done:
509 /*
510 * MRFLD WORKAROUND:
511 * before powering off IUNIT, clear the pending interrupts
512 * and disable the interrupt. driver should avoid writing 0
513 * to IIR. It could block subsequent interrupt messages.
514 * HW sighting:4568410.
515 */
516 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
517 irq &= ~BIT(INTR_IER);
518 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
519
520 atomisp_msi_irq_uninit(isp);
521 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
522 spin_unlock_irqrestore(&isp->lock, flags);
523
524 return 0;
525 }
526
527 /*
528 * WA for DDR DVFS enable/disable
529 * By default, ISP will force DDR DVFS 1600MHz before disable DVFS
530 */
punit_ddr_dvfs_enable(bool enable)531 static void punit_ddr_dvfs_enable(bool enable)
532 {
533 int reg;
534
535 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®);
536 if (enable) {
537 reg &= ~(MRFLD_BIT0 | MRFLD_BIT1);
538 } else {
539 reg |= MRFLD_BIT1;
540 reg &= ~(MRFLD_BIT0);
541 }
542 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, MRFLD_ISPSSDVFS, reg);
543 }
544
atomisp_mrfld_power(struct atomisp_device * isp,bool enable)545 static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable)
546 {
547 struct pci_dev *pdev = to_pci_dev(isp->dev);
548 unsigned long timeout;
549 u32 val = enable ? MRFLD_ISPSSPM0_IUNIT_POWER_ON :
550 MRFLD_ISPSSPM0_IUNIT_POWER_OFF;
551
552 dev_dbg(isp->dev, "IUNIT power-%s.\n", enable ? "on" : "off");
553
554 /* WA for P-Unit, if DVFS enabled, ISP timeout observed */
555 if (IS_CHT && enable) {
556 punit_ddr_dvfs_enable(false);
557 msleep(20);
558 }
559
560 /* Write to ISPSSPM0 bit[1:0] to power on/off the IUNIT */
561 iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0,
562 val, MRFLD_ISPSSPM0_ISPSSC_MASK);
563
564 /* WA:Enable DVFS */
565 if (IS_CHT && !enable)
566 punit_ddr_dvfs_enable(true);
567
568 /*
569 * There should be no IUNIT access while power-down is
570 * in progress. HW sighting: 4567865.
571 * Wait up to 50 ms for the IUNIT to shut down.
572 * And we do the same for power on.
573 */
574 timeout = jiffies + msecs_to_jiffies(50);
575 do {
576 u32 tmp;
577
578 /* Wait until ISPSSPM0 bit[25:24] shows the right value */
579 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, &tmp);
580 tmp = (tmp >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) & MRFLD_ISPSSPM0_ISPSSC_MASK;
581 if (tmp == val) {
582 trace_ipu_cstate(enable);
583 pdev->current_state = enable ? PCI_D0 : PCI_D3cold;
584 return 0;
585 }
586
587 if (time_after(jiffies, timeout))
588 break;
589
590 /* FIXME: experienced value for delay */
591 usleep_range(100, 150);
592 } while (1);
593
594 if (enable)
595 msleep(10);
596
597 dev_err(isp->dev, "IUNIT power-%s timeout.\n", enable ? "on" : "off");
598 return -EBUSY;
599 }
600
atomisp_power_off(struct device * dev)601 int atomisp_power_off(struct device *dev)
602 {
603 struct atomisp_device *isp = dev_get_drvdata(dev);
604 struct pci_dev *pdev = to_pci_dev(dev);
605 int ret;
606 u32 reg;
607
608 atomisp_css_uninit(isp);
609
610 ret = atomisp_mrfld_pre_power_down(isp);
611 if (ret)
612 return ret;
613
614 /*
615 * MRFLD IUNIT DPHY is located in an always-power-on island
616 * MRFLD HW design need all CSI ports are disabled before
617 * powering down the IUNIT.
618 */
619 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, ®);
620 reg |= MRFLD_ALL_CSI_PORTS_OFF_MASK;
621 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, reg);
622
623 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
624 pci_save_state(pdev);
625 return atomisp_mrfld_power(isp, false);
626 }
627
atomisp_power_on(struct device * dev)628 int atomisp_power_on(struct device *dev)
629 {
630 struct atomisp_device *isp = (struct atomisp_device *)
631 dev_get_drvdata(dev);
632 int ret;
633
634 ret = atomisp_mrfld_power(isp, true);
635 if (ret)
636 return ret;
637
638 pci_restore_state(to_pci_dev(dev));
639 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency);
640
641 /*restore register values for iUnit and iUnitPHY registers*/
642 if (isp->saved_regs.pcicmdsts)
643 atomisp_restore_iunit_reg(isp);
644
645 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
646
647 return atomisp_css_init(isp);
648 }
649
atomisp_suspend(struct device * dev)650 static int atomisp_suspend(struct device *dev)
651 {
652 struct atomisp_device *isp = (struct atomisp_device *)
653 dev_get_drvdata(dev);
654 unsigned long flags;
655
656 /* FIXME: Suspend is not supported by sensors. Abort if streaming. */
657 spin_lock_irqsave(&isp->lock, flags);
658 if (isp->asd.streaming) {
659 spin_unlock_irqrestore(&isp->lock, flags);
660 dev_err(isp->dev, "atomisp cannot suspend at this time.\n");
661 return -EINVAL;
662 }
663 spin_unlock_irqrestore(&isp->lock, flags);
664
665 pm_runtime_resume(dev);
666
667 isp->asd.recreate_streams_on_resume = isp->asd.stream_prepared;
668 atomisp_destroy_pipes_stream(&isp->asd);
669
670 return atomisp_power_off(dev);
671 }
672
atomisp_resume(struct device * dev)673 static int atomisp_resume(struct device *dev)
674 {
675 struct atomisp_device *isp = dev_get_drvdata(dev);
676 int ret;
677
678 ret = atomisp_power_on(dev);
679 if (ret)
680 return ret;
681
682 if (isp->asd.recreate_streams_on_resume)
683 ret = atomisp_create_pipes_stream(&isp->asd);
684
685 return ret;
686 }
687
atomisp_csi_lane_config(struct atomisp_device * isp)688 int atomisp_csi_lane_config(struct atomisp_device *isp)
689 {
690 struct pci_dev *pdev = to_pci_dev(isp->dev);
691 static const struct {
692 u8 code;
693 u8 lanes[N_MIPI_PORT_ID];
694 } portconfigs[] = {
695 /* Tangier/Merrifield available lane configurations */
696 { 0x00, { 4, 1, 0 } }, /* 00000 */
697 { 0x01, { 3, 1, 0 } }, /* 00001 */
698 { 0x02, { 2, 1, 0 } }, /* 00010 */
699 { 0x03, { 1, 1, 0 } }, /* 00011 */
700 { 0x04, { 2, 1, 2 } }, /* 00100 */
701 { 0x08, { 3, 1, 1 } }, /* 01000 */
702 { 0x09, { 2, 1, 1 } }, /* 01001 */
703 { 0x0a, { 1, 1, 1 } }, /* 01010 */
704
705 /* Anniedale/Moorefield only configurations */
706 { 0x10, { 4, 2, 0 } }, /* 10000 */
707 { 0x11, { 3, 2, 0 } }, /* 10001 */
708 { 0x12, { 2, 2, 0 } }, /* 10010 */
709 { 0x13, { 1, 2, 0 } }, /* 10011 */
710 { 0x14, { 2, 2, 2 } }, /* 10100 */
711 { 0x18, { 3, 2, 1 } }, /* 11000 */
712 { 0x19, { 2, 2, 1 } }, /* 11001 */
713 { 0x1a, { 1, 2, 1 } }, /* 11010 */
714 };
715
716 unsigned int i, j;
717 u32 csi_control;
718 int nportconfigs;
719 u32 port_config_mask;
720 int port3_lanes_shift;
721
722 if (isp->media_dev.hw_revision <
723 ATOMISP_HW_REVISION_ISP2401_LEGACY <<
724 ATOMISP_HW_REVISION_SHIFT) {
725 /* Merrifield */
726 port_config_mask = MRFLD_PORT_CONFIG_MASK;
727 port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT;
728 } else {
729 /* Moorefield / Cherryview */
730 port_config_mask = CHV_PORT_CONFIG_MASK;
731 port3_lanes_shift = CHV_PORT3_LANES_SHIFT;
732 }
733
734 if (isp->media_dev.hw_revision <
735 ATOMISP_HW_REVISION_ISP2401 <<
736 ATOMISP_HW_REVISION_SHIFT) {
737 /* Merrifield / Moorefield legacy input system */
738 nportconfigs = MRFLD_PORT_CONFIG_NUM;
739 } else {
740 /* Moorefield / Cherryview new input system */
741 nportconfigs = ARRAY_SIZE(portconfigs);
742 }
743
744 for (i = 0; i < nportconfigs; i++) {
745 for (j = 0; j < N_MIPI_PORT_ID; j++)
746 if (isp->sensor_lanes[j] &&
747 isp->sensor_lanes[j] != portconfigs[i].lanes[j])
748 break;
749
750 if (j == N_MIPI_PORT_ID)
751 break; /* Found matching setting */
752 }
753
754 if (i >= nportconfigs) {
755 dev_err(isp->dev,
756 "%s: could not find the CSI port setting for %d-%d-%d\n",
757 __func__,
758 isp->sensor_lanes[0], isp->sensor_lanes[1], isp->sensor_lanes[2]);
759 return -EINVAL;
760 }
761
762 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &csi_control);
763 csi_control &= ~port_config_mask;
764 csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT)
765 | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT))
766 | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT))
767 | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT))
768 | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT)
769 | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT)
770 | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift);
771
772 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, csi_control);
773
774 dev_dbg(isp->dev,
775 "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n",
776 __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1],
777 portconfigs[i].lanes[2], csi_control);
778
779 return 0;
780 }
781
atomisp_subdev_probe(struct atomisp_device * isp)782 static int atomisp_subdev_probe(struct atomisp_device *isp)
783 {
784 const struct atomisp_platform_data *pdata;
785 struct intel_v4l2_subdev_table *subdevs;
786 int ret, mipi_port;
787
788 ret = atomisp_csi2_bridge_parse_firmware(isp);
789 if (ret)
790 return ret;
791
792 pdata = atomisp_get_platform_data();
793 if (!pdata) {
794 dev_err(isp->dev, "no platform data available\n");
795 return 0;
796 }
797
798 /*
799 * TODO: this is left here for now to allow testing atomisp-sensor
800 * drivers which are still using the atomisp_gmin_platform infra before
801 * converting them to standard v4l2 sensor drivers using runtime-pm +
802 * ACPI for pm and v4l2_async_register_subdev_sensor() registration.
803 */
804 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) {
805 ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdevs->subdev);
806 if (ret)
807 continue;
808
809 switch (subdevs->type) {
810 case RAW_CAMERA:
811 if (subdevs->port >= ATOMISP_CAMERA_NR_PORTS) {
812 dev_err(isp->dev, "port %d not supported\n", subdevs->port);
813 break;
814 }
815
816 if (isp->sensor_subdevs[subdevs->port]) {
817 dev_err(isp->dev, "port %d already has a sensor attached\n",
818 subdevs->port);
819 break;
820 }
821
822 mipi_port = atomisp_port_to_mipi_port(isp, subdevs->port);
823 isp->sensor_lanes[mipi_port] = subdevs->lanes;
824 isp->sensor_subdevs[subdevs->port] = subdevs->subdev;
825 break;
826 case CAMERA_MOTOR:
827 if (isp->motor) {
828 dev_warn(isp->dev, "too many atomisp motors\n");
829 continue;
830 }
831 isp->motor = subdevs->subdev;
832 break;
833 case LED_FLASH:
834 if (isp->flash) {
835 dev_warn(isp->dev, "too many atomisp flash devices\n");
836 continue;
837 }
838 isp->flash = subdevs->subdev;
839 break;
840 default:
841 dev_dbg(isp->dev, "unknown subdev probed\n");
842 break;
843 }
844 }
845
846 return atomisp_csi_lane_config(isp);
847 }
848
atomisp_unregister_entities(struct atomisp_device * isp)849 static void atomisp_unregister_entities(struct atomisp_device *isp)
850 {
851 unsigned int i;
852 struct v4l2_subdev *sd, *next;
853
854 atomisp_subdev_unregister_entities(&isp->asd);
855 atomisp_tpg_unregister_entities(&isp->tpg);
856 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
857 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
858
859 list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list)
860 v4l2_device_unregister_subdev(sd);
861
862 v4l2_device_unregister(&isp->v4l2_dev);
863 media_device_unregister(&isp->media_dev);
864 media_device_cleanup(&isp->media_dev);
865
866 for (i = 0; i < isp->input_cnt; i++)
867 __v4l2_subdev_state_free(isp->inputs[i].try_sd_state);
868 }
869
atomisp_register_entities(struct atomisp_device * isp)870 static int atomisp_register_entities(struct atomisp_device *isp)
871 {
872 int ret = 0;
873 unsigned int i;
874
875 isp->media_dev.dev = isp->dev;
876
877 strscpy(isp->media_dev.model, "Intel Atom ISP",
878 sizeof(isp->media_dev.model));
879
880 media_device_init(&isp->media_dev);
881 isp->v4l2_dev.mdev = &isp->media_dev;
882 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
883 if (ret < 0) {
884 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
885 __func__, ret);
886 goto v4l2_device_failed;
887 }
888
889 ret = atomisp_subdev_probe(isp);
890 if (ret < 0)
891 goto csi_and_subdev_probe_failed;
892
893 /* Register internal entities */
894 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
895 ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i],
896 &isp->v4l2_dev);
897 if (ret == 0)
898 continue;
899
900 /* error case */
901 dev_err(isp->dev, "failed to register the CSI port: %d\n", i);
902 /* deregister all registered CSI ports */
903 while (i--)
904 atomisp_mipi_csi2_unregister_entities(
905 &isp->csi2_port[i]);
906
907 goto csi_and_subdev_probe_failed;
908 }
909
910 ret = atomisp_tpg_register_entities(&isp->tpg, &isp->v4l2_dev);
911 if (ret < 0) {
912 dev_err(isp->dev, "atomisp_tpg_register_entities\n");
913 goto tpg_register_failed;
914 }
915
916 ret = atomisp_subdev_register_subdev(&isp->asd, &isp->v4l2_dev);
917 if (ret < 0) {
918 dev_err(isp->dev, "atomisp_subdev_register_subdev fail\n");
919 goto subdev_register_failed;
920 }
921
922 return 0;
923
924 subdev_register_failed:
925 atomisp_tpg_unregister_entities(&isp->tpg);
926 tpg_register_failed:
927 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
928 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
929 csi_and_subdev_probe_failed:
930 v4l2_device_unregister(&isp->v4l2_dev);
931 v4l2_device_failed:
932 media_device_unregister(&isp->media_dev);
933 media_device_cleanup(&isp->media_dev);
934 return ret;
935 }
936
atomisp_init_sensor(struct atomisp_input_subdev * input)937 static void atomisp_init_sensor(struct atomisp_input_subdev *input)
938 {
939 static struct lock_class_key try_sd_state_key;
940 struct v4l2_subdev_mbus_code_enum mbus_code_enum = { };
941 struct v4l2_subdev_frame_size_enum fse = { };
942 struct v4l2_subdev_selection sel = { };
943 struct v4l2_subdev_state *try_sd_state, *act_sd_state;
944 int i, err;
945
946 /*
947 * FIXME: Drivers are not supposed to use __v4l2_subdev_state_alloc()
948 * but atomisp needs this for try_fmt on its /dev/video# node since
949 * it emulates a normal v4l2 device there, passing through try_fmt /
950 * set_fmt to the sensor.
951 */
952 try_sd_state = __v4l2_subdev_state_alloc(input->camera,
953 "atomisp:try_sd_state->lock", &try_sd_state_key);
954 if (IS_ERR(try_sd_state))
955 return;
956
957 input->try_sd_state = try_sd_state;
958
959 act_sd_state = v4l2_subdev_lock_and_get_active_state(input->camera);
960
961 mbus_code_enum.which = V4L2_SUBDEV_FORMAT_ACTIVE;
962 err = v4l2_subdev_call(input->camera, pad, enum_mbus_code,
963 act_sd_state, &mbus_code_enum);
964 if (!err)
965 input->code = mbus_code_enum.code;
966
967 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
968 sel.target = V4L2_SEL_TGT_NATIVE_SIZE;
969 err = v4l2_subdev_call(input->camera, pad, get_selection,
970 act_sd_state, &sel);
971 if (err)
972 goto unlock_act_sd_state;
973
974 input->native_rect = sel.r;
975
976 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
977 sel.target = V4L2_SEL_TGT_CROP_DEFAULT;
978 err = v4l2_subdev_call(input->camera, pad, get_selection,
979 act_sd_state, &sel);
980 if (err)
981 goto unlock_act_sd_state;
982
983 input->active_rect = sel.r;
984
985 /*
986 * Check for a framesize with half active_rect width and height,
987 * if found assume the sensor supports binning.
988 * Do this before changing the crop-rect since that may influence
989 * enum_frame_size results.
990 */
991 for (i = 0; ; i++) {
992 fse.index = i;
993 fse.code = input->code;
994 fse.which = V4L2_SUBDEV_FORMAT_ACTIVE;
995
996 err = v4l2_subdev_call(input->camera, pad, enum_frame_size,
997 act_sd_state, &fse);
998 if (err)
999 break;
1000
1001 if (fse.min_width <= (input->active_rect.width / 2) &&
1002 fse.min_height <= (input->active_rect.height / 2)) {
1003 input->binning_support = true;
1004 break;
1005 }
1006 }
1007
1008 /*
1009 * The ISP also wants the non-active pixels at the border of the sensor
1010 * for padding, set the crop rect to cover the entire sensor instead
1011 * of only the default active area.
1012 *
1013 * Do this for both try and active formats since the crop rect in
1014 * try_sd_state may influence (clamp size) in calls with which == try.
1015 */
1016 sel.which = V4L2_SUBDEV_FORMAT_TRY;
1017 sel.target = V4L2_SEL_TGT_CROP;
1018 sel.r = input->native_rect;
1019 v4l2_subdev_lock_state(input->try_sd_state);
1020 err = v4l2_subdev_call(input->camera, pad, set_selection,
1021 input->try_sd_state, &sel);
1022 v4l2_subdev_unlock_state(input->try_sd_state);
1023 if (err)
1024 goto unlock_act_sd_state;
1025
1026 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1027 sel.target = V4L2_SEL_TGT_CROP;
1028 sel.r = input->native_rect;
1029 err = v4l2_subdev_call(input->camera, pad, set_selection,
1030 act_sd_state, &sel);
1031 if (err)
1032 goto unlock_act_sd_state;
1033
1034 dev_info(input->camera->dev, "Supports crop native %dx%d active %dx%d binning %d\n",
1035 input->native_rect.width, input->native_rect.height,
1036 input->active_rect.width, input->active_rect.height,
1037 input->binning_support);
1038
1039 input->crop_support = true;
1040
1041 unlock_act_sd_state:
1042 if (act_sd_state)
1043 v4l2_subdev_unlock_state(act_sd_state);
1044 }
1045
atomisp_register_device_nodes(struct atomisp_device * isp)1046 int atomisp_register_device_nodes(struct atomisp_device *isp)
1047 {
1048 struct atomisp_input_subdev *input;
1049 int i, err;
1050
1051 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
1052 err = media_create_pad_link(&isp->csi2_port[i].subdev.entity,
1053 CSI2_PAD_SOURCE, &isp->asd.subdev.entity,
1054 ATOMISP_SUBDEV_PAD_SINK, 0);
1055 if (err)
1056 return err;
1057
1058 if (!isp->sensor_subdevs[i])
1059 continue;
1060
1061 input = &isp->inputs[isp->input_cnt];
1062
1063 input->type = RAW_CAMERA;
1064 input->port = i;
1065 input->camera = isp->sensor_subdevs[i];
1066
1067 atomisp_init_sensor(input);
1068
1069 /*
1070 * HACK: Currently VCM belongs to primary sensor only, but correct
1071 * approach must be to acquire from platform code which sensor
1072 * owns it.
1073 */
1074 if (i == ATOMISP_CAMERA_PORT_PRIMARY)
1075 input->motor = isp->motor;
1076
1077 err = media_create_pad_link(&input->camera->entity, 0,
1078 &isp->csi2_port[i].subdev.entity,
1079 CSI2_PAD_SINK,
1080 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1081 if (err)
1082 return err;
1083
1084 isp->input_cnt++;
1085 }
1086
1087 if (!isp->input_cnt)
1088 dev_warn(isp->dev, "no camera attached or fail to detect\n");
1089 else
1090 dev_info(isp->dev, "detected %d camera sensors\n", isp->input_cnt);
1091
1092 if (isp->input_cnt < ATOM_ISP_MAX_INPUTS) {
1093 dev_dbg(isp->dev, "TPG detected, camera_cnt: %d\n", isp->input_cnt);
1094 isp->inputs[isp->input_cnt].type = TEST_PATTERN;
1095 isp->inputs[isp->input_cnt].port = -1;
1096 isp->inputs[isp->input_cnt++].camera = &isp->tpg.sd;
1097 } else {
1098 dev_warn(isp->dev, "too many atomisp inputs, TPG ignored.\n");
1099 }
1100
1101 isp->asd.video_out.vdev.v4l2_dev = &isp->v4l2_dev;
1102 isp->asd.video_out.vdev.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1103 err = video_register_device(&isp->asd.video_out.vdev, VFL_TYPE_VIDEO, -1);
1104 if (err)
1105 return err;
1106
1107 err = media_create_pad_link(&isp->asd.subdev.entity, ATOMISP_SUBDEV_PAD_SOURCE,
1108 &isp->asd.video_out.vdev.entity, 0, 0);
1109 if (err)
1110 return err;
1111
1112 err = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
1113 if (err)
1114 return err;
1115
1116 return media_device_register(&isp->media_dev);
1117 }
1118
atomisp_initialize_modules(struct atomisp_device * isp)1119 static int atomisp_initialize_modules(struct atomisp_device *isp)
1120 {
1121 int ret;
1122
1123 ret = atomisp_mipi_csi2_init(isp);
1124 if (ret < 0) {
1125 dev_err(isp->dev, "mipi csi2 initialization failed\n");
1126 goto error_mipi_csi2;
1127 }
1128
1129 ret = atomisp_tpg_init(isp);
1130 if (ret < 0) {
1131 dev_err(isp->dev, "tpg initialization failed\n");
1132 goto error_tpg;
1133 }
1134
1135 ret = atomisp_subdev_init(isp);
1136 if (ret < 0) {
1137 dev_err(isp->dev, "ISP subdev initialization failed\n");
1138 goto error_isp_subdev;
1139 }
1140
1141 return 0;
1142
1143 error_isp_subdev:
1144 error_tpg:
1145 atomisp_tpg_cleanup(isp);
1146 error_mipi_csi2:
1147 atomisp_mipi_csi2_cleanup(isp);
1148 return ret;
1149 }
1150
atomisp_uninitialize_modules(struct atomisp_device * isp)1151 static void atomisp_uninitialize_modules(struct atomisp_device *isp)
1152 {
1153 atomisp_tpg_cleanup(isp);
1154 atomisp_mipi_csi2_cleanup(isp);
1155 }
1156
1157 const struct firmware *
atomisp_load_firmware(struct atomisp_device * isp)1158 atomisp_load_firmware(struct atomisp_device *isp)
1159 {
1160 const struct firmware *fw;
1161 int rc;
1162 char *fw_path = NULL;
1163
1164 if (skip_fwload)
1165 return NULL;
1166
1167 if (firmware_name[0] != '\0') {
1168 fw_path = firmware_name;
1169 } else {
1170 if ((isp->media_dev.hw_revision >> ATOMISP_HW_REVISION_SHIFT)
1171 == ATOMISP_HW_REVISION_ISP2401)
1172 fw_path = "shisp_2401a0_v21.bin";
1173
1174 if (isp->media_dev.hw_revision ==
1175 ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT)
1176 | ATOMISP_HW_STEPPING_A0))
1177 fw_path = "shisp_2401a0_legacy_v21.bin";
1178
1179 if (isp->media_dev.hw_revision ==
1180 ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT)
1181 | ATOMISP_HW_STEPPING_B0))
1182 fw_path = "shisp_2400b0_v21.bin";
1183 }
1184
1185 if (!fw_path) {
1186 dev_err(isp->dev, "Unsupported hw_revision 0x%x\n",
1187 isp->media_dev.hw_revision);
1188 return NULL;
1189 }
1190
1191 rc = request_firmware(&fw, fw_path, isp->dev);
1192 if (rc) {
1193 dev_err(isp->dev,
1194 "atomisp: Error %d while requesting firmware %s\n",
1195 rc, fw_path);
1196 return NULL;
1197 }
1198
1199 return fw;
1200 }
1201
1202 /*
1203 * Check for flags the driver was compiled with against the PCI
1204 * device. Always returns true on other than ISP 2400.
1205 */
is_valid_device(struct pci_dev * pdev,const struct pci_device_id * id)1206 static bool is_valid_device(struct pci_dev *pdev, const struct pci_device_id *id)
1207 {
1208 const char *name;
1209 const char *product;
1210
1211 product = dmi_get_system_info(DMI_PRODUCT_NAME);
1212
1213 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) {
1214 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1215 name = "Merrifield";
1216 break;
1217 case ATOMISP_PCI_DEVICE_SOC_BYT:
1218 name = "Baytrail";
1219 break;
1220 case ATOMISP_PCI_DEVICE_SOC_ANN:
1221 name = "Anniedale";
1222 break;
1223 case ATOMISP_PCI_DEVICE_SOC_CHT:
1224 name = "Cherrytrail";
1225 break;
1226 default:
1227 dev_err(&pdev->dev, "%s: unknown device ID %x04:%x04\n",
1228 product, id->vendor, id->device);
1229 return false;
1230 }
1231
1232 if (pdev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) {
1233 dev_err(&pdev->dev, "%s revision %d is not unsupported\n",
1234 name, pdev->revision);
1235 return false;
1236 }
1237
1238 dev_info(&pdev->dev, "Detected %s version %d (ISP240%c) on %s\n",
1239 name, pdev->revision, IS_ISP2401 ? '1' : '0', product);
1240
1241 return true;
1242 }
1243
1244 #define ATOM_ISP_PCI_BAR 0
1245
atomisp_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)1246 static int atomisp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1247 {
1248 const struct atomisp_platform_data *pdata;
1249 struct atomisp_device *isp;
1250 unsigned int start;
1251 int err, val;
1252 u32 irq;
1253
1254 if (!is_valid_device(pdev, id))
1255 return -ENODEV;
1256
1257 /* Pointer to struct device. */
1258 atomisp_dev = &pdev->dev;
1259
1260 pdata = atomisp_get_platform_data();
1261 if (!pdata)
1262 dev_warn(&pdev->dev, "no platform data available\n");
1263
1264 err = pcim_enable_device(pdev);
1265 if (err) {
1266 dev_err(&pdev->dev, "Failed to enable CI ISP device (%d)\n", err);
1267 return err;
1268 }
1269
1270 start = pci_resource_start(pdev, ATOM_ISP_PCI_BAR);
1271 dev_dbg(&pdev->dev, "start: 0x%x\n", start);
1272
1273 err = pcim_iomap_regions(pdev, BIT(ATOM_ISP_PCI_BAR), pci_name(pdev));
1274 if (err) {
1275 dev_err(&pdev->dev, "Failed to I/O memory remapping (%d)\n", err);
1276 goto ioremap_fail;
1277 }
1278
1279 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL);
1280 if (!isp) {
1281 err = -ENOMEM;
1282 goto atomisp_dev_alloc_fail;
1283 }
1284
1285 isp->dev = &pdev->dev;
1286 isp->base = pcim_iomap_table(pdev)[ATOM_ISP_PCI_BAR];
1287 isp->saved_regs.ispmmadr = start;
1288
1289 dev_dbg(&pdev->dev, "atomisp mmio base: %p\n", isp->base);
1290
1291 mutex_init(&isp->mutex);
1292 spin_lock_init(&isp->lock);
1293
1294 /* This is not a true PCI device on SoC, so the delay is not needed. */
1295 pdev->d3hot_delay = 0;
1296
1297 pci_set_drvdata(pdev, isp);
1298
1299 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) {
1300 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1301 isp->media_dev.hw_revision =
1302 (ATOMISP_HW_REVISION_ISP2400
1303 << ATOMISP_HW_REVISION_SHIFT) |
1304 ATOMISP_HW_STEPPING_B0;
1305
1306 switch (id->device) {
1307 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1308 isp->dfs = &dfs_config_merr_1179;
1309 break;
1310 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1311 isp->dfs = &dfs_config_merr_117a;
1312
1313 break;
1314 default:
1315 isp->dfs = &dfs_config_merr;
1316 break;
1317 }
1318 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1319 break;
1320 case ATOMISP_PCI_DEVICE_SOC_BYT:
1321 isp->media_dev.hw_revision =
1322 (ATOMISP_HW_REVISION_ISP2400
1323 << ATOMISP_HW_REVISION_SHIFT) |
1324 ATOMISP_HW_STEPPING_B0;
1325
1326 /*
1327 * Note: some Intel-based tablets with Android use a different
1328 * DFS table. Based on the comments at the Yocto Aero meta
1329 * version of this driver (at the ssid.h header), they're
1330 * identified via a "spid" var:
1331 *
1332 * androidboot.spid=vend:cust:manu:plat:prod:hard
1333 *
1334 * As we don't have this upstream, nor we know enough details
1335 * to use a DMI or PCI match table, the old code was just
1336 * removed, but let's keep a note here as a reminder that,
1337 * for certain devices, we may need to limit the max DFS
1338 * frequency to be below certain values, adjusting the
1339 * resolution accordingly.
1340 */
1341 isp->dfs = &dfs_config_byt;
1342
1343 /*
1344 * HPLL frequency is known to be device-specific, but we don't
1345 * have specs yet for exactly how it varies. Default to
1346 * BYT-CR but let provisioning set it via EFI variable
1347 */
1348 isp->hpll_freq = gmin_get_var_int(&pdev->dev, false, "HpllFreq", HPLL_FREQ_2000MHZ);
1349
1350 /*
1351 * for BYT/CHT we are put isp into D3cold to avoid pci registers access
1352 * in power off. Set d3cold_delay to 0 since default 100ms is not
1353 * necessary.
1354 */
1355 pdev->d3cold_delay = 0;
1356 break;
1357 case ATOMISP_PCI_DEVICE_SOC_ANN:
1358 isp->media_dev.hw_revision = ( ATOMISP_HW_REVISION_ISP2401
1359 << ATOMISP_HW_REVISION_SHIFT);
1360 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1361 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1362 isp->dfs = &dfs_config_merr;
1363 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1364 break;
1365 case ATOMISP_PCI_DEVICE_SOC_CHT:
1366 isp->media_dev.hw_revision = ( ATOMISP_HW_REVISION_ISP2401
1367 << ATOMISP_HW_REVISION_SHIFT);
1368 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1369 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1370
1371 isp->dfs = &dfs_config_cht;
1372 pdev->d3cold_delay = 0;
1373
1374 iosf_mbi_read(BT_MBI_UNIT_CCK, MBI_REG_READ, CCK_FUSE_REG_0, &val);
1375 switch (val & CCK_FUSE_HPLL_FREQ_MASK) {
1376 case 0x00:
1377 isp->hpll_freq = HPLL_FREQ_800MHZ;
1378 break;
1379 case 0x01:
1380 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1381 break;
1382 case 0x02:
1383 isp->hpll_freq = HPLL_FREQ_2000MHZ;
1384 break;
1385 default:
1386 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1387 dev_warn(&pdev->dev, "read HPLL from cck failed. Default to 1600 MHz.\n");
1388 }
1389 break;
1390 default:
1391 dev_err(&pdev->dev, "un-supported IUNIT device\n");
1392 err = -ENODEV;
1393 goto atomisp_dev_alloc_fail;
1394 }
1395
1396 dev_info(&pdev->dev, "ISP HPLL frequency base = %d MHz\n", isp->hpll_freq);
1397
1398 isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY;
1399
1400 /* Load isp firmware from user space */
1401 isp->firmware = atomisp_load_firmware(isp);
1402 if (!isp->firmware) {
1403 err = -ENOENT;
1404 dev_dbg(&pdev->dev, "Firmware load failed\n");
1405 goto load_fw_fail;
1406 }
1407
1408 err = sh_css_check_firmware_version(isp->dev, isp->firmware->data);
1409 if (err) {
1410 dev_dbg(&pdev->dev, "Firmware version check failed\n");
1411 goto fw_validation_fail;
1412 }
1413
1414 pci_set_master(pdev);
1415
1416 err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1417 if (err < 0) {
1418 dev_err(&pdev->dev, "Failed to enable msi (%d)\n", err);
1419 goto enable_msi_fail;
1420 }
1421
1422 atomisp_msi_irq_init(isp);
1423
1424 cpu_latency_qos_add_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
1425
1426 /*
1427 * for MRFLD, Software/firmware needs to write a 1 to bit 0 of
1428 * the register at CSI_RECEIVER_SELECTION_REG to enable SH CSI
1429 * backend write 0 will enable Arasan CSI backend, which has
1430 * bugs(like sighting:4567697 and 4567699) and will be removed
1431 * in B0
1432 */
1433 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
1434
1435 if ((id->device & ATOMISP_PCI_DEVICE_SOC_MASK) ==
1436 ATOMISP_PCI_DEVICE_SOC_MRFLD) {
1437 u32 csi_afe_trim;
1438
1439 /*
1440 * Workaround for imbalance data eye issue which is observed
1441 * on TNG B0.
1442 */
1443 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, &csi_afe_trim);
1444 csi_afe_trim &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1445 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1446 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1447 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1448 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1449 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT));
1450 csi_afe_trim |= (MRFLD_PCI_CSI1_HSRXCLKTRIM <<
1451 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1452 (MRFLD_PCI_CSI2_HSRXCLKTRIM <<
1453 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1454 (MRFLD_PCI_CSI3_HSRXCLKTRIM <<
1455 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT);
1456 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, csi_afe_trim);
1457 }
1458
1459 err = atomisp_initialize_modules(isp);
1460 if (err < 0) {
1461 dev_err(&pdev->dev, "atomisp_initialize_modules (%d)\n", err);
1462 goto initialize_modules_fail;
1463 }
1464
1465 err = atomisp_register_entities(isp);
1466 if (err < 0) {
1467 dev_err(&pdev->dev, "atomisp_register_entities failed (%d)\n", err);
1468 goto register_entities_fail;
1469 }
1470
1471 INIT_WORK(&isp->assert_recovery_work, atomisp_assert_recovery_work);
1472
1473 /* save the iunit context only once after all the values are init'ed. */
1474 atomisp_save_iunit_reg(isp);
1475
1476 /*
1477 * The atomisp does not use standard PCI power-management through the
1478 * PCI config space. Instead this driver directly tells the P-Unit to
1479 * disable the ISP over the IOSF. The standard PCI subsystem pm_ops will
1480 * try to access the config space before (resume) / after (suspend) this
1481 * driver has turned the ISP on / off, resulting in the following errors:
1482 *
1483 * "Unable to change power state from D0 to D3hot, device inaccessible"
1484 * "Unable to change power state from D3cold to D0, device inaccessible"
1485 *
1486 * To avoid these errors override the pm_domain so that all the PCI
1487 * subsys suspend / resume handling is skipped.
1488 */
1489 isp->pm_domain.ops.runtime_suspend = atomisp_power_off;
1490 isp->pm_domain.ops.runtime_resume = atomisp_power_on;
1491 isp->pm_domain.ops.suspend = atomisp_suspend;
1492 isp->pm_domain.ops.resume = atomisp_resume;
1493
1494 dev_pm_domain_set(&pdev->dev, &isp->pm_domain);
1495
1496 pm_runtime_put_noidle(&pdev->dev);
1497 pm_runtime_allow(&pdev->dev);
1498
1499 /* Init ISP memory management */
1500 hmm_init();
1501
1502 err = devm_request_threaded_irq(&pdev->dev, pdev->irq,
1503 atomisp_isr, atomisp_isr_thread,
1504 IRQF_SHARED, "isp_irq", isp);
1505 if (err) {
1506 dev_err(&pdev->dev, "Failed to request irq (%d)\n", err);
1507 goto request_irq_fail;
1508 }
1509
1510 /* Load firmware into ISP memory */
1511 err = atomisp_css_load_firmware(isp);
1512 if (err) {
1513 dev_err(&pdev->dev, "Failed to init css.\n");
1514 goto css_init_fail;
1515 }
1516 /* Clear FW image from memory */
1517 release_firmware(isp->firmware);
1518 isp->firmware = NULL;
1519 isp->css_env.isp_css_fw.data = NULL;
1520
1521 err = v4l2_async_nf_register(&isp->notifier);
1522 if (err) {
1523 dev_err(isp->dev, "failed to register async notifier : %d\n", err);
1524 goto css_init_fail;
1525 }
1526
1527 atomisp_drvfs_init(isp);
1528
1529 return 0;
1530
1531 css_init_fail:
1532 devm_free_irq(&pdev->dev, pdev->irq, isp);
1533 request_irq_fail:
1534 hmm_cleanup();
1535 pm_runtime_get_noresume(&pdev->dev);
1536 dev_pm_domain_set(&pdev->dev, NULL);
1537 atomisp_unregister_entities(isp);
1538 register_entities_fail:
1539 atomisp_uninitialize_modules(isp);
1540 initialize_modules_fail:
1541 cpu_latency_qos_remove_request(&isp->pm_qos);
1542 atomisp_msi_irq_uninit(isp);
1543 pci_free_irq_vectors(pdev);
1544 enable_msi_fail:
1545 fw_validation_fail:
1546 release_firmware(isp->firmware);
1547 load_fw_fail:
1548 /*
1549 * Switch off ISP, as keeping it powered on would prevent
1550 * reaching S0ix states.
1551 *
1552 * The following lines have been copied from atomisp suspend path
1553 */
1554
1555 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
1556 irq &= BIT(INTR_IIR);
1557 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
1558
1559 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
1560 irq &= ~BIT(INTR_IER);
1561 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
1562
1563 atomisp_msi_irq_uninit(isp);
1564
1565 /* Address later when we worry about the ...field chips */
1566 if (IS_ENABLED(CONFIG_PM) && atomisp_mrfld_power(isp, false))
1567 dev_err(&pdev->dev, "Failed to switch off ISP\n");
1568
1569 atomisp_dev_alloc_fail:
1570 pcim_iounmap_regions(pdev, BIT(ATOM_ISP_PCI_BAR));
1571
1572 ioremap_fail:
1573 return err;
1574 }
1575
atomisp_pci_remove(struct pci_dev * pdev)1576 static void atomisp_pci_remove(struct pci_dev *pdev)
1577 {
1578 struct atomisp_device *isp = pci_get_drvdata(pdev);
1579
1580 dev_info(&pdev->dev, "Removing atomisp driver\n");
1581
1582 atomisp_drvfs_exit();
1583
1584 ia_css_unload_firmware();
1585 hmm_cleanup();
1586
1587 pm_runtime_forbid(&pdev->dev);
1588 pm_runtime_get_noresume(&pdev->dev);
1589 dev_pm_domain_set(&pdev->dev, NULL);
1590 cpu_latency_qos_remove_request(&isp->pm_qos);
1591
1592 atomisp_msi_irq_uninit(isp);
1593 atomisp_unregister_entities(isp);
1594
1595 release_firmware(isp->firmware);
1596 }
1597
1598 static const struct pci_device_id atomisp_pci_tbl[] = {
1599 /* Merrifield */
1600 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD)},
1601 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_1179)},
1602 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_117A)},
1603 /* Baytrail */
1604 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_BYT)},
1605 /* Anniedale (Merrifield+ / Moorefield) */
1606 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_ANN)},
1607 /* Cherrytrail */
1608 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_CHT)},
1609 {0,}
1610 };
1611
1612 MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl);
1613
1614
1615 static struct pci_driver atomisp_pci_driver = {
1616 .name = "atomisp-isp2",
1617 .id_table = atomisp_pci_tbl,
1618 .probe = atomisp_pci_probe,
1619 .remove = atomisp_pci_remove,
1620 };
1621
1622 module_pci_driver(atomisp_pci_driver);
1623
1624 MODULE_AUTHOR("Wen Wang <wen.w.wang@intel.com>");
1625 MODULE_AUTHOR("Xiaolin Zhang <xiaolin.zhang@intel.com>");
1626 MODULE_LICENSE("GPL");
1627 MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver");
1628 MODULE_IMPORT_NS(INTEL_IPU_BRIDGE);
1629