1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Support for Medifield PNW Camera Imaging ISP subsystem.
4 *
5 * Copyright (c) 2010-2017 Intel Corporation. All Rights Reserved.
6 *
7 * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
8 */
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 #include <linux/pm_domain.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/pm_qos.h>
14 #include <linux/timer.h>
15 #include <linux/delay.h>
16 #include <linux/dmi.h>
17 #include <linux/interrupt.h>
18 #include <linux/bits.h>
19 #include <media/v4l2-fwnode.h>
20
21 #include <asm/iosf_mbi.h>
22
23 #include "../../include/linux/atomisp_gmin_platform.h"
24
25 #include "atomisp_cmd.h"
26 #include "atomisp_common.h"
27 #include "atomisp_fops.h"
28 #include "atomisp_ioctl.h"
29 #include "atomisp_internal.h"
30 #include "atomisp-regs.h"
31 #include "atomisp_dfs_tables.h"
32 #include "hmm/hmm.h"
33 #include "atomisp_trace_event.h"
34
35 #include "sh_css_firmware.h"
36
37 #include "device_access.h"
38
39 /* Timeouts to wait for all subdevs to be registered */
40 #define SUBDEV_WAIT_TIMEOUT 50 /* ms */
41 #define SUBDEV_WAIT_TIMEOUT_MAX_COUNT 40 /* up to 2 seconds */
42
43 /* G-Min addition: pull this in from intel_mid_pm.h */
44 #define CSTATE_EXIT_LATENCY_C1 1
45
46 /* cross component debug message flag */
47 int dbg_level;
48 module_param(dbg_level, int, 0644);
49 MODULE_PARM_DESC(dbg_level, "debug message level (default:0)");
50
51 /* log function switch */
52 int dbg_func = 1;
53 module_param(dbg_func, int, 0644);
54 MODULE_PARM_DESC(dbg_func,
55 "log function switch non/printk (default:printk)");
56
57 /*
58 * Set to 16x16 since this is the amount of lines and pixels the sensor
59 * exports extra. If these are kept at the 10x8 that they were on, in yuv
60 * downscaling modes incorrect resolutions where requested to the sensor
61 * driver with strange outcomes as a result. The proper way tot do this
62 * would be to have a list of tables the specify the sensor res, mipi rec,
63 * output res, and isp output res. however since we do not have this yet,
64 * the chosen solution is the next best thing.
65 */
66 int pad_w = 16;
67 module_param(pad_w, int, 0644);
68 MODULE_PARM_DESC(pad_w, "extra data for ISP processing");
69
70 int pad_h = 16;
71 module_param(pad_h, int, 0644);
72 MODULE_PARM_DESC(pad_h, "extra data for ISP processing");
73
74 /*
75 * FIXME: this is a hack to make easier to support ISP2401 variant.
76 * As a given system will either be ISP2401 or not, we can just use
77 * a boolean, in order to replace existing #ifdef ISP2401 everywhere.
78 *
79 * Once this driver gets into a better shape, however, the best would
80 * be to replace this to something stored inside atomisp allocated
81 * structures.
82 */
83
84 struct device *atomisp_dev;
85
86 static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = {
87 {
88 .width = ISP_FREQ_RULE_ANY,
89 .height = ISP_FREQ_RULE_ANY,
90 .fps = ISP_FREQ_RULE_ANY,
91 .isp_freq = ISP_FREQ_400MHZ,
92 .run_mode = ATOMISP_RUN_MODE_VIDEO,
93 },
94 {
95 .width = ISP_FREQ_RULE_ANY,
96 .height = ISP_FREQ_RULE_ANY,
97 .fps = ISP_FREQ_RULE_ANY,
98 .isp_freq = ISP_FREQ_400MHZ,
99 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
100 },
101 {
102 .width = ISP_FREQ_RULE_ANY,
103 .height = ISP_FREQ_RULE_ANY,
104 .fps = ISP_FREQ_RULE_ANY,
105 .isp_freq = ISP_FREQ_400MHZ,
106 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
107 },
108 };
109
110 /* Merrifield and Moorefield DFS rules */
111 static const struct atomisp_dfs_config dfs_config_merr = {
112 .lowest_freq = ISP_FREQ_200MHZ,
113 .max_freq_at_vmin = ISP_FREQ_400MHZ,
114 .highest_freq = ISP_FREQ_457MHZ,
115 .dfs_table = dfs_rules_merr,
116 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr),
117 };
118
119 static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = {
120 {
121 .width = ISP_FREQ_RULE_ANY,
122 .height = ISP_FREQ_RULE_ANY,
123 .fps = ISP_FREQ_RULE_ANY,
124 .isp_freq = ISP_FREQ_400MHZ,
125 .run_mode = ATOMISP_RUN_MODE_VIDEO,
126 },
127 {
128 .width = ISP_FREQ_RULE_ANY,
129 .height = ISP_FREQ_RULE_ANY,
130 .fps = ISP_FREQ_RULE_ANY,
131 .isp_freq = ISP_FREQ_400MHZ,
132 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
133 },
134 {
135 .width = ISP_FREQ_RULE_ANY,
136 .height = ISP_FREQ_RULE_ANY,
137 .fps = ISP_FREQ_RULE_ANY,
138 .isp_freq = ISP_FREQ_400MHZ,
139 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
140 },
141 };
142
143 static const struct atomisp_dfs_config dfs_config_merr_1179 = {
144 .lowest_freq = ISP_FREQ_200MHZ,
145 .max_freq_at_vmin = ISP_FREQ_400MHZ,
146 .highest_freq = ISP_FREQ_400MHZ,
147 .dfs_table = dfs_rules_merr_1179,
148 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179),
149 };
150
151 static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = {
152 {
153 .width = 1920,
154 .height = 1080,
155 .fps = 30,
156 .isp_freq = ISP_FREQ_266MHZ,
157 .run_mode = ATOMISP_RUN_MODE_VIDEO,
158 },
159 {
160 .width = 1080,
161 .height = 1920,
162 .fps = 30,
163 .isp_freq = ISP_FREQ_266MHZ,
164 .run_mode = ATOMISP_RUN_MODE_VIDEO,
165 },
166 {
167 .width = 1920,
168 .height = 1080,
169 .fps = 45,
170 .isp_freq = ISP_FREQ_320MHZ,
171 .run_mode = ATOMISP_RUN_MODE_VIDEO,
172 },
173 {
174 .width = 1080,
175 .height = 1920,
176 .fps = 45,
177 .isp_freq = ISP_FREQ_320MHZ,
178 .run_mode = ATOMISP_RUN_MODE_VIDEO,
179 },
180 {
181 .width = ISP_FREQ_RULE_ANY,
182 .height = ISP_FREQ_RULE_ANY,
183 .fps = 60,
184 .isp_freq = ISP_FREQ_356MHZ,
185 .run_mode = ATOMISP_RUN_MODE_VIDEO,
186 },
187 {
188 .width = ISP_FREQ_RULE_ANY,
189 .height = ISP_FREQ_RULE_ANY,
190 .fps = ISP_FREQ_RULE_ANY,
191 .isp_freq = ISP_FREQ_200MHZ,
192 .run_mode = ATOMISP_RUN_MODE_VIDEO,
193 },
194 {
195 .width = ISP_FREQ_RULE_ANY,
196 .height = ISP_FREQ_RULE_ANY,
197 .fps = ISP_FREQ_RULE_ANY,
198 .isp_freq = ISP_FREQ_400MHZ,
199 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
200 },
201 {
202 .width = ISP_FREQ_RULE_ANY,
203 .height = ISP_FREQ_RULE_ANY,
204 .fps = ISP_FREQ_RULE_ANY,
205 .isp_freq = ISP_FREQ_200MHZ,
206 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
207 },
208 };
209
210 static struct atomisp_dfs_config dfs_config_merr_117a = {
211 .lowest_freq = ISP_FREQ_200MHZ,
212 .max_freq_at_vmin = ISP_FREQ_200MHZ,
213 .highest_freq = ISP_FREQ_400MHZ,
214 .dfs_table = dfs_rules_merr_117a,
215 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a),
216 };
217
218 static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = {
219 {
220 .width = ISP_FREQ_RULE_ANY,
221 .height = ISP_FREQ_RULE_ANY,
222 .fps = ISP_FREQ_RULE_ANY,
223 .isp_freq = ISP_FREQ_400MHZ,
224 .run_mode = ATOMISP_RUN_MODE_VIDEO,
225 },
226 {
227 .width = ISP_FREQ_RULE_ANY,
228 .height = ISP_FREQ_RULE_ANY,
229 .fps = ISP_FREQ_RULE_ANY,
230 .isp_freq = ISP_FREQ_400MHZ,
231 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
232 },
233 {
234 .width = ISP_FREQ_RULE_ANY,
235 .height = ISP_FREQ_RULE_ANY,
236 .fps = ISP_FREQ_RULE_ANY,
237 .isp_freq = ISP_FREQ_400MHZ,
238 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
239 },
240 };
241
242 static const struct atomisp_dfs_config dfs_config_byt = {
243 .lowest_freq = ISP_FREQ_200MHZ,
244 .max_freq_at_vmin = ISP_FREQ_400MHZ,
245 .highest_freq = ISP_FREQ_400MHZ,
246 .dfs_table = dfs_rules_byt,
247 .dfs_table_size = ARRAY_SIZE(dfs_rules_byt),
248 };
249
250 static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = {
251 {
252 .width = ISP_FREQ_RULE_ANY,
253 .height = ISP_FREQ_RULE_ANY,
254 .fps = ISP_FREQ_RULE_ANY,
255 .isp_freq = ISP_FREQ_320MHZ,
256 .run_mode = ATOMISP_RUN_MODE_VIDEO,
257 },
258 {
259 .width = ISP_FREQ_RULE_ANY,
260 .height = ISP_FREQ_RULE_ANY,
261 .fps = ISP_FREQ_RULE_ANY,
262 .isp_freq = ISP_FREQ_356MHZ,
263 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
264 },
265 {
266 .width = ISP_FREQ_RULE_ANY,
267 .height = ISP_FREQ_RULE_ANY,
268 .fps = ISP_FREQ_RULE_ANY,
269 .isp_freq = ISP_FREQ_320MHZ,
270 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
271 },
272 };
273
274 static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = {
275 {
276 .width = ISP_FREQ_RULE_ANY,
277 .height = ISP_FREQ_RULE_ANY,
278 .fps = ISP_FREQ_RULE_ANY,
279 .isp_freq = ISP_FREQ_356MHZ,
280 .run_mode = ATOMISP_RUN_MODE_VIDEO,
281 },
282 {
283 .width = ISP_FREQ_RULE_ANY,
284 .height = ISP_FREQ_RULE_ANY,
285 .fps = ISP_FREQ_RULE_ANY,
286 .isp_freq = ISP_FREQ_356MHZ,
287 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
288 },
289 {
290 .width = ISP_FREQ_RULE_ANY,
291 .height = ISP_FREQ_RULE_ANY,
292 .fps = ISP_FREQ_RULE_ANY,
293 .isp_freq = ISP_FREQ_320MHZ,
294 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
295 },
296 };
297
298 static const struct atomisp_dfs_config dfs_config_cht = {
299 .lowest_freq = ISP_FREQ_100MHZ,
300 .max_freq_at_vmin = ISP_FREQ_356MHZ,
301 .highest_freq = ISP_FREQ_356MHZ,
302 .dfs_table = dfs_rules_cht,
303 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht),
304 };
305
306 /* This one should be visible also by atomisp_cmd.c */
307 const struct atomisp_dfs_config dfs_config_cht_soc = {
308 .lowest_freq = ISP_FREQ_100MHZ,
309 .max_freq_at_vmin = ISP_FREQ_356MHZ,
310 .highest_freq = ISP_FREQ_356MHZ,
311 .dfs_table = dfs_rules_cht_soc,
312 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc),
313 };
314
atomisp_video_init(struct atomisp_video_pipe * video)315 int atomisp_video_init(struct atomisp_video_pipe *video)
316 {
317 int ret;
318
319 video->pad.flags = MEDIA_PAD_FL_SINK;
320 ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad);
321 if (ret < 0)
322 return ret;
323
324 /* Initialize the video device. */
325 strscpy(video->vdev.name, "ATOMISP video output", sizeof(video->vdev.name));
326 video->vdev.fops = &atomisp_fops;
327 video->vdev.ioctl_ops = &atomisp_ioctl_ops;
328 video->vdev.lock = &video->isp->mutex;
329 video->vdev.release = video_device_release_empty;
330 video_set_drvdata(&video->vdev, video->isp);
331
332 return 0;
333 }
334
atomisp_video_unregister(struct atomisp_video_pipe * video)335 void atomisp_video_unregister(struct atomisp_video_pipe *video)
336 {
337 if (video_is_registered(&video->vdev)) {
338 media_entity_cleanup(&video->vdev.entity);
339 video_unregister_device(&video->vdev);
340 }
341 }
342
atomisp_save_iunit_reg(struct atomisp_device * isp)343 static int atomisp_save_iunit_reg(struct atomisp_device *isp)
344 {
345 struct pci_dev *pdev = to_pci_dev(isp->dev);
346
347 dev_dbg(isp->dev, "%s\n", __func__);
348
349 pci_read_config_word(pdev, PCI_COMMAND, &isp->saved_regs.pcicmdsts);
350 /* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */
351 pci_read_config_dword(pdev, PCI_MSI_CAPID, &isp->saved_regs.msicap);
352 pci_read_config_dword(pdev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr);
353 pci_read_config_word(pdev, PCI_MSI_DATA, &isp->saved_regs.msi_data);
354 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr);
355 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &isp->saved_regs.interrupt_control);
356
357 pci_read_config_dword(pdev, MRFLD_PCI_PMCS, &isp->saved_regs.pmcs);
358 /* Ensure read/write combining is enabled. */
359 pci_read_config_dword(pdev, PCI_I_CONTROL, &isp->saved_regs.i_control);
360 isp->saved_regs.i_control |=
361 MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING |
362 MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING;
363 pci_read_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
364 &isp->saved_regs.csi_access_viol);
365 pci_read_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
366 &isp->saved_regs.csi_rcomp_config);
367 /*
368 * Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE.
369 * ANN/CHV: RCOMP updates do not happen when using CSI2+ path
370 * and sensor sending "continuous clock".
371 * TNG/ANN/CHV: MIPI packets are lost if the HS entry sequence
372 * is missed, and IUNIT can hang.
373 * For both issues, setting this bit is a workaround.
374 */
375 isp->saved_regs.csi_rcomp_config |= MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE;
376 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
377 &isp->saved_regs.csi_afe_dly);
378 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
379 &isp->saved_regs.csi_control);
380 if (isp->media_dev.hw_revision >=
381 (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT))
382 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_PARPATHEN;
383 /*
384 * On CHT CSI_READY bit should be enabled before stream on
385 */
386 if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 <<
387 ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)))
388 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_CSI_READY;
389 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
390 &isp->saved_regs.csi_afe_rcomp_config);
391 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
392 &isp->saved_regs.csi_afe_hs_control);
393 pci_read_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
394 &isp->saved_regs.csi_deadline_control);
395 return 0;
396 }
397
atomisp_restore_iunit_reg(struct atomisp_device * isp)398 static int atomisp_restore_iunit_reg(struct atomisp_device *isp)
399 {
400 struct pci_dev *pdev = to_pci_dev(isp->dev);
401
402 dev_dbg(isp->dev, "%s\n", __func__);
403
404 pci_write_config_word(pdev, PCI_COMMAND, isp->saved_regs.pcicmdsts);
405 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, isp->saved_regs.ispmmadr);
406 pci_write_config_dword(pdev, PCI_MSI_CAPID, isp->saved_regs.msicap);
407 pci_write_config_dword(pdev, PCI_MSI_ADDR, isp->saved_regs.msi_addr);
408 pci_write_config_word(pdev, PCI_MSI_DATA, isp->saved_regs.msi_data);
409 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, isp->saved_regs.intr);
410 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, isp->saved_regs.interrupt_control);
411 pci_write_config_dword(pdev, PCI_I_CONTROL, isp->saved_regs.i_control);
412
413 pci_write_config_dword(pdev, MRFLD_PCI_PMCS, isp->saved_regs.pmcs);
414 pci_write_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
415 isp->saved_regs.csi_access_viol);
416 pci_write_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
417 isp->saved_regs.csi_rcomp_config);
418 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
419 isp->saved_regs.csi_afe_dly);
420 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
421 isp->saved_regs.csi_control);
422 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
423 isp->saved_regs.csi_afe_rcomp_config);
424 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
425 isp->saved_regs.csi_afe_hs_control);
426 pci_write_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
427 isp->saved_regs.csi_deadline_control);
428
429 /*
430 * for MRFLD, Software/firmware needs to write a 1 to bit0
431 * of the register at CSI_RECEIVER_SELECTION_REG to enable
432 * SH CSI backend write 0 will enable Arasan CSI backend,
433 * which has bugs(like sighting:4567697 and 4567699) and
434 * will be removed in B0
435 */
436 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
437 return 0;
438 }
439
atomisp_mrfld_pre_power_down(struct atomisp_device * isp)440 static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp)
441 {
442 struct pci_dev *pdev = to_pci_dev(isp->dev);
443 u32 irq;
444 unsigned long flags;
445
446 spin_lock_irqsave(&isp->lock, flags);
447
448 /*
449 * MRFLD HAS requirement: cannot power off i-unit if
450 * ISP has IRQ not serviced.
451 * So, here we need to check if there is any pending
452 * IRQ, if so, waiting for it to be served
453 */
454 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
455 irq &= BIT(INTR_IIR);
456 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
457
458 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
459 if (!(irq & BIT(INTR_IIR)))
460 goto done;
461
462 atomisp_css2_hw_store_32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF);
463 atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq);
464 if (irq != 0) {
465 dev_err(isp->dev,
466 "%s: fail to clear isp interrupt status reg=0x%x\n",
467 __func__, irq);
468 spin_unlock_irqrestore(&isp->lock, flags);
469 return -EAGAIN;
470 } else {
471 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
472 irq &= BIT(INTR_IIR);
473 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
474
475 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
476 if (!(irq & BIT(INTR_IIR))) {
477 atomisp_css2_hw_store_32(MRFLD_INTR_ENABLE_REG, 0x0);
478 goto done;
479 }
480 dev_err(isp->dev,
481 "%s: error in iunit interrupt. status reg=0x%x\n",
482 __func__, irq);
483 spin_unlock_irqrestore(&isp->lock, flags);
484 return -EAGAIN;
485 }
486 done:
487 /*
488 * MRFLD WORKAROUND:
489 * before powering off IUNIT, clear the pending interrupts
490 * and disable the interrupt. driver should avoid writing 0
491 * to IIR. It could block subsequent interrupt messages.
492 * HW sighting:4568410.
493 */
494 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
495 irq &= ~BIT(INTR_IER);
496 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
497
498 atomisp_msi_irq_uninit(isp);
499 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
500 spin_unlock_irqrestore(&isp->lock, flags);
501
502 return 0;
503 }
504
505 /*
506 * WA for DDR DVFS enable/disable
507 * By default, ISP will force DDR DVFS 1600MHz before disable DVFS
508 */
punit_ddr_dvfs_enable(bool enable)509 static void punit_ddr_dvfs_enable(bool enable)
510 {
511 int reg;
512
513 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®);
514 if (enable) {
515 reg &= ~(MRFLD_BIT0 | MRFLD_BIT1);
516 } else {
517 reg |= MRFLD_BIT1;
518 reg &= ~(MRFLD_BIT0);
519 }
520 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, MRFLD_ISPSSDVFS, reg);
521 }
522
atomisp_mrfld_power(struct atomisp_device * isp,bool enable)523 static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable)
524 {
525 struct pci_dev *pdev = to_pci_dev(isp->dev);
526 unsigned long timeout;
527 u32 val = enable ? MRFLD_ISPSSPM0_IUNIT_POWER_ON :
528 MRFLD_ISPSSPM0_IUNIT_POWER_OFF;
529
530 dev_dbg(isp->dev, "IUNIT power-%s.\n", enable ? "on" : "off");
531
532 /* WA for P-Unit, if DVFS enabled, ISP timeout observed */
533 if (IS_CHT && enable && !isp->pm_only) {
534 punit_ddr_dvfs_enable(false);
535 msleep(20);
536 }
537
538 /* Write to ISPSSPM0 bit[1:0] to power on/off the IUNIT */
539 iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0,
540 val, MRFLD_ISPSSPM0_ISPSSC_MASK);
541
542 /* WA:Enable DVFS */
543 if (IS_CHT && !enable && !isp->pm_only)
544 punit_ddr_dvfs_enable(true);
545
546 /*
547 * There should be no IUNIT access while power-down is
548 * in progress. HW sighting: 4567865.
549 * Wait up to 50 ms for the IUNIT to shut down.
550 * And we do the same for power on.
551 */
552 timeout = jiffies + msecs_to_jiffies(50);
553 do {
554 u32 tmp;
555
556 /* Wait until ISPSSPM0 bit[25:24] shows the right value */
557 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, &tmp);
558 tmp = (tmp >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) & MRFLD_ISPSSPM0_ISPSSC_MASK;
559 if (tmp == val) {
560 trace_ipu_cstate(enable);
561 pdev->current_state = enable ? PCI_D0 : PCI_D3cold;
562 return 0;
563 }
564
565 if (time_after(jiffies, timeout))
566 break;
567
568 /* FIXME: experienced value for delay */
569 usleep_range(100, 150);
570 } while (1);
571
572 dev_err(isp->dev, "IUNIT power-%s timeout.\n", enable ? "on" : "off");
573 return -EBUSY;
574 }
575
atomisp_power_off(struct device * dev)576 int atomisp_power_off(struct device *dev)
577 {
578 struct atomisp_device *isp = dev_get_drvdata(dev);
579 struct pci_dev *pdev = to_pci_dev(dev);
580 int ret;
581 u32 reg;
582
583 if (isp->pm_only) {
584 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, 0);
585 } else {
586 atomisp_css_uninit(isp);
587
588 ret = atomisp_mrfld_pre_power_down(isp);
589 if (ret)
590 return ret;
591 }
592
593 /*
594 * MRFLD IUNIT DPHY is located in an always-power-on island
595 * MRFLD HW design need all CSI ports are disabled before
596 * powering down the IUNIT.
597 */
598 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, ®);
599 reg |= MRFLD_ALL_CSI_PORTS_OFF_MASK;
600 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, reg);
601
602 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
603 pci_save_state(pdev);
604 return atomisp_mrfld_power(isp, false);
605 }
606
atomisp_power_on(struct device * dev)607 int atomisp_power_on(struct device *dev)
608 {
609 struct atomisp_device *isp = (struct atomisp_device *)
610 dev_get_drvdata(dev);
611 int ret;
612
613 ret = atomisp_mrfld_power(isp, true);
614 if (ret)
615 return ret;
616
617 pci_restore_state(to_pci_dev(dev));
618 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency);
619
620 if (isp->pm_only)
621 return 0;
622
623 /*restore register values for iUnit and iUnitPHY registers*/
624 if (isp->saved_regs.pcicmdsts)
625 atomisp_restore_iunit_reg(isp);
626
627 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
628
629 return atomisp_css_init(isp);
630 }
631
atomisp_suspend(struct device * dev)632 static int atomisp_suspend(struct device *dev)
633 {
634 struct atomisp_device *isp = (struct atomisp_device *)
635 dev_get_drvdata(dev);
636 unsigned long flags;
637
638 /* FIXME: Suspend is not supported by sensors. Abort if streaming. */
639 spin_lock_irqsave(&isp->lock, flags);
640 if (isp->asd.streaming) {
641 spin_unlock_irqrestore(&isp->lock, flags);
642 dev_err(isp->dev, "atomisp cannot suspend at this time.\n");
643 return -EINVAL;
644 }
645 spin_unlock_irqrestore(&isp->lock, flags);
646
647 pm_runtime_resume(dev);
648
649 isp->asd.recreate_streams_on_resume = isp->asd.stream_prepared;
650 atomisp_destroy_pipes_stream(&isp->asd);
651
652 return atomisp_power_off(dev);
653 }
654
atomisp_resume(struct device * dev)655 static int atomisp_resume(struct device *dev)
656 {
657 struct atomisp_device *isp = dev_get_drvdata(dev);
658 int ret;
659
660 ret = atomisp_power_on(dev);
661 if (ret)
662 return ret;
663
664 if (isp->asd.recreate_streams_on_resume)
665 ret = atomisp_create_pipes_stream(&isp->asd);
666
667 return ret;
668 }
669
atomisp_csi_lane_config(struct atomisp_device * isp)670 int atomisp_csi_lane_config(struct atomisp_device *isp)
671 {
672 struct pci_dev *pdev = to_pci_dev(isp->dev);
673 static const struct {
674 u8 code;
675 u8 lanes[N_MIPI_PORT_ID];
676 } portconfigs[] = {
677 /* Tangier/Merrifield available lane configurations */
678 { 0x00, { 4, 1, 0 } }, /* 00000 */
679 { 0x01, { 3, 1, 0 } }, /* 00001 */
680 { 0x02, { 2, 1, 0 } }, /* 00010 */
681 { 0x03, { 1, 1, 0 } }, /* 00011 */
682 { 0x04, { 2, 1, 2 } }, /* 00100 */
683 { 0x08, { 3, 1, 1 } }, /* 01000 */
684 { 0x09, { 2, 1, 1 } }, /* 01001 */
685 { 0x0a, { 1, 1, 1 } }, /* 01010 */
686
687 /* Anniedale/Moorefield only configurations */
688 { 0x10, { 4, 2, 0 } }, /* 10000 */
689 { 0x11, { 3, 2, 0 } }, /* 10001 */
690 { 0x12, { 2, 2, 0 } }, /* 10010 */
691 { 0x13, { 1, 2, 0 } }, /* 10011 */
692 { 0x14, { 2, 2, 2 } }, /* 10100 */
693 { 0x18, { 3, 2, 1 } }, /* 11000 */
694 { 0x19, { 2, 2, 1 } }, /* 11001 */
695 { 0x1a, { 1, 2, 1 } }, /* 11010 */
696 };
697
698 unsigned int i, j;
699 u32 csi_control;
700 int nportconfigs;
701 u32 port_config_mask;
702 int port3_lanes_shift;
703
704 if (isp->media_dev.hw_revision <
705 ATOMISP_HW_REVISION_ISP2401_LEGACY <<
706 ATOMISP_HW_REVISION_SHIFT) {
707 /* Merrifield */
708 port_config_mask = MRFLD_PORT_CONFIG_MASK;
709 port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT;
710 } else {
711 /* Moorefield / Cherryview */
712 port_config_mask = CHV_PORT_CONFIG_MASK;
713 port3_lanes_shift = CHV_PORT3_LANES_SHIFT;
714 }
715
716 if (isp->media_dev.hw_revision <
717 ATOMISP_HW_REVISION_ISP2401 <<
718 ATOMISP_HW_REVISION_SHIFT) {
719 /* Merrifield / Moorefield legacy input system */
720 nportconfigs = MRFLD_PORT_CONFIG_NUM;
721 } else {
722 /* Moorefield / Cherryview new input system */
723 nportconfigs = ARRAY_SIZE(portconfigs);
724 }
725
726 for (i = 0; i < nportconfigs; i++) {
727 for (j = 0; j < N_MIPI_PORT_ID; j++)
728 if (isp->sensor_lanes[j] &&
729 isp->sensor_lanes[j] != portconfigs[i].lanes[j])
730 break;
731
732 if (j == N_MIPI_PORT_ID)
733 break; /* Found matching setting */
734 }
735
736 if (i >= nportconfigs) {
737 dev_err(isp->dev,
738 "%s: could not find the CSI port setting for %d-%d-%d\n",
739 __func__,
740 isp->sensor_lanes[0], isp->sensor_lanes[1], isp->sensor_lanes[2]);
741 return -EINVAL;
742 }
743
744 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &csi_control);
745 csi_control &= ~port_config_mask;
746 csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT)
747 | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT))
748 | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT))
749 | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT))
750 | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT)
751 | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT)
752 | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift);
753
754 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, csi_control);
755
756 dev_dbg(isp->dev,
757 "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n",
758 __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1],
759 portconfigs[i].lanes[2], csi_control);
760
761 return 0;
762 }
763
atomisp_subdev_probe(struct atomisp_device * isp)764 static int atomisp_subdev_probe(struct atomisp_device *isp)
765 {
766 const struct intel_v4l2_subdev_table *subdevs;
767 int ret, mipi_port;
768
769 ret = atomisp_csi2_bridge_parse_firmware(isp);
770 if (ret)
771 return ret;
772
773 /*
774 * TODO: this is left here for now to allow testing atomisp-sensor
775 * drivers which are still using the atomisp_gmin_platform infra before
776 * converting them to standard v4l2 sensor drivers using runtime-pm +
777 * ACPI for pm and v4l2_async_register_subdev_sensor() registration.
778 */
779 for (subdevs = atomisp_platform_get_subdevs(); subdevs->subdev; subdevs++) {
780 ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdevs->subdev);
781 if (ret)
782 continue;
783
784 if (subdevs->port >= ATOMISP_CAMERA_NR_PORTS) {
785 dev_err(isp->dev, "port %d not supported\n", subdevs->port);
786 continue;
787 }
788
789 if (isp->sensor_subdevs[subdevs->port]) {
790 dev_err(isp->dev, "port %d already has a sensor attached\n",
791 subdevs->port);
792 continue;
793 }
794
795 mipi_port = atomisp_port_to_mipi_port(isp, subdevs->port);
796 isp->sensor_lanes[mipi_port] = subdevs->lanes;
797 isp->sensor_subdevs[subdevs->port] = subdevs->subdev;
798 }
799
800 return atomisp_csi_lane_config(isp);
801 }
802
atomisp_unregister_entities(struct atomisp_device * isp)803 static void atomisp_unregister_entities(struct atomisp_device *isp)
804 {
805 unsigned int i;
806 struct v4l2_subdev *sd, *next;
807
808 atomisp_subdev_unregister_entities(&isp->asd);
809 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
810 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
811
812 list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list)
813 v4l2_device_unregister_subdev(sd);
814
815 v4l2_device_unregister(&isp->v4l2_dev);
816 media_device_unregister(&isp->media_dev);
817 media_device_cleanup(&isp->media_dev);
818
819 for (i = 0; i < isp->input_cnt; i++)
820 __v4l2_subdev_state_free(isp->inputs[i].try_sd_state);
821 }
822
atomisp_register_entities(struct atomisp_device * isp)823 static int atomisp_register_entities(struct atomisp_device *isp)
824 {
825 int ret = 0;
826 unsigned int i;
827
828 isp->media_dev.dev = isp->dev;
829
830 strscpy(isp->media_dev.model, "Intel Atom ISP",
831 sizeof(isp->media_dev.model));
832
833 media_device_init(&isp->media_dev);
834 isp->v4l2_dev.mdev = &isp->media_dev;
835 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
836 if (ret < 0) {
837 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
838 __func__, ret);
839 goto v4l2_device_failed;
840 }
841
842 ret = atomisp_subdev_probe(isp);
843 if (ret < 0)
844 goto csi_and_subdev_probe_failed;
845
846 /* Register internal entities */
847 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
848 ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i],
849 &isp->v4l2_dev);
850 if (ret == 0)
851 continue;
852
853 /* error case */
854 dev_err(isp->dev, "failed to register the CSI port: %d\n", i);
855 /* deregister all registered CSI ports */
856 while (i--)
857 atomisp_mipi_csi2_unregister_entities(
858 &isp->csi2_port[i]);
859
860 goto csi_and_subdev_probe_failed;
861 }
862
863 ret = atomisp_subdev_register_subdev(&isp->asd, &isp->v4l2_dev);
864 if (ret < 0) {
865 dev_err(isp->dev, "atomisp_subdev_register_subdev fail\n");
866 goto subdev_register_failed;
867 }
868
869 return 0;
870
871 subdev_register_failed:
872 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
873 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
874 csi_and_subdev_probe_failed:
875 v4l2_device_unregister(&isp->v4l2_dev);
876 v4l2_device_failed:
877 media_device_unregister(&isp->media_dev);
878 media_device_cleanup(&isp->media_dev);
879 return ret;
880 }
881
atomisp_init_sensor(struct atomisp_input_subdev * input)882 static void atomisp_init_sensor(struct atomisp_input_subdev *input)
883 {
884 static struct lock_class_key try_sd_state_key;
885 struct v4l2_subdev_mbus_code_enum mbus_code_enum = { };
886 struct v4l2_subdev_frame_size_enum fse = { };
887 struct v4l2_subdev_selection sel = { };
888 struct v4l2_subdev_state *try_sd_state, *act_sd_state;
889 int i, err;
890
891 /*
892 * FIXME: Drivers are not supposed to use __v4l2_subdev_state_alloc()
893 * but atomisp needs this for try_fmt on its /dev/video# node since
894 * it emulates a normal v4l2 device there, passing through try_fmt /
895 * set_fmt to the sensor.
896 */
897 try_sd_state = __v4l2_subdev_state_alloc(input->sensor,
898 "atomisp:try_sd_state->lock",
899 &try_sd_state_key);
900 if (IS_ERR(try_sd_state))
901 return;
902
903 input->try_sd_state = try_sd_state;
904
905 act_sd_state = v4l2_subdev_lock_and_get_active_state(input->sensor);
906
907 mbus_code_enum.which = V4L2_SUBDEV_FORMAT_ACTIVE;
908 err = v4l2_subdev_call(input->sensor, pad, enum_mbus_code,
909 act_sd_state, &mbus_code_enum);
910 if (!err)
911 input->code = mbus_code_enum.code;
912
913 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
914 sel.target = V4L2_SEL_TGT_NATIVE_SIZE;
915 err = v4l2_subdev_call(input->sensor, pad, get_selection,
916 act_sd_state, &sel);
917 if (err)
918 goto unlock_act_sd_state;
919
920 input->native_rect = sel.r;
921
922 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
923 sel.target = V4L2_SEL_TGT_CROP_DEFAULT;
924 err = v4l2_subdev_call(input->sensor, pad, get_selection,
925 act_sd_state, &sel);
926 if (err)
927 goto unlock_act_sd_state;
928
929 input->active_rect = sel.r;
930
931 /*
932 * Check for a framesize with half active_rect width and height,
933 * if found assume the sensor supports binning.
934 * Do this before changing the crop-rect since that may influence
935 * enum_frame_size results.
936 */
937 for (i = 0; ; i++) {
938 fse.index = i;
939 fse.code = input->code;
940 fse.which = V4L2_SUBDEV_FORMAT_ACTIVE;
941
942 err = v4l2_subdev_call(input->sensor, pad, enum_frame_size,
943 act_sd_state, &fse);
944 if (err)
945 break;
946
947 if (fse.min_width <= (input->active_rect.width / 2) &&
948 fse.min_height <= (input->active_rect.height / 2)) {
949 input->binning_support = true;
950 break;
951 }
952 }
953
954 /*
955 * The ISP also wants the non-active pixels at the border of the sensor
956 * for padding, set the crop rect to cover the entire sensor instead
957 * of only the default active area.
958 *
959 * Do this for both try and active formats since the crop rect in
960 * try_sd_state may influence (clamp size) in calls with which == try.
961 */
962 sel.which = V4L2_SUBDEV_FORMAT_TRY;
963 sel.target = V4L2_SEL_TGT_CROP;
964 sel.r = input->native_rect;
965
966 /* Don't lock try_sd_state if the lock is shared with the active state */
967 if (!input->sensor->state_lock)
968 v4l2_subdev_lock_state(input->try_sd_state);
969
970 err = v4l2_subdev_call(input->sensor, pad, set_selection,
971 input->try_sd_state, &sel);
972
973 if (!input->sensor->state_lock)
974 v4l2_subdev_unlock_state(input->try_sd_state);
975
976 if (err)
977 goto unlock_act_sd_state;
978
979 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
980 sel.target = V4L2_SEL_TGT_CROP;
981 sel.r = input->native_rect;
982 err = v4l2_subdev_call(input->sensor, pad, set_selection,
983 act_sd_state, &sel);
984 if (err)
985 goto unlock_act_sd_state;
986
987 dev_info(input->sensor->dev, "Supports crop native %dx%d active %dx%d binning %d\n",
988 input->native_rect.width, input->native_rect.height,
989 input->active_rect.width, input->active_rect.height,
990 input->binning_support);
991
992 input->crop_support = true;
993
994 unlock_act_sd_state:
995 if (act_sd_state)
996 v4l2_subdev_unlock_state(act_sd_state);
997 }
998
atomisp_register_device_nodes(struct atomisp_device * isp)999 int atomisp_register_device_nodes(struct atomisp_device *isp)
1000 {
1001 struct media_pad *sensor_isp_sink, *sensor_src;
1002 struct atomisp_input_subdev *input;
1003 int i, err, source_pad;
1004
1005 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
1006 err = media_create_pad_link(&isp->csi2_port[i].subdev.entity,
1007 CSI2_PAD_SOURCE, &isp->asd.subdev.entity,
1008 ATOMISP_SUBDEV_PAD_SINK, 0);
1009 if (err)
1010 return err;
1011
1012 if (!isp->sensor_subdevs[i])
1013 continue;
1014
1015 input = &isp->inputs[isp->input_cnt];
1016
1017 input->port = i;
1018 input->csi_port = &isp->csi2_port[i].subdev;
1019 input->csi_remote_source = isp->sensor_subdevs[i];
1020
1021 /*
1022 * Special case for sensors with a ISP in the sensor modelled
1023 * as a separate v4l2-subdev, like the mt9m114.
1024 */
1025 if (isp->sensor_subdevs[i]->entity.function == MEDIA_ENT_F_PROC_VIDEO_ISP) {
1026 input->sensor_isp = isp->sensor_subdevs[i];
1027 source_pad = SENSOR_ISP_PAD_SOURCE;
1028
1029 sensor_isp_sink = &input->sensor_isp->entity.pads[SENSOR_ISP_PAD_SINK];
1030 sensor_src = media_pad_remote_pad_first(sensor_isp_sink);
1031 if (!sensor_src) {
1032 dev_err(isp->dev, "Error could not find remote pad for sensor ISP sink\n");
1033 return -ENOENT;
1034 }
1035
1036 input->sensor = media_entity_to_v4l2_subdev(sensor_src->entity);
1037 } else {
1038 input->sensor = isp->sensor_subdevs[i];
1039 source_pad = 0;
1040 }
1041
1042 atomisp_init_sensor(input);
1043
1044 err = media_create_pad_link(&isp->sensor_subdevs[i]->entity, source_pad,
1045 &isp->csi2_port[i].subdev.entity,
1046 CSI2_PAD_SINK,
1047 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1048 if (err)
1049 return err;
1050
1051 isp->input_cnt++;
1052 }
1053
1054 if (!isp->input_cnt)
1055 dev_warn(isp->dev, "no camera attached or fail to detect\n");
1056 else
1057 dev_info(isp->dev, "detected %d camera sensors\n", isp->input_cnt);
1058
1059 mutex_lock(&isp->media_dev.graph_mutex);
1060 atomisp_setup_input_links(isp);
1061 mutex_unlock(&isp->media_dev.graph_mutex);
1062
1063 isp->asd.video_out.vdev.v4l2_dev = &isp->v4l2_dev;
1064 isp->asd.video_out.vdev.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1065 err = video_register_device(&isp->asd.video_out.vdev, VFL_TYPE_VIDEO, -1);
1066 if (err)
1067 return err;
1068
1069 err = media_create_pad_link(&isp->asd.subdev.entity, ATOMISP_SUBDEV_PAD_SOURCE,
1070 &isp->asd.video_out.vdev.entity, 0,
1071 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1072 if (err)
1073 return err;
1074
1075 err = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
1076 if (err)
1077 return err;
1078
1079 return media_device_register(&isp->media_dev);
1080 }
1081
atomisp_initialize_modules(struct atomisp_device * isp)1082 static int atomisp_initialize_modules(struct atomisp_device *isp)
1083 {
1084 int ret;
1085
1086 ret = atomisp_mipi_csi2_init(isp);
1087 if (ret < 0) {
1088 dev_err(isp->dev, "mipi csi2 initialization failed\n");
1089 goto error_mipi_csi2;
1090 }
1091
1092 ret = atomisp_subdev_init(isp);
1093 if (ret < 0) {
1094 dev_err(isp->dev, "ISP subdev initialization failed\n");
1095 goto error_isp_subdev;
1096 }
1097
1098 return 0;
1099
1100 error_isp_subdev:
1101 error_mipi_csi2:
1102 atomisp_mipi_csi2_cleanup(isp);
1103 return ret;
1104 }
1105
atomisp_uninitialize_modules(struct atomisp_device * isp)1106 static void atomisp_uninitialize_modules(struct atomisp_device *isp)
1107 {
1108 atomisp_mipi_csi2_cleanup(isp);
1109 }
1110
1111 const struct firmware *
atomisp_load_firmware(struct atomisp_device * isp)1112 atomisp_load_firmware(struct atomisp_device *isp)
1113 {
1114 const struct firmware *fw;
1115 int rc;
1116 char *fw_path = NULL;
1117
1118 if ((isp->media_dev.hw_revision >> ATOMISP_HW_REVISION_SHIFT) ==
1119 ATOMISP_HW_REVISION_ISP2401)
1120 fw_path = "intel/ipu/shisp_2401a0_v21.bin";
1121
1122 if (isp->media_dev.hw_revision ==
1123 ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT) |
1124 ATOMISP_HW_STEPPING_A0))
1125 fw_path = "intel/ipu/shisp_2401a0_legacy_v21.bin";
1126
1127 if (isp->media_dev.hw_revision ==
1128 ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT) |
1129 ATOMISP_HW_STEPPING_B0))
1130 fw_path = "intel/ipu/shisp_2400b0_v21.bin";
1131
1132 if (!fw_path) {
1133 dev_err(isp->dev, "Unsupported hw_revision 0x%x\n",
1134 isp->media_dev.hw_revision);
1135 return NULL;
1136 }
1137
1138 rc = request_firmware(&fw, fw_path, isp->dev);
1139 /* Fallback to old fw_path without "intel/ipu/" prefix */
1140 if (rc)
1141 rc = request_firmware(&fw, kbasename(fw_path), isp->dev);
1142 if (rc) {
1143 dev_err(isp->dev,
1144 "atomisp: Error %d while requesting firmware %s\n",
1145 rc, fw_path);
1146 return NULL;
1147 }
1148
1149 return fw;
1150 }
1151
atomisp_pm_init(struct atomisp_device * isp)1152 static void atomisp_pm_init(struct atomisp_device *isp)
1153 {
1154 /*
1155 * The atomisp does not use standard PCI power-management through the
1156 * PCI config space. Instead this driver directly tells the P-Unit to
1157 * disable the ISP over the IOSF. The standard PCI subsystem pm_ops will
1158 * try to access the config space before (resume) / after (suspend) this
1159 * driver has turned the ISP on / off, resulting in the following errors:
1160 *
1161 * "Unable to change power state from D0 to D3hot, device inaccessible"
1162 * "Unable to change power state from D3cold to D0, device inaccessible"
1163 *
1164 * To avoid these errors override the pm_domain so that all the PCI
1165 * subsys suspend / resume handling is skipped.
1166 */
1167 isp->pm_domain.ops.runtime_suspend = atomisp_power_off;
1168 isp->pm_domain.ops.runtime_resume = atomisp_power_on;
1169 isp->pm_domain.ops.suspend = atomisp_suspend;
1170 isp->pm_domain.ops.resume = atomisp_resume;
1171
1172 cpu_latency_qos_add_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
1173 dev_pm_domain_set(isp->dev, &isp->pm_domain);
1174
1175 pm_runtime_allow(isp->dev);
1176 pm_runtime_put_sync_suspend(isp->dev);
1177 }
1178
atomisp_pm_uninit(struct atomisp_device * isp)1179 static void atomisp_pm_uninit(struct atomisp_device *isp)
1180 {
1181 pm_runtime_get_sync(isp->dev);
1182 pm_runtime_forbid(isp->dev);
1183 dev_pm_domain_set(isp->dev, NULL);
1184 cpu_latency_qos_remove_request(&isp->pm_qos);
1185 }
1186
1187 #define ATOM_ISP_PCI_BAR 0
1188
atomisp_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)1189 static int atomisp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1190 {
1191 struct atomisp_device *isp;
1192 unsigned int start;
1193 u32 val;
1194 int err;
1195
1196 /* Pointer to struct device. */
1197 atomisp_dev = &pdev->dev;
1198
1199 start = pci_resource_start(pdev, ATOM_ISP_PCI_BAR);
1200 dev_dbg(&pdev->dev, "start: 0x%x\n", start);
1201
1202 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL);
1203 if (!isp)
1204 return -ENOMEM;
1205
1206 isp->dev = &pdev->dev;
1207 isp->saved_regs.ispmmadr = start;
1208 isp->asd.isp = isp;
1209
1210 mutex_init(&isp->mutex);
1211 spin_lock_init(&isp->lock);
1212
1213 /* This is not a true PCI device on SoC, so the delay is not needed. */
1214 pdev->d3hot_delay = 0;
1215
1216 pci_set_drvdata(pdev, isp);
1217
1218 switch (id->device) {
1219 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1220 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1221 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1222 isp->media_dev.hw_revision =
1223 (ATOMISP_HW_REVISION_ISP2400
1224 << ATOMISP_HW_REVISION_SHIFT) |
1225 ATOMISP_HW_STEPPING_B0;
1226
1227 switch (id->device) {
1228 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1229 isp->dfs = &dfs_config_merr_1179;
1230 break;
1231 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1232 isp->dfs = &dfs_config_merr_117a;
1233
1234 break;
1235 default:
1236 isp->dfs = &dfs_config_merr;
1237 break;
1238 }
1239 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1240 break;
1241 case ATOMISP_PCI_DEVICE_SOC_BYT:
1242 isp->media_dev.hw_revision =
1243 (ATOMISP_HW_REVISION_ISP2400
1244 << ATOMISP_HW_REVISION_SHIFT) |
1245 ATOMISP_HW_STEPPING_B0;
1246
1247 /*
1248 * Note: some Intel-based tablets with Android use a different
1249 * DFS table. Based on the comments at the Yocto Aero meta
1250 * version of this driver (at the ssid.h header), they're
1251 * identified via a "spid" var:
1252 *
1253 * androidboot.spid=vend:cust:manu:plat:prod:hard
1254 *
1255 * As we don't have this upstream, nor we know enough details
1256 * to use a DMI or PCI match table, the old code was just
1257 * removed, but let's keep a note here as a reminder that,
1258 * for certain devices, we may need to limit the max DFS
1259 * frequency to be below certain values, adjusting the
1260 * resolution accordingly.
1261 */
1262 isp->dfs = &dfs_config_byt;
1263
1264 /*
1265 * HPLL frequency is known to be device-specific, but we don't
1266 * have specs yet for exactly how it varies. Default to
1267 * BYT-CR but let provisioning set it via EFI variable
1268 */
1269 isp->hpll_freq = gmin_get_var_int(&pdev->dev, false, "HpllFreq", HPLL_FREQ_2000MHZ);
1270
1271 /*
1272 * for BYT/CHT we are put isp into D3cold to avoid pci registers access
1273 * in power off. Set d3cold_delay to 0 since default 100ms is not
1274 * necessary.
1275 */
1276 pdev->d3cold_delay = 0;
1277 break;
1278 case ATOMISP_PCI_DEVICE_SOC_ANN:
1279 isp->media_dev.hw_revision = (ATOMISP_HW_REVISION_ISP2401
1280 << ATOMISP_HW_REVISION_SHIFT);
1281 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1282 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1283 isp->dfs = &dfs_config_merr;
1284 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1285 break;
1286 case ATOMISP_PCI_DEVICE_SOC_CHT:
1287 isp->media_dev.hw_revision = (ATOMISP_HW_REVISION_ISP2401
1288 << ATOMISP_HW_REVISION_SHIFT);
1289 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1290 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1291
1292 isp->dfs = &dfs_config_cht;
1293 pdev->d3cold_delay = 0;
1294
1295 iosf_mbi_read(BT_MBI_UNIT_CCK, MBI_REG_READ, CCK_FUSE_REG_0, &val);
1296 switch (val & CCK_FUSE_HPLL_FREQ_MASK) {
1297 case 0x00:
1298 isp->hpll_freq = HPLL_FREQ_800MHZ;
1299 break;
1300 case 0x01:
1301 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1302 break;
1303 case 0x02:
1304 isp->hpll_freq = HPLL_FREQ_2000MHZ;
1305 break;
1306 default:
1307 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1308 dev_warn(&pdev->dev, "read HPLL from cck failed. Default to 1600 MHz.\n");
1309 }
1310 break;
1311 default:
1312 dev_err(&pdev->dev, "un-supported IUNIT device\n");
1313 return -ENODEV;
1314 }
1315
1316 if (pdev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) {
1317 dev_err(&pdev->dev, "revision %d is not supported\n", pdev->revision);
1318 return -ENODEV;
1319 }
1320
1321 dev_info(&pdev->dev, "ISP HPLL frequency base = %d MHz\n", isp->hpll_freq);
1322
1323 isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY;
1324
1325 /* Load isp firmware from user space */
1326 isp->firmware = atomisp_load_firmware(isp);
1327 if (!isp->firmware) {
1328 /* No firmware continue in pm-only mode for S0i3 support */
1329 dev_info(&pdev->dev, "Continuing in power-management only mode\n");
1330 isp->pm_only = true;
1331 atomisp_pm_init(isp);
1332 return 0;
1333 }
1334
1335 err = sh_css_check_firmware_version(isp->dev, isp->firmware->data);
1336 if (err) {
1337 dev_dbg(&pdev->dev, "Firmware version check failed\n");
1338 goto error_release_firmware;
1339 }
1340
1341 err = pcim_enable_device(pdev);
1342 if (err) {
1343 dev_err(&pdev->dev, "Failed to enable ISP PCI device (%d)\n", err);
1344 goto error_release_firmware;
1345 }
1346
1347 err = pcim_iomap_regions(pdev, BIT(ATOM_ISP_PCI_BAR), pci_name(pdev));
1348 if (err) {
1349 dev_err(&pdev->dev, "Failed to I/O memory remapping (%d)\n", err);
1350 goto error_release_firmware;
1351 }
1352
1353 isp->base = pcim_iomap_table(pdev)[ATOM_ISP_PCI_BAR];
1354
1355 pci_set_master(pdev);
1356
1357 err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1358 if (err < 0) {
1359 dev_err(&pdev->dev, "Failed to enable msi (%d)\n", err);
1360 goto error_release_firmware;
1361 }
1362
1363 atomisp_msi_irq_init(isp);
1364
1365 /*
1366 * for MRFLD, Software/firmware needs to write a 1 to bit 0 of
1367 * the register at CSI_RECEIVER_SELECTION_REG to enable SH CSI
1368 * backend write 0 will enable Arasan CSI backend, which has
1369 * bugs(like sighting:4567697 and 4567699) and will be removed
1370 * in B0
1371 */
1372 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
1373
1374 switch (id->device) {
1375 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1376 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1377 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1378 /*
1379 * Workaround for imbalance data eye issue which is observed
1380 * on TNG B0.
1381 */
1382 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, &val);
1383 val &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1384 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1385 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT));
1386 val |= (MRFLD_PCI_CSI1_HSRXCLKTRIM << MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1387 (MRFLD_PCI_CSI2_HSRXCLKTRIM << MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1388 (MRFLD_PCI_CSI3_HSRXCLKTRIM << MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT);
1389 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, val);
1390 break;
1391 default:
1392 break;
1393 }
1394
1395 err = atomisp_initialize_modules(isp);
1396 if (err < 0) {
1397 dev_err(&pdev->dev, "atomisp_initialize_modules (%d)\n", err);
1398 goto error_irq_uninit;
1399 }
1400
1401 err = atomisp_register_entities(isp);
1402 if (err < 0) {
1403 dev_err(&pdev->dev, "atomisp_register_entities failed (%d)\n", err);
1404 goto error_uninitialize_modules;
1405 }
1406
1407 INIT_WORK(&isp->assert_recovery_work, atomisp_assert_recovery_work);
1408
1409 /* save the iunit context only once after all the values are init'ed. */
1410 atomisp_save_iunit_reg(isp);
1411
1412 /* Init ISP memory management */
1413 hmm_init();
1414
1415 err = devm_request_threaded_irq(&pdev->dev, pdev->irq,
1416 atomisp_isr, atomisp_isr_thread,
1417 IRQF_SHARED, "isp_irq", isp);
1418 if (err) {
1419 dev_err(&pdev->dev, "Failed to request irq (%d)\n", err);
1420 goto error_unregister_entities;
1421 }
1422
1423 /* Load firmware into ISP memory */
1424 err = atomisp_css_load_firmware(isp);
1425 if (err) {
1426 dev_err(&pdev->dev, "Failed to init css.\n");
1427 goto error_free_irq;
1428 }
1429 /* Clear FW image from memory */
1430 release_firmware(isp->firmware);
1431 isp->firmware = NULL;
1432 isp->css_env.isp_css_fw.data = NULL;
1433
1434 atomisp_pm_init(isp);
1435
1436 err = v4l2_async_nf_register(&isp->notifier);
1437 if (err) {
1438 dev_err(isp->dev, "failed to register async notifier : %d\n", err);
1439 goto error_unload_firmware;
1440 }
1441
1442 return 0;
1443
1444 error_unload_firmware:
1445 atomisp_pm_uninit(isp);
1446 ia_css_unload_firmware();
1447 error_free_irq:
1448 devm_free_irq(&pdev->dev, pdev->irq, isp);
1449 error_unregister_entities:
1450 hmm_cleanup();
1451 atomisp_unregister_entities(isp);
1452 error_uninitialize_modules:
1453 atomisp_uninitialize_modules(isp);
1454 error_irq_uninit:
1455 atomisp_msi_irq_uninit(isp);
1456 pci_free_irq_vectors(pdev);
1457 error_release_firmware:
1458 release_firmware(isp->firmware);
1459 return err;
1460 }
1461
atomisp_pci_remove(struct pci_dev * pdev)1462 static void atomisp_pci_remove(struct pci_dev *pdev)
1463 {
1464 struct atomisp_device *isp = pci_get_drvdata(pdev);
1465
1466 atomisp_pm_uninit(isp);
1467
1468 if (isp->pm_only)
1469 return;
1470
1471 /* Undo ia_css_init() from atomisp_power_on() */
1472 atomisp_css_uninit(isp);
1473 ia_css_unload_firmware();
1474 devm_free_irq(&pdev->dev, pdev->irq, isp);
1475 hmm_cleanup();
1476
1477 atomisp_unregister_entities(isp);
1478 atomisp_uninitialize_modules(isp);
1479 atomisp_msi_irq_uninit(isp);
1480 pci_free_irq_vectors(pdev);
1481 }
1482
1483 static const struct pci_device_id atomisp_pci_tbl[] = {
1484 /* Merrifield */
1485 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD)},
1486 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_1179)},
1487 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_117A)},
1488 /* Baytrail */
1489 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_BYT)},
1490 /* Anniedale (Merrifield+ / Moorefield) */
1491 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_ANN)},
1492 /* Cherrytrail */
1493 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_CHT)},
1494 {0,}
1495 };
1496 MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl);
1497
1498 static struct pci_driver atomisp_pci_driver = {
1499 .name = "atomisp-isp2",
1500 .id_table = atomisp_pci_tbl,
1501 .probe = atomisp_pci_probe,
1502 .remove = atomisp_pci_remove,
1503 };
1504
1505 module_pci_driver(atomisp_pci_driver);
1506
1507 MODULE_AUTHOR("Wen Wang <wen.w.wang@intel.com>");
1508 MODULE_AUTHOR("Xiaolin Zhang <xiaolin.zhang@intel.com>");
1509 MODULE_LICENSE("GPL");
1510 MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver");
1511 MODULE_IMPORT_NS("INTEL_IPU_BRIDGE");
1512 MODULE_IMPORT_NS("INTEL_INT3472_DISCRETE");
1513