1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Cryptographic API.
4 *
5 * Support for ATMEL SHA1/SHA256 HW acceleration.
6 *
7 * Copyright (c) 2012 Eukréa Electromatique - ATMEL
8 * Author: Nicolas Royer <nicolas@eukrea.com>
9 *
10 * Some ideas are from omap-sham.c drivers.
11 */
12
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/slab.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
19 #include <linux/io.h>
20 #include <linux/hw_random.h>
21 #include <linux/platform_device.h>
22
23 #include <linux/device.h>
24 #include <linux/dmaengine.h>
25 #include <linux/init.h>
26 #include <linux/errno.h>
27 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/delay.h>
33 #include <linux/crypto.h>
34 #include <crypto/scatterwalk.h>
35 #include <crypto/algapi.h>
36 #include <crypto/sha1.h>
37 #include <crypto/sha2.h>
38 #include <crypto/hash.h>
39 #include <crypto/internal/hash.h>
40 #include "atmel-sha-regs.h"
41 #include "atmel-authenc.h"
42
43 #define ATMEL_SHA_PRIORITY 300
44
45 /* SHA flags */
46 #define SHA_FLAGS_BUSY BIT(0)
47 #define SHA_FLAGS_FINAL BIT(1)
48 #define SHA_FLAGS_DMA_ACTIVE BIT(2)
49 #define SHA_FLAGS_OUTPUT_READY BIT(3)
50 #define SHA_FLAGS_INIT BIT(4)
51 #define SHA_FLAGS_CPU BIT(5)
52 #define SHA_FLAGS_DMA_READY BIT(6)
53 #define SHA_FLAGS_DUMP_REG BIT(7)
54
55 /* bits[11:8] are reserved. */
56
57 #define SHA_FLAGS_FINUP BIT(16)
58 #define SHA_FLAGS_SG BIT(17)
59 #define SHA_FLAGS_ERROR BIT(23)
60 #define SHA_FLAGS_PAD BIT(24)
61 #define SHA_FLAGS_RESTORE BIT(25)
62 #define SHA_FLAGS_IDATAR0 BIT(26)
63 #define SHA_FLAGS_WAIT_DATARDY BIT(27)
64
65 #define SHA_OP_INIT 0
66 #define SHA_OP_UPDATE 1
67 #define SHA_OP_FINAL 2
68 #define SHA_OP_DIGEST 3
69
70 #define SHA_BUFFER_LEN (PAGE_SIZE / 16)
71
72 #define ATMEL_SHA_DMA_THRESHOLD 56
73
74 struct atmel_sha_caps {
75 bool has_dma;
76 bool has_dualbuff;
77 bool has_sha224;
78 bool has_sha_384_512;
79 bool has_uihv;
80 bool has_hmac;
81 };
82
83 struct atmel_sha_dev;
84
85 /*
86 * .statesize = sizeof(struct atmel_sha_reqctx) must be <= PAGE_SIZE / 8 as
87 * tested by the ahash_prepare_alg() function.
88 */
89 struct atmel_sha_reqctx {
90 struct atmel_sha_dev *dd;
91 unsigned long flags;
92 unsigned long op;
93
94 u8 digest[SHA512_DIGEST_SIZE] __aligned(sizeof(u32));
95 u64 digcnt[2];
96 size_t bufcnt;
97 size_t buflen;
98 dma_addr_t dma_addr;
99
100 /* walk state */
101 struct scatterlist *sg;
102 unsigned int offset; /* offset in current sg */
103 unsigned int total; /* total request */
104
105 size_t block_size;
106 size_t hash_size;
107
108 u8 buffer[SHA_BUFFER_LEN + SHA512_BLOCK_SIZE] __aligned(sizeof(u32));
109 };
110
111 typedef int (*atmel_sha_fn_t)(struct atmel_sha_dev *);
112
113 struct atmel_sha_ctx {
114 struct atmel_sha_dev *dd;
115 atmel_sha_fn_t start;
116
117 unsigned long flags;
118 };
119
120 #define ATMEL_SHA_QUEUE_LENGTH 50
121
122 struct atmel_sha_dma {
123 struct dma_chan *chan;
124 struct dma_slave_config dma_conf;
125 struct scatterlist *sg;
126 int nents;
127 unsigned int last_sg_length;
128 };
129
130 struct atmel_sha_dev {
131 struct list_head list;
132 unsigned long phys_base;
133 struct device *dev;
134 struct clk *iclk;
135 int irq;
136 void __iomem *io_base;
137
138 spinlock_t lock;
139 struct tasklet_struct done_task;
140 struct tasklet_struct queue_task;
141
142 unsigned long flags;
143 struct crypto_queue queue;
144 struct ahash_request *req;
145 bool is_async;
146 bool force_complete;
147 atmel_sha_fn_t resume;
148 atmel_sha_fn_t cpu_transfer_complete;
149
150 struct atmel_sha_dma dma_lch_in;
151
152 struct atmel_sha_caps caps;
153
154 struct scatterlist tmp;
155
156 u32 hw_version;
157 };
158
159 struct atmel_sha_drv {
160 struct list_head dev_list;
161 spinlock_t lock;
162 };
163
164 static struct atmel_sha_drv atmel_sha = {
165 .dev_list = LIST_HEAD_INIT(atmel_sha.dev_list),
166 .lock = __SPIN_LOCK_UNLOCKED(atmel_sha.lock),
167 };
168
169 #ifdef VERBOSE_DEBUG
atmel_sha_reg_name(u32 offset,char * tmp,size_t sz,bool wr)170 static const char *atmel_sha_reg_name(u32 offset, char *tmp, size_t sz, bool wr)
171 {
172 switch (offset) {
173 case SHA_CR:
174 return "CR";
175
176 case SHA_MR:
177 return "MR";
178
179 case SHA_IER:
180 return "IER";
181
182 case SHA_IDR:
183 return "IDR";
184
185 case SHA_IMR:
186 return "IMR";
187
188 case SHA_ISR:
189 return "ISR";
190
191 case SHA_MSR:
192 return "MSR";
193
194 case SHA_BCR:
195 return "BCR";
196
197 case SHA_REG_DIN(0):
198 case SHA_REG_DIN(1):
199 case SHA_REG_DIN(2):
200 case SHA_REG_DIN(3):
201 case SHA_REG_DIN(4):
202 case SHA_REG_DIN(5):
203 case SHA_REG_DIN(6):
204 case SHA_REG_DIN(7):
205 case SHA_REG_DIN(8):
206 case SHA_REG_DIN(9):
207 case SHA_REG_DIN(10):
208 case SHA_REG_DIN(11):
209 case SHA_REG_DIN(12):
210 case SHA_REG_DIN(13):
211 case SHA_REG_DIN(14):
212 case SHA_REG_DIN(15):
213 snprintf(tmp, sz, "IDATAR[%u]", (offset - SHA_REG_DIN(0)) >> 2);
214 break;
215
216 case SHA_REG_DIGEST(0):
217 case SHA_REG_DIGEST(1):
218 case SHA_REG_DIGEST(2):
219 case SHA_REG_DIGEST(3):
220 case SHA_REG_DIGEST(4):
221 case SHA_REG_DIGEST(5):
222 case SHA_REG_DIGEST(6):
223 case SHA_REG_DIGEST(7):
224 case SHA_REG_DIGEST(8):
225 case SHA_REG_DIGEST(9):
226 case SHA_REG_DIGEST(10):
227 case SHA_REG_DIGEST(11):
228 case SHA_REG_DIGEST(12):
229 case SHA_REG_DIGEST(13):
230 case SHA_REG_DIGEST(14):
231 case SHA_REG_DIGEST(15):
232 if (wr)
233 snprintf(tmp, sz, "IDATAR[%u]",
234 16u + ((offset - SHA_REG_DIGEST(0)) >> 2));
235 else
236 snprintf(tmp, sz, "ODATAR[%u]",
237 (offset - SHA_REG_DIGEST(0)) >> 2);
238 break;
239
240 case SHA_HW_VERSION:
241 return "HWVER";
242
243 default:
244 snprintf(tmp, sz, "0x%02x", offset);
245 break;
246 }
247
248 return tmp;
249 }
250
251 #endif /* VERBOSE_DEBUG */
252
atmel_sha_read(struct atmel_sha_dev * dd,u32 offset)253 static inline u32 atmel_sha_read(struct atmel_sha_dev *dd, u32 offset)
254 {
255 u32 value = readl_relaxed(dd->io_base + offset);
256
257 #ifdef VERBOSE_DEBUG
258 if (dd->flags & SHA_FLAGS_DUMP_REG) {
259 char tmp[16];
260
261 dev_vdbg(dd->dev, "read 0x%08x from %s\n", value,
262 atmel_sha_reg_name(offset, tmp, sizeof(tmp), false));
263 }
264 #endif /* VERBOSE_DEBUG */
265
266 return value;
267 }
268
atmel_sha_write(struct atmel_sha_dev * dd,u32 offset,u32 value)269 static inline void atmel_sha_write(struct atmel_sha_dev *dd,
270 u32 offset, u32 value)
271 {
272 #ifdef VERBOSE_DEBUG
273 if (dd->flags & SHA_FLAGS_DUMP_REG) {
274 char tmp[16];
275
276 dev_vdbg(dd->dev, "write 0x%08x into %s\n", value,
277 atmel_sha_reg_name(offset, tmp, sizeof(tmp), true));
278 }
279 #endif /* VERBOSE_DEBUG */
280
281 writel_relaxed(value, dd->io_base + offset);
282 }
283
atmel_sha_complete(struct atmel_sha_dev * dd,int err)284 static inline int atmel_sha_complete(struct atmel_sha_dev *dd, int err)
285 {
286 struct ahash_request *req = dd->req;
287
288 dd->flags &= ~(SHA_FLAGS_BUSY | SHA_FLAGS_FINAL | SHA_FLAGS_CPU |
289 SHA_FLAGS_DMA_READY | SHA_FLAGS_OUTPUT_READY |
290 SHA_FLAGS_DUMP_REG);
291
292 clk_disable(dd->iclk);
293
294 if ((dd->is_async || dd->force_complete) && req->base.complete)
295 ahash_request_complete(req, err);
296
297 /* handle new request */
298 tasklet_schedule(&dd->queue_task);
299
300 return err;
301 }
302
atmel_sha_append_sg(struct atmel_sha_reqctx * ctx)303 static size_t atmel_sha_append_sg(struct atmel_sha_reqctx *ctx)
304 {
305 size_t count;
306
307 while ((ctx->bufcnt < ctx->buflen) && ctx->total) {
308 count = min(ctx->sg->length - ctx->offset, ctx->total);
309 count = min(count, ctx->buflen - ctx->bufcnt);
310
311 if (count <= 0) {
312 /*
313 * Check if count <= 0 because the buffer is full or
314 * because the sg length is 0. In the latest case,
315 * check if there is another sg in the list, a 0 length
316 * sg doesn't necessarily mean the end of the sg list.
317 */
318 if ((ctx->sg->length == 0) && !sg_is_last(ctx->sg)) {
319 ctx->sg = sg_next(ctx->sg);
320 continue;
321 } else {
322 break;
323 }
324 }
325
326 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, ctx->sg,
327 ctx->offset, count, 0);
328
329 ctx->bufcnt += count;
330 ctx->offset += count;
331 ctx->total -= count;
332
333 if (ctx->offset == ctx->sg->length) {
334 ctx->sg = sg_next(ctx->sg);
335 if (ctx->sg)
336 ctx->offset = 0;
337 else
338 ctx->total = 0;
339 }
340 }
341
342 return 0;
343 }
344
345 /*
346 * The purpose of this padding is to ensure that the padded message is a
347 * multiple of 512 bits (SHA1/SHA224/SHA256) or 1024 bits (SHA384/SHA512).
348 * The bit "1" is appended at the end of the message followed by
349 * "padlen-1" zero bits. Then a 64 bits block (SHA1/SHA224/SHA256) or
350 * 128 bits block (SHA384/SHA512) equals to the message length in bits
351 * is appended.
352 *
353 * For SHA1/SHA224/SHA256, padlen is calculated as followed:
354 * - if message length < 56 bytes then padlen = 56 - message length
355 * - else padlen = 64 + 56 - message length
356 *
357 * For SHA384/SHA512, padlen is calculated as followed:
358 * - if message length < 112 bytes then padlen = 112 - message length
359 * - else padlen = 128 + 112 - message length
360 */
atmel_sha_fill_padding(struct atmel_sha_reqctx * ctx,int length)361 static void atmel_sha_fill_padding(struct atmel_sha_reqctx *ctx, int length)
362 {
363 unsigned int index, padlen;
364 __be64 bits[2];
365 u64 size[2];
366
367 size[0] = ctx->digcnt[0];
368 size[1] = ctx->digcnt[1];
369
370 size[0] += ctx->bufcnt;
371 if (size[0] < ctx->bufcnt)
372 size[1]++;
373
374 size[0] += length;
375 if (size[0] < length)
376 size[1]++;
377
378 bits[1] = cpu_to_be64(size[0] << 3);
379 bits[0] = cpu_to_be64(size[1] << 3 | size[0] >> 61);
380
381 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
382 case SHA_FLAGS_SHA384:
383 case SHA_FLAGS_SHA512:
384 index = ctx->bufcnt & 0x7f;
385 padlen = (index < 112) ? (112 - index) : ((128+112) - index);
386 *(ctx->buffer + ctx->bufcnt) = 0x80;
387 memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1);
388 memcpy(ctx->buffer + ctx->bufcnt + padlen, bits, 16);
389 ctx->bufcnt += padlen + 16;
390 ctx->flags |= SHA_FLAGS_PAD;
391 break;
392
393 default:
394 index = ctx->bufcnt & 0x3f;
395 padlen = (index < 56) ? (56 - index) : ((64+56) - index);
396 *(ctx->buffer + ctx->bufcnt) = 0x80;
397 memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1);
398 memcpy(ctx->buffer + ctx->bufcnt + padlen, &bits[1], 8);
399 ctx->bufcnt += padlen + 8;
400 ctx->flags |= SHA_FLAGS_PAD;
401 break;
402 }
403 }
404
atmel_sha_find_dev(struct atmel_sha_ctx * tctx)405 static struct atmel_sha_dev *atmel_sha_find_dev(struct atmel_sha_ctx *tctx)
406 {
407 struct atmel_sha_dev *dd;
408
409 spin_lock_bh(&atmel_sha.lock);
410 if (!tctx->dd)
411 tctx->dd = list_first_entry_or_null(&atmel_sha.dev_list,
412 struct atmel_sha_dev, list);
413 dd = tctx->dd;
414 spin_unlock_bh(&atmel_sha.lock);
415
416 return dd;
417 }
418
atmel_sha_init(struct ahash_request * req)419 static int atmel_sha_init(struct ahash_request *req)
420 {
421 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
422 struct atmel_sha_ctx *tctx = crypto_ahash_ctx(tfm);
423 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
424 struct atmel_sha_dev *dd = atmel_sha_find_dev(tctx);
425
426 ctx->dd = dd;
427
428 ctx->flags = 0;
429
430 dev_dbg(dd->dev, "init: digest size: %u\n",
431 crypto_ahash_digestsize(tfm));
432
433 switch (crypto_ahash_digestsize(tfm)) {
434 case SHA1_DIGEST_SIZE:
435 ctx->flags |= SHA_FLAGS_SHA1;
436 ctx->block_size = SHA1_BLOCK_SIZE;
437 break;
438 case SHA224_DIGEST_SIZE:
439 ctx->flags |= SHA_FLAGS_SHA224;
440 ctx->block_size = SHA224_BLOCK_SIZE;
441 break;
442 case SHA256_DIGEST_SIZE:
443 ctx->flags |= SHA_FLAGS_SHA256;
444 ctx->block_size = SHA256_BLOCK_SIZE;
445 break;
446 case SHA384_DIGEST_SIZE:
447 ctx->flags |= SHA_FLAGS_SHA384;
448 ctx->block_size = SHA384_BLOCK_SIZE;
449 break;
450 case SHA512_DIGEST_SIZE:
451 ctx->flags |= SHA_FLAGS_SHA512;
452 ctx->block_size = SHA512_BLOCK_SIZE;
453 break;
454 default:
455 return -EINVAL;
456 }
457
458 ctx->bufcnt = 0;
459 ctx->digcnt[0] = 0;
460 ctx->digcnt[1] = 0;
461 ctx->buflen = SHA_BUFFER_LEN;
462
463 return 0;
464 }
465
atmel_sha_write_ctrl(struct atmel_sha_dev * dd,int dma)466 static void atmel_sha_write_ctrl(struct atmel_sha_dev *dd, int dma)
467 {
468 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
469 u32 valmr = SHA_MR_MODE_AUTO;
470 unsigned int i, hashsize = 0;
471
472 if (likely(dma)) {
473 if (!dd->caps.has_dma)
474 atmel_sha_write(dd, SHA_IER, SHA_INT_TXBUFE);
475 valmr = SHA_MR_MODE_PDC;
476 if (dd->caps.has_dualbuff)
477 valmr |= SHA_MR_DUALBUFF;
478 } else {
479 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
480 }
481
482 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
483 case SHA_FLAGS_SHA1:
484 valmr |= SHA_MR_ALGO_SHA1;
485 hashsize = SHA1_DIGEST_SIZE;
486 break;
487
488 case SHA_FLAGS_SHA224:
489 valmr |= SHA_MR_ALGO_SHA224;
490 hashsize = SHA256_DIGEST_SIZE;
491 break;
492
493 case SHA_FLAGS_SHA256:
494 valmr |= SHA_MR_ALGO_SHA256;
495 hashsize = SHA256_DIGEST_SIZE;
496 break;
497
498 case SHA_FLAGS_SHA384:
499 valmr |= SHA_MR_ALGO_SHA384;
500 hashsize = SHA512_DIGEST_SIZE;
501 break;
502
503 case SHA_FLAGS_SHA512:
504 valmr |= SHA_MR_ALGO_SHA512;
505 hashsize = SHA512_DIGEST_SIZE;
506 break;
507
508 default:
509 break;
510 }
511
512 /* Setting CR_FIRST only for the first iteration */
513 if (!(ctx->digcnt[0] || ctx->digcnt[1])) {
514 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST);
515 } else if (dd->caps.has_uihv && (ctx->flags & SHA_FLAGS_RESTORE)) {
516 const u32 *hash = (const u32 *)ctx->digest;
517
518 /*
519 * Restore the hardware context: update the User Initialize
520 * Hash Value (UIHV) with the value saved when the latest
521 * 'update' operation completed on this very same crypto
522 * request.
523 */
524 ctx->flags &= ~SHA_FLAGS_RESTORE;
525 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIHV);
526 for (i = 0; i < hashsize / sizeof(u32); ++i)
527 atmel_sha_write(dd, SHA_REG_DIN(i), hash[i]);
528 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST);
529 valmr |= SHA_MR_UIHV;
530 }
531 /*
532 * WARNING: If the UIHV feature is not available, the hardware CANNOT
533 * process concurrent requests: the internal registers used to store
534 * the hash/digest are still set to the partial digest output values
535 * computed during the latest round.
536 */
537
538 atmel_sha_write(dd, SHA_MR, valmr);
539 }
540
atmel_sha_wait_for_data_ready(struct atmel_sha_dev * dd,atmel_sha_fn_t resume)541 static inline int atmel_sha_wait_for_data_ready(struct atmel_sha_dev *dd,
542 atmel_sha_fn_t resume)
543 {
544 u32 isr = atmel_sha_read(dd, SHA_ISR);
545
546 if (unlikely(isr & SHA_INT_DATARDY))
547 return resume(dd);
548
549 dd->resume = resume;
550 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
551 return -EINPROGRESS;
552 }
553
atmel_sha_xmit_cpu(struct atmel_sha_dev * dd,const u8 * buf,size_t length,int final)554 static int atmel_sha_xmit_cpu(struct atmel_sha_dev *dd, const u8 *buf,
555 size_t length, int final)
556 {
557 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
558 int count, len32;
559 const u32 *buffer = (const u32 *)buf;
560
561 dev_dbg(dd->dev, "xmit_cpu: digcnt: 0x%llx 0x%llx, length: %zd, final: %d\n",
562 ctx->digcnt[1], ctx->digcnt[0], length, final);
563
564 atmel_sha_write_ctrl(dd, 0);
565
566 /* should be non-zero before next lines to disable clocks later */
567 ctx->digcnt[0] += length;
568 if (ctx->digcnt[0] < length)
569 ctx->digcnt[1]++;
570
571 if (final)
572 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
573
574 len32 = DIV_ROUND_UP(length, sizeof(u32));
575
576 dd->flags |= SHA_FLAGS_CPU;
577
578 for (count = 0; count < len32; count++)
579 atmel_sha_write(dd, SHA_REG_DIN(count), buffer[count]);
580
581 return -EINPROGRESS;
582 }
583
atmel_sha_xmit_pdc(struct atmel_sha_dev * dd,dma_addr_t dma_addr1,size_t length1,dma_addr_t dma_addr2,size_t length2,int final)584 static int atmel_sha_xmit_pdc(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
585 size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
586 {
587 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
588 int len32;
589
590 dev_dbg(dd->dev, "xmit_pdc: digcnt: 0x%llx 0x%llx, length: %zd, final: %d\n",
591 ctx->digcnt[1], ctx->digcnt[0], length1, final);
592
593 len32 = DIV_ROUND_UP(length1, sizeof(u32));
594 atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTDIS);
595 atmel_sha_write(dd, SHA_TPR, dma_addr1);
596 atmel_sha_write(dd, SHA_TCR, len32);
597
598 len32 = DIV_ROUND_UP(length2, sizeof(u32));
599 atmel_sha_write(dd, SHA_TNPR, dma_addr2);
600 atmel_sha_write(dd, SHA_TNCR, len32);
601
602 atmel_sha_write_ctrl(dd, 1);
603
604 /* should be non-zero before next lines to disable clocks later */
605 ctx->digcnt[0] += length1;
606 if (ctx->digcnt[0] < length1)
607 ctx->digcnt[1]++;
608
609 if (final)
610 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
611
612 dd->flags |= SHA_FLAGS_DMA_ACTIVE;
613
614 /* Start DMA transfer */
615 atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTEN);
616
617 return -EINPROGRESS;
618 }
619
atmel_sha_dma_callback(void * data)620 static void atmel_sha_dma_callback(void *data)
621 {
622 struct atmel_sha_dev *dd = data;
623
624 dd->is_async = true;
625
626 /* dma_lch_in - completed - wait DATRDY */
627 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
628 }
629
atmel_sha_xmit_dma(struct atmel_sha_dev * dd,dma_addr_t dma_addr1,size_t length1,dma_addr_t dma_addr2,size_t length2,int final)630 static int atmel_sha_xmit_dma(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
631 size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
632 {
633 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
634 struct dma_async_tx_descriptor *in_desc;
635 struct scatterlist sg[2];
636
637 dev_dbg(dd->dev, "xmit_dma: digcnt: 0x%llx 0x%llx, length: %zd, final: %d\n",
638 ctx->digcnt[1], ctx->digcnt[0], length1, final);
639
640 dd->dma_lch_in.dma_conf.src_maxburst = 16;
641 dd->dma_lch_in.dma_conf.dst_maxburst = 16;
642
643 dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf);
644
645 if (length2) {
646 sg_init_table(sg, 2);
647 sg_dma_address(&sg[0]) = dma_addr1;
648 sg_dma_len(&sg[0]) = length1;
649 sg_dma_address(&sg[1]) = dma_addr2;
650 sg_dma_len(&sg[1]) = length2;
651 in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 2,
652 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
653 } else {
654 sg_init_table(sg, 1);
655 sg_dma_address(&sg[0]) = dma_addr1;
656 sg_dma_len(&sg[0]) = length1;
657 in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 1,
658 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
659 }
660 if (!in_desc)
661 return atmel_sha_complete(dd, -EINVAL);
662
663 in_desc->callback = atmel_sha_dma_callback;
664 in_desc->callback_param = dd;
665
666 atmel_sha_write_ctrl(dd, 1);
667
668 /* should be non-zero before next lines to disable clocks later */
669 ctx->digcnt[0] += length1;
670 if (ctx->digcnt[0] < length1)
671 ctx->digcnt[1]++;
672
673 if (final)
674 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
675
676 dd->flags |= SHA_FLAGS_DMA_ACTIVE;
677
678 /* Start DMA transfer */
679 dmaengine_submit(in_desc);
680 dma_async_issue_pending(dd->dma_lch_in.chan);
681
682 return -EINPROGRESS;
683 }
684
atmel_sha_xmit_start(struct atmel_sha_dev * dd,dma_addr_t dma_addr1,size_t length1,dma_addr_t dma_addr2,size_t length2,int final)685 static int atmel_sha_xmit_start(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
686 size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
687 {
688 if (dd->caps.has_dma)
689 return atmel_sha_xmit_dma(dd, dma_addr1, length1,
690 dma_addr2, length2, final);
691 else
692 return atmel_sha_xmit_pdc(dd, dma_addr1, length1,
693 dma_addr2, length2, final);
694 }
695
atmel_sha_update_cpu(struct atmel_sha_dev * dd)696 static int atmel_sha_update_cpu(struct atmel_sha_dev *dd)
697 {
698 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
699 int bufcnt;
700
701 atmel_sha_append_sg(ctx);
702 atmel_sha_fill_padding(ctx, 0);
703 bufcnt = ctx->bufcnt;
704 ctx->bufcnt = 0;
705
706 return atmel_sha_xmit_cpu(dd, ctx->buffer, bufcnt, 1);
707 }
708
atmel_sha_xmit_dma_map(struct atmel_sha_dev * dd,struct atmel_sha_reqctx * ctx,size_t length,int final)709 static int atmel_sha_xmit_dma_map(struct atmel_sha_dev *dd,
710 struct atmel_sha_reqctx *ctx,
711 size_t length, int final)
712 {
713 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer,
714 ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
715 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
716 dev_err(dd->dev, "dma %zu bytes error\n", ctx->buflen +
717 ctx->block_size);
718 return atmel_sha_complete(dd, -EINVAL);
719 }
720
721 ctx->flags &= ~SHA_FLAGS_SG;
722
723 /* next call does not fail... so no unmap in the case of error */
724 return atmel_sha_xmit_start(dd, ctx->dma_addr, length, 0, 0, final);
725 }
726
atmel_sha_update_dma_slow(struct atmel_sha_dev * dd)727 static int atmel_sha_update_dma_slow(struct atmel_sha_dev *dd)
728 {
729 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
730 unsigned int final;
731 size_t count;
732
733 atmel_sha_append_sg(ctx);
734
735 final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total;
736
737 dev_dbg(dd->dev, "slow: bufcnt: %zu, digcnt: 0x%llx 0x%llx, final: %d\n",
738 ctx->bufcnt, ctx->digcnt[1], ctx->digcnt[0], final);
739
740 if (final)
741 atmel_sha_fill_padding(ctx, 0);
742
743 if (final || (ctx->bufcnt == ctx->buflen)) {
744 count = ctx->bufcnt;
745 ctx->bufcnt = 0;
746 return atmel_sha_xmit_dma_map(dd, ctx, count, final);
747 }
748
749 return 0;
750 }
751
atmel_sha_update_dma_start(struct atmel_sha_dev * dd)752 static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd)
753 {
754 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
755 unsigned int length, final, tail;
756 struct scatterlist *sg;
757 unsigned int count;
758
759 if (!ctx->total)
760 return 0;
761
762 if (ctx->bufcnt || ctx->offset)
763 return atmel_sha_update_dma_slow(dd);
764
765 dev_dbg(dd->dev, "fast: digcnt: 0x%llx 0x%llx, bufcnt: %zd, total: %u\n",
766 ctx->digcnt[1], ctx->digcnt[0], ctx->bufcnt, ctx->total);
767
768 sg = ctx->sg;
769
770 if (!IS_ALIGNED(sg->offset, sizeof(u32)))
771 return atmel_sha_update_dma_slow(dd);
772
773 if (!sg_is_last(sg) && !IS_ALIGNED(sg->length, ctx->block_size))
774 /* size is not ctx->block_size aligned */
775 return atmel_sha_update_dma_slow(dd);
776
777 length = min(ctx->total, sg->length);
778
779 if (sg_is_last(sg)) {
780 if (!(ctx->flags & SHA_FLAGS_FINUP)) {
781 /* not last sg must be ctx->block_size aligned */
782 tail = length & (ctx->block_size - 1);
783 length -= tail;
784 }
785 }
786
787 ctx->total -= length;
788 ctx->offset = length; /* offset where to start slow */
789
790 final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total;
791
792 /* Add padding */
793 if (final) {
794 tail = length & (ctx->block_size - 1);
795 length -= tail;
796 ctx->total += tail;
797 ctx->offset = length; /* offset where to start slow */
798
799 sg = ctx->sg;
800 atmel_sha_append_sg(ctx);
801
802 atmel_sha_fill_padding(ctx, length);
803
804 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer,
805 ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
806 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
807 dev_err(dd->dev, "dma %zu bytes error\n",
808 ctx->buflen + ctx->block_size);
809 return atmel_sha_complete(dd, -EINVAL);
810 }
811
812 if (length == 0) {
813 ctx->flags &= ~SHA_FLAGS_SG;
814 count = ctx->bufcnt;
815 ctx->bufcnt = 0;
816 return atmel_sha_xmit_start(dd, ctx->dma_addr, count, 0,
817 0, final);
818 } else {
819 ctx->sg = sg;
820 if (!dma_map_sg(dd->dev, ctx->sg, 1,
821 DMA_TO_DEVICE)) {
822 dev_err(dd->dev, "dma_map_sg error\n");
823 return atmel_sha_complete(dd, -EINVAL);
824 }
825
826 ctx->flags |= SHA_FLAGS_SG;
827
828 count = ctx->bufcnt;
829 ctx->bufcnt = 0;
830 return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg),
831 length, ctx->dma_addr, count, final);
832 }
833 }
834
835 if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
836 dev_err(dd->dev, "dma_map_sg error\n");
837 return atmel_sha_complete(dd, -EINVAL);
838 }
839
840 ctx->flags |= SHA_FLAGS_SG;
841
842 /* next call does not fail... so no unmap in the case of error */
843 return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg), length, 0,
844 0, final);
845 }
846
atmel_sha_update_dma_stop(struct atmel_sha_dev * dd)847 static void atmel_sha_update_dma_stop(struct atmel_sha_dev *dd)
848 {
849 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
850
851 if (ctx->flags & SHA_FLAGS_SG) {
852 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
853 if (ctx->sg->length == ctx->offset) {
854 ctx->sg = sg_next(ctx->sg);
855 if (ctx->sg)
856 ctx->offset = 0;
857 }
858 if (ctx->flags & SHA_FLAGS_PAD) {
859 dma_unmap_single(dd->dev, ctx->dma_addr,
860 ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
861 }
862 } else {
863 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen +
864 ctx->block_size, DMA_TO_DEVICE);
865 }
866 }
867
atmel_sha_update_req(struct atmel_sha_dev * dd)868 static int atmel_sha_update_req(struct atmel_sha_dev *dd)
869 {
870 struct ahash_request *req = dd->req;
871 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
872 int err;
873
874 dev_dbg(dd->dev, "update_req: total: %u, digcnt: 0x%llx 0x%llx\n",
875 ctx->total, ctx->digcnt[1], ctx->digcnt[0]);
876
877 if (ctx->flags & SHA_FLAGS_CPU)
878 err = atmel_sha_update_cpu(dd);
879 else
880 err = atmel_sha_update_dma_start(dd);
881
882 /* wait for dma completion before can take more data */
883 dev_dbg(dd->dev, "update: err: %d, digcnt: 0x%llx 0%llx\n",
884 err, ctx->digcnt[1], ctx->digcnt[0]);
885
886 return err;
887 }
888
atmel_sha_final_req(struct atmel_sha_dev * dd)889 static int atmel_sha_final_req(struct atmel_sha_dev *dd)
890 {
891 struct ahash_request *req = dd->req;
892 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
893 int err = 0;
894 int count;
895
896 if (ctx->bufcnt >= ATMEL_SHA_DMA_THRESHOLD) {
897 atmel_sha_fill_padding(ctx, 0);
898 count = ctx->bufcnt;
899 ctx->bufcnt = 0;
900 err = atmel_sha_xmit_dma_map(dd, ctx, count, 1);
901 }
902 /* faster to handle last block with cpu */
903 else {
904 atmel_sha_fill_padding(ctx, 0);
905 count = ctx->bufcnt;
906 ctx->bufcnt = 0;
907 err = atmel_sha_xmit_cpu(dd, ctx->buffer, count, 1);
908 }
909
910 dev_dbg(dd->dev, "final_req: err: %d\n", err);
911
912 return err;
913 }
914
atmel_sha_copy_hash(struct ahash_request * req)915 static void atmel_sha_copy_hash(struct ahash_request *req)
916 {
917 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
918 u32 *hash = (u32 *)ctx->digest;
919 unsigned int i, hashsize;
920
921 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
922 case SHA_FLAGS_SHA1:
923 hashsize = SHA1_DIGEST_SIZE;
924 break;
925
926 case SHA_FLAGS_SHA224:
927 case SHA_FLAGS_SHA256:
928 hashsize = SHA256_DIGEST_SIZE;
929 break;
930
931 case SHA_FLAGS_SHA384:
932 case SHA_FLAGS_SHA512:
933 hashsize = SHA512_DIGEST_SIZE;
934 break;
935
936 default:
937 /* Should not happen... */
938 return;
939 }
940
941 for (i = 0; i < hashsize / sizeof(u32); ++i)
942 hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
943 ctx->flags |= SHA_FLAGS_RESTORE;
944 }
945
atmel_sha_copy_ready_hash(struct ahash_request * req)946 static void atmel_sha_copy_ready_hash(struct ahash_request *req)
947 {
948 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
949
950 if (!req->result)
951 return;
952
953 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
954 default:
955 case SHA_FLAGS_SHA1:
956 memcpy(req->result, ctx->digest, SHA1_DIGEST_SIZE);
957 break;
958
959 case SHA_FLAGS_SHA224:
960 memcpy(req->result, ctx->digest, SHA224_DIGEST_SIZE);
961 break;
962
963 case SHA_FLAGS_SHA256:
964 memcpy(req->result, ctx->digest, SHA256_DIGEST_SIZE);
965 break;
966
967 case SHA_FLAGS_SHA384:
968 memcpy(req->result, ctx->digest, SHA384_DIGEST_SIZE);
969 break;
970
971 case SHA_FLAGS_SHA512:
972 memcpy(req->result, ctx->digest, SHA512_DIGEST_SIZE);
973 break;
974 }
975 }
976
atmel_sha_finish(struct ahash_request * req)977 static int atmel_sha_finish(struct ahash_request *req)
978 {
979 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
980 struct atmel_sha_dev *dd = ctx->dd;
981
982 if (ctx->digcnt[0] || ctx->digcnt[1])
983 atmel_sha_copy_ready_hash(req);
984
985 dev_dbg(dd->dev, "digcnt: 0x%llx 0x%llx, bufcnt: %zd\n", ctx->digcnt[1],
986 ctx->digcnt[0], ctx->bufcnt);
987
988 return 0;
989 }
990
atmel_sha_finish_req(struct ahash_request * req,int err)991 static void atmel_sha_finish_req(struct ahash_request *req, int err)
992 {
993 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
994 struct atmel_sha_dev *dd = ctx->dd;
995
996 if (!err) {
997 atmel_sha_copy_hash(req);
998 if (SHA_FLAGS_FINAL & dd->flags)
999 err = atmel_sha_finish(req);
1000 } else {
1001 ctx->flags |= SHA_FLAGS_ERROR;
1002 }
1003
1004 /* atomic operation is not needed here */
1005 (void)atmel_sha_complete(dd, err);
1006 }
1007
atmel_sha_hw_init(struct atmel_sha_dev * dd)1008 static int atmel_sha_hw_init(struct atmel_sha_dev *dd)
1009 {
1010 int err;
1011
1012 err = clk_enable(dd->iclk);
1013 if (err)
1014 return err;
1015
1016 if (!(SHA_FLAGS_INIT & dd->flags)) {
1017 atmel_sha_write(dd, SHA_CR, SHA_CR_SWRST);
1018 dd->flags |= SHA_FLAGS_INIT;
1019 }
1020
1021 return 0;
1022 }
1023
atmel_sha_get_version(struct atmel_sha_dev * dd)1024 static inline unsigned int atmel_sha_get_version(struct atmel_sha_dev *dd)
1025 {
1026 return atmel_sha_read(dd, SHA_HW_VERSION) & 0x00000fff;
1027 }
1028
atmel_sha_hw_version_init(struct atmel_sha_dev * dd)1029 static int atmel_sha_hw_version_init(struct atmel_sha_dev *dd)
1030 {
1031 int err;
1032
1033 err = atmel_sha_hw_init(dd);
1034 if (err)
1035 return err;
1036
1037 dd->hw_version = atmel_sha_get_version(dd);
1038
1039 dev_info(dd->dev,
1040 "version: 0x%x\n", dd->hw_version);
1041
1042 clk_disable(dd->iclk);
1043
1044 return 0;
1045 }
1046
atmel_sha_handle_queue(struct atmel_sha_dev * dd,struct ahash_request * req)1047 static int atmel_sha_handle_queue(struct atmel_sha_dev *dd,
1048 struct ahash_request *req)
1049 {
1050 struct crypto_async_request *async_req, *backlog;
1051 struct atmel_sha_ctx *ctx;
1052 unsigned long flags;
1053 bool start_async;
1054 int err = 0, ret = 0;
1055
1056 spin_lock_irqsave(&dd->lock, flags);
1057 if (req)
1058 ret = ahash_enqueue_request(&dd->queue, req);
1059
1060 if (SHA_FLAGS_BUSY & dd->flags) {
1061 spin_unlock_irqrestore(&dd->lock, flags);
1062 return ret;
1063 }
1064
1065 backlog = crypto_get_backlog(&dd->queue);
1066 async_req = crypto_dequeue_request(&dd->queue);
1067 if (async_req)
1068 dd->flags |= SHA_FLAGS_BUSY;
1069
1070 spin_unlock_irqrestore(&dd->lock, flags);
1071
1072 if (!async_req)
1073 return ret;
1074
1075 if (backlog)
1076 crypto_request_complete(backlog, -EINPROGRESS);
1077
1078 ctx = crypto_tfm_ctx(async_req->tfm);
1079
1080 dd->req = ahash_request_cast(async_req);
1081 start_async = (dd->req != req);
1082 dd->is_async = start_async;
1083 dd->force_complete = false;
1084
1085 /* WARNING: ctx->start() MAY change dd->is_async. */
1086 err = ctx->start(dd);
1087 return (start_async) ? ret : err;
1088 }
1089
1090 static int atmel_sha_done(struct atmel_sha_dev *dd);
1091
atmel_sha_start(struct atmel_sha_dev * dd)1092 static int atmel_sha_start(struct atmel_sha_dev *dd)
1093 {
1094 struct ahash_request *req = dd->req;
1095 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1096 int err;
1097
1098 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %u\n",
1099 ctx->op, req->nbytes);
1100
1101 err = atmel_sha_hw_init(dd);
1102 if (err)
1103 return atmel_sha_complete(dd, err);
1104
1105 /*
1106 * atmel_sha_update_req() and atmel_sha_final_req() can return either:
1107 * -EINPROGRESS: the hardware is busy and the SHA driver will resume
1108 * its job later in the done_task.
1109 * This is the main path.
1110 *
1111 * 0: the SHA driver can continue its job then release the hardware
1112 * later, if needed, with atmel_sha_finish_req().
1113 * This is the alternate path.
1114 *
1115 * < 0: an error has occurred so atmel_sha_complete(dd, err) has already
1116 * been called, hence the hardware has been released.
1117 * The SHA driver must stop its job without calling
1118 * atmel_sha_finish_req(), otherwise atmel_sha_complete() would be
1119 * called a second time.
1120 *
1121 * Please note that currently, atmel_sha_final_req() never returns 0.
1122 */
1123
1124 dd->resume = atmel_sha_done;
1125 if (ctx->op == SHA_OP_UPDATE) {
1126 err = atmel_sha_update_req(dd);
1127 if (!err && (ctx->flags & SHA_FLAGS_FINUP))
1128 /* no final() after finup() */
1129 err = atmel_sha_final_req(dd);
1130 } else if (ctx->op == SHA_OP_FINAL) {
1131 err = atmel_sha_final_req(dd);
1132 }
1133
1134 if (!err)
1135 /* done_task will not finish it, so do it here */
1136 atmel_sha_finish_req(req, err);
1137
1138 dev_dbg(dd->dev, "exit, err: %d\n", err);
1139
1140 return err;
1141 }
1142
atmel_sha_enqueue(struct ahash_request * req,unsigned int op)1143 static int atmel_sha_enqueue(struct ahash_request *req, unsigned int op)
1144 {
1145 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1146 struct atmel_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1147 struct atmel_sha_dev *dd = tctx->dd;
1148
1149 ctx->op = op;
1150
1151 return atmel_sha_handle_queue(dd, req);
1152 }
1153
atmel_sha_update(struct ahash_request * req)1154 static int atmel_sha_update(struct ahash_request *req)
1155 {
1156 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1157
1158 if (!req->nbytes)
1159 return 0;
1160
1161 ctx->total = req->nbytes;
1162 ctx->sg = req->src;
1163 ctx->offset = 0;
1164
1165 if (ctx->flags & SHA_FLAGS_FINUP) {
1166 if (ctx->bufcnt + ctx->total < ATMEL_SHA_DMA_THRESHOLD)
1167 /* faster to use CPU for short transfers */
1168 ctx->flags |= SHA_FLAGS_CPU;
1169 } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
1170 atmel_sha_append_sg(ctx);
1171 return 0;
1172 }
1173 return atmel_sha_enqueue(req, SHA_OP_UPDATE);
1174 }
1175
atmel_sha_final(struct ahash_request * req)1176 static int atmel_sha_final(struct ahash_request *req)
1177 {
1178 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1179
1180 ctx->flags |= SHA_FLAGS_FINUP;
1181
1182 if (ctx->flags & SHA_FLAGS_ERROR)
1183 return 0; /* uncompleted hash is not needed */
1184
1185 if (ctx->flags & SHA_FLAGS_PAD)
1186 /* copy ready hash (+ finalize hmac) */
1187 return atmel_sha_finish(req);
1188
1189 return atmel_sha_enqueue(req, SHA_OP_FINAL);
1190 }
1191
atmel_sha_finup(struct ahash_request * req)1192 static int atmel_sha_finup(struct ahash_request *req)
1193 {
1194 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1195 int err1, err2;
1196
1197 ctx->flags |= SHA_FLAGS_FINUP;
1198
1199 err1 = atmel_sha_update(req);
1200 if (err1 == -EINPROGRESS ||
1201 (err1 == -EBUSY && (ahash_request_flags(req) &
1202 CRYPTO_TFM_REQ_MAY_BACKLOG)))
1203 return err1;
1204
1205 /*
1206 * final() has to be always called to cleanup resources
1207 * even if udpate() failed, except EINPROGRESS
1208 */
1209 err2 = atmel_sha_final(req);
1210
1211 return err1 ?: err2;
1212 }
1213
atmel_sha_digest(struct ahash_request * req)1214 static int atmel_sha_digest(struct ahash_request *req)
1215 {
1216 return atmel_sha_init(req) ?: atmel_sha_finup(req);
1217 }
1218
1219
atmel_sha_export(struct ahash_request * req,void * out)1220 static int atmel_sha_export(struct ahash_request *req, void *out)
1221 {
1222 const struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1223
1224 memcpy(out, ctx, sizeof(*ctx));
1225 return 0;
1226 }
1227
atmel_sha_import(struct ahash_request * req,const void * in)1228 static int atmel_sha_import(struct ahash_request *req, const void *in)
1229 {
1230 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1231
1232 memcpy(ctx, in, sizeof(*ctx));
1233 return 0;
1234 }
1235
atmel_sha_cra_init(struct crypto_tfm * tfm)1236 static int atmel_sha_cra_init(struct crypto_tfm *tfm)
1237 {
1238 struct atmel_sha_ctx *ctx = crypto_tfm_ctx(tfm);
1239
1240 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1241 sizeof(struct atmel_sha_reqctx));
1242 ctx->start = atmel_sha_start;
1243
1244 return 0;
1245 }
1246
atmel_sha_alg_init(struct ahash_alg * alg)1247 static void atmel_sha_alg_init(struct ahash_alg *alg)
1248 {
1249 alg->halg.base.cra_priority = ATMEL_SHA_PRIORITY;
1250 alg->halg.base.cra_flags = CRYPTO_ALG_ASYNC |
1251 CRYPTO_ALG_KERN_DRIVER_ONLY;
1252 alg->halg.base.cra_ctxsize = sizeof(struct atmel_sha_ctx);
1253 alg->halg.base.cra_module = THIS_MODULE;
1254 alg->halg.base.cra_init = atmel_sha_cra_init;
1255
1256 alg->halg.statesize = sizeof(struct atmel_sha_reqctx);
1257
1258 alg->init = atmel_sha_init;
1259 alg->update = atmel_sha_update;
1260 alg->final = atmel_sha_final;
1261 alg->finup = atmel_sha_finup;
1262 alg->digest = atmel_sha_digest;
1263 alg->export = atmel_sha_export;
1264 alg->import = atmel_sha_import;
1265 }
1266
1267 static struct ahash_alg sha_1_256_algs[] = {
1268 {
1269 .halg.base.cra_name = "sha1",
1270 .halg.base.cra_driver_name = "atmel-sha1",
1271 .halg.base.cra_blocksize = SHA1_BLOCK_SIZE,
1272
1273 .halg.digestsize = SHA1_DIGEST_SIZE,
1274 },
1275 {
1276 .halg.base.cra_name = "sha256",
1277 .halg.base.cra_driver_name = "atmel-sha256",
1278 .halg.base.cra_blocksize = SHA256_BLOCK_SIZE,
1279
1280 .halg.digestsize = SHA256_DIGEST_SIZE,
1281 },
1282 };
1283
1284 static struct ahash_alg sha_224_alg = {
1285 .halg.base.cra_name = "sha224",
1286 .halg.base.cra_driver_name = "atmel-sha224",
1287 .halg.base.cra_blocksize = SHA224_BLOCK_SIZE,
1288
1289 .halg.digestsize = SHA224_DIGEST_SIZE,
1290 };
1291
1292 static struct ahash_alg sha_384_512_algs[] = {
1293 {
1294 .halg.base.cra_name = "sha384",
1295 .halg.base.cra_driver_name = "atmel-sha384",
1296 .halg.base.cra_blocksize = SHA384_BLOCK_SIZE,
1297
1298 .halg.digestsize = SHA384_DIGEST_SIZE,
1299 },
1300 {
1301 .halg.base.cra_name = "sha512",
1302 .halg.base.cra_driver_name = "atmel-sha512",
1303 .halg.base.cra_blocksize = SHA512_BLOCK_SIZE,
1304
1305 .halg.digestsize = SHA512_DIGEST_SIZE,
1306 },
1307 };
1308
atmel_sha_queue_task(unsigned long data)1309 static void atmel_sha_queue_task(unsigned long data)
1310 {
1311 struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data;
1312
1313 atmel_sha_handle_queue(dd, NULL);
1314 }
1315
atmel_sha_done(struct atmel_sha_dev * dd)1316 static int atmel_sha_done(struct atmel_sha_dev *dd)
1317 {
1318 int err = 0;
1319
1320 if (SHA_FLAGS_CPU & dd->flags) {
1321 if (SHA_FLAGS_OUTPUT_READY & dd->flags) {
1322 dd->flags &= ~SHA_FLAGS_OUTPUT_READY;
1323 goto finish;
1324 }
1325 } else if (SHA_FLAGS_DMA_READY & dd->flags) {
1326 if (SHA_FLAGS_DMA_ACTIVE & dd->flags) {
1327 dd->flags &= ~SHA_FLAGS_DMA_ACTIVE;
1328 atmel_sha_update_dma_stop(dd);
1329 }
1330 if (SHA_FLAGS_OUTPUT_READY & dd->flags) {
1331 /* hash or semi-hash ready */
1332 dd->flags &= ~(SHA_FLAGS_DMA_READY |
1333 SHA_FLAGS_OUTPUT_READY);
1334 err = atmel_sha_update_dma_start(dd);
1335 if (err != -EINPROGRESS)
1336 goto finish;
1337 }
1338 }
1339 return err;
1340
1341 finish:
1342 /* finish curent request */
1343 atmel_sha_finish_req(dd->req, err);
1344
1345 return err;
1346 }
1347
atmel_sha_done_task(unsigned long data)1348 static void atmel_sha_done_task(unsigned long data)
1349 {
1350 struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data;
1351
1352 dd->is_async = true;
1353 (void)dd->resume(dd);
1354 }
1355
atmel_sha_irq(int irq,void * dev_id)1356 static irqreturn_t atmel_sha_irq(int irq, void *dev_id)
1357 {
1358 struct atmel_sha_dev *sha_dd = dev_id;
1359 u32 reg;
1360
1361 reg = atmel_sha_read(sha_dd, SHA_ISR);
1362 if (reg & atmel_sha_read(sha_dd, SHA_IMR)) {
1363 atmel_sha_write(sha_dd, SHA_IDR, reg);
1364 if (SHA_FLAGS_BUSY & sha_dd->flags) {
1365 sha_dd->flags |= SHA_FLAGS_OUTPUT_READY;
1366 if (!(SHA_FLAGS_CPU & sha_dd->flags))
1367 sha_dd->flags |= SHA_FLAGS_DMA_READY;
1368 tasklet_schedule(&sha_dd->done_task);
1369 } else {
1370 dev_warn(sha_dd->dev, "SHA interrupt when no active requests.\n");
1371 }
1372 return IRQ_HANDLED;
1373 }
1374
1375 return IRQ_NONE;
1376 }
1377
1378
1379 /* DMA transfer functions */
1380
atmel_sha_dma_check_aligned(struct atmel_sha_dev * dd,struct scatterlist * sg,size_t len)1381 static bool atmel_sha_dma_check_aligned(struct atmel_sha_dev *dd,
1382 struct scatterlist *sg,
1383 size_t len)
1384 {
1385 struct atmel_sha_dma *dma = &dd->dma_lch_in;
1386 struct ahash_request *req = dd->req;
1387 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1388 size_t bs = ctx->block_size;
1389 int nents;
1390
1391 for (nents = 0; sg; sg = sg_next(sg), ++nents) {
1392 if (!IS_ALIGNED(sg->offset, sizeof(u32)))
1393 return false;
1394
1395 /*
1396 * This is the last sg, the only one that is allowed to
1397 * have an unaligned length.
1398 */
1399 if (len <= sg->length) {
1400 dma->nents = nents + 1;
1401 dma->last_sg_length = sg->length;
1402 sg->length = ALIGN(len, sizeof(u32));
1403 return true;
1404 }
1405
1406 /* All other sg lengths MUST be aligned to the block size. */
1407 if (!IS_ALIGNED(sg->length, bs))
1408 return false;
1409
1410 len -= sg->length;
1411 }
1412
1413 return false;
1414 }
1415
atmel_sha_dma_callback2(void * data)1416 static void atmel_sha_dma_callback2(void *data)
1417 {
1418 struct atmel_sha_dev *dd = data;
1419 struct atmel_sha_dma *dma = &dd->dma_lch_in;
1420 struct scatterlist *sg;
1421 int nents;
1422
1423 dma_unmap_sg(dd->dev, dma->sg, dma->nents, DMA_TO_DEVICE);
1424
1425 sg = dma->sg;
1426 for (nents = 0; nents < dma->nents - 1; ++nents)
1427 sg = sg_next(sg);
1428 sg->length = dma->last_sg_length;
1429
1430 dd->is_async = true;
1431 (void)atmel_sha_wait_for_data_ready(dd, dd->resume);
1432 }
1433
atmel_sha_dma_start(struct atmel_sha_dev * dd,struct scatterlist * src,size_t len,atmel_sha_fn_t resume)1434 static int atmel_sha_dma_start(struct atmel_sha_dev *dd,
1435 struct scatterlist *src,
1436 size_t len,
1437 atmel_sha_fn_t resume)
1438 {
1439 struct atmel_sha_dma *dma = &dd->dma_lch_in;
1440 struct dma_slave_config *config = &dma->dma_conf;
1441 struct dma_chan *chan = dma->chan;
1442 struct dma_async_tx_descriptor *desc;
1443 dma_cookie_t cookie;
1444 unsigned int sg_len;
1445 int err;
1446
1447 dd->resume = resume;
1448
1449 /*
1450 * dma->nents has already been initialized by
1451 * atmel_sha_dma_check_aligned().
1452 */
1453 dma->sg = src;
1454 sg_len = dma_map_sg(dd->dev, dma->sg, dma->nents, DMA_TO_DEVICE);
1455 if (!sg_len) {
1456 err = -ENOMEM;
1457 goto exit;
1458 }
1459
1460 config->src_maxburst = 16;
1461 config->dst_maxburst = 16;
1462 err = dmaengine_slave_config(chan, config);
1463 if (err)
1464 goto unmap_sg;
1465
1466 desc = dmaengine_prep_slave_sg(chan, dma->sg, sg_len, DMA_MEM_TO_DEV,
1467 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1468 if (!desc) {
1469 err = -ENOMEM;
1470 goto unmap_sg;
1471 }
1472
1473 desc->callback = atmel_sha_dma_callback2;
1474 desc->callback_param = dd;
1475 cookie = dmaengine_submit(desc);
1476 err = dma_submit_error(cookie);
1477 if (err)
1478 goto unmap_sg;
1479
1480 dma_async_issue_pending(chan);
1481
1482 return -EINPROGRESS;
1483
1484 unmap_sg:
1485 dma_unmap_sg(dd->dev, dma->sg, dma->nents, DMA_TO_DEVICE);
1486 exit:
1487 return atmel_sha_complete(dd, err);
1488 }
1489
1490
1491 /* CPU transfer functions */
1492
atmel_sha_cpu_transfer(struct atmel_sha_dev * dd)1493 static int atmel_sha_cpu_transfer(struct atmel_sha_dev *dd)
1494 {
1495 struct ahash_request *req = dd->req;
1496 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1497 const u32 *words = (const u32 *)ctx->buffer;
1498 size_t i, num_words;
1499 u32 isr, din, din_inc;
1500
1501 din_inc = (ctx->flags & SHA_FLAGS_IDATAR0) ? 0 : 1;
1502 for (;;) {
1503 /* Write data into the Input Data Registers. */
1504 num_words = DIV_ROUND_UP(ctx->bufcnt, sizeof(u32));
1505 for (i = 0, din = 0; i < num_words; ++i, din += din_inc)
1506 atmel_sha_write(dd, SHA_REG_DIN(din), words[i]);
1507
1508 ctx->offset += ctx->bufcnt;
1509 ctx->total -= ctx->bufcnt;
1510
1511 if (!ctx->total)
1512 break;
1513
1514 /*
1515 * Prepare next block:
1516 * Fill ctx->buffer now with the next data to be written into
1517 * IDATARx: it gives time for the SHA hardware to process
1518 * the current data so the SHA_INT_DATARDY flag might be set
1519 * in SHA_ISR when polling this register at the beginning of
1520 * the next loop.
1521 */
1522 ctx->bufcnt = min_t(size_t, ctx->block_size, ctx->total);
1523 scatterwalk_map_and_copy(ctx->buffer, ctx->sg,
1524 ctx->offset, ctx->bufcnt, 0);
1525
1526 /* Wait for hardware to be ready again. */
1527 isr = atmel_sha_read(dd, SHA_ISR);
1528 if (!(isr & SHA_INT_DATARDY)) {
1529 /* Not ready yet. */
1530 dd->resume = atmel_sha_cpu_transfer;
1531 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
1532 return -EINPROGRESS;
1533 }
1534 }
1535
1536 if (unlikely(!(ctx->flags & SHA_FLAGS_WAIT_DATARDY)))
1537 return dd->cpu_transfer_complete(dd);
1538
1539 return atmel_sha_wait_for_data_ready(dd, dd->cpu_transfer_complete);
1540 }
1541
atmel_sha_cpu_start(struct atmel_sha_dev * dd,struct scatterlist * sg,unsigned int len,bool idatar0_only,bool wait_data_ready,atmel_sha_fn_t resume)1542 static int atmel_sha_cpu_start(struct atmel_sha_dev *dd,
1543 struct scatterlist *sg,
1544 unsigned int len,
1545 bool idatar0_only,
1546 bool wait_data_ready,
1547 atmel_sha_fn_t resume)
1548 {
1549 struct ahash_request *req = dd->req;
1550 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1551
1552 if (!len)
1553 return resume(dd);
1554
1555 ctx->flags &= ~(SHA_FLAGS_IDATAR0 | SHA_FLAGS_WAIT_DATARDY);
1556
1557 if (idatar0_only)
1558 ctx->flags |= SHA_FLAGS_IDATAR0;
1559
1560 if (wait_data_ready)
1561 ctx->flags |= SHA_FLAGS_WAIT_DATARDY;
1562
1563 ctx->sg = sg;
1564 ctx->total = len;
1565 ctx->offset = 0;
1566
1567 /* Prepare the first block to be written. */
1568 ctx->bufcnt = min_t(size_t, ctx->block_size, ctx->total);
1569 scatterwalk_map_and_copy(ctx->buffer, ctx->sg,
1570 ctx->offset, ctx->bufcnt, 0);
1571
1572 dd->cpu_transfer_complete = resume;
1573 return atmel_sha_cpu_transfer(dd);
1574 }
1575
atmel_sha_cpu_hash(struct atmel_sha_dev * dd,const void * data,unsigned int datalen,bool auto_padding,atmel_sha_fn_t resume)1576 static int atmel_sha_cpu_hash(struct atmel_sha_dev *dd,
1577 const void *data, unsigned int datalen,
1578 bool auto_padding,
1579 atmel_sha_fn_t resume)
1580 {
1581 struct ahash_request *req = dd->req;
1582 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1583 u32 msglen = (auto_padding) ? datalen : 0;
1584 u32 mr = SHA_MR_MODE_AUTO;
1585
1586 if (!(IS_ALIGNED(datalen, ctx->block_size) || auto_padding))
1587 return atmel_sha_complete(dd, -EINVAL);
1588
1589 mr |= (ctx->flags & SHA_FLAGS_ALGO_MASK);
1590 atmel_sha_write(dd, SHA_MR, mr);
1591 atmel_sha_write(dd, SHA_MSR, msglen);
1592 atmel_sha_write(dd, SHA_BCR, msglen);
1593 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST);
1594
1595 sg_init_one(&dd->tmp, data, datalen);
1596 return atmel_sha_cpu_start(dd, &dd->tmp, datalen, false, true, resume);
1597 }
1598
1599
1600 /* hmac functions */
1601
1602 struct atmel_sha_hmac_key {
1603 bool valid;
1604 unsigned int keylen;
1605 u8 buffer[SHA512_BLOCK_SIZE];
1606 u8 *keydup;
1607 };
1608
atmel_sha_hmac_key_init(struct atmel_sha_hmac_key * hkey)1609 static inline void atmel_sha_hmac_key_init(struct atmel_sha_hmac_key *hkey)
1610 {
1611 memset(hkey, 0, sizeof(*hkey));
1612 }
1613
atmel_sha_hmac_key_release(struct atmel_sha_hmac_key * hkey)1614 static inline void atmel_sha_hmac_key_release(struct atmel_sha_hmac_key *hkey)
1615 {
1616 kfree(hkey->keydup);
1617 memset(hkey, 0, sizeof(*hkey));
1618 }
1619
atmel_sha_hmac_key_set(struct atmel_sha_hmac_key * hkey,const u8 * key,unsigned int keylen)1620 static inline int atmel_sha_hmac_key_set(struct atmel_sha_hmac_key *hkey,
1621 const u8 *key,
1622 unsigned int keylen)
1623 {
1624 atmel_sha_hmac_key_release(hkey);
1625
1626 if (keylen > sizeof(hkey->buffer)) {
1627 hkey->keydup = kmemdup(key, keylen, GFP_KERNEL);
1628 if (!hkey->keydup)
1629 return -ENOMEM;
1630
1631 } else {
1632 memcpy(hkey->buffer, key, keylen);
1633 }
1634
1635 hkey->valid = true;
1636 hkey->keylen = keylen;
1637 return 0;
1638 }
1639
atmel_sha_hmac_key_get(const struct atmel_sha_hmac_key * hkey,const u8 ** key,unsigned int * keylen)1640 static inline bool atmel_sha_hmac_key_get(const struct atmel_sha_hmac_key *hkey,
1641 const u8 **key,
1642 unsigned int *keylen)
1643 {
1644 if (!hkey->valid)
1645 return false;
1646
1647 *keylen = hkey->keylen;
1648 *key = (hkey->keydup) ? hkey->keydup : hkey->buffer;
1649 return true;
1650 }
1651
1652
1653 struct atmel_sha_hmac_ctx {
1654 struct atmel_sha_ctx base;
1655
1656 struct atmel_sha_hmac_key hkey;
1657 u32 ipad[SHA512_BLOCK_SIZE / sizeof(u32)];
1658 u32 opad[SHA512_BLOCK_SIZE / sizeof(u32)];
1659 atmel_sha_fn_t resume;
1660 };
1661
1662 static int atmel_sha_hmac_setup(struct atmel_sha_dev *dd,
1663 atmel_sha_fn_t resume);
1664 static int atmel_sha_hmac_prehash_key(struct atmel_sha_dev *dd,
1665 const u8 *key, unsigned int keylen);
1666 static int atmel_sha_hmac_prehash_key_done(struct atmel_sha_dev *dd);
1667 static int atmel_sha_hmac_compute_ipad_hash(struct atmel_sha_dev *dd);
1668 static int atmel_sha_hmac_compute_opad_hash(struct atmel_sha_dev *dd);
1669 static int atmel_sha_hmac_setup_done(struct atmel_sha_dev *dd);
1670
1671 static int atmel_sha_hmac_init_done(struct atmel_sha_dev *dd);
1672 static int atmel_sha_hmac_final(struct atmel_sha_dev *dd);
1673 static int atmel_sha_hmac_final_done(struct atmel_sha_dev *dd);
1674 static int atmel_sha_hmac_digest2(struct atmel_sha_dev *dd);
1675
atmel_sha_hmac_setup(struct atmel_sha_dev * dd,atmel_sha_fn_t resume)1676 static int atmel_sha_hmac_setup(struct atmel_sha_dev *dd,
1677 atmel_sha_fn_t resume)
1678 {
1679 struct ahash_request *req = dd->req;
1680 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1681 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1682 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1683 unsigned int keylen;
1684 const u8 *key;
1685 size_t bs;
1686
1687 hmac->resume = resume;
1688 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
1689 case SHA_FLAGS_SHA1:
1690 ctx->block_size = SHA1_BLOCK_SIZE;
1691 ctx->hash_size = SHA1_DIGEST_SIZE;
1692 break;
1693
1694 case SHA_FLAGS_SHA224:
1695 ctx->block_size = SHA224_BLOCK_SIZE;
1696 ctx->hash_size = SHA256_DIGEST_SIZE;
1697 break;
1698
1699 case SHA_FLAGS_SHA256:
1700 ctx->block_size = SHA256_BLOCK_SIZE;
1701 ctx->hash_size = SHA256_DIGEST_SIZE;
1702 break;
1703
1704 case SHA_FLAGS_SHA384:
1705 ctx->block_size = SHA384_BLOCK_SIZE;
1706 ctx->hash_size = SHA512_DIGEST_SIZE;
1707 break;
1708
1709 case SHA_FLAGS_SHA512:
1710 ctx->block_size = SHA512_BLOCK_SIZE;
1711 ctx->hash_size = SHA512_DIGEST_SIZE;
1712 break;
1713
1714 default:
1715 return atmel_sha_complete(dd, -EINVAL);
1716 }
1717 bs = ctx->block_size;
1718
1719 if (likely(!atmel_sha_hmac_key_get(&hmac->hkey, &key, &keylen)))
1720 return resume(dd);
1721
1722 /* Compute K' from K. */
1723 if (unlikely(keylen > bs))
1724 return atmel_sha_hmac_prehash_key(dd, key, keylen);
1725
1726 /* Prepare ipad. */
1727 memcpy((u8 *)hmac->ipad, key, keylen);
1728 memset((u8 *)hmac->ipad + keylen, 0, bs - keylen);
1729 return atmel_sha_hmac_compute_ipad_hash(dd);
1730 }
1731
atmel_sha_hmac_prehash_key(struct atmel_sha_dev * dd,const u8 * key,unsigned int keylen)1732 static int atmel_sha_hmac_prehash_key(struct atmel_sha_dev *dd,
1733 const u8 *key, unsigned int keylen)
1734 {
1735 return atmel_sha_cpu_hash(dd, key, keylen, true,
1736 atmel_sha_hmac_prehash_key_done);
1737 }
1738
atmel_sha_hmac_prehash_key_done(struct atmel_sha_dev * dd)1739 static int atmel_sha_hmac_prehash_key_done(struct atmel_sha_dev *dd)
1740 {
1741 struct ahash_request *req = dd->req;
1742 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1743 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1744 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1745 size_t ds = crypto_ahash_digestsize(tfm);
1746 size_t bs = ctx->block_size;
1747 size_t i, num_words = ds / sizeof(u32);
1748
1749 /* Prepare ipad. */
1750 for (i = 0; i < num_words; ++i)
1751 hmac->ipad[i] = atmel_sha_read(dd, SHA_REG_DIGEST(i));
1752 memset((u8 *)hmac->ipad + ds, 0, bs - ds);
1753 return atmel_sha_hmac_compute_ipad_hash(dd);
1754 }
1755
atmel_sha_hmac_compute_ipad_hash(struct atmel_sha_dev * dd)1756 static int atmel_sha_hmac_compute_ipad_hash(struct atmel_sha_dev *dd)
1757 {
1758 struct ahash_request *req = dd->req;
1759 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1760 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1761 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1762 size_t bs = ctx->block_size;
1763 size_t i, num_words = bs / sizeof(u32);
1764
1765 unsafe_memcpy(hmac->opad, hmac->ipad, bs,
1766 "fortified memcpy causes -Wrestrict warning");
1767 for (i = 0; i < num_words; ++i) {
1768 hmac->ipad[i] ^= 0x36363636;
1769 hmac->opad[i] ^= 0x5c5c5c5c;
1770 }
1771
1772 return atmel_sha_cpu_hash(dd, hmac->ipad, bs, false,
1773 atmel_sha_hmac_compute_opad_hash);
1774 }
1775
atmel_sha_hmac_compute_opad_hash(struct atmel_sha_dev * dd)1776 static int atmel_sha_hmac_compute_opad_hash(struct atmel_sha_dev *dd)
1777 {
1778 struct ahash_request *req = dd->req;
1779 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1780 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1781 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1782 size_t bs = ctx->block_size;
1783 size_t hs = ctx->hash_size;
1784 size_t i, num_words = hs / sizeof(u32);
1785
1786 for (i = 0; i < num_words; ++i)
1787 hmac->ipad[i] = atmel_sha_read(dd, SHA_REG_DIGEST(i));
1788 return atmel_sha_cpu_hash(dd, hmac->opad, bs, false,
1789 atmel_sha_hmac_setup_done);
1790 }
1791
atmel_sha_hmac_setup_done(struct atmel_sha_dev * dd)1792 static int atmel_sha_hmac_setup_done(struct atmel_sha_dev *dd)
1793 {
1794 struct ahash_request *req = dd->req;
1795 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1796 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1797 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1798 size_t hs = ctx->hash_size;
1799 size_t i, num_words = hs / sizeof(u32);
1800
1801 for (i = 0; i < num_words; ++i)
1802 hmac->opad[i] = atmel_sha_read(dd, SHA_REG_DIGEST(i));
1803 atmel_sha_hmac_key_release(&hmac->hkey);
1804 return hmac->resume(dd);
1805 }
1806
atmel_sha_hmac_start(struct atmel_sha_dev * dd)1807 static int atmel_sha_hmac_start(struct atmel_sha_dev *dd)
1808 {
1809 struct ahash_request *req = dd->req;
1810 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1811 int err;
1812
1813 err = atmel_sha_hw_init(dd);
1814 if (err)
1815 return atmel_sha_complete(dd, err);
1816
1817 switch (ctx->op) {
1818 case SHA_OP_INIT:
1819 err = atmel_sha_hmac_setup(dd, atmel_sha_hmac_init_done);
1820 break;
1821
1822 case SHA_OP_UPDATE:
1823 dd->resume = atmel_sha_done;
1824 err = atmel_sha_update_req(dd);
1825 break;
1826
1827 case SHA_OP_FINAL:
1828 dd->resume = atmel_sha_hmac_final;
1829 err = atmel_sha_final_req(dd);
1830 break;
1831
1832 case SHA_OP_DIGEST:
1833 err = atmel_sha_hmac_setup(dd, atmel_sha_hmac_digest2);
1834 break;
1835
1836 default:
1837 return atmel_sha_complete(dd, -EINVAL);
1838 }
1839
1840 return err;
1841 }
1842
atmel_sha_hmac_setkey(struct crypto_ahash * tfm,const u8 * key,unsigned int keylen)1843 static int atmel_sha_hmac_setkey(struct crypto_ahash *tfm, const u8 *key,
1844 unsigned int keylen)
1845 {
1846 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1847
1848 return atmel_sha_hmac_key_set(&hmac->hkey, key, keylen);
1849 }
1850
atmel_sha_hmac_init(struct ahash_request * req)1851 static int atmel_sha_hmac_init(struct ahash_request *req)
1852 {
1853 int err;
1854
1855 err = atmel_sha_init(req);
1856 if (err)
1857 return err;
1858
1859 return atmel_sha_enqueue(req, SHA_OP_INIT);
1860 }
1861
atmel_sha_hmac_init_done(struct atmel_sha_dev * dd)1862 static int atmel_sha_hmac_init_done(struct atmel_sha_dev *dd)
1863 {
1864 struct ahash_request *req = dd->req;
1865 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1866 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1867 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1868 size_t bs = ctx->block_size;
1869 size_t hs = ctx->hash_size;
1870
1871 ctx->bufcnt = 0;
1872 ctx->digcnt[0] = bs;
1873 ctx->digcnt[1] = 0;
1874 ctx->flags |= SHA_FLAGS_RESTORE;
1875 memcpy(ctx->digest, hmac->ipad, hs);
1876 return atmel_sha_complete(dd, 0);
1877 }
1878
atmel_sha_hmac_final(struct atmel_sha_dev * dd)1879 static int atmel_sha_hmac_final(struct atmel_sha_dev *dd)
1880 {
1881 struct ahash_request *req = dd->req;
1882 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1883 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1884 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1885 u32 *digest = (u32 *)ctx->digest;
1886 size_t ds = crypto_ahash_digestsize(tfm);
1887 size_t bs = ctx->block_size;
1888 size_t hs = ctx->hash_size;
1889 size_t i, num_words;
1890 u32 mr;
1891
1892 /* Save d = SHA((K' + ipad) | msg). */
1893 num_words = ds / sizeof(u32);
1894 for (i = 0; i < num_words; ++i)
1895 digest[i] = atmel_sha_read(dd, SHA_REG_DIGEST(i));
1896
1897 /* Restore context to finish computing SHA((K' + opad) | d). */
1898 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIHV);
1899 num_words = hs / sizeof(u32);
1900 for (i = 0; i < num_words; ++i)
1901 atmel_sha_write(dd, SHA_REG_DIN(i), hmac->opad[i]);
1902
1903 mr = SHA_MR_MODE_AUTO | SHA_MR_UIHV;
1904 mr |= (ctx->flags & SHA_FLAGS_ALGO_MASK);
1905 atmel_sha_write(dd, SHA_MR, mr);
1906 atmel_sha_write(dd, SHA_MSR, bs + ds);
1907 atmel_sha_write(dd, SHA_BCR, ds);
1908 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST);
1909
1910 sg_init_one(&dd->tmp, digest, ds);
1911 return atmel_sha_cpu_start(dd, &dd->tmp, ds, false, true,
1912 atmel_sha_hmac_final_done);
1913 }
1914
atmel_sha_hmac_final_done(struct atmel_sha_dev * dd)1915 static int atmel_sha_hmac_final_done(struct atmel_sha_dev *dd)
1916 {
1917 /*
1918 * req->result might not be sizeof(u32) aligned, so copy the
1919 * digest into ctx->digest[] before memcpy() the data into
1920 * req->result.
1921 */
1922 atmel_sha_copy_hash(dd->req);
1923 atmel_sha_copy_ready_hash(dd->req);
1924 return atmel_sha_complete(dd, 0);
1925 }
1926
atmel_sha_hmac_digest(struct ahash_request * req)1927 static int atmel_sha_hmac_digest(struct ahash_request *req)
1928 {
1929 int err;
1930
1931 err = atmel_sha_init(req);
1932 if (err)
1933 return err;
1934
1935 return atmel_sha_enqueue(req, SHA_OP_DIGEST);
1936 }
1937
atmel_sha_hmac_digest2(struct atmel_sha_dev * dd)1938 static int atmel_sha_hmac_digest2(struct atmel_sha_dev *dd)
1939 {
1940 struct ahash_request *req = dd->req;
1941 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1942 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1943 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
1944 struct scatterlist *sgbuf;
1945 size_t hs = ctx->hash_size;
1946 size_t i, num_words = hs / sizeof(u32);
1947 bool use_dma = false;
1948 u32 mr;
1949
1950 /* Special case for empty message. */
1951 if (!req->nbytes) {
1952 req->nbytes = 0;
1953 ctx->bufcnt = 0;
1954 ctx->digcnt[0] = 0;
1955 ctx->digcnt[1] = 0;
1956 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
1957 case SHA_FLAGS_SHA1:
1958 case SHA_FLAGS_SHA224:
1959 case SHA_FLAGS_SHA256:
1960 atmel_sha_fill_padding(ctx, 64);
1961 break;
1962
1963 case SHA_FLAGS_SHA384:
1964 case SHA_FLAGS_SHA512:
1965 atmel_sha_fill_padding(ctx, 128);
1966 break;
1967 }
1968 sg_init_one(&dd->tmp, ctx->buffer, ctx->bufcnt);
1969 }
1970
1971 /* Check DMA threshold and alignment. */
1972 if (req->nbytes > ATMEL_SHA_DMA_THRESHOLD &&
1973 atmel_sha_dma_check_aligned(dd, req->src, req->nbytes))
1974 use_dma = true;
1975
1976 /* Write both initial hash values to compute a HMAC. */
1977 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIHV);
1978 for (i = 0; i < num_words; ++i)
1979 atmel_sha_write(dd, SHA_REG_DIN(i), hmac->ipad[i]);
1980
1981 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIEHV);
1982 for (i = 0; i < num_words; ++i)
1983 atmel_sha_write(dd, SHA_REG_DIN(i), hmac->opad[i]);
1984
1985 /* Write the Mode, Message Size, Bytes Count then Control Registers. */
1986 mr = (SHA_MR_HMAC | SHA_MR_DUALBUFF);
1987 mr |= ctx->flags & SHA_FLAGS_ALGO_MASK;
1988 if (use_dma)
1989 mr |= SHA_MR_MODE_IDATAR0;
1990 else
1991 mr |= SHA_MR_MODE_AUTO;
1992 atmel_sha_write(dd, SHA_MR, mr);
1993
1994 atmel_sha_write(dd, SHA_MSR, req->nbytes);
1995 atmel_sha_write(dd, SHA_BCR, req->nbytes);
1996
1997 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST);
1998
1999 /* Special case for empty message. */
2000 if (!req->nbytes) {
2001 sgbuf = &dd->tmp;
2002 req->nbytes = ctx->bufcnt;
2003 } else {
2004 sgbuf = req->src;
2005 }
2006
2007 /* Process data. */
2008 if (use_dma)
2009 return atmel_sha_dma_start(dd, sgbuf, req->nbytes,
2010 atmel_sha_hmac_final_done);
2011
2012 return atmel_sha_cpu_start(dd, sgbuf, req->nbytes, false, true,
2013 atmel_sha_hmac_final_done);
2014 }
2015
atmel_sha_hmac_cra_init(struct crypto_tfm * tfm)2016 static int atmel_sha_hmac_cra_init(struct crypto_tfm *tfm)
2017 {
2018 struct atmel_sha_hmac_ctx *hmac = crypto_tfm_ctx(tfm);
2019
2020 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2021 sizeof(struct atmel_sha_reqctx));
2022 hmac->base.start = atmel_sha_hmac_start;
2023 atmel_sha_hmac_key_init(&hmac->hkey);
2024
2025 return 0;
2026 }
2027
atmel_sha_hmac_cra_exit(struct crypto_tfm * tfm)2028 static void atmel_sha_hmac_cra_exit(struct crypto_tfm *tfm)
2029 {
2030 struct atmel_sha_hmac_ctx *hmac = crypto_tfm_ctx(tfm);
2031
2032 atmel_sha_hmac_key_release(&hmac->hkey);
2033 }
2034
atmel_sha_hmac_alg_init(struct ahash_alg * alg)2035 static void atmel_sha_hmac_alg_init(struct ahash_alg *alg)
2036 {
2037 alg->halg.base.cra_priority = ATMEL_SHA_PRIORITY;
2038 alg->halg.base.cra_flags = CRYPTO_ALG_ASYNC |
2039 CRYPTO_ALG_KERN_DRIVER_ONLY;
2040 alg->halg.base.cra_ctxsize = sizeof(struct atmel_sha_hmac_ctx);
2041 alg->halg.base.cra_module = THIS_MODULE;
2042 alg->halg.base.cra_init = atmel_sha_hmac_cra_init;
2043 alg->halg.base.cra_exit = atmel_sha_hmac_cra_exit;
2044
2045 alg->halg.statesize = sizeof(struct atmel_sha_reqctx);
2046
2047 alg->init = atmel_sha_hmac_init;
2048 alg->update = atmel_sha_update;
2049 alg->final = atmel_sha_final;
2050 alg->digest = atmel_sha_hmac_digest;
2051 alg->setkey = atmel_sha_hmac_setkey;
2052 alg->export = atmel_sha_export;
2053 alg->import = atmel_sha_import;
2054 }
2055
2056 static struct ahash_alg sha_hmac_algs[] = {
2057 {
2058 .halg.base.cra_name = "hmac(sha1)",
2059 .halg.base.cra_driver_name = "atmel-hmac-sha1",
2060 .halg.base.cra_blocksize = SHA1_BLOCK_SIZE,
2061
2062 .halg.digestsize = SHA1_DIGEST_SIZE,
2063 },
2064 {
2065 .halg.base.cra_name = "hmac(sha224)",
2066 .halg.base.cra_driver_name = "atmel-hmac-sha224",
2067 .halg.base.cra_blocksize = SHA224_BLOCK_SIZE,
2068
2069 .halg.digestsize = SHA224_DIGEST_SIZE,
2070 },
2071 {
2072 .halg.base.cra_name = "hmac(sha256)",
2073 .halg.base.cra_driver_name = "atmel-hmac-sha256",
2074 .halg.base.cra_blocksize = SHA256_BLOCK_SIZE,
2075
2076 .halg.digestsize = SHA256_DIGEST_SIZE,
2077 },
2078 {
2079 .halg.base.cra_name = "hmac(sha384)",
2080 .halg.base.cra_driver_name = "atmel-hmac-sha384",
2081 .halg.base.cra_blocksize = SHA384_BLOCK_SIZE,
2082
2083 .halg.digestsize = SHA384_DIGEST_SIZE,
2084 },
2085 {
2086 .halg.base.cra_name = "hmac(sha512)",
2087 .halg.base.cra_driver_name = "atmel-hmac-sha512",
2088 .halg.base.cra_blocksize = SHA512_BLOCK_SIZE,
2089
2090 .halg.digestsize = SHA512_DIGEST_SIZE,
2091 },
2092 };
2093
2094 #if IS_ENABLED(CONFIG_CRYPTO_DEV_ATMEL_AUTHENC)
2095 /* authenc functions */
2096
2097 static int atmel_sha_authenc_init2(struct atmel_sha_dev *dd);
2098 static int atmel_sha_authenc_init_done(struct atmel_sha_dev *dd);
2099 static int atmel_sha_authenc_final_done(struct atmel_sha_dev *dd);
2100
2101
2102 struct atmel_sha_authenc_ctx {
2103 struct crypto_ahash *tfm;
2104 };
2105
2106 struct atmel_sha_authenc_reqctx {
2107 struct atmel_sha_reqctx base;
2108
2109 atmel_aes_authenc_fn_t cb;
2110 struct atmel_aes_dev *aes_dev;
2111
2112 /* _init() parameters. */
2113 struct scatterlist *assoc;
2114 u32 assoclen;
2115 u32 textlen;
2116
2117 /* _final() parameters. */
2118 u32 *digest;
2119 unsigned int digestlen;
2120 };
2121
atmel_sha_authenc_complete(void * data,int err)2122 static void atmel_sha_authenc_complete(void *data, int err)
2123 {
2124 struct ahash_request *req = data;
2125 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2126
2127 authctx->cb(authctx->aes_dev, err, authctx->base.dd->is_async);
2128 }
2129
atmel_sha_authenc_start(struct atmel_sha_dev * dd)2130 static int atmel_sha_authenc_start(struct atmel_sha_dev *dd)
2131 {
2132 struct ahash_request *req = dd->req;
2133 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2134 int err;
2135
2136 /*
2137 * Force atmel_sha_complete() to call req->base.complete(), ie
2138 * atmel_sha_authenc_complete(), which in turn calls authctx->cb().
2139 */
2140 dd->force_complete = true;
2141
2142 err = atmel_sha_hw_init(dd);
2143 return authctx->cb(authctx->aes_dev, err, dd->is_async);
2144 }
2145
atmel_sha_authenc_is_ready(void)2146 bool atmel_sha_authenc_is_ready(void)
2147 {
2148 struct atmel_sha_ctx dummy;
2149
2150 dummy.dd = NULL;
2151 return (atmel_sha_find_dev(&dummy) != NULL);
2152 }
2153 EXPORT_SYMBOL_GPL(atmel_sha_authenc_is_ready);
2154
atmel_sha_authenc_get_reqsize(void)2155 unsigned int atmel_sha_authenc_get_reqsize(void)
2156 {
2157 return sizeof(struct atmel_sha_authenc_reqctx);
2158 }
2159 EXPORT_SYMBOL_GPL(atmel_sha_authenc_get_reqsize);
2160
atmel_sha_authenc_spawn(unsigned long mode)2161 struct atmel_sha_authenc_ctx *atmel_sha_authenc_spawn(unsigned long mode)
2162 {
2163 struct atmel_sha_authenc_ctx *auth;
2164 struct crypto_ahash *tfm;
2165 struct atmel_sha_ctx *tctx;
2166 const char *name;
2167 int err = -EINVAL;
2168
2169 switch (mode & SHA_FLAGS_MODE_MASK) {
2170 case SHA_FLAGS_HMAC_SHA1:
2171 name = "atmel-hmac-sha1";
2172 break;
2173
2174 case SHA_FLAGS_HMAC_SHA224:
2175 name = "atmel-hmac-sha224";
2176 break;
2177
2178 case SHA_FLAGS_HMAC_SHA256:
2179 name = "atmel-hmac-sha256";
2180 break;
2181
2182 case SHA_FLAGS_HMAC_SHA384:
2183 name = "atmel-hmac-sha384";
2184 break;
2185
2186 case SHA_FLAGS_HMAC_SHA512:
2187 name = "atmel-hmac-sha512";
2188 break;
2189
2190 default:
2191 goto error;
2192 }
2193
2194 tfm = crypto_alloc_ahash(name, 0, 0);
2195 if (IS_ERR(tfm)) {
2196 err = PTR_ERR(tfm);
2197 goto error;
2198 }
2199 tctx = crypto_ahash_ctx(tfm);
2200 tctx->start = atmel_sha_authenc_start;
2201 tctx->flags = mode;
2202
2203 auth = kzalloc_obj(*auth);
2204 if (!auth) {
2205 err = -ENOMEM;
2206 goto err_free_ahash;
2207 }
2208 auth->tfm = tfm;
2209
2210 return auth;
2211
2212 err_free_ahash:
2213 crypto_free_ahash(tfm);
2214 error:
2215 return ERR_PTR(err);
2216 }
2217 EXPORT_SYMBOL_GPL(atmel_sha_authenc_spawn);
2218
atmel_sha_authenc_free(struct atmel_sha_authenc_ctx * auth)2219 void atmel_sha_authenc_free(struct atmel_sha_authenc_ctx *auth)
2220 {
2221 if (auth)
2222 crypto_free_ahash(auth->tfm);
2223 kfree(auth);
2224 }
2225 EXPORT_SYMBOL_GPL(atmel_sha_authenc_free);
2226
atmel_sha_authenc_setkey(struct atmel_sha_authenc_ctx * auth,const u8 * key,unsigned int keylen,u32 flags)2227 int atmel_sha_authenc_setkey(struct atmel_sha_authenc_ctx *auth,
2228 const u8 *key, unsigned int keylen, u32 flags)
2229 {
2230 struct crypto_ahash *tfm = auth->tfm;
2231
2232 crypto_ahash_clear_flags(tfm, CRYPTO_TFM_REQ_MASK);
2233 crypto_ahash_set_flags(tfm, flags & CRYPTO_TFM_REQ_MASK);
2234 return crypto_ahash_setkey(tfm, key, keylen);
2235 }
2236 EXPORT_SYMBOL_GPL(atmel_sha_authenc_setkey);
2237
atmel_sha_authenc_schedule(struct ahash_request * req,struct atmel_sha_authenc_ctx * auth,atmel_aes_authenc_fn_t cb,struct atmel_aes_dev * aes_dev)2238 int atmel_sha_authenc_schedule(struct ahash_request *req,
2239 struct atmel_sha_authenc_ctx *auth,
2240 atmel_aes_authenc_fn_t cb,
2241 struct atmel_aes_dev *aes_dev)
2242 {
2243 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2244 struct atmel_sha_reqctx *ctx = &authctx->base;
2245 struct crypto_ahash *tfm = auth->tfm;
2246 struct atmel_sha_ctx *tctx = crypto_ahash_ctx(tfm);
2247 struct atmel_sha_dev *dd;
2248
2249 /* Reset request context (MUST be done first). */
2250 memset(authctx, 0, sizeof(*authctx));
2251
2252 /* Get SHA device. */
2253 dd = atmel_sha_find_dev(tctx);
2254 if (!dd)
2255 return cb(aes_dev, -ENODEV, false);
2256
2257 /* Init request context. */
2258 ctx->dd = dd;
2259 ctx->buflen = SHA_BUFFER_LEN;
2260 authctx->cb = cb;
2261 authctx->aes_dev = aes_dev;
2262 ahash_request_set_tfm(req, tfm);
2263 ahash_request_set_callback(req, 0, atmel_sha_authenc_complete, req);
2264
2265 return atmel_sha_handle_queue(dd, req);
2266 }
2267 EXPORT_SYMBOL_GPL(atmel_sha_authenc_schedule);
2268
atmel_sha_authenc_init(struct ahash_request * req,struct scatterlist * assoc,unsigned int assoclen,unsigned int textlen,atmel_aes_authenc_fn_t cb,struct atmel_aes_dev * aes_dev)2269 int atmel_sha_authenc_init(struct ahash_request *req,
2270 struct scatterlist *assoc, unsigned int assoclen,
2271 unsigned int textlen,
2272 atmel_aes_authenc_fn_t cb,
2273 struct atmel_aes_dev *aes_dev)
2274 {
2275 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2276 struct atmel_sha_reqctx *ctx = &authctx->base;
2277 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
2278 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
2279 struct atmel_sha_dev *dd = ctx->dd;
2280
2281 if (unlikely(!IS_ALIGNED(assoclen, sizeof(u32))))
2282 return atmel_sha_complete(dd, -EINVAL);
2283
2284 authctx->cb = cb;
2285 authctx->aes_dev = aes_dev;
2286 authctx->assoc = assoc;
2287 authctx->assoclen = assoclen;
2288 authctx->textlen = textlen;
2289
2290 ctx->flags = hmac->base.flags;
2291 return atmel_sha_hmac_setup(dd, atmel_sha_authenc_init2);
2292 }
2293 EXPORT_SYMBOL_GPL(atmel_sha_authenc_init);
2294
atmel_sha_authenc_init2(struct atmel_sha_dev * dd)2295 static int atmel_sha_authenc_init2(struct atmel_sha_dev *dd)
2296 {
2297 struct ahash_request *req = dd->req;
2298 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2299 struct atmel_sha_reqctx *ctx = &authctx->base;
2300 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
2301 struct atmel_sha_hmac_ctx *hmac = crypto_ahash_ctx(tfm);
2302 size_t hs = ctx->hash_size;
2303 size_t i, num_words = hs / sizeof(u32);
2304 u32 mr, msg_size;
2305
2306 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIHV);
2307 for (i = 0; i < num_words; ++i)
2308 atmel_sha_write(dd, SHA_REG_DIN(i), hmac->ipad[i]);
2309
2310 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIEHV);
2311 for (i = 0; i < num_words; ++i)
2312 atmel_sha_write(dd, SHA_REG_DIN(i), hmac->opad[i]);
2313
2314 mr = (SHA_MR_MODE_IDATAR0 |
2315 SHA_MR_HMAC |
2316 SHA_MR_DUALBUFF);
2317 mr |= ctx->flags & SHA_FLAGS_ALGO_MASK;
2318 atmel_sha_write(dd, SHA_MR, mr);
2319
2320 msg_size = authctx->assoclen + authctx->textlen;
2321 atmel_sha_write(dd, SHA_MSR, msg_size);
2322 atmel_sha_write(dd, SHA_BCR, msg_size);
2323
2324 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST);
2325
2326 /* Process assoc data. */
2327 return atmel_sha_cpu_start(dd, authctx->assoc, authctx->assoclen,
2328 true, false,
2329 atmel_sha_authenc_init_done);
2330 }
2331
atmel_sha_authenc_init_done(struct atmel_sha_dev * dd)2332 static int atmel_sha_authenc_init_done(struct atmel_sha_dev *dd)
2333 {
2334 struct ahash_request *req = dd->req;
2335 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2336
2337 return authctx->cb(authctx->aes_dev, 0, dd->is_async);
2338 }
2339
atmel_sha_authenc_final(struct ahash_request * req,u32 * digest,unsigned int digestlen,atmel_aes_authenc_fn_t cb,struct atmel_aes_dev * aes_dev)2340 int atmel_sha_authenc_final(struct ahash_request *req,
2341 u32 *digest, unsigned int digestlen,
2342 atmel_aes_authenc_fn_t cb,
2343 struct atmel_aes_dev *aes_dev)
2344 {
2345 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2346 struct atmel_sha_reqctx *ctx = &authctx->base;
2347 struct atmel_sha_dev *dd = ctx->dd;
2348
2349 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
2350 case SHA_FLAGS_SHA1:
2351 authctx->digestlen = SHA1_DIGEST_SIZE;
2352 break;
2353
2354 case SHA_FLAGS_SHA224:
2355 authctx->digestlen = SHA224_DIGEST_SIZE;
2356 break;
2357
2358 case SHA_FLAGS_SHA256:
2359 authctx->digestlen = SHA256_DIGEST_SIZE;
2360 break;
2361
2362 case SHA_FLAGS_SHA384:
2363 authctx->digestlen = SHA384_DIGEST_SIZE;
2364 break;
2365
2366 case SHA_FLAGS_SHA512:
2367 authctx->digestlen = SHA512_DIGEST_SIZE;
2368 break;
2369
2370 default:
2371 return atmel_sha_complete(dd, -EINVAL);
2372 }
2373 if (authctx->digestlen > digestlen)
2374 authctx->digestlen = digestlen;
2375
2376 authctx->cb = cb;
2377 authctx->aes_dev = aes_dev;
2378 authctx->digest = digest;
2379 return atmel_sha_wait_for_data_ready(dd,
2380 atmel_sha_authenc_final_done);
2381 }
2382 EXPORT_SYMBOL_GPL(atmel_sha_authenc_final);
2383
atmel_sha_authenc_final_done(struct atmel_sha_dev * dd)2384 static int atmel_sha_authenc_final_done(struct atmel_sha_dev *dd)
2385 {
2386 struct ahash_request *req = dd->req;
2387 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2388 size_t i, num_words = authctx->digestlen / sizeof(u32);
2389
2390 for (i = 0; i < num_words; ++i)
2391 authctx->digest[i] = atmel_sha_read(dd, SHA_REG_DIGEST(i));
2392
2393 return atmel_sha_complete(dd, 0);
2394 }
2395
atmel_sha_authenc_abort(struct ahash_request * req)2396 void atmel_sha_authenc_abort(struct ahash_request *req)
2397 {
2398 struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
2399 struct atmel_sha_reqctx *ctx = &authctx->base;
2400 struct atmel_sha_dev *dd = ctx->dd;
2401
2402 /* Prevent atmel_sha_complete() from calling req->base.complete(). */
2403 dd->is_async = false;
2404 dd->force_complete = false;
2405 (void)atmel_sha_complete(dd, 0);
2406 }
2407 EXPORT_SYMBOL_GPL(atmel_sha_authenc_abort);
2408
2409 #endif /* CONFIG_CRYPTO_DEV_ATMEL_AUTHENC */
2410
2411
atmel_sha_unregister_algs(struct atmel_sha_dev * dd)2412 static void atmel_sha_unregister_algs(struct atmel_sha_dev *dd)
2413 {
2414 if (dd->caps.has_hmac)
2415 crypto_unregister_ahashes(sha_hmac_algs,
2416 ARRAY_SIZE(sha_hmac_algs));
2417
2418 crypto_unregister_ahashes(sha_1_256_algs, ARRAY_SIZE(sha_1_256_algs));
2419
2420 if (dd->caps.has_sha224)
2421 crypto_unregister_ahash(&sha_224_alg);
2422
2423 if (dd->caps.has_sha_384_512)
2424 crypto_unregister_ahashes(sha_384_512_algs,
2425 ARRAY_SIZE(sha_384_512_algs));
2426 }
2427
atmel_sha_register_algs(struct atmel_sha_dev * dd)2428 static int atmel_sha_register_algs(struct atmel_sha_dev *dd)
2429 {
2430 int err, i;
2431
2432 for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++) {
2433 atmel_sha_alg_init(&sha_1_256_algs[i]);
2434
2435 err = crypto_register_ahash(&sha_1_256_algs[i]);
2436 if (err)
2437 goto err_sha_1_256_algs;
2438 }
2439
2440 if (dd->caps.has_sha224) {
2441 atmel_sha_alg_init(&sha_224_alg);
2442
2443 err = crypto_register_ahash(&sha_224_alg);
2444 if (err)
2445 goto err_sha_224_algs;
2446 }
2447
2448 if (dd->caps.has_sha_384_512) {
2449 for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++) {
2450 atmel_sha_alg_init(&sha_384_512_algs[i]);
2451
2452 err = crypto_register_ahash(&sha_384_512_algs[i]);
2453 if (err)
2454 goto err_sha_384_512_algs;
2455 }
2456 }
2457
2458 if (dd->caps.has_hmac) {
2459 for (i = 0; i < ARRAY_SIZE(sha_hmac_algs); i++) {
2460 atmel_sha_hmac_alg_init(&sha_hmac_algs[i]);
2461
2462 err = crypto_register_ahash(&sha_hmac_algs[i]);
2463 if (err)
2464 goto err_sha_hmac_algs;
2465 }
2466 }
2467
2468 return 0;
2469
2470 /*i = ARRAY_SIZE(sha_hmac_algs);*/
2471 err_sha_hmac_algs:
2472 crypto_unregister_ahashes(sha_hmac_algs, i);
2473 i = ARRAY_SIZE(sha_384_512_algs);
2474 err_sha_384_512_algs:
2475 crypto_unregister_ahashes(sha_384_512_algs, i);
2476 crypto_unregister_ahash(&sha_224_alg);
2477 err_sha_224_algs:
2478 i = ARRAY_SIZE(sha_1_256_algs);
2479 err_sha_1_256_algs:
2480 crypto_unregister_ahashes(sha_1_256_algs, i);
2481
2482 return err;
2483 }
2484
atmel_sha_dma_init(struct atmel_sha_dev * dd)2485 static int atmel_sha_dma_init(struct atmel_sha_dev *dd)
2486 {
2487 dd->dma_lch_in.chan = dma_request_chan(dd->dev, "tx");
2488 if (IS_ERR(dd->dma_lch_in.chan)) {
2489 return dev_err_probe(dd->dev, PTR_ERR(dd->dma_lch_in.chan),
2490 "DMA channel is not available\n");
2491 }
2492
2493 dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
2494 SHA_REG_DIN(0);
2495 dd->dma_lch_in.dma_conf.src_maxburst = 1;
2496 dd->dma_lch_in.dma_conf.src_addr_width =
2497 DMA_SLAVE_BUSWIDTH_4_BYTES;
2498 dd->dma_lch_in.dma_conf.dst_maxburst = 1;
2499 dd->dma_lch_in.dma_conf.dst_addr_width =
2500 DMA_SLAVE_BUSWIDTH_4_BYTES;
2501 dd->dma_lch_in.dma_conf.device_fc = false;
2502
2503 return 0;
2504 }
2505
atmel_sha_dma_cleanup(struct atmel_sha_dev * dd)2506 static void atmel_sha_dma_cleanup(struct atmel_sha_dev *dd)
2507 {
2508 dma_release_channel(dd->dma_lch_in.chan);
2509 }
2510
atmel_sha_get_cap(struct atmel_sha_dev * dd)2511 static void atmel_sha_get_cap(struct atmel_sha_dev *dd)
2512 {
2513
2514 dd->caps.has_dma = 0;
2515 dd->caps.has_dualbuff = 0;
2516 dd->caps.has_sha224 = 0;
2517 dd->caps.has_sha_384_512 = 0;
2518 dd->caps.has_uihv = 0;
2519 dd->caps.has_hmac = 0;
2520
2521 /* keep only major version number */
2522 switch (dd->hw_version & 0xff0) {
2523 case 0x800:
2524 case 0x700:
2525 case 0x600:
2526 case 0x510:
2527 dd->caps.has_dma = 1;
2528 dd->caps.has_dualbuff = 1;
2529 dd->caps.has_sha224 = 1;
2530 dd->caps.has_sha_384_512 = 1;
2531 dd->caps.has_uihv = 1;
2532 dd->caps.has_hmac = 1;
2533 break;
2534 case 0x420:
2535 dd->caps.has_dma = 1;
2536 dd->caps.has_dualbuff = 1;
2537 dd->caps.has_sha224 = 1;
2538 dd->caps.has_sha_384_512 = 1;
2539 dd->caps.has_uihv = 1;
2540 break;
2541 case 0x410:
2542 dd->caps.has_dma = 1;
2543 dd->caps.has_dualbuff = 1;
2544 dd->caps.has_sha224 = 1;
2545 dd->caps.has_sha_384_512 = 1;
2546 break;
2547 case 0x400:
2548 dd->caps.has_dma = 1;
2549 dd->caps.has_dualbuff = 1;
2550 dd->caps.has_sha224 = 1;
2551 break;
2552 case 0x320:
2553 break;
2554 default:
2555 dev_warn(dd->dev,
2556 "Unmanaged sha version, set minimum capabilities\n");
2557 break;
2558 }
2559 }
2560
2561 static const struct of_device_id atmel_sha_dt_ids[] = {
2562 { .compatible = "atmel,at91sam9g46-sha" },
2563 { /* sentinel */ }
2564 };
2565
2566 MODULE_DEVICE_TABLE(of, atmel_sha_dt_ids);
2567
atmel_sha_probe(struct platform_device * pdev)2568 static int atmel_sha_probe(struct platform_device *pdev)
2569 {
2570 struct atmel_sha_dev *sha_dd;
2571 struct device *dev = &pdev->dev;
2572 struct resource *sha_res;
2573 int err;
2574
2575 sha_dd = devm_kzalloc(&pdev->dev, sizeof(*sha_dd), GFP_KERNEL);
2576 if (!sha_dd)
2577 return -ENOMEM;
2578
2579 sha_dd->dev = dev;
2580
2581 platform_set_drvdata(pdev, sha_dd);
2582
2583 INIT_LIST_HEAD(&sha_dd->list);
2584 spin_lock_init(&sha_dd->lock);
2585
2586 tasklet_init(&sha_dd->done_task, atmel_sha_done_task,
2587 (unsigned long)sha_dd);
2588 tasklet_init(&sha_dd->queue_task, atmel_sha_queue_task,
2589 (unsigned long)sha_dd);
2590
2591 crypto_init_queue(&sha_dd->queue, ATMEL_SHA_QUEUE_LENGTH);
2592
2593 sha_dd->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &sha_res);
2594 if (IS_ERR(sha_dd->io_base)) {
2595 err = PTR_ERR(sha_dd->io_base);
2596 goto err_tasklet_kill;
2597 }
2598 sha_dd->phys_base = sha_res->start;
2599
2600 /* Get the IRQ */
2601 sha_dd->irq = platform_get_irq(pdev, 0);
2602 if (sha_dd->irq < 0) {
2603 err = sha_dd->irq;
2604 goto err_tasklet_kill;
2605 }
2606
2607 err = devm_request_irq(&pdev->dev, sha_dd->irq, atmel_sha_irq,
2608 IRQF_SHARED, "atmel-sha", sha_dd);
2609 if (err) {
2610 dev_err(dev, "unable to request sha irq.\n");
2611 goto err_tasklet_kill;
2612 }
2613
2614 /* Initializing the clock */
2615 sha_dd->iclk = devm_clk_get_prepared(&pdev->dev, "sha_clk");
2616 if (IS_ERR(sha_dd->iclk)) {
2617 dev_err(dev, "clock initialization failed.\n");
2618 err = PTR_ERR(sha_dd->iclk);
2619 goto err_tasklet_kill;
2620 }
2621
2622 err = atmel_sha_hw_version_init(sha_dd);
2623 if (err)
2624 goto err_tasklet_kill;
2625
2626 atmel_sha_get_cap(sha_dd);
2627
2628 if (sha_dd->caps.has_dma) {
2629 err = atmel_sha_dma_init(sha_dd);
2630 if (err)
2631 goto err_tasklet_kill;
2632
2633 dev_info(dev, "using %s for DMA transfers\n",
2634 dma_chan_name(sha_dd->dma_lch_in.chan));
2635 }
2636
2637 spin_lock(&atmel_sha.lock);
2638 list_add_tail(&sha_dd->list, &atmel_sha.dev_list);
2639 spin_unlock(&atmel_sha.lock);
2640
2641 err = atmel_sha_register_algs(sha_dd);
2642 if (err)
2643 goto err_algs;
2644
2645 dev_info(dev, "Atmel SHA1/SHA256%s%s\n",
2646 sha_dd->caps.has_sha224 ? "/SHA224" : "",
2647 sha_dd->caps.has_sha_384_512 ? "/SHA384/SHA512" : "");
2648
2649 return 0;
2650
2651 err_algs:
2652 spin_lock(&atmel_sha.lock);
2653 list_del(&sha_dd->list);
2654 spin_unlock(&atmel_sha.lock);
2655 if (sha_dd->caps.has_dma)
2656 atmel_sha_dma_cleanup(sha_dd);
2657 err_tasklet_kill:
2658 tasklet_kill(&sha_dd->queue_task);
2659 tasklet_kill(&sha_dd->done_task);
2660
2661 return err;
2662 }
2663
atmel_sha_remove(struct platform_device * pdev)2664 static void atmel_sha_remove(struct platform_device *pdev)
2665 {
2666 struct atmel_sha_dev *sha_dd = platform_get_drvdata(pdev);
2667
2668 spin_lock(&atmel_sha.lock);
2669 list_del(&sha_dd->list);
2670 spin_unlock(&atmel_sha.lock);
2671
2672 atmel_sha_unregister_algs(sha_dd);
2673
2674 tasklet_kill(&sha_dd->queue_task);
2675 tasklet_kill(&sha_dd->done_task);
2676
2677 if (sha_dd->caps.has_dma)
2678 atmel_sha_dma_cleanup(sha_dd);
2679 }
2680
2681 static struct platform_driver atmel_sha_driver = {
2682 .probe = atmel_sha_probe,
2683 .remove = atmel_sha_remove,
2684 .driver = {
2685 .name = "atmel_sha",
2686 .of_match_table = atmel_sha_dt_ids,
2687 },
2688 };
2689
2690 module_platform_driver(atmel_sha_driver);
2691
2692 MODULE_DESCRIPTION("Atmel SHA (1/256/224/384/512) hw acceleration support.");
2693 MODULE_LICENSE("GPL v2");
2694 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");
2695