1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include "debug.h"
8 #include "hal.h"
9 #include "hal_tx.h"
10 #include "hal_rx.h"
11 #include "hal_desc.h"
12 #include "hif.h"
13
ath12k_hal_reo_set_desc_hdr(struct hal_desc_header * hdr,u8 owner,u8 buffer_type,u32 magic)14 static void ath12k_hal_reo_set_desc_hdr(struct hal_desc_header *hdr,
15 u8 owner, u8 buffer_type, u32 magic)
16 {
17 hdr->info0 = le32_encode_bits(owner, HAL_DESC_HDR_INFO0_OWNER) |
18 le32_encode_bits(buffer_type, HAL_DESC_HDR_INFO0_BUF_TYPE);
19
20 /* Magic pattern in reserved bits for debugging */
21 hdr->info0 |= le32_encode_bits(magic, HAL_DESC_HDR_INFO0_DBG_RESERVED);
22 }
23
ath12k_hal_reo_cmd_queue_stats(struct hal_tlv_64_hdr * tlv,struct ath12k_hal_reo_cmd * cmd)24 static int ath12k_hal_reo_cmd_queue_stats(struct hal_tlv_64_hdr *tlv,
25 struct ath12k_hal_reo_cmd *cmd)
26 {
27 struct hal_reo_get_queue_stats *desc;
28
29 tlv->tl = le64_encode_bits(HAL_REO_GET_QUEUE_STATS, HAL_TLV_HDR_TAG) |
30 le64_encode_bits(sizeof(*desc), HAL_TLV_HDR_LEN);
31
32 desc = (struct hal_reo_get_queue_stats *)tlv->value;
33 memset_startat(desc, 0, queue_addr_lo);
34
35 desc->cmd.info0 &= ~cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED);
36 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS)
37 desc->cmd.info0 |= cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED);
38
39 desc->queue_addr_lo = cpu_to_le32(cmd->addr_lo);
40 desc->info0 = le32_encode_bits(cmd->addr_hi,
41 HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI);
42 if (cmd->flag & HAL_REO_CMD_FLG_STATS_CLEAR)
43 desc->info0 |= cpu_to_le32(HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS);
44
45 return le32_get_bits(desc->cmd.info0, HAL_REO_CMD_HDR_INFO0_CMD_NUMBER);
46 }
47
ath12k_hal_reo_cmd_flush_cache(struct ath12k_hal * hal,struct hal_tlv_64_hdr * tlv,struct ath12k_hal_reo_cmd * cmd)48 static int ath12k_hal_reo_cmd_flush_cache(struct ath12k_hal *hal,
49 struct hal_tlv_64_hdr *tlv,
50 struct ath12k_hal_reo_cmd *cmd)
51 {
52 struct hal_reo_flush_cache *desc;
53 u8 avail_slot = ffz(hal->avail_blk_resource);
54
55 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) {
56 if (avail_slot >= HAL_MAX_AVAIL_BLK_RES)
57 return -ENOSPC;
58
59 hal->current_blk_index = avail_slot;
60 }
61
62 tlv->tl = le64_encode_bits(HAL_REO_FLUSH_CACHE, HAL_TLV_HDR_TAG) |
63 le64_encode_bits(sizeof(*desc), HAL_TLV_HDR_LEN);
64
65 desc = (struct hal_reo_flush_cache *)tlv->value;
66 memset_startat(desc, 0, cache_addr_lo);
67
68 desc->cmd.info0 &= ~cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED);
69 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS)
70 desc->cmd.info0 |= cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED);
71
72 desc->cache_addr_lo = cpu_to_le32(cmd->addr_lo);
73 desc->info0 = le32_encode_bits(cmd->addr_hi,
74 HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI);
75
76 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS)
77 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS);
78
79 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) {
80 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE);
81 desc->info0 |=
82 le32_encode_bits(avail_slot,
83 HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX);
84 }
85
86 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_NO_INVAL)
87 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE);
88
89 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_ALL)
90 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL);
91
92 return le32_get_bits(desc->cmd.info0, HAL_REO_CMD_HDR_INFO0_CMD_NUMBER);
93 }
94
ath12k_hal_reo_cmd_update_rx_queue(struct hal_tlv_64_hdr * tlv,struct ath12k_hal_reo_cmd * cmd)95 static int ath12k_hal_reo_cmd_update_rx_queue(struct hal_tlv_64_hdr *tlv,
96 struct ath12k_hal_reo_cmd *cmd)
97 {
98 struct hal_reo_update_rx_queue *desc;
99
100 tlv->tl = le64_encode_bits(HAL_REO_UPDATE_RX_REO_QUEUE, HAL_TLV_HDR_TAG) |
101 le64_encode_bits(sizeof(*desc), HAL_TLV_HDR_LEN);
102
103 desc = (struct hal_reo_update_rx_queue *)tlv->value;
104 memset_startat(desc, 0, queue_addr_lo);
105
106 desc->cmd.info0 &= ~cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED);
107 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS)
108 desc->cmd.info0 |= cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED);
109
110 desc->queue_addr_lo = cpu_to_le32(cmd->addr_lo);
111 desc->info0 =
112 le32_encode_bits(cmd->addr_hi,
113 HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI) |
114 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_RX_QUEUE_NUM),
115 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM) |
116 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_VLD),
117 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD) |
118 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_ALDC),
119 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT) |
120 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_DIS_DUP_DETECTION),
121 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION) |
122 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_SOFT_REORDER_EN),
123 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN) |
124 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_AC),
125 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC) |
126 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_BAR),
127 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR) |
128 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_RETRY),
129 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY) |
130 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_CHECK_2K_MODE),
131 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE) |
132 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_OOR_MODE),
133 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE) |
134 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_BA_WINDOW_SIZE),
135 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE) |
136 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_CHECK),
137 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK) |
138 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_EVEN_PN),
139 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN) |
140 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_UNEVEN_PN),
141 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN) |
142 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE),
143 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE) |
144 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_SIZE),
145 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE) |
146 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG),
147 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG) |
148 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_SVLD),
149 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD) |
150 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_SSN),
151 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN) |
152 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_SEQ_2K_ERR),
153 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR) |
154 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_VALID),
155 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID) |
156 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN),
157 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN);
158
159 desc->info1 =
160 le32_encode_bits(cmd->rx_queue_num,
161 HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER) |
162 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_VLD),
163 HAL_REO_UPD_RX_QUEUE_INFO1_VLD) |
164 le32_encode_bits(u32_get_bits(cmd->upd1, HAL_REO_CMD_UPD1_ALDC),
165 HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER) |
166 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_DIS_DUP_DETECTION),
167 HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION) |
168 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_SOFT_REORDER_EN),
169 HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN) |
170 le32_encode_bits(u32_get_bits(cmd->upd1, HAL_REO_CMD_UPD1_AC),
171 HAL_REO_UPD_RX_QUEUE_INFO1_AC) |
172 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_BAR),
173 HAL_REO_UPD_RX_QUEUE_INFO1_BAR) |
174 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_CHECK_2K_MODE),
175 HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE) |
176 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_RETRY),
177 HAL_REO_UPD_RX_QUEUE_INFO1_RETRY) |
178 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_OOR_MODE),
179 HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE) |
180 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_CHECK),
181 HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK) |
182 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_EVEN_PN),
183 HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN) |
184 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_UNEVEN_PN),
185 HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN) |
186 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE),
187 HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE) |
188 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG),
189 HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG);
190
191 if (cmd->pn_size == 24)
192 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_24;
193 else if (cmd->pn_size == 48)
194 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_48;
195 else if (cmd->pn_size == 128)
196 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_128;
197
198 if (cmd->ba_window_size < 1)
199 cmd->ba_window_size = 1;
200
201 if (cmd->ba_window_size == 1)
202 cmd->ba_window_size++;
203
204 desc->info2 =
205 le32_encode_bits(cmd->ba_window_size - 1,
206 HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE) |
207 le32_encode_bits(cmd->pn_size, HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE) |
208 le32_encode_bits(!!(cmd->upd2 & HAL_REO_CMD_UPD2_SVLD),
209 HAL_REO_UPD_RX_QUEUE_INFO2_SVLD) |
210 le32_encode_bits(u32_get_bits(cmd->upd2, HAL_REO_CMD_UPD2_SSN),
211 HAL_REO_UPD_RX_QUEUE_INFO2_SSN) |
212 le32_encode_bits(!!(cmd->upd2 & HAL_REO_CMD_UPD2_SEQ_2K_ERR),
213 HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR) |
214 le32_encode_bits(!!(cmd->upd2 & HAL_REO_CMD_UPD2_PN_ERR),
215 HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR);
216
217 return le32_get_bits(desc->cmd.info0, HAL_REO_CMD_HDR_INFO0_CMD_NUMBER);
218 }
219
ath12k_hal_reo_cmd_send(struct ath12k_base * ab,struct hal_srng * srng,enum hal_reo_cmd_type type,struct ath12k_hal_reo_cmd * cmd)220 int ath12k_hal_reo_cmd_send(struct ath12k_base *ab, struct hal_srng *srng,
221 enum hal_reo_cmd_type type,
222 struct ath12k_hal_reo_cmd *cmd)
223 {
224 struct hal_tlv_64_hdr *reo_desc;
225 int ret;
226
227 spin_lock_bh(&srng->lock);
228
229 ath12k_hal_srng_access_begin(ab, srng);
230 reo_desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
231 if (!reo_desc) {
232 ret = -ENOBUFS;
233 goto out;
234 }
235
236 switch (type) {
237 case HAL_REO_CMD_GET_QUEUE_STATS:
238 ret = ath12k_hal_reo_cmd_queue_stats(reo_desc, cmd);
239 break;
240 case HAL_REO_CMD_FLUSH_CACHE:
241 ret = ath12k_hal_reo_cmd_flush_cache(&ab->hal, reo_desc, cmd);
242 break;
243 case HAL_REO_CMD_UPDATE_RX_QUEUE:
244 ret = ath12k_hal_reo_cmd_update_rx_queue(reo_desc, cmd);
245 break;
246 case HAL_REO_CMD_FLUSH_QUEUE:
247 case HAL_REO_CMD_UNBLOCK_CACHE:
248 case HAL_REO_CMD_FLUSH_TIMEOUT_LIST:
249 ath12k_warn(ab, "Unsupported reo command %d\n", type);
250 ret = -EOPNOTSUPP;
251 break;
252 default:
253 ath12k_warn(ab, "Unknown reo command %d\n", type);
254 ret = -EINVAL;
255 break;
256 }
257
258 out:
259 ath12k_hal_srng_access_end(ab, srng);
260 spin_unlock_bh(&srng->lock);
261
262 return ret;
263 }
264
ath12k_hal_rx_buf_addr_info_set(struct ath12k_buffer_addr * binfo,dma_addr_t paddr,u32 cookie,u8 manager)265 void ath12k_hal_rx_buf_addr_info_set(struct ath12k_buffer_addr *binfo,
266 dma_addr_t paddr, u32 cookie, u8 manager)
267 {
268 u32 paddr_lo, paddr_hi;
269
270 paddr_lo = lower_32_bits(paddr);
271 paddr_hi = upper_32_bits(paddr);
272 binfo->info0 = le32_encode_bits(paddr_lo, BUFFER_ADDR_INFO0_ADDR);
273 binfo->info1 = le32_encode_bits(paddr_hi, BUFFER_ADDR_INFO1_ADDR) |
274 le32_encode_bits(cookie, BUFFER_ADDR_INFO1_SW_COOKIE) |
275 le32_encode_bits(manager, BUFFER_ADDR_INFO1_RET_BUF_MGR);
276 }
277
ath12k_hal_rx_buf_addr_info_get(struct ath12k_buffer_addr * binfo,dma_addr_t * paddr,u32 * cookie,u8 * rbm)278 void ath12k_hal_rx_buf_addr_info_get(struct ath12k_buffer_addr *binfo,
279 dma_addr_t *paddr,
280 u32 *cookie, u8 *rbm)
281 {
282 *paddr = (((u64)le32_get_bits(binfo->info1, BUFFER_ADDR_INFO1_ADDR)) << 32) |
283 le32_get_bits(binfo->info0, BUFFER_ADDR_INFO0_ADDR);
284 *cookie = le32_get_bits(binfo->info1, BUFFER_ADDR_INFO1_SW_COOKIE);
285 *rbm = le32_get_bits(binfo->info1, BUFFER_ADDR_INFO1_RET_BUF_MGR);
286 }
287
ath12k_hal_rx_msdu_link_info_get(struct hal_rx_msdu_link * link,u32 * num_msdus,u32 * msdu_cookies,enum hal_rx_buf_return_buf_manager * rbm)288 void ath12k_hal_rx_msdu_link_info_get(struct hal_rx_msdu_link *link, u32 *num_msdus,
289 u32 *msdu_cookies,
290 enum hal_rx_buf_return_buf_manager *rbm)
291 {
292 struct hal_rx_msdu_details *msdu;
293 u32 val;
294 int i;
295
296 *num_msdus = HAL_NUM_RX_MSDUS_PER_LINK_DESC;
297
298 msdu = &link->msdu_link[0];
299 *rbm = le32_get_bits(msdu->buf_addr_info.info1,
300 BUFFER_ADDR_INFO1_RET_BUF_MGR);
301
302 for (i = 0; i < *num_msdus; i++) {
303 msdu = &link->msdu_link[i];
304
305 val = le32_get_bits(msdu->buf_addr_info.info0,
306 BUFFER_ADDR_INFO0_ADDR);
307 if (val == 0) {
308 *num_msdus = i;
309 break;
310 }
311 *msdu_cookies = le32_get_bits(msdu->buf_addr_info.info1,
312 BUFFER_ADDR_INFO1_SW_COOKIE);
313 msdu_cookies++;
314 }
315 }
316
ath12k_hal_desc_reo_parse_err(struct ath12k_base * ab,struct hal_reo_dest_ring * desc,dma_addr_t * paddr,u32 * desc_bank)317 int ath12k_hal_desc_reo_parse_err(struct ath12k_base *ab,
318 struct hal_reo_dest_ring *desc,
319 dma_addr_t *paddr, u32 *desc_bank)
320 {
321 enum hal_reo_dest_ring_push_reason push_reason;
322 enum hal_reo_dest_ring_error_code err_code;
323 u32 cookie, val;
324
325 push_reason = le32_get_bits(desc->info0,
326 HAL_REO_DEST_RING_INFO0_PUSH_REASON);
327 err_code = le32_get_bits(desc->info0,
328 HAL_REO_DEST_RING_INFO0_ERROR_CODE);
329 ab->device_stats.reo_error[err_code]++;
330
331 if (push_reason != HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED &&
332 push_reason != HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) {
333 ath12k_warn(ab, "expected error push reason code, received %d\n",
334 push_reason);
335 return -EINVAL;
336 }
337
338 val = le32_get_bits(desc->info0, HAL_REO_DEST_RING_INFO0_BUFFER_TYPE);
339 if (val != HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC) {
340 ath12k_warn(ab, "expected buffer type link_desc");
341 return -EINVAL;
342 }
343
344 ath12k_hal_rx_reo_ent_paddr_get(ab, &desc->buf_addr_info, paddr, &cookie);
345 *desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK);
346
347 return 0;
348 }
349
ath12k_hal_wbm_desc_parse_err(struct ath12k_base * ab,void * desc,struct hal_rx_wbm_rel_info * rel_info)350 int ath12k_hal_wbm_desc_parse_err(struct ath12k_base *ab, void *desc,
351 struct hal_rx_wbm_rel_info *rel_info)
352 {
353 struct hal_wbm_release_ring *wbm_desc = desc;
354 struct hal_wbm_release_ring_cc_rx *wbm_cc_desc = desc;
355 enum hal_wbm_rel_desc_type type;
356 enum hal_wbm_rel_src_module rel_src;
357 bool hw_cc_done;
358 u64 desc_va;
359 u32 val;
360
361 type = le32_get_bits(wbm_desc->info0, HAL_WBM_RELEASE_INFO0_DESC_TYPE);
362 /* We expect only WBM_REL buffer type */
363 if (type != HAL_WBM_REL_DESC_TYPE_REL_MSDU) {
364 WARN_ON(1);
365 return -EINVAL;
366 }
367
368 rel_src = le32_get_bits(wbm_desc->info0,
369 HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE);
370 if (rel_src != HAL_WBM_REL_SRC_MODULE_RXDMA &&
371 rel_src != HAL_WBM_REL_SRC_MODULE_REO)
372 return -EINVAL;
373
374 /* The format of wbm rel ring desc changes based on the
375 * hw cookie conversion status
376 */
377 hw_cc_done = le32_get_bits(wbm_desc->info0,
378 HAL_WBM_RELEASE_RX_INFO0_CC_STATUS);
379
380 if (!hw_cc_done) {
381 val = le32_get_bits(wbm_desc->buf_addr_info.info1,
382 BUFFER_ADDR_INFO1_RET_BUF_MGR);
383 if (val != HAL_RX_BUF_RBM_SW3_BM) {
384 ab->device_stats.invalid_rbm++;
385 return -EINVAL;
386 }
387
388 rel_info->cookie = le32_get_bits(wbm_desc->buf_addr_info.info1,
389 BUFFER_ADDR_INFO1_SW_COOKIE);
390
391 rel_info->rx_desc = NULL;
392 } else {
393 val = le32_get_bits(wbm_cc_desc->info0,
394 HAL_WBM_RELEASE_RX_CC_INFO0_RBM);
395 if (val != HAL_RX_BUF_RBM_SW3_BM) {
396 ab->device_stats.invalid_rbm++;
397 return -EINVAL;
398 }
399
400 rel_info->cookie = le32_get_bits(wbm_cc_desc->info1,
401 HAL_WBM_RELEASE_RX_CC_INFO1_COOKIE);
402
403 desc_va = ((u64)le32_to_cpu(wbm_cc_desc->buf_va_hi) << 32 |
404 le32_to_cpu(wbm_cc_desc->buf_va_lo));
405 rel_info->rx_desc =
406 (struct ath12k_rx_desc_info *)((unsigned long)desc_va);
407 }
408
409 rel_info->err_rel_src = rel_src;
410 rel_info->hw_cc_done = hw_cc_done;
411
412 rel_info->first_msdu = le32_get_bits(wbm_desc->info3,
413 HAL_WBM_RELEASE_INFO3_FIRST_MSDU);
414 rel_info->last_msdu = le32_get_bits(wbm_desc->info3,
415 HAL_WBM_RELEASE_INFO3_LAST_MSDU);
416 rel_info->continuation = le32_get_bits(wbm_desc->info3,
417 HAL_WBM_RELEASE_INFO3_CONTINUATION);
418
419 if (rel_info->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO) {
420 rel_info->push_reason =
421 le32_get_bits(wbm_desc->info0,
422 HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON);
423 rel_info->err_code =
424 le32_get_bits(wbm_desc->info0,
425 HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE);
426 } else {
427 rel_info->push_reason =
428 le32_get_bits(wbm_desc->info0,
429 HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON);
430 rel_info->err_code =
431 le32_get_bits(wbm_desc->info0,
432 HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE);
433 }
434
435 return 0;
436 }
437
ath12k_hal_rx_reo_ent_paddr_get(struct ath12k_base * ab,struct ath12k_buffer_addr * buff_addr,dma_addr_t * paddr,u32 * cookie)438 void ath12k_hal_rx_reo_ent_paddr_get(struct ath12k_base *ab,
439 struct ath12k_buffer_addr *buff_addr,
440 dma_addr_t *paddr, u32 *cookie)
441 {
442 *paddr = ((u64)(le32_get_bits(buff_addr->info1,
443 BUFFER_ADDR_INFO1_ADDR)) << 32) |
444 le32_get_bits(buff_addr->info0, BUFFER_ADDR_INFO0_ADDR);
445
446 *cookie = le32_get_bits(buff_addr->info1, BUFFER_ADDR_INFO1_SW_COOKIE);
447 }
448
ath12k_hal_rx_reo_ent_buf_paddr_get(void * rx_desc,dma_addr_t * paddr,u32 * sw_cookie,struct ath12k_buffer_addr ** pp_buf_addr,u8 * rbm,u32 * msdu_cnt)449 void ath12k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc, dma_addr_t *paddr,
450 u32 *sw_cookie,
451 struct ath12k_buffer_addr **pp_buf_addr,
452 u8 *rbm, u32 *msdu_cnt)
453 {
454 struct hal_reo_entrance_ring *reo_ent_ring =
455 (struct hal_reo_entrance_ring *)rx_desc;
456 struct ath12k_buffer_addr *buf_addr_info;
457 struct rx_mpdu_desc *rx_mpdu_desc_info_details;
458
459 rx_mpdu_desc_info_details =
460 (struct rx_mpdu_desc *)&reo_ent_ring->rx_mpdu_info;
461
462 *msdu_cnt = le32_get_bits(rx_mpdu_desc_info_details->info0,
463 RX_MPDU_DESC_INFO0_MSDU_COUNT);
464
465 buf_addr_info = (struct ath12k_buffer_addr *)&reo_ent_ring->buf_addr_info;
466
467 *paddr = (((u64)le32_get_bits(buf_addr_info->info1,
468 BUFFER_ADDR_INFO1_ADDR)) << 32) |
469 le32_get_bits(buf_addr_info->info0,
470 BUFFER_ADDR_INFO0_ADDR);
471
472 *sw_cookie = le32_get_bits(buf_addr_info->info1,
473 BUFFER_ADDR_INFO1_SW_COOKIE);
474 *rbm = le32_get_bits(buf_addr_info->info1,
475 BUFFER_ADDR_INFO1_RET_BUF_MGR);
476
477 *pp_buf_addr = (void *)buf_addr_info;
478 }
479
ath12k_hal_rx_msdu_list_get(struct ath12k * ar,struct hal_rx_msdu_link * link_desc,struct hal_rx_msdu_list * msdu_list,u16 * num_msdus)480 void ath12k_hal_rx_msdu_list_get(struct ath12k *ar,
481 struct hal_rx_msdu_link *link_desc,
482 struct hal_rx_msdu_list *msdu_list,
483 u16 *num_msdus)
484 {
485 struct hal_rx_msdu_details *msdu_details = NULL;
486 struct rx_msdu_desc *msdu_desc_info = NULL;
487 u32 last = 0, first = 0;
488 u8 tmp = 0;
489 int i;
490
491 last = u32_encode_bits(last, RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
492 first = u32_encode_bits(first, RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
493 msdu_details = &link_desc->msdu_link[0];
494
495 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
496 if (!i && le32_get_bits(msdu_details[i].buf_addr_info.info0,
497 BUFFER_ADDR_INFO0_ADDR) == 0)
498 break;
499 if (le32_get_bits(msdu_details[i].buf_addr_info.info0,
500 BUFFER_ADDR_INFO0_ADDR) == 0) {
501 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
502 msdu_desc_info->info0 |= cpu_to_le32(last);
503 break;
504 }
505 msdu_desc_info = &msdu_details[i].rx_msdu_info;
506
507 if (!i)
508 msdu_desc_info->info0 |= cpu_to_le32(first);
509 else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
510 msdu_desc_info->info0 |= cpu_to_le32(last);
511 msdu_list->msdu_info[i].msdu_flags = le32_to_cpu(msdu_desc_info->info0);
512 msdu_list->msdu_info[i].msdu_len =
513 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
514 msdu_list->sw_cookie[i] =
515 le32_get_bits(msdu_details[i].buf_addr_info.info1,
516 BUFFER_ADDR_INFO1_SW_COOKIE);
517 tmp = le32_get_bits(msdu_details[i].buf_addr_info.info1,
518 BUFFER_ADDR_INFO1_RET_BUF_MGR);
519 msdu_list->paddr[i] =
520 ((u64)(le32_get_bits(msdu_details[i].buf_addr_info.info1,
521 BUFFER_ADDR_INFO1_ADDR)) << 32) |
522 le32_get_bits(msdu_details[i].buf_addr_info.info0,
523 BUFFER_ADDR_INFO0_ADDR);
524 msdu_list->rbm[i] = tmp;
525 }
526 *num_msdus = i;
527 }
528
ath12k_hal_rx_msdu_link_desc_set(struct ath12k_base * ab,struct hal_wbm_release_ring * desc,struct ath12k_buffer_addr * buf_addr_info,enum hal_wbm_rel_bm_act action)529 void ath12k_hal_rx_msdu_link_desc_set(struct ath12k_base *ab,
530 struct hal_wbm_release_ring *desc,
531 struct ath12k_buffer_addr *buf_addr_info,
532 enum hal_wbm_rel_bm_act action)
533 {
534 desc->buf_addr_info = *buf_addr_info;
535 desc->info0 |= le32_encode_bits(HAL_WBM_REL_SRC_MODULE_SW,
536 HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE) |
537 le32_encode_bits(action, HAL_WBM_RELEASE_INFO0_BM_ACTION) |
538 le32_encode_bits(HAL_WBM_REL_DESC_TYPE_MSDU_LINK,
539 HAL_WBM_RELEASE_INFO0_DESC_TYPE);
540 }
541
ath12k_hal_reo_status_queue_stats(struct ath12k_base * ab,struct hal_tlv_64_hdr * tlv,struct hal_reo_status * status)542 void ath12k_hal_reo_status_queue_stats(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv,
543 struct hal_reo_status *status)
544 {
545 struct hal_reo_get_queue_stats_status *desc =
546 (struct hal_reo_get_queue_stats_status *)tlv->value;
547
548 status->uniform_hdr.cmd_num =
549 le32_get_bits(desc->hdr.info0,
550 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM);
551 status->uniform_hdr.cmd_status =
552 le32_get_bits(desc->hdr.info0,
553 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS);
554
555 ath12k_dbg(ab, ATH12K_DBG_HAL, "Queue stats status:\n");
556 ath12k_dbg(ab, ATH12K_DBG_HAL, "header: cmd_num %d status %d\n",
557 status->uniform_hdr.cmd_num,
558 status->uniform_hdr.cmd_status);
559 ath12k_dbg(ab, ATH12K_DBG_HAL, "ssn %u cur_idx %u\n",
560 le32_get_bits(desc->info0,
561 HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN),
562 le32_get_bits(desc->info0,
563 HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX));
564 ath12k_dbg(ab, ATH12K_DBG_HAL, "pn = [%08x, %08x, %08x, %08x]\n",
565 desc->pn[0], desc->pn[1], desc->pn[2], desc->pn[3]);
566 ath12k_dbg(ab, ATH12K_DBG_HAL, "last_rx: enqueue_tstamp %08x dequeue_tstamp %08x\n",
567 desc->last_rx_enqueue_timestamp,
568 desc->last_rx_dequeue_timestamp);
569 ath12k_dbg(ab, ATH12K_DBG_HAL, "rx_bitmap [%08x %08x %08x %08x %08x %08x %08x %08x]\n",
570 desc->rx_bitmap[0], desc->rx_bitmap[1], desc->rx_bitmap[2],
571 desc->rx_bitmap[3], desc->rx_bitmap[4], desc->rx_bitmap[5],
572 desc->rx_bitmap[6], desc->rx_bitmap[7]);
573 ath12k_dbg(ab, ATH12K_DBG_HAL, "count: cur_mpdu %u cur_msdu %u\n",
574 le32_get_bits(desc->info1,
575 HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT),
576 le32_get_bits(desc->info1,
577 HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT));
578 ath12k_dbg(ab, ATH12K_DBG_HAL, "fwd_timeout %u fwd_bar %u dup_count %u\n",
579 le32_get_bits(desc->info2,
580 HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT),
581 le32_get_bits(desc->info2,
582 HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT),
583 le32_get_bits(desc->info2,
584 HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT));
585 ath12k_dbg(ab, ATH12K_DBG_HAL, "frames_in_order %u bar_rcvd %u\n",
586 le32_get_bits(desc->info3,
587 HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT),
588 le32_get_bits(desc->info3,
589 HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT));
590 ath12k_dbg(ab, ATH12K_DBG_HAL, "num_mpdus %d num_msdus %d total_bytes %d\n",
591 desc->num_mpdu_frames, desc->num_msdu_frames,
592 desc->total_bytes);
593 ath12k_dbg(ab, ATH12K_DBG_HAL, "late_rcvd %u win_jump_2k %u hole_cnt %u\n",
594 le32_get_bits(desc->info4,
595 HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU),
596 le32_get_bits(desc->info2,
597 HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_WINDOW_JMP2K),
598 le32_get_bits(desc->info4,
599 HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT));
600 ath12k_dbg(ab, ATH12K_DBG_HAL, "looping count %u\n",
601 le32_get_bits(desc->info5,
602 HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT));
603 }
604
ath12k_hal_reo_flush_queue_status(struct ath12k_base * ab,struct hal_tlv_64_hdr * tlv,struct hal_reo_status * status)605 void ath12k_hal_reo_flush_queue_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv,
606 struct hal_reo_status *status)
607 {
608 struct hal_reo_flush_queue_status *desc =
609 (struct hal_reo_flush_queue_status *)tlv->value;
610
611 status->uniform_hdr.cmd_num =
612 le32_get_bits(desc->hdr.info0,
613 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM);
614 status->uniform_hdr.cmd_status =
615 le32_get_bits(desc->hdr.info0,
616 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS);
617 status->u.flush_queue.err_detected =
618 le32_get_bits(desc->info0,
619 HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED);
620 }
621
ath12k_hal_reo_flush_cache_status(struct ath12k_base * ab,struct hal_tlv_64_hdr * tlv,struct hal_reo_status * status)622 void ath12k_hal_reo_flush_cache_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv,
623 struct hal_reo_status *status)
624 {
625 struct ath12k_hal *hal = &ab->hal;
626 struct hal_reo_flush_cache_status *desc =
627 (struct hal_reo_flush_cache_status *)tlv->value;
628
629 status->uniform_hdr.cmd_num =
630 le32_get_bits(desc->hdr.info0,
631 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM);
632 status->uniform_hdr.cmd_status =
633 le32_get_bits(desc->hdr.info0,
634 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS);
635
636 status->u.flush_cache.err_detected =
637 le32_get_bits(desc->info0,
638 HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR);
639 status->u.flush_cache.err_code =
640 le32_get_bits(desc->info0,
641 HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE);
642 if (!status->u.flush_cache.err_code)
643 hal->avail_blk_resource |= BIT(hal->current_blk_index);
644
645 status->u.flush_cache.cache_controller_flush_status_hit =
646 le32_get_bits(desc->info0,
647 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT);
648
649 status->u.flush_cache.cache_controller_flush_status_desc_type =
650 le32_get_bits(desc->info0,
651 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE);
652 status->u.flush_cache.cache_controller_flush_status_client_id =
653 le32_get_bits(desc->info0,
654 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID);
655 status->u.flush_cache.cache_controller_flush_status_err =
656 le32_get_bits(desc->info0,
657 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR);
658 status->u.flush_cache.cache_controller_flush_status_cnt =
659 le32_get_bits(desc->info0,
660 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT);
661 }
662
ath12k_hal_reo_unblk_cache_status(struct ath12k_base * ab,struct hal_tlv_64_hdr * tlv,struct hal_reo_status * status)663 void ath12k_hal_reo_unblk_cache_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv,
664 struct hal_reo_status *status)
665 {
666 struct ath12k_hal *hal = &ab->hal;
667 struct hal_reo_unblock_cache_status *desc =
668 (struct hal_reo_unblock_cache_status *)tlv->value;
669
670 status->uniform_hdr.cmd_num =
671 le32_get_bits(desc->hdr.info0,
672 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM);
673 status->uniform_hdr.cmd_status =
674 le32_get_bits(desc->hdr.info0,
675 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS);
676
677 status->u.unblock_cache.err_detected =
678 le32_get_bits(desc->info0,
679 HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR);
680 status->u.unblock_cache.unblock_type =
681 le32_get_bits(desc->info0,
682 HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE);
683
684 if (!status->u.unblock_cache.err_detected &&
685 status->u.unblock_cache.unblock_type ==
686 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE)
687 hal->avail_blk_resource &= ~BIT(hal->current_blk_index);
688 }
689
ath12k_hal_reo_flush_timeout_list_status(struct ath12k_base * ab,struct hal_tlv_64_hdr * tlv,struct hal_reo_status * status)690 void ath12k_hal_reo_flush_timeout_list_status(struct ath12k_base *ab,
691 struct hal_tlv_64_hdr *tlv,
692 struct hal_reo_status *status)
693 {
694 struct hal_reo_flush_timeout_list_status *desc =
695 (struct hal_reo_flush_timeout_list_status *)tlv->value;
696
697 status->uniform_hdr.cmd_num =
698 le32_get_bits(desc->hdr.info0,
699 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM);
700 status->uniform_hdr.cmd_status =
701 le32_get_bits(desc->hdr.info0,
702 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS);
703
704 status->u.timeout_list.err_detected =
705 le32_get_bits(desc->info0,
706 HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR);
707 status->u.timeout_list.list_empty =
708 le32_get_bits(desc->info0,
709 HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY);
710
711 status->u.timeout_list.release_desc_cnt =
712 le32_get_bits(desc->info1,
713 HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT);
714 status->u.timeout_list.fwd_buf_cnt =
715 le32_get_bits(desc->info0,
716 HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT);
717 }
718
ath12k_hal_reo_desc_thresh_reached_status(struct ath12k_base * ab,struct hal_tlv_64_hdr * tlv,struct hal_reo_status * status)719 void ath12k_hal_reo_desc_thresh_reached_status(struct ath12k_base *ab,
720 struct hal_tlv_64_hdr *tlv,
721 struct hal_reo_status *status)
722 {
723 struct hal_reo_desc_thresh_reached_status *desc =
724 (struct hal_reo_desc_thresh_reached_status *)tlv->value;
725
726 status->uniform_hdr.cmd_num =
727 le32_get_bits(desc->hdr.info0,
728 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM);
729 status->uniform_hdr.cmd_status =
730 le32_get_bits(desc->hdr.info0,
731 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS);
732
733 status->u.desc_thresh_reached.threshold_idx =
734 le32_get_bits(desc->info0,
735 HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX);
736
737 status->u.desc_thresh_reached.link_desc_counter0 =
738 le32_get_bits(desc->info1,
739 HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0);
740
741 status->u.desc_thresh_reached.link_desc_counter1 =
742 le32_get_bits(desc->info2,
743 HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1);
744
745 status->u.desc_thresh_reached.link_desc_counter2 =
746 le32_get_bits(desc->info3,
747 HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2);
748
749 status->u.desc_thresh_reached.link_desc_counter_sum =
750 le32_get_bits(desc->info4,
751 HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM);
752 }
753
ath12k_hal_reo_update_rx_reo_queue_status(struct ath12k_base * ab,struct hal_tlv_64_hdr * tlv,struct hal_reo_status * status)754 void ath12k_hal_reo_update_rx_reo_queue_status(struct ath12k_base *ab,
755 struct hal_tlv_64_hdr *tlv,
756 struct hal_reo_status *status)
757 {
758 struct hal_reo_status_hdr *desc =
759 (struct hal_reo_status_hdr *)tlv->value;
760
761 status->uniform_hdr.cmd_num =
762 le32_get_bits(desc->info0,
763 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM);
764 status->uniform_hdr.cmd_status =
765 le32_get_bits(desc->info0,
766 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS);
767 }
768
ath12k_hal_reo_qdesc_size(u32 ba_window_size,u8 tid)769 u32 ath12k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid)
770 {
771 u32 num_ext_desc, num_1k_desc = 0;
772
773 if (ba_window_size <= 1) {
774 if (tid != HAL_DESC_REO_NON_QOS_TID)
775 num_ext_desc = 1;
776 else
777 num_ext_desc = 0;
778
779 } else if (ba_window_size <= 105) {
780 num_ext_desc = 1;
781 } else if (ba_window_size <= 210) {
782 num_ext_desc = 2;
783 } else if (ba_window_size <= 256) {
784 num_ext_desc = 3;
785 } else {
786 num_ext_desc = 10;
787 num_1k_desc = 1;
788 }
789
790 return sizeof(struct hal_rx_reo_queue) +
791 (num_ext_desc * sizeof(struct hal_rx_reo_queue_ext)) +
792 (num_1k_desc * sizeof(struct hal_rx_reo_queue_1k));
793 }
794
ath12k_hal_reo_qdesc_setup(struct hal_rx_reo_queue * qdesc,int tid,u32 ba_window_size,u32 start_seq,enum hal_pn_type type)795 void ath12k_hal_reo_qdesc_setup(struct hal_rx_reo_queue *qdesc,
796 int tid, u32 ba_window_size,
797 u32 start_seq, enum hal_pn_type type)
798 {
799 struct hal_rx_reo_queue_ext *ext_desc;
800
801 ath12k_hal_reo_set_desc_hdr(&qdesc->desc_hdr, HAL_DESC_REO_OWNED,
802 HAL_DESC_REO_QUEUE_DESC,
803 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0);
804
805 qdesc->rx_queue_num = le32_encode_bits(tid, HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER);
806
807 qdesc->info0 =
808 le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_VLD) |
809 le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER) |
810 le32_encode_bits(ath12k_tid_to_ac(tid), HAL_RX_REO_QUEUE_INFO0_AC);
811
812 if (ba_window_size < 1)
813 ba_window_size = 1;
814
815 if (ba_window_size == 1 && tid != HAL_DESC_REO_NON_QOS_TID)
816 ba_window_size++;
817
818 if (ba_window_size == 1)
819 qdesc->info0 |= le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_RETRY);
820
821 qdesc->info0 |= le32_encode_bits(ba_window_size - 1,
822 HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE);
823 switch (type) {
824 case HAL_PN_TYPE_NONE:
825 case HAL_PN_TYPE_WAPI_EVEN:
826 case HAL_PN_TYPE_WAPI_UNEVEN:
827 break;
828 case HAL_PN_TYPE_WPA:
829 qdesc->info0 |=
830 le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_PN_CHECK) |
831 le32_encode_bits(HAL_RX_REO_QUEUE_PN_SIZE_48,
832 HAL_RX_REO_QUEUE_INFO0_PN_SIZE);
833 break;
834 }
835
836 /* TODO: Set Ignore ampdu flags based on BA window size and/or
837 * AMPDU capabilities
838 */
839 qdesc->info0 |= le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG);
840
841 qdesc->info1 |= le32_encode_bits(0, HAL_RX_REO_QUEUE_INFO1_SVLD);
842
843 if (start_seq <= 0xfff)
844 qdesc->info1 = le32_encode_bits(start_seq,
845 HAL_RX_REO_QUEUE_INFO1_SSN);
846
847 if (tid == HAL_DESC_REO_NON_QOS_TID)
848 return;
849
850 ext_desc = qdesc->ext_desc;
851
852 /* TODO: HW queue descriptors are currently allocated for max BA
853 * window size for all QOS TIDs so that same descriptor can be used
854 * later when ADDBA request is received. This should be changed to
855 * allocate HW queue descriptors based on BA window size being
856 * negotiated (0 for non BA cases), and reallocate when BA window
857 * size changes and also send WMI message to FW to change the REO
858 * queue descriptor in Rx peer entry as part of dp_rx_tid_update.
859 */
860 memset(ext_desc, 0, 3 * sizeof(*ext_desc));
861 ath12k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED,
862 HAL_DESC_REO_QUEUE_EXT_DESC,
863 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1);
864 ext_desc++;
865 ath12k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED,
866 HAL_DESC_REO_QUEUE_EXT_DESC,
867 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2);
868 ext_desc++;
869 ath12k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED,
870 HAL_DESC_REO_QUEUE_EXT_DESC,
871 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3);
872 }
873
ath12k_hal_reo_init_cmd_ring(struct ath12k_base * ab,struct hal_srng * srng)874 void ath12k_hal_reo_init_cmd_ring(struct ath12k_base *ab,
875 struct hal_srng *srng)
876 {
877 struct hal_srng_params params;
878 struct hal_tlv_64_hdr *tlv;
879 struct hal_reo_get_queue_stats *desc;
880 int i, cmd_num = 1;
881 int entry_size;
882 u8 *entry;
883
884 memset(¶ms, 0, sizeof(params));
885
886 entry_size = ath12k_hal_srng_get_entrysize(ab, HAL_REO_CMD);
887 ath12k_hal_srng_get_params(ab, srng, ¶ms);
888 entry = (u8 *)params.ring_base_vaddr;
889
890 for (i = 0; i < params.num_entries; i++) {
891 tlv = (struct hal_tlv_64_hdr *)entry;
892 desc = (struct hal_reo_get_queue_stats *)tlv->value;
893 desc->cmd.info0 = le32_encode_bits(cmd_num++,
894 HAL_REO_CMD_HDR_INFO0_CMD_NUMBER);
895 entry += entry_size;
896 }
897 }
898
ath12k_hal_reo_hw_setup(struct ath12k_base * ab,u32 ring_hash_map)899 void ath12k_hal_reo_hw_setup(struct ath12k_base *ab, u32 ring_hash_map)
900 {
901 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
902 u32 val;
903
904 val = ath12k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
905
906 val |= u32_encode_bits(1, HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE) |
907 u32_encode_bits(1, HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE);
908 ath12k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
909
910 val = ath12k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTRL_ADDR(ab));
911
912 val &= ~(HAL_REO1_MISC_CTL_FRAG_DST_RING |
913 HAL_REO1_MISC_CTL_BAR_DST_RING);
914 val |= u32_encode_bits(HAL_SRNG_RING_ID_REO2SW0,
915 HAL_REO1_MISC_CTL_FRAG_DST_RING);
916 val |= u32_encode_bits(HAL_SRNG_RING_ID_REO2SW0,
917 HAL_REO1_MISC_CTL_BAR_DST_RING);
918 ath12k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTRL_ADDR(ab), val);
919
920 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
921 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC);
922 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
923 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC);
924 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
925 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC);
926 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
927 HAL_DEFAULT_VO_REO_TIMEOUT_USEC);
928
929 ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
930 ring_hash_map);
931 ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
932 ring_hash_map);
933 }
934
ath12k_hal_reo_shared_qaddr_cache_clear(struct ath12k_base * ab)935 void ath12k_hal_reo_shared_qaddr_cache_clear(struct ath12k_base *ab)
936 {
937 u32 val;
938
939 lockdep_assert_held(&ab->base_lock);
940 val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_REO_REG +
941 HAL_REO1_QDESC_ADDR(ab));
942
943 val |= u32_encode_bits(1, HAL_REO_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY);
944 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG +
945 HAL_REO1_QDESC_ADDR(ab), val);
946
947 val &= ~HAL_REO_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY;
948 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG +
949 HAL_REO1_QDESC_ADDR(ab), val);
950 }
951