1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022, 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include "dp_rx.h"
8 #include "debug.h"
9 #include "hif.h"
10
11 const struct ce_attr ath12k_host_ce_config_qcn9274[] = {
12 /* CE0: host->target HTC control and raw streams */
13 {
14 .flags = CE_ATTR_FLAGS,
15 .src_nentries = 16,
16 .src_sz_max = 2048,
17 .dest_nentries = 0,
18 },
19
20 /* CE1: target->host HTT + HTC control */
21 {
22 .flags = CE_ATTR_FLAGS,
23 .src_nentries = 0,
24 .src_sz_max = 2048,
25 .dest_nentries = 512,
26 .recv_cb = ath12k_htc_rx_completion_handler,
27 },
28
29 /* CE2: target->host WMI */
30 {
31 .flags = CE_ATTR_FLAGS,
32 .src_nentries = 0,
33 .src_sz_max = 2048,
34 .dest_nentries = 128,
35 .recv_cb = ath12k_htc_rx_completion_handler,
36 },
37
38 /* CE3: host->target WMI (mac0) */
39 {
40 .flags = CE_ATTR_FLAGS,
41 .src_nentries = 32,
42 .src_sz_max = 2048,
43 .dest_nentries = 0,
44 },
45
46 /* CE4: host->target HTT */
47 {
48 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
49 .src_nentries = 2048,
50 .src_sz_max = 256,
51 .dest_nentries = 0,
52 },
53
54 /* CE5: target->host pktlog */
55 {
56 .flags = CE_ATTR_FLAGS,
57 .src_nentries = 0,
58 .src_sz_max = 2048,
59 .dest_nentries = 512,
60 .recv_cb = ath12k_dp_htt_htc_t2h_msg_handler,
61 },
62
63 /* CE6: target autonomous hif_memcpy */
64 {
65 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
66 .src_nentries = 0,
67 .src_sz_max = 0,
68 .dest_nentries = 0,
69 },
70
71 /* CE7: host->target WMI (mac1) */
72 {
73 .flags = CE_ATTR_FLAGS,
74 .src_nentries = 32,
75 .src_sz_max = 2048,
76 .dest_nentries = 0,
77 },
78
79 /* CE8: target autonomous hif_memcpy */
80 {
81 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
82 .src_nentries = 0,
83 .src_sz_max = 0,
84 .dest_nentries = 0,
85 },
86
87 /* CE9: MHI */
88 {
89 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
90 .src_nentries = 0,
91 .src_sz_max = 0,
92 .dest_nentries = 0,
93 },
94
95 /* CE10: MHI */
96 {
97 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
98 .src_nentries = 0,
99 .src_sz_max = 0,
100 .dest_nentries = 0,
101 },
102
103 /* CE11: MHI */
104 {
105 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
106 .src_nentries = 0,
107 .src_sz_max = 0,
108 .dest_nentries = 0,
109 },
110
111 /* CE12: CV Prefetch */
112 {
113 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
114 .src_nentries = 0,
115 .src_sz_max = 0,
116 .dest_nentries = 0,
117 },
118
119 /* CE13: CV Prefetch */
120 {
121 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
122 .src_nentries = 0,
123 .src_sz_max = 0,
124 .dest_nentries = 0,
125 },
126
127 /* CE14: target->host dbg log */
128 {
129 .flags = CE_ATTR_FLAGS,
130 .src_nentries = 0,
131 .src_sz_max = 2048,
132 .dest_nentries = 512,
133 .recv_cb = ath12k_htc_rx_completion_handler,
134 },
135
136 /* CE15: reserved for future use */
137 {
138 .flags = (CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
139 .src_nentries = 0,
140 .src_sz_max = 0,
141 .dest_nentries = 0,
142 },
143 };
144
145 const struct ce_attr ath12k_host_ce_config_wcn7850[] = {
146 /* CE0: host->target HTC control and raw streams */
147 {
148 .flags = CE_ATTR_FLAGS,
149 .src_nentries = 16,
150 .src_sz_max = 2048,
151 .dest_nentries = 0,
152 },
153
154 /* CE1: target->host HTT + HTC control */
155 {
156 .flags = CE_ATTR_FLAGS,
157 .src_nentries = 0,
158 .src_sz_max = 2048,
159 .dest_nentries = 512,
160 .recv_cb = ath12k_htc_rx_completion_handler,
161 },
162
163 /* CE2: target->host WMI */
164 {
165 .flags = CE_ATTR_FLAGS,
166 .src_nentries = 0,
167 .src_sz_max = 2048,
168 .dest_nentries = 64,
169 .recv_cb = ath12k_htc_rx_completion_handler,
170 },
171
172 /* CE3: host->target WMI (mac0) */
173 {
174 .flags = CE_ATTR_FLAGS,
175 .src_nentries = 32,
176 .src_sz_max = 2048,
177 .dest_nentries = 0,
178 },
179
180 /* CE4: host->target HTT */
181 {
182 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
183 .src_nentries = 2048,
184 .src_sz_max = 256,
185 .dest_nentries = 0,
186 },
187
188 /* CE5: target->host pktlog */
189 {
190 .flags = CE_ATTR_FLAGS,
191 .src_nentries = 0,
192 .src_sz_max = 0,
193 .dest_nentries = 0,
194 },
195
196 /* CE6: target autonomous hif_memcpy */
197 {
198 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
199 .src_nentries = 0,
200 .src_sz_max = 0,
201 .dest_nentries = 0,
202 },
203
204 /* CE7: host->target WMI (mac1) */
205 {
206 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
207 .src_nentries = 0,
208 .src_sz_max = 2048,
209 .dest_nentries = 0,
210 },
211
212 /* CE8: target autonomous hif_memcpy */
213 {
214 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
215 .src_nentries = 0,
216 .src_sz_max = 0,
217 .dest_nentries = 0,
218 },
219
220 };
221
222 const struct ce_attr ath12k_host_ce_config_ipq5332[] = {
223 /* CE0: host->target HTC control and raw streams */
224 {
225 .flags = CE_ATTR_FLAGS,
226 .src_nentries = 16,
227 .src_sz_max = 2048,
228 .dest_nentries = 0,
229 },
230 /* CE1: target->host HTT + HTC control */
231 {
232 .flags = CE_ATTR_FLAGS,
233 .src_nentries = 0,
234 .src_sz_max = 2048,
235 .dest_nentries = 512,
236 .recv_cb = ath12k_htc_rx_completion_handler,
237 },
238 /* CE2: target->host WMI */
239 {
240 .flags = CE_ATTR_FLAGS,
241 .src_nentries = 0,
242 .src_sz_max = 2048,
243 .dest_nentries = 128,
244 .recv_cb = ath12k_htc_rx_completion_handler,
245 },
246 /* CE3: host->target WMI */
247 {
248 .flags = CE_ATTR_FLAGS,
249 .src_nentries = 32,
250 .src_sz_max = 2048,
251 .dest_nentries = 0,
252 },
253 /* CE4: host->target HTT */
254 {
255 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
256 .src_nentries = 2048,
257 .src_sz_max = 256,
258 .dest_nentries = 0,
259 },
260 /* CE5: target -> host PKTLOG */
261 {
262 .flags = CE_ATTR_FLAGS,
263 .src_nentries = 0,
264 .src_sz_max = 2048,
265 .dest_nentries = 512,
266 .recv_cb = ath12k_dp_htt_htc_t2h_msg_handler,
267 },
268 /* CE6: Target autonomous HIF_memcpy */
269 {
270 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
271 .src_nentries = 0,
272 .src_sz_max = 0,
273 .dest_nentries = 0,
274 },
275 /* CE7: CV Prefetch */
276 {
277 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
278 .src_nentries = 0,
279 .src_sz_max = 0,
280 .dest_nentries = 0,
281 },
282 /* CE8: Target HIF memcpy (Generic HIF memcypy) */
283 {
284 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
285 .src_nentries = 0,
286 .src_sz_max = 0,
287 .dest_nentries = 0,
288 },
289 /* CE9: WMI logging/CFR/Spectral/Radar */
290 {
291 .flags = CE_ATTR_FLAGS,
292 .src_nentries = 0,
293 .src_sz_max = 2048,
294 .dest_nentries = 128,
295 },
296 /* CE10: Unused */
297 {
298 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
299 .src_nentries = 0,
300 .src_sz_max = 0,
301 .dest_nentries = 0,
302 },
303 /* CE11: Unused */
304 {
305 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
306 .src_nentries = 0,
307 .src_sz_max = 0,
308 .dest_nentries = 0,
309 },
310 };
311
ath12k_ce_rx_buf_enqueue_pipe(struct ath12k_ce_pipe * pipe,struct sk_buff * skb,dma_addr_t paddr)312 static int ath12k_ce_rx_buf_enqueue_pipe(struct ath12k_ce_pipe *pipe,
313 struct sk_buff *skb, dma_addr_t paddr)
314 {
315 struct ath12k_base *ab = pipe->ab;
316 struct ath12k_ce_ring *ring = pipe->dest_ring;
317 struct hal_srng *srng;
318 unsigned int write_index;
319 unsigned int nentries_mask = ring->nentries_mask;
320 struct hal_ce_srng_dest_desc *desc;
321 int ret;
322
323 lockdep_assert_held(&ab->ce.ce_lock);
324
325 write_index = ring->write_index;
326
327 srng = &ab->hal.srng_list[ring->hal_ring_id];
328
329 spin_lock_bh(&srng->lock);
330
331 ath12k_hal_srng_access_begin(ab, srng);
332
333 if (unlikely(ath12k_hal_srng_src_num_free(ab, srng, false) < 1)) {
334 ret = -ENOSPC;
335 goto exit;
336 }
337
338 desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
339 if (!desc) {
340 ret = -ENOSPC;
341 goto exit;
342 }
343
344 ath12k_hal_ce_dst_set_desc(desc, paddr);
345
346 ring->skb[write_index] = skb;
347 write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
348 ring->write_index = write_index;
349
350 pipe->rx_buf_needed--;
351
352 ret = 0;
353 exit:
354 ath12k_hal_srng_access_end(ab, srng);
355
356 spin_unlock_bh(&srng->lock);
357
358 return ret;
359 }
360
ath12k_ce_rx_post_pipe(struct ath12k_ce_pipe * pipe)361 static int ath12k_ce_rx_post_pipe(struct ath12k_ce_pipe *pipe)
362 {
363 struct ath12k_base *ab = pipe->ab;
364 struct sk_buff *skb;
365 dma_addr_t paddr;
366 int ret = 0;
367
368 if (!(pipe->dest_ring || pipe->status_ring))
369 return 0;
370
371 spin_lock_bh(&ab->ce.ce_lock);
372 while (pipe->rx_buf_needed) {
373 skb = dev_alloc_skb(pipe->buf_sz);
374 if (!skb) {
375 ret = -ENOMEM;
376 goto exit;
377 }
378
379 WARN_ON_ONCE(!IS_ALIGNED((unsigned long)skb->data, 4));
380
381 paddr = dma_map_single(ab->dev, skb->data,
382 skb->len + skb_tailroom(skb),
383 DMA_FROM_DEVICE);
384 if (unlikely(dma_mapping_error(ab->dev, paddr))) {
385 ath12k_warn(ab, "failed to dma map ce rx buf\n");
386 dev_kfree_skb_any(skb);
387 ret = -EIO;
388 goto exit;
389 }
390
391 ATH12K_SKB_RXCB(skb)->paddr = paddr;
392
393 ret = ath12k_ce_rx_buf_enqueue_pipe(pipe, skb, paddr);
394 if (ret) {
395 ath12k_warn(ab, "failed to enqueue rx buf: %d\n", ret);
396 dma_unmap_single(ab->dev, paddr,
397 skb->len + skb_tailroom(skb),
398 DMA_FROM_DEVICE);
399 dev_kfree_skb_any(skb);
400 goto exit;
401 }
402 }
403
404 exit:
405 spin_unlock_bh(&ab->ce.ce_lock);
406 return ret;
407 }
408
ath12k_ce_completed_recv_next(struct ath12k_ce_pipe * pipe,struct sk_buff ** skb,int * nbytes)409 static int ath12k_ce_completed_recv_next(struct ath12k_ce_pipe *pipe,
410 struct sk_buff **skb, int *nbytes)
411 {
412 struct ath12k_base *ab = pipe->ab;
413 struct hal_ce_srng_dst_status_desc *desc;
414 struct hal_srng *srng;
415 unsigned int sw_index;
416 unsigned int nentries_mask;
417 int ret = 0;
418
419 spin_lock_bh(&ab->ce.ce_lock);
420
421 sw_index = pipe->dest_ring->sw_index;
422 nentries_mask = pipe->dest_ring->nentries_mask;
423
424 srng = &ab->hal.srng_list[pipe->status_ring->hal_ring_id];
425
426 spin_lock_bh(&srng->lock);
427
428 ath12k_hal_srng_access_begin(ab, srng);
429
430 desc = ath12k_hal_srng_dst_get_next_entry(ab, srng);
431 if (!desc) {
432 ret = -EIO;
433 goto err;
434 }
435
436 *nbytes = ath12k_hal_ce_dst_status_get_length(desc);
437
438 *skb = pipe->dest_ring->skb[sw_index];
439 pipe->dest_ring->skb[sw_index] = NULL;
440
441 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
442 pipe->dest_ring->sw_index = sw_index;
443
444 pipe->rx_buf_needed++;
445 err:
446 ath12k_hal_srng_access_end(ab, srng);
447
448 spin_unlock_bh(&srng->lock);
449
450 spin_unlock_bh(&ab->ce.ce_lock);
451
452 return ret;
453 }
454
ath12k_ce_recv_process_cb(struct ath12k_ce_pipe * pipe)455 static void ath12k_ce_recv_process_cb(struct ath12k_ce_pipe *pipe)
456 {
457 struct ath12k_base *ab = pipe->ab;
458 struct sk_buff *skb;
459 struct sk_buff_head list;
460 unsigned int nbytes, max_nbytes;
461 int ret;
462
463 __skb_queue_head_init(&list);
464 while (ath12k_ce_completed_recv_next(pipe, &skb, &nbytes) == 0) {
465 max_nbytes = skb->len + skb_tailroom(skb);
466 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
467 max_nbytes, DMA_FROM_DEVICE);
468
469 if (unlikely(max_nbytes < nbytes || nbytes == 0)) {
470 ath12k_warn(ab, "unexpected rx length (nbytes %d, max %d)",
471 nbytes, max_nbytes);
472 dev_kfree_skb_any(skb);
473 continue;
474 }
475
476 skb_put(skb, nbytes);
477 __skb_queue_tail(&list, skb);
478 }
479
480 while ((skb = __skb_dequeue(&list))) {
481 ath12k_dbg(ab, ATH12K_DBG_AHB, "rx ce pipe %d len %d\n",
482 pipe->pipe_num, skb->len);
483 pipe->recv_cb(ab, skb);
484 }
485
486 ret = ath12k_ce_rx_post_pipe(pipe);
487 if (ret && ret != -ENOSPC) {
488 ath12k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n",
489 pipe->pipe_num, ret);
490 mod_timer(&ab->rx_replenish_retry,
491 jiffies + ATH12K_CE_RX_POST_RETRY_JIFFIES);
492 }
493 }
494
ath12k_ce_completed_send_next(struct ath12k_ce_pipe * pipe)495 static struct sk_buff *ath12k_ce_completed_send_next(struct ath12k_ce_pipe *pipe)
496 {
497 struct ath12k_base *ab = pipe->ab;
498 struct hal_ce_srng_src_desc *desc;
499 struct hal_srng *srng;
500 unsigned int sw_index;
501 unsigned int nentries_mask;
502 struct sk_buff *skb;
503
504 spin_lock_bh(&ab->ce.ce_lock);
505
506 sw_index = pipe->src_ring->sw_index;
507 nentries_mask = pipe->src_ring->nentries_mask;
508
509 srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id];
510
511 spin_lock_bh(&srng->lock);
512
513 ath12k_hal_srng_access_begin(ab, srng);
514
515 desc = ath12k_hal_srng_src_reap_next(ab, srng);
516 if (!desc) {
517 skb = ERR_PTR(-EIO);
518 goto err_unlock;
519 }
520
521 skb = pipe->src_ring->skb[sw_index];
522
523 pipe->src_ring->skb[sw_index] = NULL;
524
525 sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
526 pipe->src_ring->sw_index = sw_index;
527
528 err_unlock:
529 spin_unlock_bh(&srng->lock);
530
531 spin_unlock_bh(&ab->ce.ce_lock);
532
533 return skb;
534 }
535
ath12k_ce_send_done_cb(struct ath12k_ce_pipe * pipe)536 static void ath12k_ce_send_done_cb(struct ath12k_ce_pipe *pipe)
537 {
538 struct ath12k_base *ab = pipe->ab;
539 struct sk_buff *skb;
540
541 while (!IS_ERR(skb = ath12k_ce_completed_send_next(pipe))) {
542 if (!skb)
543 continue;
544
545 dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr, skb->len,
546 DMA_TO_DEVICE);
547 dev_kfree_skb_any(skb);
548 }
549 }
550
ath12k_ce_srng_msi_ring_params_setup(struct ath12k_base * ab,u32 ce_id,struct hal_srng_params * ring_params)551 static void ath12k_ce_srng_msi_ring_params_setup(struct ath12k_base *ab, u32 ce_id,
552 struct hal_srng_params *ring_params)
553 {
554 u32 msi_data_start;
555 u32 msi_data_count, msi_data_idx;
556 u32 msi_irq_start;
557 u32 addr_lo;
558 u32 addr_hi;
559 int ret;
560
561 ret = ath12k_hif_get_user_msi_vector(ab, "CE",
562 &msi_data_count, &msi_data_start,
563 &msi_irq_start);
564
565 if (ret)
566 return;
567
568 ath12k_hif_get_msi_address(ab, &addr_lo, &addr_hi);
569 ath12k_hif_get_ce_msi_idx(ab, ce_id, &msi_data_idx);
570
571 ring_params->msi_addr = addr_lo;
572 ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32);
573 ring_params->msi_data = (msi_data_idx % msi_data_count) + msi_data_start;
574 ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR;
575 }
576
ath12k_ce_init_ring(struct ath12k_base * ab,struct ath12k_ce_ring * ce_ring,int ce_id,enum hal_ring_type type)577 static int ath12k_ce_init_ring(struct ath12k_base *ab,
578 struct ath12k_ce_ring *ce_ring,
579 int ce_id, enum hal_ring_type type)
580 {
581 struct hal_srng_params params = {};
582 int ret;
583
584 params.ring_base_paddr = ce_ring->base_addr_ce_space;
585 params.ring_base_vaddr = ce_ring->base_addr_owner_space;
586 params.num_entries = ce_ring->nentries;
587
588 if (!(CE_ATTR_DIS_INTR & ab->hw_params->host_ce_config[ce_id].flags))
589 ath12k_ce_srng_msi_ring_params_setup(ab, ce_id, ¶ms);
590
591 switch (type) {
592 case HAL_CE_SRC:
593 if (!(CE_ATTR_DIS_INTR & ab->hw_params->host_ce_config[ce_id].flags))
594 params.intr_batch_cntr_thres_entries = 1;
595 break;
596 case HAL_CE_DST:
597 params.max_buffer_len = ab->hw_params->host_ce_config[ce_id].src_sz_max;
598 if (!(ab->hw_params->host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) {
599 params.intr_timer_thres_us = 1024;
600 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN;
601 params.low_threshold = ce_ring->nentries - 3;
602 }
603 break;
604 case HAL_CE_DST_STATUS:
605 if (!(ab->hw_params->host_ce_config[ce_id].flags & CE_ATTR_DIS_INTR)) {
606 params.intr_batch_cntr_thres_entries = 1;
607 params.intr_timer_thres_us = 0x1000;
608 }
609 break;
610 default:
611 ath12k_warn(ab, "Invalid CE ring type %d\n", type);
612 return -EINVAL;
613 }
614
615 /* TODO: Init other params needed by HAL to init the ring */
616
617 ret = ath12k_hal_srng_setup(ab, type, ce_id, 0, ¶ms);
618 if (ret < 0) {
619 ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n",
620 ret, ce_id);
621 return ret;
622 }
623
624 ce_ring->hal_ring_id = ret;
625
626 return 0;
627 }
628
629 static struct ath12k_ce_ring *
ath12k_ce_alloc_ring(struct ath12k_base * ab,int nentries,int desc_sz)630 ath12k_ce_alloc_ring(struct ath12k_base *ab, int nentries, int desc_sz)
631 {
632 struct ath12k_ce_ring *ce_ring;
633 dma_addr_t base_addr;
634
635 ce_ring = kzalloc(struct_size(ce_ring, skb, nentries), GFP_KERNEL);
636 if (!ce_ring)
637 return ERR_PTR(-ENOMEM);
638
639 ce_ring->nentries = nentries;
640 ce_ring->nentries_mask = nentries - 1;
641
642 /* Legacy platforms that do not support cache
643 * coherent DMA are unsupported
644 */
645 ce_ring->base_addr_owner_space_unaligned =
646 dma_alloc_coherent(ab->dev,
647 nentries * desc_sz + CE_DESC_RING_ALIGN,
648 &base_addr, GFP_KERNEL);
649 if (!ce_ring->base_addr_owner_space_unaligned) {
650 kfree(ce_ring);
651 return ERR_PTR(-ENOMEM);
652 }
653
654 ce_ring->base_addr_ce_space_unaligned = base_addr;
655
656 ce_ring->base_addr_owner_space =
657 PTR_ALIGN(ce_ring->base_addr_owner_space_unaligned,
658 CE_DESC_RING_ALIGN);
659
660 ce_ring->base_addr_ce_space = ALIGN(ce_ring->base_addr_ce_space_unaligned,
661 CE_DESC_RING_ALIGN);
662
663 return ce_ring;
664 }
665
ath12k_ce_alloc_pipe(struct ath12k_base * ab,int ce_id)666 static int ath12k_ce_alloc_pipe(struct ath12k_base *ab, int ce_id)
667 {
668 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id];
669 const struct ce_attr *attr = &ab->hw_params->host_ce_config[ce_id];
670 struct ath12k_ce_ring *ring;
671 int nentries;
672 int desc_sz;
673
674 pipe->attr_flags = attr->flags;
675
676 if (attr->src_nentries) {
677 pipe->send_cb = ath12k_ce_send_done_cb;
678 nentries = roundup_pow_of_two(attr->src_nentries);
679 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_SRC);
680 ring = ath12k_ce_alloc_ring(ab, nentries, desc_sz);
681 if (IS_ERR(ring))
682 return PTR_ERR(ring);
683 pipe->src_ring = ring;
684 }
685
686 if (attr->dest_nentries) {
687 pipe->recv_cb = attr->recv_cb;
688 nentries = roundup_pow_of_two(attr->dest_nentries);
689 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST);
690 ring = ath12k_ce_alloc_ring(ab, nentries, desc_sz);
691 if (IS_ERR(ring))
692 return PTR_ERR(ring);
693 pipe->dest_ring = ring;
694
695 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS);
696 ring = ath12k_ce_alloc_ring(ab, nentries, desc_sz);
697 if (IS_ERR(ring))
698 return PTR_ERR(ring);
699 pipe->status_ring = ring;
700 }
701
702 return 0;
703 }
704
ath12k_ce_per_engine_service(struct ath12k_base * ab,u16 ce_id)705 void ath12k_ce_per_engine_service(struct ath12k_base *ab, u16 ce_id)
706 {
707 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id];
708
709 if (pipe->send_cb)
710 pipe->send_cb(pipe);
711
712 if (pipe->recv_cb)
713 ath12k_ce_recv_process_cb(pipe);
714 }
715
ath12k_ce_poll_send_completed(struct ath12k_base * ab,u8 pipe_id)716 void ath12k_ce_poll_send_completed(struct ath12k_base *ab, u8 pipe_id)
717 {
718 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id];
719
720 if ((pipe->attr_flags & CE_ATTR_DIS_INTR) && pipe->send_cb)
721 pipe->send_cb(pipe);
722 }
723
ath12k_ce_send(struct ath12k_base * ab,struct sk_buff * skb,u8 pipe_id,u16 transfer_id)724 int ath12k_ce_send(struct ath12k_base *ab, struct sk_buff *skb, u8 pipe_id,
725 u16 transfer_id)
726 {
727 struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id];
728 struct hal_ce_srng_src_desc *desc;
729 struct hal_srng *srng;
730 unsigned int write_index, sw_index;
731 unsigned int nentries_mask;
732 int ret = 0;
733 u8 byte_swap_data = 0;
734 int num_used;
735
736 /* Check if some entries could be regained by handling tx completion if
737 * the CE has interrupts disabled and the used entries is more than the
738 * defined usage threshold.
739 */
740 if (pipe->attr_flags & CE_ATTR_DIS_INTR) {
741 spin_lock_bh(&ab->ce.ce_lock);
742 write_index = pipe->src_ring->write_index;
743
744 sw_index = pipe->src_ring->sw_index;
745
746 if (write_index >= sw_index)
747 num_used = write_index - sw_index;
748 else
749 num_used = pipe->src_ring->nentries - sw_index +
750 write_index;
751
752 spin_unlock_bh(&ab->ce.ce_lock);
753
754 if (num_used > ATH12K_CE_USAGE_THRESHOLD)
755 ath12k_ce_poll_send_completed(ab, pipe->pipe_num);
756 }
757
758 if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags))
759 return -ESHUTDOWN;
760
761 spin_lock_bh(&ab->ce.ce_lock);
762
763 write_index = pipe->src_ring->write_index;
764 nentries_mask = pipe->src_ring->nentries_mask;
765
766 srng = &ab->hal.srng_list[pipe->src_ring->hal_ring_id];
767
768 spin_lock_bh(&srng->lock);
769
770 ath12k_hal_srng_access_begin(ab, srng);
771
772 if (unlikely(ath12k_hal_srng_src_num_free(ab, srng, false) < 1)) {
773 ath12k_hal_srng_access_end(ab, srng);
774 ret = -ENOBUFS;
775 goto unlock;
776 }
777
778 desc = ath12k_hal_srng_src_get_next_reaped(ab, srng);
779 if (!desc) {
780 ath12k_hal_srng_access_end(ab, srng);
781 ret = -ENOBUFS;
782 goto unlock;
783 }
784
785 if (pipe->attr_flags & CE_ATTR_BYTE_SWAP_DATA)
786 byte_swap_data = 1;
787
788 ath12k_hal_ce_src_set_desc(desc, ATH12K_SKB_CB(skb)->paddr,
789 skb->len, transfer_id, byte_swap_data);
790
791 pipe->src_ring->skb[write_index] = skb;
792 pipe->src_ring->write_index = CE_RING_IDX_INCR(nentries_mask,
793 write_index);
794
795 ath12k_hal_srng_access_end(ab, srng);
796
797 unlock:
798 spin_unlock_bh(&srng->lock);
799
800 spin_unlock_bh(&ab->ce.ce_lock);
801
802 return ret;
803 }
804
ath12k_ce_rx_pipe_cleanup(struct ath12k_ce_pipe * pipe)805 static void ath12k_ce_rx_pipe_cleanup(struct ath12k_ce_pipe *pipe)
806 {
807 struct ath12k_base *ab = pipe->ab;
808 struct ath12k_ce_ring *ring = pipe->dest_ring;
809 struct sk_buff *skb;
810 int i;
811
812 if (!(ring && pipe->buf_sz))
813 return;
814
815 for (i = 0; i < ring->nentries; i++) {
816 skb = ring->skb[i];
817 if (!skb)
818 continue;
819
820 ring->skb[i] = NULL;
821 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
822 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
823 dev_kfree_skb_any(skb);
824 }
825 }
826
ath12k_ce_cleanup_pipes(struct ath12k_base * ab)827 void ath12k_ce_cleanup_pipes(struct ath12k_base *ab)
828 {
829 struct ath12k_ce_pipe *pipe;
830 int pipe_num;
831
832 for (pipe_num = 0; pipe_num < ab->hw_params->ce_count; pipe_num++) {
833 pipe = &ab->ce.ce_pipe[pipe_num];
834 ath12k_ce_rx_pipe_cleanup(pipe);
835
836 /* Cleanup any src CE's which have interrupts disabled */
837 ath12k_ce_poll_send_completed(ab, pipe_num);
838
839 /* NOTE: Should we also clean up tx buffer in all pipes? */
840 }
841 }
842
ath12k_ce_rx_post_buf(struct ath12k_base * ab)843 void ath12k_ce_rx_post_buf(struct ath12k_base *ab)
844 {
845 struct ath12k_ce_pipe *pipe;
846 int i;
847 int ret;
848
849 for (i = 0; i < ab->hw_params->ce_count; i++) {
850 pipe = &ab->ce.ce_pipe[i];
851 ret = ath12k_ce_rx_post_pipe(pipe);
852 if (ret) {
853 if (ret == -ENOSPC)
854 continue;
855
856 ath12k_warn(ab, "failed to post rx buf to pipe: %d err: %d\n",
857 i, ret);
858 mod_timer(&ab->rx_replenish_retry,
859 jiffies + ATH12K_CE_RX_POST_RETRY_JIFFIES);
860
861 return;
862 }
863 }
864 }
865
ath12k_ce_rx_replenish_retry(struct timer_list * t)866 void ath12k_ce_rx_replenish_retry(struct timer_list *t)
867 {
868 struct ath12k_base *ab = timer_container_of(ab, t, rx_replenish_retry);
869
870 ath12k_ce_rx_post_buf(ab);
871 }
872
ath12k_ce_shadow_config(struct ath12k_base * ab)873 static void ath12k_ce_shadow_config(struct ath12k_base *ab)
874 {
875 int i;
876
877 for (i = 0; i < ab->hw_params->ce_count; i++) {
878 if (ab->hw_params->host_ce_config[i].src_nentries)
879 ath12k_hal_srng_update_shadow_config(ab, HAL_CE_SRC, i);
880
881 if (ab->hw_params->host_ce_config[i].dest_nentries) {
882 ath12k_hal_srng_update_shadow_config(ab, HAL_CE_DST, i);
883 ath12k_hal_srng_update_shadow_config(ab, HAL_CE_DST_STATUS, i);
884 }
885 }
886 }
887
ath12k_ce_get_shadow_config(struct ath12k_base * ab,u32 ** shadow_cfg,u32 * shadow_cfg_len)888 void ath12k_ce_get_shadow_config(struct ath12k_base *ab,
889 u32 **shadow_cfg, u32 *shadow_cfg_len)
890 {
891 if (!ab->hw_params->supports_shadow_regs)
892 return;
893
894 ath12k_hal_srng_get_shadow_config(ab, shadow_cfg, shadow_cfg_len);
895
896 /* shadow is already configured */
897 if (*shadow_cfg_len)
898 return;
899
900 /* shadow isn't configured yet, configure now.
901 * non-CE srngs are configured firstly, then
902 * all CE srngs.
903 */
904 ath12k_hal_srng_shadow_config(ab);
905 ath12k_ce_shadow_config(ab);
906
907 /* get the shadow configuration */
908 ath12k_hal_srng_get_shadow_config(ab, shadow_cfg, shadow_cfg_len);
909 }
910
ath12k_ce_init_pipes(struct ath12k_base * ab)911 int ath12k_ce_init_pipes(struct ath12k_base *ab)
912 {
913 struct ath12k_ce_pipe *pipe;
914 int i;
915 int ret;
916
917 ath12k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v3,
918 &ab->qmi.ce_cfg.shadow_reg_v3_len);
919
920 for (i = 0; i < ab->hw_params->ce_count; i++) {
921 pipe = &ab->ce.ce_pipe[i];
922
923 if (pipe->src_ring) {
924 ret = ath12k_ce_init_ring(ab, pipe->src_ring, i,
925 HAL_CE_SRC);
926 if (ret) {
927 ath12k_warn(ab, "failed to init src ring: %d\n",
928 ret);
929 /* Should we clear any partial init */
930 return ret;
931 }
932
933 pipe->src_ring->write_index = 0;
934 pipe->src_ring->sw_index = 0;
935 }
936
937 if (pipe->dest_ring) {
938 ret = ath12k_ce_init_ring(ab, pipe->dest_ring, i,
939 HAL_CE_DST);
940 if (ret) {
941 ath12k_warn(ab, "failed to init dest ring: %d\n",
942 ret);
943 /* Should we clear any partial init */
944 return ret;
945 }
946
947 pipe->rx_buf_needed = pipe->dest_ring->nentries ?
948 pipe->dest_ring->nentries - 2 : 0;
949
950 pipe->dest_ring->write_index = 0;
951 pipe->dest_ring->sw_index = 0;
952 }
953
954 if (pipe->status_ring) {
955 ret = ath12k_ce_init_ring(ab, pipe->status_ring, i,
956 HAL_CE_DST_STATUS);
957 if (ret) {
958 ath12k_warn(ab, "failed to init dest status ing: %d\n",
959 ret);
960 /* Should we clear any partial init */
961 return ret;
962 }
963
964 pipe->status_ring->write_index = 0;
965 pipe->status_ring->sw_index = 0;
966 }
967 }
968
969 return 0;
970 }
971
ath12k_ce_free_pipes(struct ath12k_base * ab)972 void ath12k_ce_free_pipes(struct ath12k_base *ab)
973 {
974 struct ath12k_ce_pipe *pipe;
975 int desc_sz;
976 int i;
977
978 for (i = 0; i < ab->hw_params->ce_count; i++) {
979 pipe = &ab->ce.ce_pipe[i];
980
981 if (pipe->src_ring) {
982 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_SRC);
983 dma_free_coherent(ab->dev,
984 pipe->src_ring->nentries * desc_sz +
985 CE_DESC_RING_ALIGN,
986 pipe->src_ring->base_addr_owner_space,
987 pipe->src_ring->base_addr_ce_space);
988 kfree(pipe->src_ring);
989 pipe->src_ring = NULL;
990 }
991
992 if (pipe->dest_ring) {
993 desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST);
994 dma_free_coherent(ab->dev,
995 pipe->dest_ring->nentries * desc_sz +
996 CE_DESC_RING_ALIGN,
997 pipe->dest_ring->base_addr_owner_space,
998 pipe->dest_ring->base_addr_ce_space);
999 kfree(pipe->dest_ring);
1000 pipe->dest_ring = NULL;
1001 }
1002
1003 if (pipe->status_ring) {
1004 desc_sz =
1005 ath12k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS);
1006 dma_free_coherent(ab->dev,
1007 pipe->status_ring->nentries * desc_sz +
1008 CE_DESC_RING_ALIGN,
1009 pipe->status_ring->base_addr_owner_space,
1010 pipe->status_ring->base_addr_ce_space);
1011 kfree(pipe->status_ring);
1012 pipe->status_ring = NULL;
1013 }
1014 }
1015 }
1016
ath12k_ce_alloc_pipes(struct ath12k_base * ab)1017 int ath12k_ce_alloc_pipes(struct ath12k_base *ab)
1018 {
1019 struct ath12k_ce_pipe *pipe;
1020 int i;
1021 int ret;
1022 const struct ce_attr *attr;
1023
1024 spin_lock_init(&ab->ce.ce_lock);
1025
1026 for (i = 0; i < ab->hw_params->ce_count; i++) {
1027 attr = &ab->hw_params->host_ce_config[i];
1028 pipe = &ab->ce.ce_pipe[i];
1029 pipe->pipe_num = i;
1030 pipe->ab = ab;
1031 pipe->buf_sz = attr->src_sz_max;
1032
1033 ret = ath12k_ce_alloc_pipe(ab, i);
1034 if (ret) {
1035 /* Free any partial successful allocation */
1036 ath12k_ce_free_pipes(ab);
1037 return ret;
1038 }
1039 }
1040
1041 return 0;
1042 }
1043
ath12k_ce_get_attr_flags(struct ath12k_base * ab,int ce_id)1044 int ath12k_ce_get_attr_flags(struct ath12k_base *ab, int ce_id)
1045 {
1046 if (ce_id >= ab->hw_params->ce_count)
1047 return -EINVAL;
1048
1049 return ab->hw_params->host_ce_config[ce_id].flags;
1050 }
1051