1 /*
2 * Copyright (C) 2007 Atmel Corporation.
3 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
4 *
5 * Under GPLv2
6 */
7
8 #include <linux/module.h>
9 #include <linux/io.h>
10 #include <linux/mm.h>
11 #include <linux/pm.h>
12
13 #include <asm/mach/map.h>
14
15 #include <mach/hardware.h>
16 #include <mach/cpu.h>
17 #include <mach/at91_dbgu.h>
18 #include <mach/at91_pmc.h>
19 #include <mach/at91_shdwc.h>
20
21 #include "soc.h"
22 #include "generic.h"
23
24 struct at91_init_soc __initdata at91_boot_soc;
25
26 struct at91_socinfo at91_soc_initdata;
27 EXPORT_SYMBOL(at91_soc_initdata);
28
at91rm9200_set_type(int type)29 void __init at91rm9200_set_type(int type)
30 {
31 if (type == ARCH_REVISON_9200_PQFP)
32 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
33 else
34 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
35
36 pr_info("AT91: filled in soc subtype: %s\n",
37 at91_get_soc_subtype(&at91_soc_initdata));
38 }
39
at91_init_irq_default(void)40 void __init at91_init_irq_default(void)
41 {
42 at91_init_interrupts(at91_boot_soc.default_irq_priority);
43 }
44
at91_init_interrupts(unsigned int * priority)45 void __init at91_init_interrupts(unsigned int *priority)
46 {
47 /* Initialize the AIC interrupt controller */
48 at91_aic_init(priority);
49
50 /* Enable GPIO interrupts */
51 at91_gpio_irq_setup();
52 }
53
54 static struct map_desc sram_desc[2] __initdata;
55
at91_init_sram(int bank,unsigned long base,unsigned int length)56 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
57 {
58 struct map_desc *desc = &sram_desc[bank];
59
60 desc->virtual = AT91_IO_VIRT_BASE - length;
61 if (bank > 0)
62 desc->virtual -= sram_desc[bank - 1].length;
63
64 desc->pfn = __phys_to_pfn(base);
65 desc->length = length;
66 desc->type = MT_DEVICE;
67
68 pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
69 base, length, desc->virtual);
70
71 iotable_init(desc, 1);
72 }
73
74 static struct map_desc at91_io_desc __initdata = {
75 .virtual = AT91_VA_BASE_SYS,
76 .pfn = __phys_to_pfn(AT91_BASE_SYS),
77 .length = SZ_16K,
78 .type = MT_DEVICE,
79 };
80
soc_detect(u32 dbgu_base)81 static void __init soc_detect(u32 dbgu_base)
82 {
83 u32 cidr, socid;
84
85 cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
86 socid = cidr & ~AT91_CIDR_VERSION;
87
88 switch (socid) {
89 case ARCH_ID_AT91CAP9: {
90 #ifdef CONFIG_AT91_PMC_UNIT
91 u32 pmc_ver = at91_sys_read(AT91_PMC_VER);
92
93 if (pmc_ver == ARCH_REVISION_CAP9_B)
94 at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_B;
95 else if (pmc_ver == ARCH_REVISION_CAP9_C)
96 at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_C;
97 #endif
98 at91_soc_initdata.type = AT91_SOC_CAP9;
99 at91_boot_soc = at91cap9_soc;
100 break;
101 }
102
103 case ARCH_ID_AT91RM9200:
104 at91_soc_initdata.type = AT91_SOC_RM9200;
105 at91_boot_soc = at91rm9200_soc;
106 break;
107
108 case ARCH_ID_AT91SAM9260:
109 at91_soc_initdata.type = AT91_SOC_SAM9260;
110 at91_boot_soc = at91sam9260_soc;
111 break;
112
113 case ARCH_ID_AT91SAM9261:
114 at91_soc_initdata.type = AT91_SOC_SAM9261;
115 at91_boot_soc = at91sam9261_soc;
116 break;
117
118 case ARCH_ID_AT91SAM9263:
119 at91_soc_initdata.type = AT91_SOC_SAM9263;
120 at91_boot_soc = at91sam9263_soc;
121 break;
122
123 case ARCH_ID_AT91SAM9G20:
124 at91_soc_initdata.type = AT91_SOC_SAM9G20;
125 at91_boot_soc = at91sam9260_soc;
126 break;
127
128 case ARCH_ID_AT91SAM9G45:
129 at91_soc_initdata.type = AT91_SOC_SAM9G45;
130 if (cidr == ARCH_ID_AT91SAM9G45ES)
131 at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
132 at91_boot_soc = at91sam9g45_soc;
133 break;
134
135 case ARCH_ID_AT91SAM9RL64:
136 at91_soc_initdata.type = AT91_SOC_SAM9RL;
137 at91_boot_soc = at91sam9rl_soc;
138 break;
139
140 case ARCH_ID_AT91SAM9X5:
141 at91_soc_initdata.type = AT91_SOC_SAM9X5;
142 at91_boot_soc = at91sam9x5_soc;
143 break;
144 }
145
146 /* at91sam9g10 */
147 if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
148 at91_soc_initdata.type = AT91_SOC_SAM9G10;
149 at91_boot_soc = at91sam9261_soc;
150 }
151 /* at91sam9xe */
152 else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
153 at91_soc_initdata.type = AT91_SOC_SAM9260;
154 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
155 at91_boot_soc = at91sam9260_soc;
156 }
157
158 if (!at91_soc_is_detected())
159 return;
160
161 at91_soc_initdata.cidr = cidr;
162
163 /* sub version of soc */
164 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
165
166 if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
167 switch (at91_soc_initdata.exid) {
168 case ARCH_EXID_AT91SAM9M10:
169 at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
170 break;
171 case ARCH_EXID_AT91SAM9G46:
172 at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
173 break;
174 case ARCH_EXID_AT91SAM9M11:
175 at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
176 break;
177 }
178 }
179
180 if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
181 switch (at91_soc_initdata.exid) {
182 case ARCH_EXID_AT91SAM9G15:
183 at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
184 break;
185 case ARCH_EXID_AT91SAM9G35:
186 at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
187 break;
188 case ARCH_EXID_AT91SAM9X35:
189 at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
190 break;
191 case ARCH_EXID_AT91SAM9G25:
192 at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
193 break;
194 case ARCH_EXID_AT91SAM9X25:
195 at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
196 break;
197 }
198 }
199 }
200
201 static const char *soc_name[] = {
202 [AT91_SOC_RM9200] = "at91rm9200",
203 [AT91_SOC_CAP9] = "at91cap9",
204 [AT91_SOC_SAM9260] = "at91sam9260",
205 [AT91_SOC_SAM9261] = "at91sam9261",
206 [AT91_SOC_SAM9263] = "at91sam9263",
207 [AT91_SOC_SAM9G10] = "at91sam9g10",
208 [AT91_SOC_SAM9G20] = "at91sam9g20",
209 [AT91_SOC_SAM9G45] = "at91sam9g45",
210 [AT91_SOC_SAM9RL] = "at91sam9rl",
211 [AT91_SOC_SAM9X5] = "at91sam9x5",
212 [AT91_SOC_NONE] = "Unknown"
213 };
214
at91_get_soc_type(struct at91_socinfo * c)215 const char *at91_get_soc_type(struct at91_socinfo *c)
216 {
217 return soc_name[c->type];
218 }
219 EXPORT_SYMBOL(at91_get_soc_type);
220
221 static const char *soc_subtype_name[] = {
222 [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
223 [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
224 [AT91_SOC_CAP9_REV_B] = "at91cap9 revB",
225 [AT91_SOC_CAP9_REV_C] = "at91cap9 revC",
226 [AT91_SOC_SAM9XE] = "at91sam9xe",
227 [AT91_SOC_SAM9G45ES] = "at91sam9g45es",
228 [AT91_SOC_SAM9M10] = "at91sam9m10",
229 [AT91_SOC_SAM9G46] = "at91sam9g46",
230 [AT91_SOC_SAM9M11] = "at91sam9m11",
231 [AT91_SOC_SAM9G15] = "at91sam9g15",
232 [AT91_SOC_SAM9G35] = "at91sam9g35",
233 [AT91_SOC_SAM9X35] = "at91sam9x35",
234 [AT91_SOC_SAM9G25] = "at91sam9g25",
235 [AT91_SOC_SAM9X25] = "at91sam9x25",
236 [AT91_SOC_SUBTYPE_NONE] = "Unknown"
237 };
238
at91_get_soc_subtype(struct at91_socinfo * c)239 const char *at91_get_soc_subtype(struct at91_socinfo *c)
240 {
241 return soc_subtype_name[c->subtype];
242 }
243 EXPORT_SYMBOL(at91_get_soc_subtype);
244
at91_map_io(void)245 void __init at91_map_io(void)
246 {
247 /* Map peripherals */
248 iotable_init(&at91_io_desc, 1);
249
250 at91_soc_initdata.type = AT91_SOC_NONE;
251 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
252
253 soc_detect(AT91_BASE_DBGU0);
254 if (!at91_soc_is_detected())
255 soc_detect(AT91_BASE_DBGU1);
256
257 if (!at91_soc_is_detected())
258 panic("AT91: Impossible to detect the SOC type");
259
260 pr_info("AT91: Detected soc type: %s\n",
261 at91_get_soc_type(&at91_soc_initdata));
262 pr_info("AT91: Detected soc subtype: %s\n",
263 at91_get_soc_subtype(&at91_soc_initdata));
264
265 if (!at91_soc_is_enabled())
266 panic("AT91: Soc not enabled");
267
268 if (at91_boot_soc.map_io)
269 at91_boot_soc.map_io();
270 }
271
272 void __iomem *at91_shdwc_base = NULL;
273
at91sam9_poweroff(void)274 static void at91sam9_poweroff(void)
275 {
276 at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
277 }
278
at91_ioremap_shdwc(u32 base_addr)279 void __init at91_ioremap_shdwc(u32 base_addr)
280 {
281 at91_shdwc_base = ioremap(base_addr, 16);
282 if (!at91_shdwc_base)
283 panic("Impossible to ioremap at91_shdwc_base\n");
284 pm_power_off = at91sam9_poweroff;
285 }
286
287 void __iomem *at91_rstc_base;
288
at91_ioremap_rstc(u32 base_addr)289 void __init at91_ioremap_rstc(u32 base_addr)
290 {
291 at91_rstc_base = ioremap(base_addr, 16);
292 if (!at91_rstc_base)
293 panic("Impossible to ioremap at91_rstc_base\n");
294 }
295
at91_initialize(unsigned long main_clock)296 void __init at91_initialize(unsigned long main_clock)
297 {
298 at91_boot_soc.ioremap_registers();
299
300 /* Init clock subsystem */
301 at91_clock_init(main_clock);
302
303 /* Register the processor-specific clocks */
304 at91_boot_soc.register_clocks();
305
306 at91_boot_soc.init();
307 }
308