1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file contains platform specific structure definitions
4 * and init function used by Arrow Lake PCH.
5 *
6 * Copyright (c) 2022, Intel Corporation.
7 * All Rights Reserved.
8 *
9 */
10
11 #include <linux/pci.h>
12 #include "core.h"
13 #include "../pmt/telemetry.h"
14
15 /* PMC SSRAM PMT Telemetry GUID */
16 #define IOEP_LPM_REQ_GUID 0x5077612
17 #define SOCS_LPM_REQ_GUID 0x8478657
18 #define PCHS_LPM_REQ_GUID 0x9684572
19 #define SOCM_LPM_REQ_GUID 0x2625030
20
21 static const u8 ARL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};
22
23 static const struct pmc_bit_map arl_socs_ltr_show_map[] = {
24 {"SOUTHPORT_A", CNP_PMC_LTR_SPA},
25 {"SOUTHPORT_B", CNP_PMC_LTR_SPB},
26 {"SATA", CNP_PMC_LTR_SATA},
27 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
28 {"XHCI", CNP_PMC_LTR_XHCI},
29 {"SOUTHPORT_F", ADL_PMC_LTR_SPF},
30 {"ME", CNP_PMC_LTR_ME},
31 /* EVA is Enterprise Value Add, doesn't really exist on PCH */
32 {"SATA1", CNP_PMC_LTR_EVA},
33 {"SOUTHPORT_C", CNP_PMC_LTR_SPC},
34 {"HD_AUDIO", CNP_PMC_LTR_AZ},
35 {"CNV", CNP_PMC_LTR_CNV},
36 {"LPSS", CNP_PMC_LTR_LPSS},
37 {"SOUTHPORT_D", CNP_PMC_LTR_SPD},
38 {"SOUTHPORT_E", CNP_PMC_LTR_SPE},
39 {"SATA2", CNP_PMC_LTR_CAM},
40 {"ESPI", CNP_PMC_LTR_ESPI},
41 {"SCC", CNP_PMC_LTR_SCC},
42 {"ISH", CNP_PMC_LTR_ISH},
43 {"UFSX2", CNP_PMC_LTR_UFSX2},
44 {"EMMC", CNP_PMC_LTR_EMMC},
45 /*
46 * Check intel_pmc_core_ids[] users of cnp_reg_map for
47 * a list of core SoCs using this.
48 */
49 {"WIGIG", ICL_PMC_LTR_WIGIG},
50 {"THC0", TGL_PMC_LTR_THC0},
51 {"THC1", TGL_PMC_LTR_THC1},
52 {"SOUTHPORT_G", MTL_PMC_LTR_SPG},
53 {"Reserved", ARL_SOCS_PMC_LTR_RESERVED},
54 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC},
55 {"DMI3", ARL_PMC_LTR_DMI3},
56
57 /* Below two cannot be used for LTR_IGNORE */
58 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
59 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
60 {}
61 };
62
63 static const struct pmc_bit_map arl_socs_clocksource_status_map[] = {
64 {"AON2_OFF_STS", BIT(0)},
65 {"AON3_OFF_STS", BIT(1)},
66 {"AON4_OFF_STS", BIT(2)},
67 {"AON5_OFF_STS", BIT(3)},
68 {"AON1_OFF_STS", BIT(4)},
69 {"XTAL_LVM_OFF_STS", BIT(5)},
70 {"AON3_SPL_OFF_STS", BIT(9)},
71 {"DMI3FPW_0_PLL_OFF_STS", BIT(10)},
72 {"DMI3FPW_1_PLL_OFF_STS", BIT(11)},
73 {"G5X16FPW_0_PLL_OFF_STS", BIT(14)},
74 {"G5X16FPW_1_PLL_OFF_STS", BIT(15)},
75 {"G5X16FPW_2_PLL_OFF_STS", BIT(16)},
76 {"XTAL_AGGR_OFF_STS", BIT(17)},
77 {"USB2_PLL_OFF_STS", BIT(18)},
78 {"G5X16FPW_3_PLL_OFF_STS", BIT(19)},
79 {"BCLK_EXT_INJ_CLK_OFF_STS", BIT(20)},
80 {"PHY_OC_EXT_INJ_CLK_OFF_STS", BIT(21)},
81 {"FILTER_PLL_OFF_STS", BIT(22)},
82 {"FABRIC_PLL_OFF_STS", BIT(25)},
83 {"SOC_PLL_OFF_STS", BIT(26)},
84 {"PCIEFAB_PLL_OFF_STS", BIT(27)},
85 {"REF_PLL_OFF_STS", BIT(28)},
86 {"GENLOCK_FILTER_PLL_OFF_STS", BIT(30)},
87 {"RTC_PLL_OFF_STS", BIT(31)},
88 {}
89 };
90
91 static const struct pmc_bit_map arl_socs_power_gating_status_0_map[] = {
92 {"PMC_PGD0_PG_STS", BIT(0)},
93 {"DMI_PGD0_PG_STS", BIT(1)},
94 {"ESPISPI_PGD0_PG_STS", BIT(2)},
95 {"XHCI_PGD0_PG_STS", BIT(3)},
96 {"SPA_PGD0_PG_STS", BIT(4)},
97 {"SPB_PGD0_PG_STS", BIT(5)},
98 {"SPC_PGD0_PG_STS", BIT(6)},
99 {"GBE_PGD0_PG_STS", BIT(7)},
100 {"SATA_PGD0_PG_STS", BIT(8)},
101 {"FIACPCB_P5x16_PGD0_PG_STS", BIT(9)},
102 {"G5x16FPW_PGD0_PG_STS", BIT(10)},
103 {"FIA_D_PGD0_PG_STS", BIT(11)},
104 {"MPFPW2_PGD0_PG_STS", BIT(12)},
105 {"SPD_PGD0_PG_STS", BIT(13)},
106 {"LPSS_PGD0_PG_STS", BIT(14)},
107 {"LPC_PGD0_PG_STS", BIT(15)},
108 {"SMB_PGD0_PG_STS", BIT(16)},
109 {"ISH_PGD0_PG_STS", BIT(17)},
110 {"P2S_PGD0_PG_STS", BIT(18)},
111 {"NPK_PGD0_PG_STS", BIT(19)},
112 {"DMI3FPW_PGD0_PG_STS", BIT(20)},
113 {"GBETSN1_PGD0_PG_STS", BIT(21)},
114 {"FUSE_PGD0_PG_STS", BIT(22)},
115 {"FIACPCB_D_PGD0_PG_STS", BIT(23)},
116 {"FUSEGPSB_PGD0_PG_STS", BIT(24)},
117 {"XDCI_PGD0_PG_STS", BIT(25)},
118 {"EXI_PGD0_PG_STS", BIT(26)},
119 {"CSE_PGD0_PG_STS", BIT(27)},
120 {"KVMCC_PGD0_PG_STS", BIT(28)},
121 {"PMT_PGD0_PG_STS", BIT(29)},
122 {"CLINK_PGD0_PG_STS", BIT(30)},
123 {"PTIO_PGD0_PG_STS", BIT(31)},
124 {}
125 };
126
127 static const struct pmc_bit_map arl_socs_power_gating_status_1_map[] = {
128 {"USBR0_PGD0_PG_STS", BIT(0)},
129 {"SUSRAM_PGD0_PG_STS", BIT(1)},
130 {"SMT1_PGD0_PG_STS", BIT(2)},
131 {"FIACPCB_U_PGD0_PG_STS", BIT(3)},
132 {"SMS2_PGD0_PG_STS", BIT(4)},
133 {"SMS1_PGD0_PG_STS", BIT(5)},
134 {"CSMERTC_PGD0_PG_STS", BIT(6)},
135 {"CSMEPSF_PGD0_PG_STS", BIT(7)},
136 {"SBR0_PGD0_PG_STS", BIT(8)},
137 {"SBR1_PGD0_PG_STS", BIT(9)},
138 {"SBR2_PGD0_PG_STS", BIT(10)},
139 {"SBR3_PGD0_PG_STS", BIT(11)},
140 {"MPFPW1_PGD0_PG_STS", BIT(12)},
141 {"SBR5_PGD0_PG_STS", BIT(13)},
142 {"FIA_X_PGD0_PG_STS", BIT(14)},
143 {"FIACPCB_X_PGD0_PG_STS", BIT(15)},
144 {"SBRG_PGD0_PG_STS", BIT(16)},
145 {"SOC_D2D_PGD1_PG_STS", BIT(17)},
146 {"PSF4_PGD0_PG_STS", BIT(18)},
147 {"CNVI_PGD0_PG_STS", BIT(19)},
148 {"UFSX2_PGD0_PG_STS", BIT(20)},
149 {"ENDBG_PGD0_PG_STS", BIT(21)},
150 {"DBG_PSF_PGD0_PG_STS", BIT(22)},
151 {"SBR6_PGD0_PG_STS", BIT(23)},
152 {"SOC_D2D_PGD2_PG_STS", BIT(24)},
153 {"NPK_PGD1_PG_STS", BIT(25)},
154 {"DMI3_PGD0_PG_STS", BIT(26)},
155 {"DBG_SBR_PGD0_PG_STS", BIT(27)},
156 {"SOC_D2D_PGD0_PG_STS", BIT(28)},
157 {"PSF6_PGD0_PG_STS", BIT(29)},
158 {"PSF7_PGD0_PG_STS", BIT(30)},
159 {"MPFPW3_PGD0_PG_STS", BIT(31)},
160 {}
161 };
162
163 static const struct pmc_bit_map arl_socs_power_gating_status_2_map[] = {
164 {"PSF8_PGD0_PG_STS", BIT(0)},
165 {"FIA_PGD0_PG_STS", BIT(1)},
166 {"SOC_D2D_PGD3_PG_STS", BIT(2)},
167 {"FIA_U_PGD0_PG_STS", BIT(3)},
168 {"TAM_PGD0_PG_STS", BIT(4)},
169 {"GBETSN_PGD0_PG_STS", BIT(5)},
170 {"TBTLSX_PGD0_PG_STS", BIT(6)},
171 {"THC0_PGD0_PG_STS", BIT(7)},
172 {"THC1_PGD0_PG_STS", BIT(8)},
173 {"PMC_PGD1_PG_STS", BIT(9)},
174 {"FIA_P5x16_PGD0_PG_STS", BIT(10)},
175 {"GNA_PGD0_PG_STS", BIT(11)},
176 {"ACE_PGD0_PG_STS", BIT(12)},
177 {"ACE_PGD1_PG_STS", BIT(13)},
178 {"ACE_PGD2_PG_STS", BIT(14)},
179 {"ACE_PGD3_PG_STS", BIT(15)},
180 {"ACE_PGD4_PG_STS", BIT(16)},
181 {"ACE_PGD5_PG_STS", BIT(17)},
182 {"ACE_PGD6_PG_STS", BIT(18)},
183 {"ACE_PGD7_PG_STS", BIT(19)},
184 {"ACE_PGD8_PG_STS", BIT(20)},
185 {"FIA_PGS_PGD0_PG_STS", BIT(21)},
186 {"FIACPCB_PGS_PGD0_PG_STS", BIT(22)},
187 {"FUSEPMSB_PGD0_PG_STS", BIT(23)},
188 {}
189 };
190
191 static const struct pmc_bit_map arl_socs_d3_status_2_map[] = {
192 {"CSMERTC_D3_STS", BIT(1)},
193 {"SUSRAM_D3_STS", BIT(2)},
194 {"CSE_D3_STS", BIT(4)},
195 {"KVMCC_D3_STS", BIT(5)},
196 {"USBR0_D3_STS", BIT(6)},
197 {"ISH_D3_STS", BIT(7)},
198 {"SMT1_D3_STS", BIT(8)},
199 {"SMT2_D3_STS", BIT(9)},
200 {"SMT3_D3_STS", BIT(10)},
201 {"GNA_D3_STS", BIT(12)},
202 {"CLINK_D3_STS", BIT(14)},
203 {"PTIO_D3_STS", BIT(16)},
204 {"PMT_D3_STS", BIT(17)},
205 {"SMS1_D3_STS", BIT(18)},
206 {"SMS2_D3_STS", BIT(19)},
207 {}
208 };
209
210 static const struct pmc_bit_map arl_socs_d3_status_3_map[] = {
211 {"GBETSN_D3_STS", BIT(13)},
212 {"THC0_D3_STS", BIT(14)},
213 {"THC1_D3_STS", BIT(15)},
214 {"ACE_D3_STS", BIT(23)},
215 {}
216 };
217
218 static const struct pmc_bit_map arl_socs_vnn_req_status_3_map[] = {
219 {"DTS0_VNN_REQ_STS", BIT(7)},
220 {"GPIOCOM5_VNN_REQ_STS", BIT(11)},
221 {}
222 };
223
224 static const struct pmc_bit_map *arl_socs_lpm_maps[] = {
225 arl_socs_clocksource_status_map,
226 arl_socs_power_gating_status_0_map,
227 arl_socs_power_gating_status_1_map,
228 arl_socs_power_gating_status_2_map,
229 mtl_socm_d3_status_0_map,
230 mtl_socm_d3_status_1_map,
231 arl_socs_d3_status_2_map,
232 arl_socs_d3_status_3_map,
233 mtl_socm_vnn_req_status_0_map,
234 mtl_socm_vnn_req_status_1_map,
235 mtl_socm_vnn_req_status_2_map,
236 arl_socs_vnn_req_status_3_map,
237 mtl_socm_vnn_misc_status_map,
238 mtl_socm_signal_status_map,
239 NULL
240 };
241
242 static const struct pmc_bit_map arl_socs_pfear_map[] = {
243 {"RSVD64", BIT(0)},
244 {"RSVD65", BIT(1)},
245 {"RSVD66", BIT(2)},
246 {"RSVD67", BIT(3)},
247 {"RSVD68", BIT(4)},
248 {"GBETSN", BIT(5)},
249 {"TBTLSX", BIT(6)},
250 {}
251 };
252
253 static const struct pmc_bit_map *ext_arl_socs_pfear_map[] = {
254 mtl_socm_pfear_map,
255 arl_socs_pfear_map,
256 NULL
257 };
258
259 static const struct pmc_reg_map arl_socs_reg_map = {
260 .pfear_sts = ext_arl_socs_pfear_map,
261 .ppfear_buckets = ARL_SOCS_PPFEAR_NUM_ENTRIES,
262 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
263 .lpm_sts = arl_socs_lpm_maps,
264 .ltr_ignore_max = ARL_SOCS_NUM_IP_IGN_ALLOWED,
265 .ltr_show_sts = arl_socs_ltr_show_map,
266 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
267 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
268 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
269 .msr_sts = msr_map,
270 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
271 .regmap_length = MTL_SOC_PMC_MMIO_REG_LEN,
272 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
273 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
274 .lpm_priority_offset = MTL_LPM_PRI_OFFSET,
275 .lpm_en_offset = MTL_LPM_EN_OFFSET,
276 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
277 .lpm_status_offset = MTL_LPM_STATUS_OFFSET,
278 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
279 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
280 .lpm_num_maps = ADL_LPM_NUM_MAPS,
281 .lpm_reg_index = ARL_LPM_REG_INDEX,
282 .etr3_offset = ETR3_OFFSET,
283 .pson_residency_offset = TGL_PSON_RESIDENCY_OFFSET,
284 .pson_residency_counter_step = TGL_PSON_RES_COUNTER_STEP,
285 };
286
287 static const struct pmc_bit_map arl_pchs_ltr_show_map[] = {
288 {"SOUTHPORT_A", CNP_PMC_LTR_SPA},
289 {"SOUTHPORT_B", CNP_PMC_LTR_SPB},
290 {"SATA", CNP_PMC_LTR_SATA},
291 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
292 {"XHCI", CNP_PMC_LTR_XHCI},
293 {"SOUTHPORT_F", ADL_PMC_LTR_SPF},
294 {"ME", CNP_PMC_LTR_ME},
295 /* EVA is Enterprise Value Add, doesn't really exist on PCH */
296 {"SATA1", CNP_PMC_LTR_EVA},
297 {"SOUTHPORT_C", CNP_PMC_LTR_SPC},
298 {"HD_AUDIO", CNP_PMC_LTR_AZ},
299 {"CNV", CNP_PMC_LTR_CNV},
300 {"LPSS", CNP_PMC_LTR_LPSS},
301 {"SOUTHPORT_D", CNP_PMC_LTR_SPD},
302 {"SOUTHPORT_E", CNP_PMC_LTR_SPE},
303 {"SATA2", CNP_PMC_LTR_CAM},
304 {"ESPI", CNP_PMC_LTR_ESPI},
305 {"SCC", CNP_PMC_LTR_SCC},
306 {"ISH", CNP_PMC_LTR_ISH},
307 {"UFSX2", CNP_PMC_LTR_UFSX2},
308 {"EMMC", CNP_PMC_LTR_EMMC},
309 /*
310 * Check intel_pmc_core_ids[] users of cnp_reg_map for
311 * a list of core SoCs using this.
312 */
313 {"WIGIG", ICL_PMC_LTR_WIGIG},
314 {"THC0", TGL_PMC_LTR_THC0},
315 {"THC1", TGL_PMC_LTR_THC1},
316 {"SOUTHPORT_G", MTL_PMC_LTR_SPG},
317 {"ESE", MTL_PMC_LTR_ESE},
318 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC},
319 {"DMI3", ARL_PMC_LTR_DMI3},
320
321 /* Below two cannot be used for LTR_IGNORE */
322 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
323 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
324 {}
325 };
326
327 static const struct pmc_bit_map arl_pchs_clocksource_status_map[] = {
328 {"AON2_OFF_STS", BIT(0)},
329 {"AON3_OFF_STS", BIT(1)},
330 {"AON4_OFF_STS", BIT(2)},
331 {"AON2_SPL_OFF_STS", BIT(3)},
332 {"AONL_OFF_STS", BIT(4)},
333 {"XTAL_LVM_OFF_STS", BIT(5)},
334 {"AON5_ACRO_OFF_STS", BIT(6)},
335 {"AON6_ACRO_OFF_STS", BIT(7)},
336 {"USB3_PLL_OFF_STS", BIT(8)},
337 {"ACRO_OFF_STS", BIT(9)},
338 {"AUDIO_PLL_OFF_STS", BIT(10)},
339 {"MAIN_CRO_OFF_STS", BIT(11)},
340 {"MAIN_DIVIDER_OFF_STS", BIT(12)},
341 {"REF_PLL_NON_OC_OFF_STS", BIT(13)},
342 {"DMI_PLL_OFF_STS", BIT(14)},
343 {"PHY_EXT_INJ_OFF_STS", BIT(15)},
344 {"AON6_MCRO_OFF_STS", BIT(16)},
345 {"XTAL_AGGR_OFF_STS", BIT(17)},
346 {"USB2_PLL_OFF_STS", BIT(18)},
347 {"TSN0_PLL_OFF_STS", BIT(19)},
348 {"TSN1_PLL_OFF_STS", BIT(20)},
349 {"GBE_PLL_OFF_STS", BIT(21)},
350 {"SATA_PLL_OFF_STS", BIT(22)},
351 {"PCIE0_PLL_OFF_STS", BIT(23)},
352 {"PCIE1_PLL_OFF_STS", BIT(24)},
353 {"PCIE2_PLL_OFF_STS", BIT(26)},
354 {"PCIE3_PLL_OFF_STS", BIT(27)},
355 {"REF_PLL_OFF_STS", BIT(28)},
356 {"PCIE4_PLL_OFF_STS", BIT(29)},
357 {"PCIE5_PLL_OFF_STS", BIT(30)},
358 {"REF38P4_PLL_OFF_STS", BIT(31)},
359 {}
360 };
361
362 static const struct pmc_bit_map arl_pchs_power_gating_status_0_map[] = {
363 {"PMC_PGD0_PG_STS", BIT(0)},
364 {"DMI_PGD0_PG_STS", BIT(1)},
365 {"ESPISPI_PGD0_PG_STS", BIT(2)},
366 {"XHCI_PGD0_PG_STS", BIT(3)},
367 {"SPA_PGD0_PG_STS", BIT(4)},
368 {"SPB_PGD0_PG_STS", BIT(5)},
369 {"SPC_PGD0_PG_STS", BIT(6)},
370 {"GBE_PGD0_PG_STS", BIT(7)},
371 {"SATA_PGD0_PG_STS", BIT(8)},
372 {"FIA_X_PGD0_PG_STS", BIT(9)},
373 {"MPFPW4_PGD0_PG_STS", BIT(10)},
374 {"EAH_PGD0_PG_STS", BIT(11)},
375 {"MPFPW1_PGD0_PG_STS", BIT(12)},
376 {"SPD_PGD0_PG_STS", BIT(13)},
377 {"LPSS_PGD0_PG_STS", BIT(14)},
378 {"LPC_PGD0_PG_STS", BIT(15)},
379 {"SMB_PGD0_PG_STS", BIT(16)},
380 {"ISH_PGD0_PG_STS", BIT(17)},
381 {"P2S_PGD0_PG_STS", BIT(18)},
382 {"NPK_PGD0_PG_STS", BIT(19)},
383 {"U3FPW1_PGD0_PG_STS", BIT(20)},
384 {"PECI_PGD0_PG_STS", BIT(21)},
385 {"FUSE_PGD0_PG_STS", BIT(22)},
386 {"SBR8_PGD0_PG_STS", BIT(23)},
387 {"EXE_PGD0_PG_STS", BIT(24)},
388 {"XDCI_PGD0_PG_STS", BIT(25)},
389 {"EXI_PGD0_PG_STS", BIT(26)},
390 {"CSE_PGD0_PG_STS", BIT(27)},
391 {"KVMCC_PGD0_PG_STS", BIT(28)},
392 {"PMT_PGD0_PG_STS", BIT(29)},
393 {"CLINK_PGD0_PG_STS", BIT(30)},
394 {"PTIO_PGD0_PG_STS", BIT(31)},
395 {}
396 };
397
398 static const struct pmc_bit_map arl_pchs_power_gating_status_1_map[] = {
399 {"USBR0_PGD0_PG_STS", BIT(0)},
400 {"SUSRAM_PGD0_PG_STS", BIT(1)},
401 {"SMT1_PGD0_PG_STS", BIT(2)},
402 {"SMT4_PGD0_PG_STS", BIT(3)},
403 {"SMS2_PGD0_PG_STS", BIT(4)},
404 {"SMS1_PGD0_PG_STS", BIT(5)},
405 {"CSMERTC_PGD0_PG_STS", BIT(6)},
406 {"CSMEPSF_PGD0_PG_STS", BIT(7)},
407 {"SBR0_PGD0_PG_STS", BIT(8)},
408 {"SBR1_PGD0_PG_STS", BIT(9)},
409 {"SBR2_PGD0_PG_STS", BIT(10)},
410 {"SBR3_PGD0_PG_STS", BIT(11)},
411 {"SBR4_PGD0_PG_STS", BIT(12)},
412 {"SBR5_PGD0_PG_STS", BIT(13)},
413 {"MPFPW3_PGD0_PG_STS", BIT(14)},
414 {"PSF1_PGD0_PG_STS", BIT(15)},
415 {"PSF2_PGD0_PG_STS", BIT(16)},
416 {"PSF3_PGD0_PG_STS", BIT(17)},
417 {"PSF4_PGD0_PG_STS", BIT(18)},
418 {"CNVI_PGD0_PG_STS", BIT(19)},
419 {"DMI3_PGD0_PG_STS", BIT(20)},
420 {"ENDBG_PGD0_PG_STS", BIT(21)},
421 {"DBG_SBR_PGD0_PG_STS", BIT(22)},
422 {"SBR6_PGD0_PG_STS", BIT(23)},
423 {"SBR7_PGD0_PG_STS", BIT(24)},
424 {"NPK_PGD1_PG_STS", BIT(25)},
425 {"U3FPW3_PGD0_PG_STS", BIT(26)},
426 {"MPFPW2_PGD0_PG_STS", BIT(27)},
427 {"MPFPW7_PGD0_PG_STS", BIT(28)},
428 {"GBETSN1_PGD0_PG_STS", BIT(29)},
429 {"PSF7_PGD0_PG_STS", BIT(30)},
430 {"FIA2_PGD0_PG_STS", BIT(31)},
431 {}
432 };
433
434 static const struct pmc_bit_map arl_pchs_power_gating_status_2_map[] = {
435 {"U3FPW2_PGD0_PG_STS", BIT(0)},
436 {"FIA_PGD0_PG_STS", BIT(1)},
437 {"FIACPCB_X_PGD0_PG_STS", BIT(2)},
438 {"FIA1_PGD0_PG_STS", BIT(3)},
439 {"TAM_PGD0_PG_STS", BIT(4)},
440 {"GBETSN_PGD0_PG_STS", BIT(5)},
441 {"SBR9_PGD0_PG_STS", BIT(6)},
442 {"THC0_PGD0_PG_STS", BIT(7)},
443 {"THC1_PGD0_PG_STS", BIT(8)},
444 {"PMC_PGD1_PG_STS", BIT(9)},
445 {"DBC_PGD0_PG_STS", BIT(10)},
446 {"DBG_PSF_PGD0_PG_STS", BIT(11)},
447 {"SPF_PGD0_PG_STS", BIT(12)},
448 {"ACE_PGD0_PG_STS", BIT(13)},
449 {"ACE_PGD1_PG_STS", BIT(14)},
450 {"ACE_PGD2_PG_STS", BIT(15)},
451 {"ACE_PGD3_PG_STS", BIT(16)},
452 {"ACE_PGD4_PG_STS", BIT(17)},
453 {"ACE_PGD5_PG_STS", BIT(18)},
454 {"ACE_PGD6_PG_STS", BIT(19)},
455 {"ACE_PGD7_PG_STS", BIT(20)},
456 {"SPE_PGD0_PG_STS", BIT(21)},
457 {"MPFPW5_PG_STS", BIT(22)},
458 {}
459 };
460
461 static const struct pmc_bit_map arl_pchs_d3_status_0_map[] = {
462 {"SPF_D3_STS", BIT(0)},
463 {"LPSS_D3_STS", BIT(3)},
464 {"XDCI_D3_STS", BIT(4)},
465 {"XHCI_D3_STS", BIT(5)},
466 {"SPA_D3_STS", BIT(12)},
467 {"SPB_D3_STS", BIT(13)},
468 {"SPC_D3_STS", BIT(14)},
469 {"SPD_D3_STS", BIT(15)},
470 {"SPE_D3_STS", BIT(16)},
471 {"ESPISPI_D3_STS", BIT(18)},
472 {"SATA_D3_STS", BIT(20)},
473 {"PSTH_D3_STS", BIT(21)},
474 {"DMI_D3_STS", BIT(22)},
475 {}
476 };
477
478 static const struct pmc_bit_map arl_pchs_d3_status_1_map[] = {
479 {"GBETSN1_D3_STS", BIT(14)},
480 {"GBE_D3_STS", BIT(19)},
481 {"ITSS_D3_STS", BIT(23)},
482 {"P2S_D3_STS", BIT(24)},
483 {"CNVI_D3_STS", BIT(27)},
484 {}
485 };
486
487 static const struct pmc_bit_map arl_pchs_d3_status_2_map[] = {
488 {"CSMERTC_D3_STS", BIT(1)},
489 {"SUSRAM_D3_STS", BIT(2)},
490 {"CSE_D3_STS", BIT(4)},
491 {"KVMCC_D3_STS", BIT(5)},
492 {"USBR0_D3_STS", BIT(6)},
493 {"ISH_D3_STS", BIT(7)},
494 {"SMT1_D3_STS", BIT(8)},
495 {"SMT2_D3_STS", BIT(9)},
496 {"SMT3_D3_STS", BIT(10)},
497 {"SMT4_D3_STS", BIT(11)},
498 {"SMT5_D3_STS", BIT(12)},
499 {"SMT6_D3_STS", BIT(13)},
500 {"CLINK_D3_STS", BIT(14)},
501 {"PTIO_D3_STS", BIT(16)},
502 {"PMT_D3_STS", BIT(17)},
503 {"SMS1_D3_STS", BIT(18)},
504 {"SMS2_D3_STS", BIT(19)},
505 {}
506 };
507
508 static const struct pmc_bit_map arl_pchs_d3_status_3_map[] = {
509 {"ESE_D3_STS", BIT(3)},
510 {"GBETSN_D3_STS", BIT(13)},
511 {"THC0_D3_STS", BIT(14)},
512 {"THC1_D3_STS", BIT(15)},
513 {"ACE_D3_STS", BIT(23)},
514 {}
515 };
516
517 static const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[] = {
518 {"FIA_VNN_REQ_STS", BIT(17)},
519 {"ESPISPI_VNN_REQ_STS", BIT(18)},
520 {}
521 };
522
523 static const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[] = {
524 {"NPK_VNN_REQ_STS", BIT(4)},
525 {"DFXAGG_VNN_REQ_STS", BIT(8)},
526 {"EXI_VNN_REQ_STS", BIT(9)},
527 {"GBE_VNN_REQ_STS", BIT(19)},
528 {"SMB_VNN_REQ_STS", BIT(25)},
529 {"LPC_VNN_REQ_STS", BIT(26)},
530 {"CNVI_VNN_REQ_STS", BIT(27)},
531 {}
532 };
533
534 static const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[] = {
535 {"FIA2_VNN_REQ_STS", BIT(0)},
536 {"CSMERTC_VNN_REQ_STS", BIT(1)},
537 {"CSE_VNN_REQ_STS", BIT(4)},
538 {"ISH_VNN_REQ_STS", BIT(7)},
539 {"SMT1_VNN_REQ_STS", BIT(8)},
540 {"SMT4_VNN_REQ_STS", BIT(11)},
541 {"CLINK_VNN_REQ_STS", BIT(14)},
542 {"SMS1_VNN_REQ_STS", BIT(18)},
543 {"SMS2_VNN_REQ_STS", BIT(19)},
544 {"GPIOCOM4_VNN_REQ_STS", BIT(20)},
545 {"GPIOCOM3_VNN_REQ_STS", BIT(21)},
546 {"GPIOCOM2_VNN_REQ_STS", BIT(22)},
547 {"GPIOCOM1_VNN_REQ_STS", BIT(23)},
548 {"GPIOCOM0_VNN_REQ_STS", BIT(24)},
549 {}
550 };
551
552 static const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[] = {
553 {"ESE_VNN_REQ_STS", BIT(3)},
554 {"DTS0_VNN_REQ_STS", BIT(7)},
555 {"GPIOCOM5_VNN_REQ_STS", BIT(11)},
556 {"FIA1_VNN_REQ_STS", BIT(12)},
557 {}
558 };
559
560 static const struct pmc_bit_map arl_pchs_vnn_misc_status_map[] = {
561 {"CPU_C10_REQ_STS", BIT(0)},
562 {"TS_OFF_REQ_STS", BIT(1)},
563 {"PNDE_MET_REQ_STS", BIT(2)},
564 {"PCIE_DEEP_PM_REQ_STS", BIT(3)},
565 {"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4)},
566 {"ISH_VNNAON_REQ_STS", BIT(7)},
567 {"IOE_COND_MET_S02I2_0_REQ_STS", BIT(8)},
568 {"IOE_COND_MET_S02I2_1_REQ_STS", BIT(9)},
569 {"IOE_COND_MET_S02I2_2_REQ_STS", BIT(10)},
570 {"PLT_GREATER_REQ_STS", BIT(11)},
571 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)},
572 {"PM_SYNC_STATES_REQ_STS", BIT(14)},
573 {"EA_REQ_STS", BIT(15)},
574 {"DMI_CLKREQ_B_REQ_STS", BIT(16)},
575 {"BRK_EV_EN_REQ_STS", BIT(17)},
576 {"AUTO_DEMO_EN_REQ_STS", BIT(18)},
577 {"ITSS_CLK_SRC_REQ_STS", BIT(19)},
578 {"ARC_IDLE_REQ_STS", BIT(21)},
579 {"DMI_IN_REQ_STS", BIT(22)},
580 {"FIA_DEEP_PM_REQ_STS", BIT(23)},
581 {"XDCI_ATTACHED_REQ_STS", BIT(24)},
582 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)},
583 {"PRE_WAKE0_REQ_STS", BIT(27)},
584 {"PRE_WAKE1_REQ_STS", BIT(28)},
585 {"PRE_WAKE2_EN_REQ_STS", BIT(29)},
586 {"CNVI_V1P05_REQ_STS", BIT(31)},
587 {}
588 };
589
590 static const struct pmc_bit_map arl_pchs_signal_status_map[] = {
591 {"LSX_Wake0_STS", BIT(0)},
592 {"LSX_Wake1_STS", BIT(1)},
593 {"LSX_Wake2_STS", BIT(2)},
594 {"LSX_Wake3_STS", BIT(3)},
595 {"LSX_Wake4_STS", BIT(4)},
596 {"LSX_Wake5_STS", BIT(5)},
597 {"LSX_Wake6_STS", BIT(6)},
598 {"LSX_Wake7_STS", BIT(7)},
599 {"Int_Timer_SS_Wake0_STS", BIT(8)},
600 {"Int_Timer_SS_Wake1_STS", BIT(9)},
601 {"Int_Timer_SS_Wake0_STS", BIT(10)},
602 {"Int_Timer_SS_Wake1_STS", BIT(11)},
603 {"Int_Timer_SS_Wake2_STS", BIT(12)},
604 {"Int_Timer_SS_Wake3_STS", BIT(13)},
605 {"Int_Timer_SS_Wake4_STS", BIT(14)},
606 {"Int_Timer_SS_Wake5_STS", BIT(15)},
607 {}
608 };
609
610 static const struct pmc_bit_map *arl_pchs_lpm_maps[] = {
611 arl_pchs_clocksource_status_map,
612 arl_pchs_power_gating_status_0_map,
613 arl_pchs_power_gating_status_1_map,
614 arl_pchs_power_gating_status_2_map,
615 arl_pchs_d3_status_0_map,
616 arl_pchs_d3_status_1_map,
617 arl_pchs_d3_status_2_map,
618 arl_pchs_d3_status_3_map,
619 arl_pchs_vnn_req_status_0_map,
620 arl_pchs_vnn_req_status_1_map,
621 arl_pchs_vnn_req_status_2_map,
622 arl_pchs_vnn_req_status_3_map,
623 arl_pchs_vnn_misc_status_map,
624 arl_pchs_signal_status_map,
625 NULL
626 };
627
628 static const struct pmc_reg_map arl_pchs_reg_map = {
629 .pfear_sts = ext_arl_socs_pfear_map,
630 .ppfear_buckets = ARL_SOCS_PPFEAR_NUM_ENTRIES,
631 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
632 .ltr_ignore_max = ARL_SOCS_NUM_IP_IGN_ALLOWED,
633 .lpm_sts = arl_pchs_lpm_maps,
634 .ltr_show_sts = arl_pchs_ltr_show_map,
635 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
636 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
637 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
638 .msr_sts = msr_map,
639 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
640 .regmap_length = ARL_PCH_PMC_MMIO_REG_LEN,
641 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
642 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
643 .lpm_priority_offset = MTL_LPM_PRI_OFFSET,
644 .lpm_en_offset = MTL_LPM_EN_OFFSET,
645 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
646 .lpm_status_offset = MTL_LPM_STATUS_OFFSET,
647 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
648 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
649 .lpm_num_maps = ADL_LPM_NUM_MAPS,
650 .lpm_reg_index = ARL_LPM_REG_INDEX,
651 .etr3_offset = ETR3_OFFSET,
652 };
653
654 #define PMC_DEVID_SOCM 0x777f
655 #define PMC_DEVID_SOCS 0xae7f
656 #define PMC_DEVID_IOEP 0x7ecf
657 #define PMC_DEVID_PCHS 0x7f27
658 static struct pmc_info arl_pmc_info_list[] = {
659 {
660 .guid = IOEP_LPM_REQ_GUID,
661 .devid = PMC_DEVID_IOEP,
662 .map = &mtl_ioep_reg_map,
663 },
664 {
665 .guid = SOCS_LPM_REQ_GUID,
666 .devid = PMC_DEVID_SOCS,
667 .map = &arl_socs_reg_map,
668 },
669 {
670 .guid = PCHS_LPM_REQ_GUID,
671 .devid = PMC_DEVID_PCHS,
672 .map = &arl_pchs_reg_map,
673 },
674 {
675 .guid = SOCM_LPM_REQ_GUID,
676 .devid = PMC_DEVID_SOCM,
677 .map = &mtl_socm_reg_map,
678 },
679 {}
680 };
681
682 #define ARL_NPU_PCI_DEV 0xad1d
683 #define ARL_GNA_PCI_DEV 0xae4c
684 #define ARL_H_NPU_PCI_DEV 0x7d1d
685 #define ARL_H_GNA_PCI_DEV 0x774c
686 /*
687 * Set power state of select devices that do not have drivers to D3
688 * so that they do not block Package C entry.
689 */
arl_d3_fixup(void)690 static void arl_d3_fixup(void)
691 {
692 pmc_core_set_device_d3(ARL_NPU_PCI_DEV);
693 pmc_core_set_device_d3(ARL_GNA_PCI_DEV);
694 }
695
arl_h_d3_fixup(void)696 static void arl_h_d3_fixup(void)
697 {
698 pmc_core_set_device_d3(ARL_H_NPU_PCI_DEV);
699 pmc_core_set_device_d3(ARL_H_GNA_PCI_DEV);
700 }
701
arl_resume(struct pmc_dev * pmcdev)702 static int arl_resume(struct pmc_dev *pmcdev)
703 {
704 arl_d3_fixup();
705
706 return cnl_resume(pmcdev);
707 }
708
arl_h_resume(struct pmc_dev * pmcdev)709 static int arl_h_resume(struct pmc_dev *pmcdev)
710 {
711 arl_h_d3_fixup();
712
713 return cnl_resume(pmcdev);
714 }
715
arl_core_init(struct pmc_dev * pmcdev,struct pmc_dev_info * pmc_dev_info)716 static int arl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
717 {
718 arl_d3_fixup();
719 return generic_core_init(pmcdev, pmc_dev_info);
720 }
721
arl_h_core_init(struct pmc_dev * pmcdev,struct pmc_dev_info * pmc_dev_info)722 static int arl_h_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
723 {
724 arl_h_d3_fixup();
725 return generic_core_init(pmcdev, pmc_dev_info);
726 }
727
728 struct pmc_dev_info arl_pmc_dev = {
729 .pci_func = 0,
730 .dmu_guid = ARL_PMT_DMU_GUID,
731 .regmap_list = arl_pmc_info_list,
732 .map = &arl_socs_reg_map,
733 .suspend = cnl_suspend,
734 .resume = arl_resume,
735 .init = arl_core_init,
736 };
737
738 struct pmc_dev_info arl_h_pmc_dev = {
739 .pci_func = 2,
740 .dmu_guid = ARL_PMT_DMU_GUID,
741 .regmap_list = arl_pmc_info_list,
742 .map = &mtl_socm_reg_map,
743 .suspend = cnl_suspend,
744 .resume = arl_h_resume,
745 .init = arl_h_core_init,
746 };
747