1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_dpm.h"
29 #include "amdgpu_smu.h"
30 #include "atomfirmware.h"
31 #include "amdgpu_atomfirmware.h"
32 #include "amdgpu_atombios.h"
33 #include "smu_v11_0.h"
34 #include "smu11_driver_if_arcturus.h"
35 #include "soc15_common.h"
36 #include "atom.h"
37 #include "arcturus_ppt.h"
38 #include "smu_v11_0_pptable.h"
39 #include "arcturus_ppsmc.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/i2c.h>
46 #include <linux/pci.h>
47 #include "amdgpu_ras.h"
48 #include "smu_cmn.h"
49
50 /*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59
60 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
61 [smu_feature] = {1, (arcturus_feature)}
62
63 #define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF
64 #define SMU_FEATURES_LOW_SHIFT 0
65 #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000
66 #define SMU_FEATURES_HIGH_SHIFT 32
67
68 #define SMC_DPM_FEATURE ( \
69 FEATURE_DPM_PREFETCHER_MASK | \
70 FEATURE_DPM_GFXCLK_MASK | \
71 FEATURE_DPM_UCLK_MASK | \
72 FEATURE_DPM_SOCCLK_MASK | \
73 FEATURE_DPM_MP0CLK_MASK | \
74 FEATURE_DPM_FCLK_MASK | \
75 FEATURE_DPM_XGMI_MASK)
76
77 /* possible frequency drift (1Mhz) */
78 #define EPSILON 1
79
80 #define smnPCIE_ESM_CTRL 0x111003D0
81
82 #define mmCG_FDO_CTRL0_ARCT 0x8B
83 #define mmCG_FDO_CTRL0_ARCT_BASE_IDX 0
84
85 #define mmCG_FDO_CTRL1_ARCT 0x8C
86 #define mmCG_FDO_CTRL1_ARCT_BASE_IDX 0
87
88 #define mmCG_FDO_CTRL2_ARCT 0x8D
89 #define mmCG_FDO_CTRL2_ARCT_BASE_IDX 0
90
91 #define mmCG_TACH_CTRL_ARCT 0x8E
92 #define mmCG_TACH_CTRL_ARCT_BASE_IDX 0
93
94 #define mmCG_TACH_STATUS_ARCT 0x8F
95 #define mmCG_TACH_STATUS_ARCT_BASE_IDX 0
96
97 #define mmCG_THERMAL_STATUS_ARCT 0x90
98 #define mmCG_THERMAL_STATUS_ARCT_BASE_IDX 0
99
100 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
101 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
102 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
103 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
104 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
105 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
106 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
107 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
108 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
109 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
110 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0),
111 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0),
112 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 0),
113 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 0),
114 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
115 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
116 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
117 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
118 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
119 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
120 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
121 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0),
122 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
123 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0),
124 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
125 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
126 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
127 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
128 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
129 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0),
130 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
131 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0),
132 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0),
133 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
134 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
135 MSG_MAP(SetDfSwitchType, PPSMC_MSG_SetDfSwitchType, 0),
136 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
137 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
138 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
139 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
140 MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0, 0),
141 MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0, 0),
142 MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1, 0),
143 MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1, 0),
144 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
145 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0),
146 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0),
147 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 0),
148 MSG_MAP(RunAfllBtc, PPSMC_MSG_RunAfllBtc, 0),
149 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
150 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
151 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
152 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
153 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
154 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0),
155 MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode, 0),
156 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0),
157 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
158 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
159 MSG_MAP(ReadSerialNumTop32, PPSMC_MSG_ReadSerialNumTop32, 1),
160 MSG_MAP(ReadSerialNumBottom32, PPSMC_MSG_ReadSerialNumBottom32, 1),
161 MSG_MAP(LightSBR, PPSMC_MSG_LightSBR, 0),
162 };
163
164 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
165 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
166 CLK_MAP(SCLK, PPCLK_GFXCLK),
167 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
168 CLK_MAP(FCLK, PPCLK_FCLK),
169 CLK_MAP(UCLK, PPCLK_UCLK),
170 CLK_MAP(MCLK, PPCLK_UCLK),
171 CLK_MAP(DCLK, PPCLK_DCLK),
172 CLK_MAP(VCLK, PPCLK_VCLK),
173 };
174
175 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
176 FEA_MAP(DPM_PREFETCHER),
177 FEA_MAP(DPM_GFXCLK),
178 FEA_MAP(DPM_UCLK),
179 FEA_MAP(DPM_SOCCLK),
180 FEA_MAP(DPM_FCLK),
181 FEA_MAP(DPM_MP0CLK),
182 FEA_MAP(DPM_XGMI),
183 FEA_MAP(DS_GFXCLK),
184 FEA_MAP(DS_SOCCLK),
185 FEA_MAP(DS_LCLK),
186 FEA_MAP(DS_FCLK),
187 FEA_MAP(DS_UCLK),
188 FEA_MAP(GFX_ULV),
189 ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT),
190 FEA_MAP(RSMU_SMN_CG),
191 FEA_MAP(WAFL_CG),
192 FEA_MAP(PPT),
193 FEA_MAP(TDC),
194 FEA_MAP(APCC_PLUS),
195 FEA_MAP(VR0HOT),
196 FEA_MAP(VR1HOT),
197 FEA_MAP(FW_CTF),
198 FEA_MAP(FAN_CONTROL),
199 FEA_MAP(THERMAL),
200 FEA_MAP(OUT_OF_BAND_MONITOR),
201 FEA_MAP(TEMP_DEPENDENT_VMIN),
202 };
203
204 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
205 TAB_MAP(PPTABLE),
206 TAB_MAP(AVFS),
207 TAB_MAP(AVFS_PSM_DEBUG),
208 TAB_MAP(AVFS_FUSE_OVERRIDE),
209 TAB_MAP(PMSTATUSLOG),
210 TAB_MAP(SMU_METRICS),
211 TAB_MAP(DRIVER_SMU_CONFIG),
212 TAB_MAP(OVERDRIVE),
213 TAB_MAP(I2C_COMMANDS),
214 TAB_MAP(ACTIVITY_MONITOR_COEFF),
215 };
216
217 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
218 PWR_MAP(AC),
219 PWR_MAP(DC),
220 };
221
222 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
223 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
224 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
225 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
226 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
227 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
228 };
229
230 static const uint8_t arcturus_throttler_map[] = {
231 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
232 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
233 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
234 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
235 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
236 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
237 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
238 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
239 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
240 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
241 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
242 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
243 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
244 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
245 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
246 [THROTTLER_VRHOT0_BIT] = (SMU_THROTTLER_VRHOT0_BIT),
247 [THROTTLER_VRHOT1_BIT] = (SMU_THROTTLER_VRHOT1_BIT),
248 };
249
arcturus_tables_init(struct smu_context * smu)250 static int arcturus_tables_init(struct smu_context *smu)
251 {
252 struct smu_table_context *smu_table = &smu->smu_table;
253 struct smu_table *tables = smu_table->tables;
254
255 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
256 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
257
258 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
259 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
260
261 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
262 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
263
264 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
265 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
266
267 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
268 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
269 AMDGPU_GEM_DOMAIN_VRAM);
270
271 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
272 if (!smu_table->metrics_table)
273 return -ENOMEM;
274 smu_table->metrics_time = 0;
275
276 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
277 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
278 if (!smu_table->gpu_metrics_table) {
279 kfree(smu_table->metrics_table);
280 return -ENOMEM;
281 }
282
283 return 0;
284 }
285
arcturus_allocate_dpm_context(struct smu_context * smu)286 static int arcturus_allocate_dpm_context(struct smu_context *smu)
287 {
288 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
289
290 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
291 GFP_KERNEL);
292 if (!smu_dpm->dpm_context)
293 return -ENOMEM;
294 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
295
296 return 0;
297 }
298
arcturus_init_smc_tables(struct smu_context * smu)299 static int arcturus_init_smc_tables(struct smu_context *smu)
300 {
301 int ret = 0;
302
303 ret = arcturus_tables_init(smu);
304 if (ret)
305 return ret;
306
307 ret = arcturus_allocate_dpm_context(smu);
308 if (ret)
309 return ret;
310
311 return smu_v11_0_init_smc_tables(smu);
312 }
313
314 static int
arcturus_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)315 arcturus_get_allowed_feature_mask(struct smu_context *smu,
316 uint32_t *feature_mask, uint32_t num)
317 {
318 if (num > 2)
319 return -EINVAL;
320
321 /* pptable will handle the features to enable */
322 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
323
324 return 0;
325 }
326
arcturus_set_default_dpm_table(struct smu_context * smu)327 static int arcturus_set_default_dpm_table(struct smu_context *smu)
328 {
329 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
330 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
331 struct smu_11_0_dpm_table *dpm_table = NULL;
332 int ret = 0;
333
334 /* socclk dpm table setup */
335 dpm_table = &dpm_context->dpm_tables.soc_table;
336 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
337 ret = smu_v11_0_set_single_dpm_table(smu,
338 SMU_SOCCLK,
339 dpm_table);
340 if (ret)
341 return ret;
342 dpm_table->is_fine_grained =
343 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
344 } else {
345 dpm_table->count = 1;
346 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
347 dpm_table->dpm_levels[0].enabled = true;
348 dpm_table->min = dpm_table->dpm_levels[0].value;
349 dpm_table->max = dpm_table->dpm_levels[0].value;
350 }
351
352 /* gfxclk dpm table setup */
353 dpm_table = &dpm_context->dpm_tables.gfx_table;
354 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
355 ret = smu_v11_0_set_single_dpm_table(smu,
356 SMU_GFXCLK,
357 dpm_table);
358 if (ret)
359 return ret;
360 dpm_table->is_fine_grained =
361 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
362 } else {
363 dpm_table->count = 1;
364 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
365 dpm_table->dpm_levels[0].enabled = true;
366 dpm_table->min = dpm_table->dpm_levels[0].value;
367 dpm_table->max = dpm_table->dpm_levels[0].value;
368 }
369
370 /* memclk dpm table setup */
371 dpm_table = &dpm_context->dpm_tables.uclk_table;
372 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
373 ret = smu_v11_0_set_single_dpm_table(smu,
374 SMU_UCLK,
375 dpm_table);
376 if (ret)
377 return ret;
378 dpm_table->is_fine_grained =
379 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
380 } else {
381 dpm_table->count = 1;
382 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
383 dpm_table->dpm_levels[0].enabled = true;
384 dpm_table->min = dpm_table->dpm_levels[0].value;
385 dpm_table->max = dpm_table->dpm_levels[0].value;
386 }
387
388 /* fclk dpm table setup */
389 dpm_table = &dpm_context->dpm_tables.fclk_table;
390 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
391 ret = smu_v11_0_set_single_dpm_table(smu,
392 SMU_FCLK,
393 dpm_table);
394 if (ret)
395 return ret;
396 dpm_table->is_fine_grained =
397 !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
398 } else {
399 dpm_table->count = 1;
400 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
401 dpm_table->dpm_levels[0].enabled = true;
402 dpm_table->min = dpm_table->dpm_levels[0].value;
403 dpm_table->max = dpm_table->dpm_levels[0].value;
404 }
405
406 return 0;
407 }
408
arcturus_check_bxco_support(struct smu_context * smu)409 static void arcturus_check_bxco_support(struct smu_context *smu)
410 {
411 struct smu_table_context *table_context = &smu->smu_table;
412 struct smu_11_0_powerplay_table *powerplay_table =
413 table_context->power_play_table;
414 struct smu_baco_context *smu_baco = &smu->smu_baco;
415 struct amdgpu_device *adev = smu->adev;
416 uint32_t val;
417
418 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
419 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
420 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
421 smu_baco->platform_support =
422 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
423 false;
424 }
425 }
426
arcturus_check_fan_support(struct smu_context * smu)427 static void arcturus_check_fan_support(struct smu_context *smu)
428 {
429 struct smu_table_context *table_context = &smu->smu_table;
430 PPTable_t *pptable = table_context->driver_pptable;
431
432 /* No sort of fan control possible if PPTable has it disabled */
433 smu->adev->pm.no_fan =
434 !(pptable->FeaturesToRun[0] & FEATURE_FAN_CONTROL_MASK);
435 if (smu->adev->pm.no_fan)
436 dev_info_once(smu->adev->dev,
437 "PMFW based fan control disabled");
438 }
439
arcturus_check_powerplay_table(struct smu_context * smu)440 static int arcturus_check_powerplay_table(struct smu_context *smu)
441 {
442 struct smu_table_context *table_context = &smu->smu_table;
443 struct smu_11_0_powerplay_table *powerplay_table =
444 table_context->power_play_table;
445
446 arcturus_check_bxco_support(smu);
447 arcturus_check_fan_support(smu);
448
449 table_context->thermal_controller_type =
450 powerplay_table->thermal_controller_type;
451
452 return 0;
453 }
454
arcturus_store_powerplay_table(struct smu_context * smu)455 static int arcturus_store_powerplay_table(struct smu_context *smu)
456 {
457 struct smu_table_context *table_context = &smu->smu_table;
458 struct smu_11_0_powerplay_table *powerplay_table =
459 table_context->power_play_table;
460
461 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
462 sizeof(PPTable_t));
463
464 return 0;
465 }
466
arcturus_append_powerplay_table(struct smu_context * smu)467 static int arcturus_append_powerplay_table(struct smu_context *smu)
468 {
469 struct smu_table_context *table_context = &smu->smu_table;
470 PPTable_t *smc_pptable = table_context->driver_pptable;
471 struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
472 int index, ret;
473
474 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
475 smc_dpm_info);
476
477 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
478 (uint8_t **)&smc_dpm_table);
479 if (ret)
480 return ret;
481
482 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
483 smc_dpm_table->table_header.format_revision,
484 smc_dpm_table->table_header.content_revision);
485
486 if ((smc_dpm_table->table_header.format_revision == 4) &&
487 (smc_dpm_table->table_header.content_revision == 6))
488 smu_memcpy_trailing(smc_pptable, MaxVoltageStepGfx, BoardReserved,
489 smc_dpm_table, maxvoltagestepgfx);
490 return 0;
491 }
492
arcturus_setup_pptable(struct smu_context * smu)493 static int arcturus_setup_pptable(struct smu_context *smu)
494 {
495 int ret = 0;
496
497 ret = smu_v11_0_setup_pptable(smu);
498 if (ret)
499 return ret;
500
501 ret = arcturus_store_powerplay_table(smu);
502 if (ret)
503 return ret;
504
505 ret = arcturus_append_powerplay_table(smu);
506 if (ret)
507 return ret;
508
509 ret = arcturus_check_powerplay_table(smu);
510 if (ret)
511 return ret;
512
513 return ret;
514 }
515
arcturus_run_btc(struct smu_context * smu)516 static int arcturus_run_btc(struct smu_context *smu)
517 {
518 int ret = 0;
519
520 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
521 if (ret) {
522 dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
523 return ret;
524 }
525
526 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
527 }
528
arcturus_populate_umd_state_clk(struct smu_context * smu)529 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
530 {
531 struct smu_11_0_dpm_context *dpm_context =
532 smu->smu_dpm.dpm_context;
533 struct smu_11_0_dpm_table *gfx_table =
534 &dpm_context->dpm_tables.gfx_table;
535 struct smu_11_0_dpm_table *mem_table =
536 &dpm_context->dpm_tables.uclk_table;
537 struct smu_11_0_dpm_table *soc_table =
538 &dpm_context->dpm_tables.soc_table;
539 struct smu_umd_pstate_table *pstate_table =
540 &smu->pstate_table;
541
542 pstate_table->gfxclk_pstate.min = gfx_table->min;
543 pstate_table->gfxclk_pstate.peak = gfx_table->max;
544
545 pstate_table->uclk_pstate.min = mem_table->min;
546 pstate_table->uclk_pstate.peak = mem_table->max;
547
548 pstate_table->socclk_pstate.min = soc_table->min;
549 pstate_table->socclk_pstate.peak = soc_table->max;
550
551 if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
552 mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
553 soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
554 pstate_table->gfxclk_pstate.standard =
555 gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
556 pstate_table->uclk_pstate.standard =
557 mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
558 pstate_table->socclk_pstate.standard =
559 soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
560 } else {
561 pstate_table->gfxclk_pstate.standard =
562 pstate_table->gfxclk_pstate.min;
563 pstate_table->uclk_pstate.standard =
564 pstate_table->uclk_pstate.min;
565 pstate_table->socclk_pstate.standard =
566 pstate_table->socclk_pstate.min;
567 }
568
569 return 0;
570 }
571
arcturus_get_clk_table(struct smu_context * smu,struct pp_clock_levels_with_latency * clocks,struct smu_11_0_dpm_table * dpm_table)572 static void arcturus_get_clk_table(struct smu_context *smu,
573 struct pp_clock_levels_with_latency *clocks,
574 struct smu_11_0_dpm_table *dpm_table)
575 {
576 uint32_t i;
577
578 clocks->num_levels = min_t(uint32_t,
579 dpm_table->count,
580 (uint32_t)PP_MAX_CLOCK_LEVELS);
581
582 for (i = 0; i < clocks->num_levels; i++) {
583 clocks->data[i].clocks_in_khz =
584 dpm_table->dpm_levels[i].value * 1000;
585 clocks->data[i].latency_in_us = 0;
586 }
587 }
588
arcturus_freqs_in_same_level(int32_t frequency1,int32_t frequency2)589 static int arcturus_freqs_in_same_level(int32_t frequency1,
590 int32_t frequency2)
591 {
592 return (abs(frequency1 - frequency2) <= EPSILON);
593 }
594
arcturus_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)595 static int arcturus_get_smu_metrics_data(struct smu_context *smu,
596 MetricsMember_t member,
597 uint32_t *value)
598 {
599 struct smu_table_context *smu_table = &smu->smu_table;
600 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
601 int ret = 0;
602
603 ret = smu_cmn_get_metrics_table(smu,
604 NULL,
605 false);
606 if (ret)
607 return ret;
608
609 switch (member) {
610 case METRICS_CURR_GFXCLK:
611 *value = metrics->CurrClock[PPCLK_GFXCLK];
612 break;
613 case METRICS_CURR_SOCCLK:
614 *value = metrics->CurrClock[PPCLK_SOCCLK];
615 break;
616 case METRICS_CURR_UCLK:
617 *value = metrics->CurrClock[PPCLK_UCLK];
618 break;
619 case METRICS_CURR_VCLK:
620 *value = metrics->CurrClock[PPCLK_VCLK];
621 break;
622 case METRICS_CURR_DCLK:
623 *value = metrics->CurrClock[PPCLK_DCLK];
624 break;
625 case METRICS_CURR_FCLK:
626 *value = metrics->CurrClock[PPCLK_FCLK];
627 break;
628 case METRICS_AVERAGE_GFXCLK:
629 *value = metrics->AverageGfxclkFrequency;
630 break;
631 case METRICS_AVERAGE_SOCCLK:
632 *value = metrics->AverageSocclkFrequency;
633 break;
634 case METRICS_AVERAGE_UCLK:
635 *value = metrics->AverageUclkFrequency;
636 break;
637 case METRICS_AVERAGE_VCLK:
638 *value = metrics->AverageVclkFrequency;
639 break;
640 case METRICS_AVERAGE_DCLK:
641 *value = metrics->AverageDclkFrequency;
642 break;
643 case METRICS_AVERAGE_GFXACTIVITY:
644 *value = metrics->AverageGfxActivity;
645 break;
646 case METRICS_AVERAGE_MEMACTIVITY:
647 *value = metrics->AverageUclkActivity;
648 break;
649 case METRICS_AVERAGE_VCNACTIVITY:
650 *value = metrics->VcnActivityPercentage;
651 break;
652 case METRICS_AVERAGE_SOCKETPOWER:
653 *value = metrics->AverageSocketPower << 8;
654 break;
655 case METRICS_TEMPERATURE_EDGE:
656 *value = metrics->TemperatureEdge *
657 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
658 break;
659 case METRICS_TEMPERATURE_HOTSPOT:
660 *value = metrics->TemperatureHotspot *
661 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
662 break;
663 case METRICS_TEMPERATURE_MEM:
664 *value = metrics->TemperatureHBM *
665 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
666 break;
667 case METRICS_TEMPERATURE_VRGFX:
668 *value = metrics->TemperatureVrGfx *
669 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
670 break;
671 case METRICS_TEMPERATURE_VRSOC:
672 *value = metrics->TemperatureVrSoc *
673 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
674 break;
675 case METRICS_TEMPERATURE_VRMEM:
676 *value = metrics->TemperatureVrMem *
677 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
678 break;
679 case METRICS_THROTTLER_STATUS:
680 *value = metrics->ThrottlerStatus;
681 break;
682 case METRICS_CURR_FANSPEED:
683 *value = metrics->CurrFanSpeed;
684 break;
685 default:
686 *value = UINT_MAX;
687 break;
688 }
689
690 return ret;
691 }
692
arcturus_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)693 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
694 enum smu_clk_type clk_type,
695 uint32_t *value)
696 {
697 MetricsMember_t member_type;
698 int clk_id = 0;
699
700 if (!value)
701 return -EINVAL;
702
703 clk_id = smu_cmn_to_asic_specific_index(smu,
704 CMN2ASIC_MAPPING_CLK,
705 clk_type);
706 if (clk_id < 0)
707 return -EINVAL;
708
709 switch (clk_id) {
710 case PPCLK_GFXCLK:
711 /*
712 * CurrClock[clk_id] can provide accurate
713 * output only when the dpm feature is enabled.
714 * We can use Average_* for dpm disabled case.
715 * But this is available for gfxclk/uclk/socclk/vclk/dclk.
716 */
717 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
718 member_type = METRICS_CURR_GFXCLK;
719 else
720 member_type = METRICS_AVERAGE_GFXCLK;
721 break;
722 case PPCLK_UCLK:
723 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
724 member_type = METRICS_CURR_UCLK;
725 else
726 member_type = METRICS_AVERAGE_UCLK;
727 break;
728 case PPCLK_SOCCLK:
729 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
730 member_type = METRICS_CURR_SOCCLK;
731 else
732 member_type = METRICS_AVERAGE_SOCCLK;
733 break;
734 case PPCLK_VCLK:
735 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
736 member_type = METRICS_CURR_VCLK;
737 else
738 member_type = METRICS_AVERAGE_VCLK;
739 break;
740 case PPCLK_DCLK:
741 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
742 member_type = METRICS_CURR_DCLK;
743 else
744 member_type = METRICS_AVERAGE_DCLK;
745 break;
746 case PPCLK_FCLK:
747 member_type = METRICS_CURR_FCLK;
748 break;
749 default:
750 return -EINVAL;
751 }
752
753 return arcturus_get_smu_metrics_data(smu,
754 member_type,
755 value);
756 }
757
arcturus_emit_clk_levels(struct smu_context * smu,enum smu_clk_type type,char * buf,int * offset)758 static int arcturus_emit_clk_levels(struct smu_context *smu,
759 enum smu_clk_type type, char *buf, int *offset)
760 {
761 int ret = 0;
762 struct pp_clock_levels_with_latency clocks;
763 struct smu_11_0_dpm_table *single_dpm_table;
764 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
765 struct smu_11_0_dpm_context *dpm_context = NULL;
766 uint32_t gen_speed, lane_width;
767 uint32_t i, cur_value = 0;
768 bool freq_match;
769 unsigned int clock_mhz;
770 static const char attempt_string[] = "Attempt to get current";
771
772 if (amdgpu_ras_intr_triggered()) {
773 *offset += sysfs_emit_at(buf, *offset, "unavailable\n");
774 return -EBUSY;
775 }
776
777 dpm_context = smu_dpm->dpm_context;
778
779 switch (type) {
780 case SMU_SCLK:
781 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &cur_value);
782 if (ret) {
783 dev_err(smu->adev->dev, "%s gfx clk Failed!", attempt_string);
784 return ret;
785 }
786
787 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
788 arcturus_get_clk_table(smu, &clocks, single_dpm_table);
789
790 break;
791
792 case SMU_MCLK:
793 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &cur_value);
794 if (ret) {
795 dev_err(smu->adev->dev, "%s mclk Failed!", attempt_string);
796 return ret;
797 }
798
799 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
800 arcturus_get_clk_table(smu, &clocks, single_dpm_table);
801
802 break;
803
804 case SMU_SOCCLK:
805 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &cur_value);
806 if (ret) {
807 dev_err(smu->adev->dev, "%s socclk Failed!", attempt_string);
808 return ret;
809 }
810
811 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
812 arcturus_get_clk_table(smu, &clocks, single_dpm_table);
813
814 break;
815
816 case SMU_FCLK:
817 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &cur_value);
818 if (ret) {
819 dev_err(smu->adev->dev, "%s fclk Failed!", attempt_string);
820 return ret;
821 }
822
823 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
824 arcturus_get_clk_table(smu, &clocks, single_dpm_table);
825
826 break;
827
828 case SMU_VCLK:
829 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &cur_value);
830 if (ret) {
831 dev_err(smu->adev->dev, "%s vclk Failed!", attempt_string);
832 return ret;
833 }
834
835 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
836 arcturus_get_clk_table(smu, &clocks, single_dpm_table);
837
838 break;
839
840 case SMU_DCLK:
841 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &cur_value);
842 if (ret) {
843 dev_err(smu->adev->dev, "%s dclk Failed!", attempt_string);
844 return ret;
845 }
846
847 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
848 arcturus_get_clk_table(smu, &clocks, single_dpm_table);
849
850 break;
851
852 case SMU_PCIE:
853 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
854 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
855 break;
856
857 default:
858 return -EINVAL;
859 }
860
861 switch (type) {
862 case SMU_SCLK:
863 case SMU_MCLK:
864 case SMU_SOCCLK:
865 case SMU_FCLK:
866 case SMU_VCLK:
867 case SMU_DCLK:
868 /*
869 * For DPM disabled case, there will be only one clock level.
870 * And it's safe to assume that is always the current clock.
871 */
872 for (i = 0; i < clocks.num_levels; i++) {
873 clock_mhz = clocks.data[i].clocks_in_khz / 1000;
874 freq_match = arcturus_freqs_in_same_level(clock_mhz, cur_value);
875 freq_match |= (clocks.num_levels == 1);
876
877 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
878 i, clock_mhz,
879 freq_match ? "*" : "");
880 }
881 break;
882
883 case SMU_PCIE:
884 *offset += sysfs_emit_at(buf, *offset, "0: %s %s %dMhz *\n",
885 (gen_speed == 0) ? "2.5GT/s," :
886 (gen_speed == 1) ? "5.0GT/s," :
887 (gen_speed == 2) ? "8.0GT/s," :
888 (gen_speed == 3) ? "16.0GT/s," : "",
889 (lane_width == 1) ? "x1" :
890 (lane_width == 2) ? "x2" :
891 (lane_width == 3) ? "x4" :
892 (lane_width == 4) ? "x8" :
893 (lane_width == 5) ? "x12" :
894 (lane_width == 6) ? "x16" : "",
895 smu->smu_table.boot_values.lclk / 100);
896 break;
897
898 default:
899 return -EINVAL;
900 }
901
902 return 0;
903 }
904
arcturus_upload_dpm_level(struct smu_context * smu,bool max,uint32_t feature_mask,uint32_t level)905 static int arcturus_upload_dpm_level(struct smu_context *smu,
906 bool max,
907 uint32_t feature_mask,
908 uint32_t level)
909 {
910 struct smu_11_0_dpm_context *dpm_context =
911 smu->smu_dpm.dpm_context;
912 uint32_t freq;
913 int ret = 0;
914
915 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
916 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
917 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
918 ret = smu_cmn_send_smc_msg_with_param(smu,
919 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
920 (PPCLK_GFXCLK << 16) | (freq & 0xffff),
921 NULL);
922 if (ret) {
923 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
924 max ? "max" : "min");
925 return ret;
926 }
927 }
928
929 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
930 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
931 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
932 ret = smu_cmn_send_smc_msg_with_param(smu,
933 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
934 (PPCLK_UCLK << 16) | (freq & 0xffff),
935 NULL);
936 if (ret) {
937 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
938 max ? "max" : "min");
939 return ret;
940 }
941 }
942
943 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
944 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
945 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
946 ret = smu_cmn_send_smc_msg_with_param(smu,
947 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
948 (PPCLK_SOCCLK << 16) | (freq & 0xffff),
949 NULL);
950 if (ret) {
951 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
952 max ? "max" : "min");
953 return ret;
954 }
955 }
956
957 return ret;
958 }
959
arcturus_force_clk_levels(struct smu_context * smu,enum smu_clk_type type,uint32_t mask)960 static int arcturus_force_clk_levels(struct smu_context *smu,
961 enum smu_clk_type type, uint32_t mask)
962 {
963 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
964 struct smu_11_0_dpm_table *single_dpm_table = NULL;
965 uint32_t soft_min_level, soft_max_level;
966 int ret = 0;
967
968 if ((smu->smc_fw_version >= 0x361200) &&
969 (smu->smc_fw_version <= 0x361a00)) {
970 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
971 "54.18 - 54.26(included) SMU firmwares\n");
972 return -EOPNOTSUPP;
973 }
974
975 soft_min_level = mask ? (ffs(mask) - 1) : 0;
976 soft_max_level = mask ? (fls(mask) - 1) : 0;
977
978 switch (type) {
979 case SMU_SCLK:
980 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
981 if (soft_max_level >= single_dpm_table->count) {
982 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
983 soft_max_level, single_dpm_table->count - 1);
984 ret = -EINVAL;
985 break;
986 }
987
988 ret = arcturus_upload_dpm_level(smu,
989 false,
990 FEATURE_DPM_GFXCLK_MASK,
991 soft_min_level);
992 if (ret) {
993 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
994 break;
995 }
996
997 ret = arcturus_upload_dpm_level(smu,
998 true,
999 FEATURE_DPM_GFXCLK_MASK,
1000 soft_max_level);
1001 if (ret)
1002 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1003
1004 break;
1005
1006 case SMU_MCLK:
1007 case SMU_SOCCLK:
1008 case SMU_FCLK:
1009 /*
1010 * Should not arrive here since Arcturus does not
1011 * support mclk/socclk/fclk softmin/softmax settings
1012 */
1013 ret = -EINVAL;
1014 break;
1015
1016 default:
1017 break;
1018 }
1019
1020 return ret;
1021 }
1022
arcturus_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)1023 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
1024 struct smu_temperature_range *range)
1025 {
1026 struct smu_table_context *table_context = &smu->smu_table;
1027 struct smu_11_0_powerplay_table *powerplay_table =
1028 table_context->power_play_table;
1029 PPTable_t *pptable = smu->smu_table.driver_pptable;
1030
1031 if (!range)
1032 return -EINVAL;
1033
1034 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1035
1036 range->max = pptable->TedgeLimit *
1037 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1038 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1039 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1040 range->hotspot_crit_max = pptable->ThotspotLimit *
1041 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1042 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1043 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1044 range->mem_crit_max = pptable->TmemLimit *
1045 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1046 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1047 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1048 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1049
1050 return 0;
1051 }
1052
arcturus_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1053 static int arcturus_read_sensor(struct smu_context *smu,
1054 enum amd_pp_sensors sensor,
1055 void *data, uint32_t *size)
1056 {
1057 struct smu_table_context *table_context = &smu->smu_table;
1058 PPTable_t *pptable = table_context->driver_pptable;
1059 int ret = 0;
1060
1061 if (amdgpu_ras_intr_triggered())
1062 return 0;
1063
1064 if (!data || !size)
1065 return -EINVAL;
1066
1067 switch (sensor) {
1068 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1069 *(uint32_t *)data = pptable->FanMaximumRpm;
1070 *size = 4;
1071 break;
1072 case AMDGPU_PP_SENSOR_MEM_LOAD:
1073 ret = arcturus_get_smu_metrics_data(smu,
1074 METRICS_AVERAGE_MEMACTIVITY,
1075 (uint32_t *)data);
1076 *size = 4;
1077 break;
1078 case AMDGPU_PP_SENSOR_GPU_LOAD:
1079 ret = arcturus_get_smu_metrics_data(smu,
1080 METRICS_AVERAGE_GFXACTIVITY,
1081 (uint32_t *)data);
1082 *size = 4;
1083 break;
1084 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1085 ret = arcturus_get_smu_metrics_data(smu,
1086 METRICS_AVERAGE_SOCKETPOWER,
1087 (uint32_t *)data);
1088 *size = 4;
1089 break;
1090 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1091 ret = arcturus_get_smu_metrics_data(smu,
1092 METRICS_TEMPERATURE_HOTSPOT,
1093 (uint32_t *)data);
1094 *size = 4;
1095 break;
1096 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1097 ret = arcturus_get_smu_metrics_data(smu,
1098 METRICS_TEMPERATURE_EDGE,
1099 (uint32_t *)data);
1100 *size = 4;
1101 break;
1102 case AMDGPU_PP_SENSOR_MEM_TEMP:
1103 ret = arcturus_get_smu_metrics_data(smu,
1104 METRICS_TEMPERATURE_MEM,
1105 (uint32_t *)data);
1106 *size = 4;
1107 break;
1108 case AMDGPU_PP_SENSOR_GFX_MCLK:
1109 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1110 /* the output clock frequency in 10K unit */
1111 *(uint32_t *)data *= 100;
1112 *size = 4;
1113 break;
1114 case AMDGPU_PP_SENSOR_GFX_SCLK:
1115 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1116 *(uint32_t *)data *= 100;
1117 *size = 4;
1118 break;
1119 case AMDGPU_PP_SENSOR_VDDGFX:
1120 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1121 *size = 4;
1122 break;
1123 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1124 default:
1125 ret = -EOPNOTSUPP;
1126 break;
1127 }
1128
1129 return ret;
1130 }
1131
arcturus_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1132 static int arcturus_set_fan_static_mode(struct smu_context *smu,
1133 uint32_t mode)
1134 {
1135 struct amdgpu_device *adev = smu->adev;
1136
1137 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
1138 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
1139 CG_FDO_CTRL2, TMIN, 0));
1140 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
1141 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
1142 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1143
1144 return 0;
1145 }
1146
arcturus_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1147 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1148 uint32_t *speed)
1149 {
1150 struct amdgpu_device *adev = smu->adev;
1151 uint32_t crystal_clock_freq = 2500;
1152 uint32_t tach_status;
1153 uint64_t tmp64;
1154 int ret = 0;
1155
1156 if (!speed)
1157 return -EINVAL;
1158
1159 switch (smu_v11_0_get_fan_control_mode(smu)) {
1160 case AMD_FAN_CTRL_AUTO:
1161 ret = arcturus_get_smu_metrics_data(smu,
1162 METRICS_CURR_FANSPEED,
1163 speed);
1164 break;
1165 default:
1166 /*
1167 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1168 * detected via register retrieving. To workaround this, we will
1169 * report the fan speed as 0 RPM if user just requested such.
1170 */
1171 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM)
1172 && !smu->user_dpm_profile.fan_speed_rpm) {
1173 *speed = 0;
1174 return 0;
1175 }
1176
1177 tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1178 tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT);
1179 if (tach_status) {
1180 do_div(tmp64, tach_status);
1181 *speed = (uint32_t)tmp64;
1182 } else {
1183 *speed = 0;
1184 }
1185
1186 break;
1187 }
1188
1189 return ret;
1190 }
1191
arcturus_set_fan_speed_pwm(struct smu_context * smu,uint32_t speed)1192 static int arcturus_set_fan_speed_pwm(struct smu_context *smu,
1193 uint32_t speed)
1194 {
1195 struct amdgpu_device *adev = smu->adev;
1196 uint32_t duty100, duty;
1197 uint64_t tmp64;
1198
1199 speed = min_t(uint32_t, speed, 255);
1200
1201 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
1202 CG_FDO_CTRL1, FMAX_DUTY100);
1203 if (!duty100)
1204 return -EINVAL;
1205
1206 tmp64 = (uint64_t)speed * duty100;
1207 do_div(tmp64, 255);
1208 duty = (uint32_t)tmp64;
1209
1210 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT,
1211 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT),
1212 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1213
1214 return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1215 }
1216
arcturus_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1217 static int arcturus_set_fan_speed_rpm(struct smu_context *smu,
1218 uint32_t speed)
1219 {
1220 struct amdgpu_device *adev = smu->adev;
1221 /*
1222 * crystal_clock_freq used for fan speed rpm calculation is
1223 * always 25Mhz. So, hardcode it as 2500(in 10K unit).
1224 */
1225 uint32_t crystal_clock_freq = 2500;
1226 uint32_t tach_period;
1227
1228 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1229 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT,
1230 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),
1231 CG_TACH_CTRL, TARGET_PERIOD,
1232 tach_period));
1233
1234 return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1235 }
1236
arcturus_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)1237 static int arcturus_get_fan_speed_pwm(struct smu_context *smu,
1238 uint32_t *speed)
1239 {
1240 struct amdgpu_device *adev = smu->adev;
1241 uint32_t duty100, duty;
1242 uint64_t tmp64;
1243
1244 /*
1245 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1246 * detected via register retrieving. To workaround this, we will
1247 * report the fan speed as 0 PWM if user just requested such.
1248 */
1249 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM)
1250 && !smu->user_dpm_profile.fan_speed_pwm) {
1251 *speed = 0;
1252 return 0;
1253 }
1254
1255 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
1256 CG_FDO_CTRL1, FMAX_DUTY100);
1257 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT),
1258 CG_THERMAL_STATUS, FDO_PWM_DUTY);
1259
1260 if (duty100) {
1261 tmp64 = (uint64_t)duty * 255;
1262 do_div(tmp64, duty100);
1263 *speed = min_t(uint32_t, tmp64, 255);
1264 } else {
1265 *speed = 0;
1266 }
1267
1268 return 0;
1269 }
1270
arcturus_get_fan_parameters(struct smu_context * smu)1271 static int arcturus_get_fan_parameters(struct smu_context *smu)
1272 {
1273 PPTable_t *pptable = smu->smu_table.driver_pptable;
1274
1275 smu->fan_max_rpm = pptable->FanMaximumRpm;
1276
1277 return 0;
1278 }
1279
arcturus_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)1280 static int arcturus_get_power_limit(struct smu_context *smu,
1281 uint32_t *current_power_limit,
1282 uint32_t *default_power_limit,
1283 uint32_t *max_power_limit,
1284 uint32_t *min_power_limit)
1285 {
1286 struct smu_11_0_powerplay_table *powerplay_table =
1287 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1288 PPTable_t *pptable = smu->smu_table.driver_pptable;
1289 uint32_t power_limit, od_percent_upper, od_percent_lower;
1290
1291 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1292 /* the last hope to figure out the ppt limit */
1293 if (!pptable) {
1294 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1295 return -EINVAL;
1296 }
1297 power_limit =
1298 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1299 }
1300
1301 if (current_power_limit)
1302 *current_power_limit = power_limit;
1303 if (default_power_limit)
1304 *default_power_limit = power_limit;
1305
1306 if (smu->od_enabled)
1307 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1308 else
1309 od_percent_upper = 0;
1310
1311 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1312
1313 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
1314 od_percent_upper, od_percent_lower, power_limit);
1315
1316 if (max_power_limit) {
1317 *max_power_limit = power_limit * (100 + od_percent_upper);
1318 *max_power_limit /= 100;
1319 }
1320
1321 if (min_power_limit) {
1322 *min_power_limit = power_limit * (100 - od_percent_lower);
1323 *min_power_limit /= 100;
1324 }
1325
1326 return 0;
1327 }
1328
arcturus_get_power_profile_mode(struct smu_context * smu,char * buf)1329 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1330 char *buf)
1331 {
1332 DpmActivityMonitorCoeffInt_t activity_monitor;
1333 static const char *title[] = {
1334 "PROFILE_INDEX(NAME)",
1335 "CLOCK_TYPE(NAME)",
1336 "FPS",
1337 "UseRlcBusy",
1338 "MinActiveFreqType",
1339 "MinActiveFreq",
1340 "BoosterFreqType",
1341 "BoosterFreq",
1342 "PD_Data_limit_c",
1343 "PD_Data_error_coeff",
1344 "PD_Data_error_rate_coeff"};
1345 uint32_t i, size = 0;
1346 int16_t workload_type = 0;
1347 int result = 0;
1348
1349 if (!buf)
1350 return -EINVAL;
1351
1352 if (smu->smc_fw_version >= 0x360d00)
1353 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1354 title[0], title[1], title[2], title[3], title[4], title[5],
1355 title[6], title[7], title[8], title[9], title[10]);
1356 else
1357 size += sysfs_emit_at(buf, size, "%16s\n",
1358 title[0]);
1359
1360 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1361 /*
1362 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1363 * Not all profile modes are supported on arcturus.
1364 */
1365 workload_type = smu_cmn_to_asic_specific_index(smu,
1366 CMN2ASIC_MAPPING_WORKLOAD,
1367 i);
1368 if (workload_type < 0)
1369 continue;
1370
1371 if (smu->smc_fw_version >= 0x360d00) {
1372 result = smu_cmn_update_table(smu,
1373 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1374 workload_type,
1375 (void *)(&activity_monitor),
1376 false);
1377 if (result) {
1378 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1379 return result;
1380 }
1381 }
1382
1383 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1384 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1385
1386 if (smu->smc_fw_version >= 0x360d00) {
1387 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1388 " ",
1389 0,
1390 "GFXCLK",
1391 activity_monitor.Gfx_FPS,
1392 activity_monitor.Gfx_UseRlcBusy,
1393 activity_monitor.Gfx_MinActiveFreqType,
1394 activity_monitor.Gfx_MinActiveFreq,
1395 activity_monitor.Gfx_BoosterFreqType,
1396 activity_monitor.Gfx_BoosterFreq,
1397 activity_monitor.Gfx_PD_Data_limit_c,
1398 activity_monitor.Gfx_PD_Data_error_coeff,
1399 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1400
1401 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1402 " ",
1403 1,
1404 "UCLK",
1405 activity_monitor.Mem_FPS,
1406 activity_monitor.Mem_UseRlcBusy,
1407 activity_monitor.Mem_MinActiveFreqType,
1408 activity_monitor.Mem_MinActiveFreq,
1409 activity_monitor.Mem_BoosterFreqType,
1410 activity_monitor.Mem_BoosterFreq,
1411 activity_monitor.Mem_PD_Data_limit_c,
1412 activity_monitor.Mem_PD_Data_error_coeff,
1413 activity_monitor.Mem_PD_Data_error_rate_coeff);
1414 }
1415 }
1416
1417 return size;
1418 }
1419
arcturus_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1420 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1421 long *input,
1422 uint32_t size)
1423 {
1424 DpmActivityMonitorCoeffInt_t activity_monitor;
1425 int workload_type = 0;
1426 uint32_t profile_mode = input[size];
1427 int ret = 0;
1428
1429 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1430 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1431 return -EINVAL;
1432 }
1433
1434
1435 if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1436 (smu->smc_fw_version >= 0x360d00)) {
1437 ret = smu_cmn_update_table(smu,
1438 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1439 WORKLOAD_PPLIB_CUSTOM_BIT,
1440 (void *)(&activity_monitor),
1441 false);
1442 if (ret) {
1443 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1444 return ret;
1445 }
1446
1447 switch (input[0]) {
1448 case 0: /* Gfxclk */
1449 activity_monitor.Gfx_FPS = input[1];
1450 activity_monitor.Gfx_UseRlcBusy = input[2];
1451 activity_monitor.Gfx_MinActiveFreqType = input[3];
1452 activity_monitor.Gfx_MinActiveFreq = input[4];
1453 activity_monitor.Gfx_BoosterFreqType = input[5];
1454 activity_monitor.Gfx_BoosterFreq = input[6];
1455 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1456 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1457 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1458 break;
1459 case 1: /* Uclk */
1460 activity_monitor.Mem_FPS = input[1];
1461 activity_monitor.Mem_UseRlcBusy = input[2];
1462 activity_monitor.Mem_MinActiveFreqType = input[3];
1463 activity_monitor.Mem_MinActiveFreq = input[4];
1464 activity_monitor.Mem_BoosterFreqType = input[5];
1465 activity_monitor.Mem_BoosterFreq = input[6];
1466 activity_monitor.Mem_PD_Data_limit_c = input[7];
1467 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1468 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1469 break;
1470 }
1471
1472 ret = smu_cmn_update_table(smu,
1473 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1474 WORKLOAD_PPLIB_CUSTOM_BIT,
1475 (void *)(&activity_monitor),
1476 true);
1477 if (ret) {
1478 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1479 return ret;
1480 }
1481 }
1482
1483 /*
1484 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1485 * Not all profile modes are supported on arcturus.
1486 */
1487 workload_type = smu_cmn_to_asic_specific_index(smu,
1488 CMN2ASIC_MAPPING_WORKLOAD,
1489 profile_mode);
1490 if (workload_type < 0) {
1491 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
1492 return -EINVAL;
1493 }
1494
1495 ret = smu_cmn_send_smc_msg_with_param(smu,
1496 SMU_MSG_SetWorkloadMask,
1497 1 << workload_type,
1498 NULL);
1499 if (ret) {
1500 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
1501 return ret;
1502 }
1503
1504 smu->power_profile_mode = profile_mode;
1505
1506 return 0;
1507 }
1508
arcturus_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1509 static int arcturus_set_performance_level(struct smu_context *smu,
1510 enum amd_dpm_forced_level level)
1511 {
1512 switch (level) {
1513 case AMD_DPM_FORCED_LEVEL_HIGH:
1514 case AMD_DPM_FORCED_LEVEL_LOW:
1515 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1516 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1517 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1518 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1519 if ((smu->smc_fw_version >= 0x361200) &&
1520 (smu->smc_fw_version <= 0x361a00)) {
1521 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1522 "54.18 - 54.26(included) SMU firmwares\n");
1523 return -EOPNOTSUPP;
1524 }
1525 break;
1526 default:
1527 break;
1528 }
1529
1530 return smu_v11_0_set_performance_level(smu, level);
1531 }
1532
arcturus_dump_pptable(struct smu_context * smu)1533 static void arcturus_dump_pptable(struct smu_context *smu)
1534 {
1535 struct smu_table_context *table_context = &smu->smu_table;
1536 PPTable_t *pptable = table_context->driver_pptable;
1537 int i;
1538
1539 dev_info(smu->adev->dev, "Dumped PPTable:\n");
1540
1541 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1542
1543 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1544 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1545
1546 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1547 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1548 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1549 }
1550
1551 dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1552 dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1553 dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1554 dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1555
1556 dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit);
1557 dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit);
1558 dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit);
1559 dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1560 dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1561 dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1562 dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit);
1563
1564 dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1565 dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1566
1567 dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1568
1569 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1570 dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding);
1571
1572 dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1573 dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1574 dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1575 dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1576
1577 dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1578 dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1579 dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1580 dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1581
1582 dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1583 dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1584
1585 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1586 " .VoltageMode = 0x%02x\n"
1587 " .SnapToDiscrete = 0x%02x\n"
1588 " .NumDiscreteLevels = 0x%02x\n"
1589 " .padding = 0x%02x\n"
1590 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1591 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1592 " .SsFmin = 0x%04x\n"
1593 " .Padding_16 = 0x%04x\n",
1594 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1595 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1596 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1597 pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1598 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1599 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1600 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1601 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1602 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1603 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1604 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1605
1606 dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"
1607 " .VoltageMode = 0x%02x\n"
1608 " .SnapToDiscrete = 0x%02x\n"
1609 " .NumDiscreteLevels = 0x%02x\n"
1610 " .padding = 0x%02x\n"
1611 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1612 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1613 " .SsFmin = 0x%04x\n"
1614 " .Padding_16 = 0x%04x\n",
1615 pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1616 pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1617 pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1618 pptable->DpmDescriptor[PPCLK_VCLK].padding,
1619 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1620 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1621 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1622 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1623 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1624 pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1625 pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1626
1627 dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"
1628 " .VoltageMode = 0x%02x\n"
1629 " .SnapToDiscrete = 0x%02x\n"
1630 " .NumDiscreteLevels = 0x%02x\n"
1631 " .padding = 0x%02x\n"
1632 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1633 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1634 " .SsFmin = 0x%04x\n"
1635 " .Padding_16 = 0x%04x\n",
1636 pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1637 pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1638 pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1639 pptable->DpmDescriptor[PPCLK_DCLK].padding,
1640 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1641 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1642 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1643 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1644 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1645 pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1646 pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1647
1648 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1649 " .VoltageMode = 0x%02x\n"
1650 " .SnapToDiscrete = 0x%02x\n"
1651 " .NumDiscreteLevels = 0x%02x\n"
1652 " .padding = 0x%02x\n"
1653 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1654 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1655 " .SsFmin = 0x%04x\n"
1656 " .Padding_16 = 0x%04x\n",
1657 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1658 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1659 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1660 pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1661 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1662 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1663 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1664 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1665 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1666 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1667 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1668
1669 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1670 " .VoltageMode = 0x%02x\n"
1671 " .SnapToDiscrete = 0x%02x\n"
1672 " .NumDiscreteLevels = 0x%02x\n"
1673 " .padding = 0x%02x\n"
1674 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1675 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1676 " .SsFmin = 0x%04x\n"
1677 " .Padding_16 = 0x%04x\n",
1678 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1679 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1680 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1681 pptable->DpmDescriptor[PPCLK_UCLK].padding,
1682 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1683 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1684 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1685 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1686 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1687 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1688 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1689
1690 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1691 " .VoltageMode = 0x%02x\n"
1692 " .SnapToDiscrete = 0x%02x\n"
1693 " .NumDiscreteLevels = 0x%02x\n"
1694 " .padding = 0x%02x\n"
1695 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1696 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1697 " .SsFmin = 0x%04x\n"
1698 " .Padding_16 = 0x%04x\n",
1699 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1700 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1701 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1702 pptable->DpmDescriptor[PPCLK_FCLK].padding,
1703 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1704 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1705 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1706 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1707 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1708 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1709 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1710
1711
1712 dev_info(smu->adev->dev, "FreqTableGfx\n");
1713 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1714 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1715
1716 dev_info(smu->adev->dev, "FreqTableVclk\n");
1717 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1718 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1719
1720 dev_info(smu->adev->dev, "FreqTableDclk\n");
1721 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1722 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1723
1724 dev_info(smu->adev->dev, "FreqTableSocclk\n");
1725 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1726 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1727
1728 dev_info(smu->adev->dev, "FreqTableUclk\n");
1729 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1730 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1731
1732 dev_info(smu->adev->dev, "FreqTableFclk\n");
1733 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1734 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1735
1736 dev_info(smu->adev->dev, "Mp0clkFreq\n");
1737 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1738 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1739
1740 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
1741 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1742 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1743
1744 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1745 dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1746 dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1747 dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1748 dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1749 dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1750 dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1751 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1752 dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456);
1753
1754 dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm);
1755 dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1756 dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1757 dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1758
1759 dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp);
1760 dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp);
1761
1762 dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge);
1763 dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot);
1764 dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1765 dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1766 dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem);
1767 dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm);
1768
1769 dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin);
1770 dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1771 dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1772 dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1773 dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1774 dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1775 dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1776 dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1777 dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1778
1779 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1780 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1781 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1782 dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1783
1784 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1785 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1786 dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1787 dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1788
1789 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1790 pptable->dBtcGbGfxPll.a,
1791 pptable->dBtcGbGfxPll.b,
1792 pptable->dBtcGbGfxPll.c);
1793 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1794 pptable->dBtcGbGfxAfll.a,
1795 pptable->dBtcGbGfxAfll.b,
1796 pptable->dBtcGbGfxAfll.c);
1797 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1798 pptable->dBtcGbSoc.a,
1799 pptable->dBtcGbSoc.b,
1800 pptable->dBtcGbSoc.c);
1801
1802 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1803 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1804 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1805 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1806 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1807 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1808
1809 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1810 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1811 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1812 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1813 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1814 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1815 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1816 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1817
1818 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1819 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1820
1821 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1822 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1823 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1824 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1825
1826 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1827 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1828 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1829 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1830
1831 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1832 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1833
1834 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
1835 for (i = 0; i < NUM_XGMI_LEVELS; i++)
1836 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1837 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1838 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1839
1840 dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1841 dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1842 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1843 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1844 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1845 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1846 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1847 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1848
1849 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1850 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1851 pptable->ReservedEquation0.a,
1852 pptable->ReservedEquation0.b,
1853 pptable->ReservedEquation0.c);
1854 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1855 pptable->ReservedEquation1.a,
1856 pptable->ReservedEquation1.b,
1857 pptable->ReservedEquation1.c);
1858 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1859 pptable->ReservedEquation2.a,
1860 pptable->ReservedEquation2.b,
1861 pptable->ReservedEquation2.c);
1862 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1863 pptable->ReservedEquation3.a,
1864 pptable->ReservedEquation3.b,
1865 pptable->ReservedEquation3.c);
1866
1867 dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1868 dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv);
1869
1870 dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1871 dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1872 dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1873
1874 dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow);
1875 dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1876
1877 dev_info(smu->adev->dev, "Board Parameters:\n");
1878 dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1879 dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1880
1881 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1882 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1883 dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1884 dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1885
1886 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1887 dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1888
1889 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1890 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
1891 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1892
1893 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1894 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
1895 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1896
1897 dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1898 dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset);
1899 dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1900
1901 dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1902 dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset);
1903 dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1904
1905 dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio);
1906 dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1907 dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio);
1908 dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1909
1910 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1911 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1912 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1913
1914 dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1915 dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1916 dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1917
1918 dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1919 dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1920 dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1921
1922 dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1923 dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1924 dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1925
1926 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1927 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
1928 dev_info(smu->adev->dev, " .Enabled = %d\n",
1929 pptable->I2cControllers[i].Enabled);
1930 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
1931 pptable->I2cControllers[i].SlaveAddress);
1932 dev_info(smu->adev->dev, " .ControllerPort = %d\n",
1933 pptable->I2cControllers[i].ControllerPort);
1934 dev_info(smu->adev->dev, " .ControllerName = %d\n",
1935 pptable->I2cControllers[i].ControllerName);
1936 dev_info(smu->adev->dev, " .ThermalThrottler = %d\n",
1937 pptable->I2cControllers[i].ThermalThrotter);
1938 dev_info(smu->adev->dev, " .I2cProtocol = %d\n",
1939 pptable->I2cControllers[i].I2cProtocol);
1940 dev_info(smu->adev->dev, " .Speed = %d\n",
1941 pptable->I2cControllers[i].Speed);
1942 }
1943
1944 dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1945 dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth);
1946
1947 dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower);
1948
1949 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
1950 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1951 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1952 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
1953 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1954 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1955 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
1956 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1957 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1958 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
1959 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1960 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1961
1962 }
1963
arcturus_is_dpm_running(struct smu_context * smu)1964 static bool arcturus_is_dpm_running(struct smu_context *smu)
1965 {
1966 int ret = 0;
1967 uint64_t feature_enabled;
1968
1969 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1970 if (ret)
1971 return false;
1972
1973 return !!(feature_enabled & SMC_DPM_FEATURE);
1974 }
1975
arcturus_dpm_set_vcn_enable(struct smu_context * smu,bool enable)1976 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1977 {
1978 int ret = 0;
1979
1980 if (enable) {
1981 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
1982 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 1);
1983 if (ret) {
1984 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
1985 return ret;
1986 }
1987 }
1988 } else {
1989 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
1990 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 0);
1991 if (ret) {
1992 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
1993 return ret;
1994 }
1995 }
1996 }
1997
1998 return ret;
1999 }
2000
arcturus_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)2001 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
2002 struct i2c_msg *msg, int num_msgs)
2003 {
2004 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2005 struct amdgpu_device *adev = smu_i2c->adev;
2006 struct smu_context *smu = adev->powerplay.pp_handle;
2007 struct smu_table_context *smu_table = &smu->smu_table;
2008 struct smu_table *table = &smu_table->driver_table;
2009 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2010 int i, j, r, c;
2011 u16 dir;
2012
2013 if (!adev->pm.dpm_enabled)
2014 return -EBUSY;
2015
2016 req = kzalloc(sizeof(*req), GFP_KERNEL);
2017 if (!req)
2018 return -ENOMEM;
2019
2020 req->I2CcontrollerPort = smu_i2c->port;
2021 req->I2CSpeed = I2C_SPEED_FAST_400K;
2022 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2023 dir = msg[0].flags & I2C_M_RD;
2024
2025 for (c = i = 0; i < num_msgs; i++) {
2026 for (j = 0; j < msg[i].len; j++, c++) {
2027 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2028
2029 if (!(msg[i].flags & I2C_M_RD)) {
2030 /* write */
2031 cmd->Cmd = I2C_CMD_WRITE;
2032 cmd->RegisterAddr = msg[i].buf[j];
2033 }
2034
2035 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2036 /* The direction changes.
2037 */
2038 dir = msg[i].flags & I2C_M_RD;
2039 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2040 }
2041
2042 req->NumCmds++;
2043
2044 /*
2045 * Insert STOP if we are at the last byte of either last
2046 * message for the transaction or the client explicitly
2047 * requires a STOP at this particular message.
2048 */
2049 if ((j == msg[i].len - 1) &&
2050 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2051 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2052 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2053 }
2054 }
2055 }
2056 mutex_lock(&adev->pm.mutex);
2057 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2058 if (r)
2059 goto fail;
2060
2061 for (c = i = 0; i < num_msgs; i++) {
2062 if (!(msg[i].flags & I2C_M_RD)) {
2063 c += msg[i].len;
2064 continue;
2065 }
2066 for (j = 0; j < msg[i].len; j++, c++) {
2067 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2068
2069 msg[i].buf[j] = cmd->Data;
2070 }
2071 }
2072 r = num_msgs;
2073 fail:
2074 mutex_unlock(&adev->pm.mutex);
2075 kfree(req);
2076 return r;
2077 }
2078
arcturus_i2c_func(struct i2c_adapter * adap)2079 static u32 arcturus_i2c_func(struct i2c_adapter *adap)
2080 {
2081 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2082 }
2083
2084
2085 static const struct i2c_algorithm arcturus_i2c_algo = {
2086 .master_xfer = arcturus_i2c_xfer,
2087 .functionality = arcturus_i2c_func,
2088 };
2089
2090
2091 static const struct i2c_adapter_quirks arcturus_i2c_control_quirks = {
2092 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2093 .max_read_len = MAX_SW_I2C_COMMANDS,
2094 .max_write_len = MAX_SW_I2C_COMMANDS,
2095 .max_comb_1st_msg_len = 2,
2096 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2097 };
2098
arcturus_i2c_control_init(struct smu_context * smu)2099 static int arcturus_i2c_control_init(struct smu_context *smu)
2100 {
2101 struct amdgpu_device *adev = smu->adev;
2102 int res, i;
2103
2104 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2105 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2106 struct i2c_adapter *control = &smu_i2c->adapter;
2107
2108 smu_i2c->adev = adev;
2109 smu_i2c->port = i;
2110 mutex_init(&smu_i2c->mutex);
2111 control->owner = THIS_MODULE;
2112 control->class = I2C_CLASS_HWMON;
2113 control->dev.parent = &adev->pdev->dev;
2114 control->algo = &arcturus_i2c_algo;
2115 control->quirks = &arcturus_i2c_control_quirks;
2116 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2117 i2c_set_adapdata(control, smu_i2c);
2118
2119 res = i2c_add_adapter(control);
2120 if (res) {
2121 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2122 goto Out_err;
2123 }
2124 }
2125
2126 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2127 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
2128
2129 return 0;
2130 Out_err:
2131 for ( ; i >= 0; i--) {
2132 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2133 struct i2c_adapter *control = &smu_i2c->adapter;
2134
2135 i2c_del_adapter(control);
2136 }
2137 return res;
2138 }
2139
arcturus_i2c_control_fini(struct smu_context * smu)2140 static void arcturus_i2c_control_fini(struct smu_context *smu)
2141 {
2142 struct amdgpu_device *adev = smu->adev;
2143 int i;
2144
2145 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2146 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2147 struct i2c_adapter *control = &smu_i2c->adapter;
2148
2149 i2c_del_adapter(control);
2150 }
2151 adev->pm.ras_eeprom_i2c_bus = NULL;
2152 adev->pm.fru_eeprom_i2c_bus = NULL;
2153 }
2154
arcturus_get_unique_id(struct smu_context * smu)2155 static void arcturus_get_unique_id(struct smu_context *smu)
2156 {
2157 struct amdgpu_device *adev = smu->adev;
2158 uint32_t top32 = 0, bottom32 = 0;
2159 uint64_t id;
2160
2161 /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2162 if (smu->smc_fw_version < 0x361700) {
2163 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
2164 return;
2165 }
2166
2167 /* Get the SN to turn into a Unique ID */
2168 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2169 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2170
2171 id = ((uint64_t)bottom32 << 32) | top32;
2172 adev->unique_id = id;
2173 }
2174
arcturus_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)2175 static int arcturus_set_df_cstate(struct smu_context *smu,
2176 enum pp_df_cstate state)
2177 {
2178 struct amdgpu_device *adev = smu->adev;
2179
2180 /*
2181 * Arcturus does not need the cstate disablement
2182 * prerequisite for gpu reset.
2183 */
2184 if (amdgpu_in_reset(adev) || adev->in_suspend)
2185 return 0;
2186
2187 /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2188 if (smu->smc_fw_version < 0x360F00) {
2189 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2190 return -EINVAL;
2191 }
2192
2193 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2194 }
2195
arcturus_select_xgmi_plpd_policy(struct smu_context * smu,enum pp_xgmi_plpd_mode mode)2196 static int arcturus_select_xgmi_plpd_policy(struct smu_context *smu,
2197 enum pp_xgmi_plpd_mode mode)
2198 {
2199 /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2200 if (smu->smc_fw_version < 0x00361700) {
2201 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
2202 return -EINVAL;
2203 }
2204
2205 if (mode == XGMI_PLPD_DEFAULT)
2206 return smu_cmn_send_smc_msg_with_param(smu,
2207 SMU_MSG_GmiPwrDnControl,
2208 1, NULL);
2209 else if (mode == XGMI_PLPD_DISALLOW)
2210 return smu_cmn_send_smc_msg_with_param(smu,
2211 SMU_MSG_GmiPwrDnControl,
2212 0, NULL);
2213 else
2214 return -EINVAL;
2215 }
2216
2217 static const struct throttling_logging_label {
2218 uint32_t feature_mask;
2219 const char *label;
2220 } logging_label[] = {
2221 {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
2222 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
2223 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
2224 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
2225 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
2226 {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
2227 {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
2228 };
arcturus_log_thermal_throttling_event(struct smu_context * smu)2229 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2230 {
2231 int ret;
2232 int throttler_idx, throttling_events = 0, buf_idx = 0;
2233 struct amdgpu_device *adev = smu->adev;
2234 uint32_t throttler_status;
2235 char log_buf[256];
2236
2237 ret = arcturus_get_smu_metrics_data(smu,
2238 METRICS_THROTTLER_STATUS,
2239 &throttler_status);
2240 if (ret)
2241 return;
2242
2243 memset(log_buf, 0, sizeof(log_buf));
2244 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
2245 throttler_idx++) {
2246 if (throttler_status & logging_label[throttler_idx].feature_mask) {
2247 throttling_events++;
2248 buf_idx += snprintf(log_buf + buf_idx,
2249 sizeof(log_buf) - buf_idx,
2250 "%s%s",
2251 throttling_events > 1 ? " and " : "",
2252 logging_label[throttler_idx].label);
2253 if (buf_idx >= sizeof(log_buf)) {
2254 dev_err(adev->dev, "buffer overflow!\n");
2255 log_buf[sizeof(log_buf) - 1] = '\0';
2256 break;
2257 }
2258 }
2259 }
2260
2261 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
2262 log_buf);
2263 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
2264 smu_cmn_get_indep_throttler_status(throttler_status,
2265 arcturus_throttler_map));
2266 }
2267
arcturus_get_current_pcie_link_speed(struct smu_context * smu)2268 static uint16_t arcturus_get_current_pcie_link_speed(struct smu_context *smu)
2269 {
2270 struct amdgpu_device *adev = smu->adev;
2271 uint32_t esm_ctrl;
2272
2273 /* TODO: confirm this on real target */
2274 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2275 if ((esm_ctrl >> 15) & 0x1FFFF)
2276 return (uint16_t)(((esm_ctrl >> 8) & 0x3F) + 128);
2277
2278 return smu_v11_0_get_current_pcie_link_speed(smu);
2279 }
2280
arcturus_get_gpu_metrics(struct smu_context * smu,void ** table)2281 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
2282 void **table)
2283 {
2284 struct smu_table_context *smu_table = &smu->smu_table;
2285 struct gpu_metrics_v1_3 *gpu_metrics =
2286 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2287 SmuMetrics_t metrics;
2288 int ret = 0;
2289
2290 ret = smu_cmn_get_metrics_table(smu,
2291 &metrics,
2292 true);
2293 if (ret)
2294 return ret;
2295
2296 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2297
2298 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2299 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2300 gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2301 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2302 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2303 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2304
2305 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2306 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2307 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2308
2309 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2310 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2311
2312 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2313 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2314 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2315 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2316 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2317
2318 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2319 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2320 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2321 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2322 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2323
2324 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2325 gpu_metrics->indep_throttle_status =
2326 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2327 arcturus_throttler_map);
2328
2329 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2330
2331 gpu_metrics->pcie_link_width =
2332 smu_v11_0_get_current_pcie_link_width(smu);
2333 gpu_metrics->pcie_link_speed =
2334 arcturus_get_current_pcie_link_speed(smu);
2335
2336 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2337
2338 *table = (void *)gpu_metrics;
2339
2340 return sizeof(struct gpu_metrics_v1_3);
2341 }
2342
2343 static const struct pptable_funcs arcturus_ppt_funcs = {
2344 /* init dpm */
2345 .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2346 /* btc */
2347 .run_btc = arcturus_run_btc,
2348 /* dpm/clk tables */
2349 .set_default_dpm_table = arcturus_set_default_dpm_table,
2350 .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2351 .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2352 .emit_clk_levels = arcturus_emit_clk_levels,
2353 .force_clk_levels = arcturus_force_clk_levels,
2354 .read_sensor = arcturus_read_sensor,
2355 .get_fan_speed_pwm = arcturus_get_fan_speed_pwm,
2356 .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2357 .get_power_profile_mode = arcturus_get_power_profile_mode,
2358 .set_power_profile_mode = arcturus_set_power_profile_mode,
2359 .set_performance_level = arcturus_set_performance_level,
2360 /* debug (internal used) */
2361 .dump_pptable = arcturus_dump_pptable,
2362 .get_power_limit = arcturus_get_power_limit,
2363 .is_dpm_running = arcturus_is_dpm_running,
2364 .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
2365 .i2c_init = arcturus_i2c_control_init,
2366 .i2c_fini = arcturus_i2c_control_fini,
2367 .get_unique_id = arcturus_get_unique_id,
2368 .init_microcode = smu_v11_0_init_microcode,
2369 .load_microcode = smu_v11_0_load_microcode,
2370 .fini_microcode = smu_v11_0_fini_microcode,
2371 .init_smc_tables = arcturus_init_smc_tables,
2372 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2373 .init_power = smu_v11_0_init_power,
2374 .fini_power = smu_v11_0_fini_power,
2375 .check_fw_status = smu_v11_0_check_fw_status,
2376 /* pptable related */
2377 .setup_pptable = arcturus_setup_pptable,
2378 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2379 .check_fw_version = smu_v11_0_check_fw_version,
2380 .write_pptable = smu_cmn_write_pptable,
2381 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2382 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2383 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2384 .system_features_control = smu_v11_0_system_features_control,
2385 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2386 .send_smc_msg = smu_cmn_send_smc_msg,
2387 .init_display_count = NULL,
2388 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2389 .get_enabled_mask = smu_cmn_get_enabled_mask,
2390 .feature_is_enabled = smu_cmn_feature_is_enabled,
2391 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2392 .notify_display_change = NULL,
2393 .set_power_limit = smu_v11_0_set_power_limit,
2394 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2395 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2396 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2397 .set_min_dcef_deep_sleep = NULL,
2398 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2399 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2400 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2401 .set_fan_speed_pwm = arcturus_set_fan_speed_pwm,
2402 .set_fan_speed_rpm = arcturus_set_fan_speed_rpm,
2403 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2404 .gfx_off_control = smu_v11_0_gfx_off_control,
2405 .register_irq_handler = smu_v11_0_register_irq_handler,
2406 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2407 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2408 .baco_is_support = smu_v11_0_baco_is_support,
2409 .baco_enter = smu_v11_0_baco_enter,
2410 .baco_exit = smu_v11_0_baco_exit,
2411 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2412 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2413 .set_df_cstate = arcturus_set_df_cstate,
2414 .select_xgmi_plpd_policy = arcturus_select_xgmi_plpd_policy,
2415 .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2416 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2417 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2418 .get_gpu_metrics = arcturus_get_gpu_metrics,
2419 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2420 .deep_sleep_control = smu_v11_0_deep_sleep_control,
2421 .get_fan_parameters = arcturus_get_fan_parameters,
2422 .interrupt_work = smu_v11_0_interrupt_work,
2423 .smu_handle_passthrough_sbr = smu_v11_0_handle_passthrough_sbr,
2424 .set_mp1_state = smu_cmn_set_mp1_state,
2425 };
2426
arcturus_set_ppt_funcs(struct smu_context * smu)2427 void arcturus_set_ppt_funcs(struct smu_context *smu)
2428 {
2429 smu->ppt_funcs = &arcturus_ppt_funcs;
2430 smu->message_map = arcturus_message_map;
2431 smu->clock_map = arcturus_clk_map;
2432 smu->feature_map = arcturus_feature_mask_map;
2433 smu->table_map = arcturus_table_map;
2434 smu->pwr_src_map = arcturus_pwr_src_map;
2435 smu->workload_map = arcturus_workload_map;
2436 smu_v11_0_set_smu_mailbox_registers(smu);
2437 }
2438