1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_smu.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "amdgpu_atombios.h"
32 #include "smu_v11_0.h"
33 #include "smu11_driver_if_arcturus.h"
34 #include "soc15_common.h"
35 #include "atom.h"
36 #include "power_state.h"
37 #include "arcturus_ppt.h"
38 #include "smu_v11_0_pptable.h"
39 #include "arcturus_ppsmc.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/i2c.h>
46 #include <linux/pci.h>
47 #include "amdgpu_ras.h"
48 #include "smu_cmn.h"
49
50 /*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61
62 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
63 [smu_feature] = {1, (arcturus_feature)}
64
65 #define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF
66 #define SMU_FEATURES_LOW_SHIFT 0
67 #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000
68 #define SMU_FEATURES_HIGH_SHIFT 32
69
70 #define SMC_DPM_FEATURE ( \
71 FEATURE_DPM_PREFETCHER_MASK | \
72 FEATURE_DPM_GFXCLK_MASK | \
73 FEATURE_DPM_UCLK_MASK | \
74 FEATURE_DPM_SOCCLK_MASK | \
75 FEATURE_DPM_MP0CLK_MASK | \
76 FEATURE_DPM_FCLK_MASK | \
77 FEATURE_DPM_XGMI_MASK)
78
79 /* possible frequency drift (1Mhz) */
80 #define EPSILON 1
81
82 #define smnPCIE_ESM_CTRL 0x111003D0
83
84 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
85 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
86 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
87 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
88 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
89 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
90 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
91 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
92 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
93 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
94 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0),
95 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0),
96 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 0),
97 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 0),
98 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
99 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
100 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
101 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
102 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
103 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
104 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
105 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0),
106 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
107 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0),
108 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
109 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
110 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
111 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
112 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
113 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0),
114 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
115 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0),
116 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0),
117 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
118 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
119 MSG_MAP(SetDfSwitchType, PPSMC_MSG_SetDfSwitchType, 0),
120 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
121 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
122 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
123 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
124 MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0, 0),
125 MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0, 0),
126 MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1, 0),
127 MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1, 0),
128 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
129 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0),
130 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0),
131 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 0),
132 MSG_MAP(RunAfllBtc, PPSMC_MSG_RunAfllBtc, 0),
133 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
134 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
135 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
136 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
137 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
138 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0),
139 MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode, 0),
140 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0),
141 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
142 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
143 MSG_MAP(ReadSerialNumTop32, PPSMC_MSG_ReadSerialNumTop32, 1),
144 MSG_MAP(ReadSerialNumBottom32, PPSMC_MSG_ReadSerialNumBottom32, 1),
145 };
146
147 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
148 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
149 CLK_MAP(SCLK, PPCLK_GFXCLK),
150 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
151 CLK_MAP(FCLK, PPCLK_FCLK),
152 CLK_MAP(UCLK, PPCLK_UCLK),
153 CLK_MAP(MCLK, PPCLK_UCLK),
154 CLK_MAP(DCLK, PPCLK_DCLK),
155 CLK_MAP(VCLK, PPCLK_VCLK),
156 };
157
158 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
159 FEA_MAP(DPM_PREFETCHER),
160 FEA_MAP(DPM_GFXCLK),
161 FEA_MAP(DPM_UCLK),
162 FEA_MAP(DPM_SOCCLK),
163 FEA_MAP(DPM_FCLK),
164 FEA_MAP(DPM_MP0CLK),
165 ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
166 FEA_MAP(DS_GFXCLK),
167 FEA_MAP(DS_SOCCLK),
168 FEA_MAP(DS_LCLK),
169 FEA_MAP(DS_FCLK),
170 FEA_MAP(DS_UCLK),
171 FEA_MAP(GFX_ULV),
172 ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
173 FEA_MAP(RSMU_SMN_CG),
174 FEA_MAP(WAFL_CG),
175 FEA_MAP(PPT),
176 FEA_MAP(TDC),
177 FEA_MAP(APCC_PLUS),
178 FEA_MAP(VR0HOT),
179 FEA_MAP(VR1HOT),
180 FEA_MAP(FW_CTF),
181 FEA_MAP(FAN_CONTROL),
182 FEA_MAP(THERMAL),
183 FEA_MAP(OUT_OF_BAND_MONITOR),
184 FEA_MAP(TEMP_DEPENDENT_VMIN),
185 };
186
187 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
188 TAB_MAP(PPTABLE),
189 TAB_MAP(AVFS),
190 TAB_MAP(AVFS_PSM_DEBUG),
191 TAB_MAP(AVFS_FUSE_OVERRIDE),
192 TAB_MAP(PMSTATUSLOG),
193 TAB_MAP(SMU_METRICS),
194 TAB_MAP(DRIVER_SMU_CONFIG),
195 TAB_MAP(OVERDRIVE),
196 TAB_MAP(I2C_COMMANDS),
197 TAB_MAP(ACTIVITY_MONITOR_COEFF),
198 };
199
200 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
201 PWR_MAP(AC),
202 PWR_MAP(DC),
203 };
204
205 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
208 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
209 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
210 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
211 };
212
arcturus_tables_init(struct smu_context * smu)213 static int arcturus_tables_init(struct smu_context *smu)
214 {
215 struct smu_table_context *smu_table = &smu->smu_table;
216 struct smu_table *tables = smu_table->tables;
217
218 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
219 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
220
221 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
222 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
223
224 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
225 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
226
227 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
228 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
229
230 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
231 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
232 AMDGPU_GEM_DOMAIN_VRAM);
233
234 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
235 if (!smu_table->metrics_table)
236 return -ENOMEM;
237 smu_table->metrics_time = 0;
238
239 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
240 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
241 if (!smu_table->gpu_metrics_table) {
242 kfree(smu_table->metrics_table);
243 return -ENOMEM;
244 }
245
246 return 0;
247 }
248
arcturus_allocate_dpm_context(struct smu_context * smu)249 static int arcturus_allocate_dpm_context(struct smu_context *smu)
250 {
251 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
252
253 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
254 GFP_KERNEL);
255 if (!smu_dpm->dpm_context)
256 return -ENOMEM;
257 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
258
259 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
260 GFP_KERNEL);
261 if (!smu_dpm->dpm_current_power_state)
262 return -ENOMEM;
263
264 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
265 GFP_KERNEL);
266 if (!smu_dpm->dpm_request_power_state)
267 return -ENOMEM;
268
269 return 0;
270 }
271
arcturus_init_smc_tables(struct smu_context * smu)272 static int arcturus_init_smc_tables(struct smu_context *smu)
273 {
274 int ret = 0;
275
276 ret = arcturus_tables_init(smu);
277 if (ret)
278 return ret;
279
280 ret = arcturus_allocate_dpm_context(smu);
281 if (ret)
282 return ret;
283
284 return smu_v11_0_init_smc_tables(smu);
285 }
286
287 static int
arcturus_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)288 arcturus_get_allowed_feature_mask(struct smu_context *smu,
289 uint32_t *feature_mask, uint32_t num)
290 {
291 if (num > 2)
292 return -EINVAL;
293
294 /* pptable will handle the features to enable */
295 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
296
297 return 0;
298 }
299
arcturus_set_default_dpm_table(struct smu_context * smu)300 static int arcturus_set_default_dpm_table(struct smu_context *smu)
301 {
302 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
303 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
304 struct smu_11_0_dpm_table *dpm_table = NULL;
305 int ret = 0;
306
307 /* socclk dpm table setup */
308 dpm_table = &dpm_context->dpm_tables.soc_table;
309 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
310 ret = smu_v11_0_set_single_dpm_table(smu,
311 SMU_SOCCLK,
312 dpm_table);
313 if (ret)
314 return ret;
315 dpm_table->is_fine_grained =
316 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
317 } else {
318 dpm_table->count = 1;
319 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
320 dpm_table->dpm_levels[0].enabled = true;
321 dpm_table->min = dpm_table->dpm_levels[0].value;
322 dpm_table->max = dpm_table->dpm_levels[0].value;
323 }
324
325 /* gfxclk dpm table setup */
326 dpm_table = &dpm_context->dpm_tables.gfx_table;
327 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
328 ret = smu_v11_0_set_single_dpm_table(smu,
329 SMU_GFXCLK,
330 dpm_table);
331 if (ret)
332 return ret;
333 dpm_table->is_fine_grained =
334 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
335 } else {
336 dpm_table->count = 1;
337 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
338 dpm_table->dpm_levels[0].enabled = true;
339 dpm_table->min = dpm_table->dpm_levels[0].value;
340 dpm_table->max = dpm_table->dpm_levels[0].value;
341 }
342
343 /* memclk dpm table setup */
344 dpm_table = &dpm_context->dpm_tables.uclk_table;
345 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
346 ret = smu_v11_0_set_single_dpm_table(smu,
347 SMU_UCLK,
348 dpm_table);
349 if (ret)
350 return ret;
351 dpm_table->is_fine_grained =
352 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
353 } else {
354 dpm_table->count = 1;
355 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
356 dpm_table->dpm_levels[0].enabled = true;
357 dpm_table->min = dpm_table->dpm_levels[0].value;
358 dpm_table->max = dpm_table->dpm_levels[0].value;
359 }
360
361 /* fclk dpm table setup */
362 dpm_table = &dpm_context->dpm_tables.fclk_table;
363 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
364 ret = smu_v11_0_set_single_dpm_table(smu,
365 SMU_FCLK,
366 dpm_table);
367 if (ret)
368 return ret;
369 dpm_table->is_fine_grained =
370 !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
371 } else {
372 dpm_table->count = 1;
373 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
374 dpm_table->dpm_levels[0].enabled = true;
375 dpm_table->min = dpm_table->dpm_levels[0].value;
376 dpm_table->max = dpm_table->dpm_levels[0].value;
377 }
378
379 return 0;
380 }
381
arcturus_check_powerplay_table(struct smu_context * smu)382 static int arcturus_check_powerplay_table(struct smu_context *smu)
383 {
384 struct smu_table_context *table_context = &smu->smu_table;
385 struct smu_11_0_powerplay_table *powerplay_table =
386 table_context->power_play_table;
387 struct smu_baco_context *smu_baco = &smu->smu_baco;
388
389 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
390 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
391 smu_baco->platform_support = true;
392
393 table_context->thermal_controller_type =
394 powerplay_table->thermal_controller_type;
395
396 return 0;
397 }
398
arcturus_store_powerplay_table(struct smu_context * smu)399 static int arcturus_store_powerplay_table(struct smu_context *smu)
400 {
401 struct smu_table_context *table_context = &smu->smu_table;
402 struct smu_11_0_powerplay_table *powerplay_table =
403 table_context->power_play_table;
404
405 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
406 sizeof(PPTable_t));
407
408 return 0;
409 }
410
arcturus_append_powerplay_table(struct smu_context * smu)411 static int arcturus_append_powerplay_table(struct smu_context *smu)
412 {
413 struct smu_table_context *table_context = &smu->smu_table;
414 PPTable_t *smc_pptable = table_context->driver_pptable;
415 struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
416 int index, ret;
417
418 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
419 smc_dpm_info);
420
421 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
422 (uint8_t **)&smc_dpm_table);
423 if (ret)
424 return ret;
425
426 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
427 smc_dpm_table->table_header.format_revision,
428 smc_dpm_table->table_header.content_revision);
429
430 if ((smc_dpm_table->table_header.format_revision == 4) &&
431 (smc_dpm_table->table_header.content_revision == 6))
432 memcpy(&smc_pptable->MaxVoltageStepGfx,
433 &smc_dpm_table->maxvoltagestepgfx,
434 sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
435
436 return 0;
437 }
438
arcturus_setup_pptable(struct smu_context * smu)439 static int arcturus_setup_pptable(struct smu_context *smu)
440 {
441 int ret = 0;
442
443 ret = smu_v11_0_setup_pptable(smu);
444 if (ret)
445 return ret;
446
447 ret = arcturus_store_powerplay_table(smu);
448 if (ret)
449 return ret;
450
451 ret = arcturus_append_powerplay_table(smu);
452 if (ret)
453 return ret;
454
455 ret = arcturus_check_powerplay_table(smu);
456 if (ret)
457 return ret;
458
459 return ret;
460 }
461
arcturus_run_btc(struct smu_context * smu)462 static int arcturus_run_btc(struct smu_context *smu)
463 {
464 int ret = 0;
465
466 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
467 if (ret) {
468 dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
469 return ret;
470 }
471
472 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
473 }
474
arcturus_populate_umd_state_clk(struct smu_context * smu)475 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
476 {
477 struct smu_11_0_dpm_context *dpm_context =
478 smu->smu_dpm.dpm_context;
479 struct smu_11_0_dpm_table *gfx_table =
480 &dpm_context->dpm_tables.gfx_table;
481 struct smu_11_0_dpm_table *mem_table =
482 &dpm_context->dpm_tables.uclk_table;
483 struct smu_11_0_dpm_table *soc_table =
484 &dpm_context->dpm_tables.soc_table;
485 struct smu_umd_pstate_table *pstate_table =
486 &smu->pstate_table;
487
488 pstate_table->gfxclk_pstate.min = gfx_table->min;
489 pstate_table->gfxclk_pstate.peak = gfx_table->max;
490
491 pstate_table->uclk_pstate.min = mem_table->min;
492 pstate_table->uclk_pstate.peak = mem_table->max;
493
494 pstate_table->socclk_pstate.min = soc_table->min;
495 pstate_table->socclk_pstate.peak = soc_table->max;
496
497 if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
498 mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
499 soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
500 pstate_table->gfxclk_pstate.standard =
501 gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
502 pstate_table->uclk_pstate.standard =
503 mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
504 pstate_table->socclk_pstate.standard =
505 soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
506 } else {
507 pstate_table->gfxclk_pstate.standard =
508 pstate_table->gfxclk_pstate.min;
509 pstate_table->uclk_pstate.standard =
510 pstate_table->uclk_pstate.min;
511 pstate_table->socclk_pstate.standard =
512 pstate_table->socclk_pstate.min;
513 }
514
515 return 0;
516 }
517
arcturus_get_clk_table(struct smu_context * smu,struct pp_clock_levels_with_latency * clocks,struct smu_11_0_dpm_table * dpm_table)518 static int arcturus_get_clk_table(struct smu_context *smu,
519 struct pp_clock_levels_with_latency *clocks,
520 struct smu_11_0_dpm_table *dpm_table)
521 {
522 int i, count;
523
524 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
525 clocks->num_levels = count;
526
527 for (i = 0; i < count; i++) {
528 clocks->data[i].clocks_in_khz =
529 dpm_table->dpm_levels[i].value * 1000;
530 clocks->data[i].latency_in_us = 0;
531 }
532
533 return 0;
534 }
535
arcturus_freqs_in_same_level(int32_t frequency1,int32_t frequency2)536 static int arcturus_freqs_in_same_level(int32_t frequency1,
537 int32_t frequency2)
538 {
539 return (abs(frequency1 - frequency2) <= EPSILON);
540 }
541
arcturus_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)542 static int arcturus_get_smu_metrics_data(struct smu_context *smu,
543 MetricsMember_t member,
544 uint32_t *value)
545 {
546 struct smu_table_context *smu_table= &smu->smu_table;
547 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
548 int ret = 0;
549
550 mutex_lock(&smu->metrics_lock);
551
552 ret = smu_cmn_get_metrics_table_locked(smu,
553 NULL,
554 false);
555 if (ret) {
556 mutex_unlock(&smu->metrics_lock);
557 return ret;
558 }
559
560 switch (member) {
561 case METRICS_CURR_GFXCLK:
562 *value = metrics->CurrClock[PPCLK_GFXCLK];
563 break;
564 case METRICS_CURR_SOCCLK:
565 *value = metrics->CurrClock[PPCLK_SOCCLK];
566 break;
567 case METRICS_CURR_UCLK:
568 *value = metrics->CurrClock[PPCLK_UCLK];
569 break;
570 case METRICS_CURR_VCLK:
571 *value = metrics->CurrClock[PPCLK_VCLK];
572 break;
573 case METRICS_CURR_DCLK:
574 *value = metrics->CurrClock[PPCLK_DCLK];
575 break;
576 case METRICS_CURR_FCLK:
577 *value = metrics->CurrClock[PPCLK_FCLK];
578 break;
579 case METRICS_AVERAGE_GFXCLK:
580 *value = metrics->AverageGfxclkFrequency;
581 break;
582 case METRICS_AVERAGE_SOCCLK:
583 *value = metrics->AverageSocclkFrequency;
584 break;
585 case METRICS_AVERAGE_UCLK:
586 *value = metrics->AverageUclkFrequency;
587 break;
588 case METRICS_AVERAGE_VCLK:
589 *value = metrics->AverageVclkFrequency;
590 break;
591 case METRICS_AVERAGE_DCLK:
592 *value = metrics->AverageDclkFrequency;
593 break;
594 case METRICS_AVERAGE_GFXACTIVITY:
595 *value = metrics->AverageGfxActivity;
596 break;
597 case METRICS_AVERAGE_MEMACTIVITY:
598 *value = metrics->AverageUclkActivity;
599 break;
600 case METRICS_AVERAGE_VCNACTIVITY:
601 *value = metrics->VcnActivityPercentage;
602 break;
603 case METRICS_AVERAGE_SOCKETPOWER:
604 *value = metrics->AverageSocketPower << 8;
605 break;
606 case METRICS_TEMPERATURE_EDGE:
607 *value = metrics->TemperatureEdge *
608 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
609 break;
610 case METRICS_TEMPERATURE_HOTSPOT:
611 *value = metrics->TemperatureHotspot *
612 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
613 break;
614 case METRICS_TEMPERATURE_MEM:
615 *value = metrics->TemperatureHBM *
616 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
617 break;
618 case METRICS_TEMPERATURE_VRGFX:
619 *value = metrics->TemperatureVrGfx *
620 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
621 break;
622 case METRICS_TEMPERATURE_VRSOC:
623 *value = metrics->TemperatureVrSoc *
624 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
625 break;
626 case METRICS_TEMPERATURE_VRMEM:
627 *value = metrics->TemperatureVrMem *
628 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
629 break;
630 case METRICS_THROTTLER_STATUS:
631 *value = metrics->ThrottlerStatus;
632 break;
633 case METRICS_CURR_FANSPEED:
634 *value = metrics->CurrFanSpeed;
635 break;
636 default:
637 *value = UINT_MAX;
638 break;
639 }
640
641 mutex_unlock(&smu->metrics_lock);
642
643 return ret;
644 }
645
arcturus_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)646 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
647 enum smu_clk_type clk_type,
648 uint32_t *value)
649 {
650 MetricsMember_t member_type;
651 int clk_id = 0;
652
653 if (!value)
654 return -EINVAL;
655
656 clk_id = smu_cmn_to_asic_specific_index(smu,
657 CMN2ASIC_MAPPING_CLK,
658 clk_type);
659 if (clk_id < 0)
660 return -EINVAL;
661
662 switch (clk_id) {
663 case PPCLK_GFXCLK:
664 /*
665 * CurrClock[clk_id] can provide accurate
666 * output only when the dpm feature is enabled.
667 * We can use Average_* for dpm disabled case.
668 * But this is available for gfxclk/uclk/socclk/vclk/dclk.
669 */
670 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
671 member_type = METRICS_CURR_GFXCLK;
672 else
673 member_type = METRICS_AVERAGE_GFXCLK;
674 break;
675 case PPCLK_UCLK:
676 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
677 member_type = METRICS_CURR_UCLK;
678 else
679 member_type = METRICS_AVERAGE_UCLK;
680 break;
681 case PPCLK_SOCCLK:
682 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
683 member_type = METRICS_CURR_SOCCLK;
684 else
685 member_type = METRICS_AVERAGE_SOCCLK;
686 break;
687 case PPCLK_VCLK:
688 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
689 member_type = METRICS_CURR_VCLK;
690 else
691 member_type = METRICS_AVERAGE_VCLK;
692 break;
693 case PPCLK_DCLK:
694 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
695 member_type = METRICS_CURR_DCLK;
696 else
697 member_type = METRICS_AVERAGE_DCLK;
698 break;
699 case PPCLK_FCLK:
700 member_type = METRICS_CURR_FCLK;
701 break;
702 default:
703 return -EINVAL;
704 }
705
706 return arcturus_get_smu_metrics_data(smu,
707 member_type,
708 value);
709 }
710
arcturus_print_clk_levels(struct smu_context * smu,enum smu_clk_type type,char * buf)711 static int arcturus_print_clk_levels(struct smu_context *smu,
712 enum smu_clk_type type, char *buf)
713 {
714 int i, now, size = 0;
715 int ret = 0;
716 struct pp_clock_levels_with_latency clocks;
717 struct smu_11_0_dpm_table *single_dpm_table;
718 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
719 struct smu_11_0_dpm_context *dpm_context = NULL;
720
721 if (amdgpu_ras_intr_triggered())
722 return snprintf(buf, PAGE_SIZE, "unavailable\n");
723
724 dpm_context = smu_dpm->dpm_context;
725
726 switch (type) {
727 case SMU_SCLK:
728 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
729 if (ret) {
730 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
731 return ret;
732 }
733
734 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
735 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
736 if (ret) {
737 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
738 return ret;
739 }
740
741 /*
742 * For DPM disabled case, there will be only one clock level.
743 * And it's safe to assume that is always the current clock.
744 */
745 for (i = 0; i < clocks.num_levels; i++)
746 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
747 clocks.data[i].clocks_in_khz / 1000,
748 (clocks.num_levels == 1) ? "*" :
749 (arcturus_freqs_in_same_level(
750 clocks.data[i].clocks_in_khz / 1000,
751 now) ? "*" : ""));
752 break;
753
754 case SMU_MCLK:
755 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
756 if (ret) {
757 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
758 return ret;
759 }
760
761 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
762 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
763 if (ret) {
764 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
765 return ret;
766 }
767
768 for (i = 0; i < clocks.num_levels; i++)
769 size += sprintf(buf + size, "%d: %uMhz %s\n",
770 i, clocks.data[i].clocks_in_khz / 1000,
771 (clocks.num_levels == 1) ? "*" :
772 (arcturus_freqs_in_same_level(
773 clocks.data[i].clocks_in_khz / 1000,
774 now) ? "*" : ""));
775 break;
776
777 case SMU_SOCCLK:
778 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
779 if (ret) {
780 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
781 return ret;
782 }
783
784 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
785 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
786 if (ret) {
787 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
788 return ret;
789 }
790
791 for (i = 0; i < clocks.num_levels; i++)
792 size += sprintf(buf + size, "%d: %uMhz %s\n",
793 i, clocks.data[i].clocks_in_khz / 1000,
794 (clocks.num_levels == 1) ? "*" :
795 (arcturus_freqs_in_same_level(
796 clocks.data[i].clocks_in_khz / 1000,
797 now) ? "*" : ""));
798 break;
799
800 case SMU_FCLK:
801 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
802 if (ret) {
803 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
804 return ret;
805 }
806
807 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
808 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
809 if (ret) {
810 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
811 return ret;
812 }
813
814 for (i = 0; i < single_dpm_table->count; i++)
815 size += sprintf(buf + size, "%d: %uMhz %s\n",
816 i, single_dpm_table->dpm_levels[i].value,
817 (clocks.num_levels == 1) ? "*" :
818 (arcturus_freqs_in_same_level(
819 clocks.data[i].clocks_in_khz / 1000,
820 now) ? "*" : ""));
821 break;
822
823 default:
824 break;
825 }
826
827 return size;
828 }
829
arcturus_upload_dpm_level(struct smu_context * smu,bool max,uint32_t feature_mask,uint32_t level)830 static int arcturus_upload_dpm_level(struct smu_context *smu,
831 bool max,
832 uint32_t feature_mask,
833 uint32_t level)
834 {
835 struct smu_11_0_dpm_context *dpm_context =
836 smu->smu_dpm.dpm_context;
837 uint32_t freq;
838 int ret = 0;
839
840 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
841 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
842 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
843 ret = smu_cmn_send_smc_msg_with_param(smu,
844 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
845 (PPCLK_GFXCLK << 16) | (freq & 0xffff),
846 NULL);
847 if (ret) {
848 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
849 max ? "max" : "min");
850 return ret;
851 }
852 }
853
854 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
855 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
856 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
857 ret = smu_cmn_send_smc_msg_with_param(smu,
858 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
859 (PPCLK_UCLK << 16) | (freq & 0xffff),
860 NULL);
861 if (ret) {
862 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
863 max ? "max" : "min");
864 return ret;
865 }
866 }
867
868 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
869 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
870 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
871 ret = smu_cmn_send_smc_msg_with_param(smu,
872 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
873 (PPCLK_SOCCLK << 16) | (freq & 0xffff),
874 NULL);
875 if (ret) {
876 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
877 max ? "max" : "min");
878 return ret;
879 }
880 }
881
882 return ret;
883 }
884
arcturus_force_clk_levels(struct smu_context * smu,enum smu_clk_type type,uint32_t mask)885 static int arcturus_force_clk_levels(struct smu_context *smu,
886 enum smu_clk_type type, uint32_t mask)
887 {
888 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
889 struct smu_11_0_dpm_table *single_dpm_table = NULL;
890 uint32_t soft_min_level, soft_max_level;
891 uint32_t smu_version;
892 int ret = 0;
893
894 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
895 if (ret) {
896 dev_err(smu->adev->dev, "Failed to get smu version!\n");
897 return ret;
898 }
899
900 if ((smu_version >= 0x361200) &&
901 (smu_version <= 0x361a00)) {
902 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
903 "54.18 - 54.26(included) SMU firmwares\n");
904 return -EOPNOTSUPP;
905 }
906
907 soft_min_level = mask ? (ffs(mask) - 1) : 0;
908 soft_max_level = mask ? (fls(mask) - 1) : 0;
909
910 switch (type) {
911 case SMU_SCLK:
912 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
913 if (soft_max_level >= single_dpm_table->count) {
914 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
915 soft_max_level, single_dpm_table->count - 1);
916 ret = -EINVAL;
917 break;
918 }
919
920 ret = arcturus_upload_dpm_level(smu,
921 false,
922 FEATURE_DPM_GFXCLK_MASK,
923 soft_min_level);
924 if (ret) {
925 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
926 break;
927 }
928
929 ret = arcturus_upload_dpm_level(smu,
930 true,
931 FEATURE_DPM_GFXCLK_MASK,
932 soft_max_level);
933 if (ret)
934 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
935
936 break;
937
938 case SMU_MCLK:
939 case SMU_SOCCLK:
940 case SMU_FCLK:
941 /*
942 * Should not arrive here since Arcturus does not
943 * support mclk/socclk/fclk softmin/softmax settings
944 */
945 ret = -EINVAL;
946 break;
947
948 default:
949 break;
950 }
951
952 return ret;
953 }
954
arcturus_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)955 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
956 struct smu_temperature_range *range)
957 {
958 struct smu_table_context *table_context = &smu->smu_table;
959 struct smu_11_0_powerplay_table *powerplay_table =
960 table_context->power_play_table;
961 PPTable_t *pptable = smu->smu_table.driver_pptable;
962
963 if (!range)
964 return -EINVAL;
965
966 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
967
968 range->max = pptable->TedgeLimit *
969 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
970 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
971 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
972 range->hotspot_crit_max = pptable->ThotspotLimit *
973 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
974 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
975 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
976 range->mem_crit_max = pptable->TmemLimit *
977 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
978 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
979 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
980 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
981
982 return 0;
983 }
984
arcturus_get_current_activity_percent(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)985 static int arcturus_get_current_activity_percent(struct smu_context *smu,
986 enum amd_pp_sensors sensor,
987 uint32_t *value)
988 {
989 int ret = 0;
990
991 if (!value)
992 return -EINVAL;
993
994 switch (sensor) {
995 case AMDGPU_PP_SENSOR_GPU_LOAD:
996 ret = arcturus_get_smu_metrics_data(smu,
997 METRICS_AVERAGE_GFXACTIVITY,
998 value);
999 break;
1000 case AMDGPU_PP_SENSOR_MEM_LOAD:
1001 ret = arcturus_get_smu_metrics_data(smu,
1002 METRICS_AVERAGE_MEMACTIVITY,
1003 value);
1004 break;
1005 default:
1006 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1007 return -EINVAL;
1008 }
1009
1010 return ret;
1011 }
1012
arcturus_get_gpu_power(struct smu_context * smu,uint32_t * value)1013 static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
1014 {
1015 if (!value)
1016 return -EINVAL;
1017
1018 return arcturus_get_smu_metrics_data(smu,
1019 METRICS_AVERAGE_SOCKETPOWER,
1020 value);
1021 }
1022
arcturus_thermal_get_temperature(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1023 static int arcturus_thermal_get_temperature(struct smu_context *smu,
1024 enum amd_pp_sensors sensor,
1025 uint32_t *value)
1026 {
1027 int ret = 0;
1028
1029 if (!value)
1030 return -EINVAL;
1031
1032 switch (sensor) {
1033 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1034 ret = arcturus_get_smu_metrics_data(smu,
1035 METRICS_TEMPERATURE_HOTSPOT,
1036 value);
1037 break;
1038 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1039 ret = arcturus_get_smu_metrics_data(smu,
1040 METRICS_TEMPERATURE_EDGE,
1041 value);
1042 break;
1043 case AMDGPU_PP_SENSOR_MEM_TEMP:
1044 ret = arcturus_get_smu_metrics_data(smu,
1045 METRICS_TEMPERATURE_MEM,
1046 value);
1047 break;
1048 default:
1049 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1050 return -EINVAL;
1051 }
1052
1053 return ret;
1054 }
1055
arcturus_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1056 static int arcturus_read_sensor(struct smu_context *smu,
1057 enum amd_pp_sensors sensor,
1058 void *data, uint32_t *size)
1059 {
1060 struct smu_table_context *table_context = &smu->smu_table;
1061 PPTable_t *pptable = table_context->driver_pptable;
1062 int ret = 0;
1063
1064 if (amdgpu_ras_intr_triggered())
1065 return 0;
1066
1067 if (!data || !size)
1068 return -EINVAL;
1069
1070 mutex_lock(&smu->sensor_lock);
1071 switch (sensor) {
1072 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1073 *(uint32_t *)data = pptable->FanMaximumRpm;
1074 *size = 4;
1075 break;
1076 case AMDGPU_PP_SENSOR_MEM_LOAD:
1077 case AMDGPU_PP_SENSOR_GPU_LOAD:
1078 ret = arcturus_get_current_activity_percent(smu,
1079 sensor,
1080 (uint32_t *)data);
1081 *size = 4;
1082 break;
1083 case AMDGPU_PP_SENSOR_GPU_POWER:
1084 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
1085 *size = 4;
1086 break;
1087 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1088 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1089 case AMDGPU_PP_SENSOR_MEM_TEMP:
1090 ret = arcturus_thermal_get_temperature(smu, sensor,
1091 (uint32_t *)data);
1092 *size = 4;
1093 break;
1094 case AMDGPU_PP_SENSOR_GFX_MCLK:
1095 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1096 /* the output clock frequency in 10K unit */
1097 *(uint32_t *)data *= 100;
1098 *size = 4;
1099 break;
1100 case AMDGPU_PP_SENSOR_GFX_SCLK:
1101 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1102 *(uint32_t *)data *= 100;
1103 *size = 4;
1104 break;
1105 case AMDGPU_PP_SENSOR_VDDGFX:
1106 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1107 *size = 4;
1108 break;
1109 default:
1110 ret = -EOPNOTSUPP;
1111 break;
1112 }
1113 mutex_unlock(&smu->sensor_lock);
1114
1115 return ret;
1116 }
1117
arcturus_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1118 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1119 uint32_t *speed)
1120 {
1121 if (!speed)
1122 return -EINVAL;
1123
1124 switch (smu_v11_0_get_fan_control_mode(smu)) {
1125 case AMD_FAN_CTRL_AUTO:
1126 return arcturus_get_smu_metrics_data(smu,
1127 METRICS_CURR_FANSPEED,
1128 speed);
1129 default:
1130 return smu_v11_0_get_fan_speed_rpm(smu, speed);
1131 }
1132 }
1133
arcturus_get_fan_parameters(struct smu_context * smu)1134 static int arcturus_get_fan_parameters(struct smu_context *smu)
1135 {
1136 PPTable_t *pptable = smu->smu_table.driver_pptable;
1137
1138 smu->fan_max_rpm = pptable->FanMaximumRpm;
1139
1140 return 0;
1141 }
1142
arcturus_get_power_limit(struct smu_context * smu)1143 static int arcturus_get_power_limit(struct smu_context *smu)
1144 {
1145 struct smu_11_0_powerplay_table *powerplay_table =
1146 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1147 PPTable_t *pptable = smu->smu_table.driver_pptable;
1148 uint32_t power_limit, od_percent;
1149
1150 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1151 /* the last hope to figure out the ppt limit */
1152 if (!pptable) {
1153 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1154 return -EINVAL;
1155 }
1156 power_limit =
1157 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1158 }
1159 smu->current_power_limit = power_limit;
1160
1161 if (smu->od_enabled) {
1162 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1163
1164 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1165
1166 power_limit *= (100 + od_percent);
1167 power_limit /= 100;
1168 }
1169 smu->max_power_limit = power_limit;
1170
1171 return 0;
1172 }
1173
arcturus_get_power_profile_mode(struct smu_context * smu,char * buf)1174 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1175 char *buf)
1176 {
1177 DpmActivityMonitorCoeffInt_t activity_monitor;
1178 static const char *profile_name[] = {
1179 "BOOTUP_DEFAULT",
1180 "3D_FULL_SCREEN",
1181 "POWER_SAVING",
1182 "VIDEO",
1183 "VR",
1184 "COMPUTE",
1185 "CUSTOM"};
1186 static const char *title[] = {
1187 "PROFILE_INDEX(NAME)",
1188 "CLOCK_TYPE(NAME)",
1189 "FPS",
1190 "UseRlcBusy",
1191 "MinActiveFreqType",
1192 "MinActiveFreq",
1193 "BoosterFreqType",
1194 "BoosterFreq",
1195 "PD_Data_limit_c",
1196 "PD_Data_error_coeff",
1197 "PD_Data_error_rate_coeff"};
1198 uint32_t i, size = 0;
1199 int16_t workload_type = 0;
1200 int result = 0;
1201 uint32_t smu_version;
1202
1203 if (!buf)
1204 return -EINVAL;
1205
1206 result = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1207 if (result)
1208 return result;
1209
1210 if (smu_version >= 0x360d00)
1211 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1212 title[0], title[1], title[2], title[3], title[4], title[5],
1213 title[6], title[7], title[8], title[9], title[10]);
1214 else
1215 size += sprintf(buf + size, "%16s\n",
1216 title[0]);
1217
1218 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1219 /*
1220 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1221 * Not all profile modes are supported on arcturus.
1222 */
1223 workload_type = smu_cmn_to_asic_specific_index(smu,
1224 CMN2ASIC_MAPPING_WORKLOAD,
1225 i);
1226 if (workload_type < 0)
1227 continue;
1228
1229 if (smu_version >= 0x360d00) {
1230 result = smu_cmn_update_table(smu,
1231 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1232 workload_type,
1233 (void *)(&activity_monitor),
1234 false);
1235 if (result) {
1236 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1237 return result;
1238 }
1239 }
1240
1241 size += sprintf(buf + size, "%2d %14s%s\n",
1242 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1243
1244 if (smu_version >= 0x360d00) {
1245 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1246 " ",
1247 0,
1248 "GFXCLK",
1249 activity_monitor.Gfx_FPS,
1250 activity_monitor.Gfx_UseRlcBusy,
1251 activity_monitor.Gfx_MinActiveFreqType,
1252 activity_monitor.Gfx_MinActiveFreq,
1253 activity_monitor.Gfx_BoosterFreqType,
1254 activity_monitor.Gfx_BoosterFreq,
1255 activity_monitor.Gfx_PD_Data_limit_c,
1256 activity_monitor.Gfx_PD_Data_error_coeff,
1257 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1258
1259 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1260 " ",
1261 1,
1262 "UCLK",
1263 activity_monitor.Mem_FPS,
1264 activity_monitor.Mem_UseRlcBusy,
1265 activity_monitor.Mem_MinActiveFreqType,
1266 activity_monitor.Mem_MinActiveFreq,
1267 activity_monitor.Mem_BoosterFreqType,
1268 activity_monitor.Mem_BoosterFreq,
1269 activity_monitor.Mem_PD_Data_limit_c,
1270 activity_monitor.Mem_PD_Data_error_coeff,
1271 activity_monitor.Mem_PD_Data_error_rate_coeff);
1272 }
1273 }
1274
1275 return size;
1276 }
1277
arcturus_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1278 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1279 long *input,
1280 uint32_t size)
1281 {
1282 DpmActivityMonitorCoeffInt_t activity_monitor;
1283 int workload_type = 0;
1284 uint32_t profile_mode = input[size];
1285 int ret = 0;
1286 uint32_t smu_version;
1287
1288 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1289 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1290 return -EINVAL;
1291 }
1292
1293 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1294 if (ret)
1295 return ret;
1296
1297 if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1298 (smu_version >=0x360d00)) {
1299 ret = smu_cmn_update_table(smu,
1300 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1301 WORKLOAD_PPLIB_CUSTOM_BIT,
1302 (void *)(&activity_monitor),
1303 false);
1304 if (ret) {
1305 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1306 return ret;
1307 }
1308
1309 switch (input[0]) {
1310 case 0: /* Gfxclk */
1311 activity_monitor.Gfx_FPS = input[1];
1312 activity_monitor.Gfx_UseRlcBusy = input[2];
1313 activity_monitor.Gfx_MinActiveFreqType = input[3];
1314 activity_monitor.Gfx_MinActiveFreq = input[4];
1315 activity_monitor.Gfx_BoosterFreqType = input[5];
1316 activity_monitor.Gfx_BoosterFreq = input[6];
1317 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1318 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1319 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1320 break;
1321 case 1: /* Uclk */
1322 activity_monitor.Mem_FPS = input[1];
1323 activity_monitor.Mem_UseRlcBusy = input[2];
1324 activity_monitor.Mem_MinActiveFreqType = input[3];
1325 activity_monitor.Mem_MinActiveFreq = input[4];
1326 activity_monitor.Mem_BoosterFreqType = input[5];
1327 activity_monitor.Mem_BoosterFreq = input[6];
1328 activity_monitor.Mem_PD_Data_limit_c = input[7];
1329 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1330 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1331 break;
1332 }
1333
1334 ret = smu_cmn_update_table(smu,
1335 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1336 WORKLOAD_PPLIB_CUSTOM_BIT,
1337 (void *)(&activity_monitor),
1338 true);
1339 if (ret) {
1340 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1341 return ret;
1342 }
1343 }
1344
1345 /*
1346 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1347 * Not all profile modes are supported on arcturus.
1348 */
1349 workload_type = smu_cmn_to_asic_specific_index(smu,
1350 CMN2ASIC_MAPPING_WORKLOAD,
1351 profile_mode);
1352 if (workload_type < 0) {
1353 dev_err(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
1354 return -EINVAL;
1355 }
1356
1357 ret = smu_cmn_send_smc_msg_with_param(smu,
1358 SMU_MSG_SetWorkloadMask,
1359 1 << workload_type,
1360 NULL);
1361 if (ret) {
1362 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
1363 return ret;
1364 }
1365
1366 smu->power_profile_mode = profile_mode;
1367
1368 return 0;
1369 }
1370
arcturus_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1371 static int arcturus_set_performance_level(struct smu_context *smu,
1372 enum amd_dpm_forced_level level)
1373 {
1374 uint32_t smu_version;
1375 int ret;
1376
1377 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1378 if (ret) {
1379 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1380 return ret;
1381 }
1382
1383 switch (level) {
1384 case AMD_DPM_FORCED_LEVEL_HIGH:
1385 case AMD_DPM_FORCED_LEVEL_LOW:
1386 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1387 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1388 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1389 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1390 if ((smu_version >= 0x361200) &&
1391 (smu_version <= 0x361a00)) {
1392 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1393 "54.18 - 54.26(included) SMU firmwares\n");
1394 return -EOPNOTSUPP;
1395 }
1396 break;
1397 default:
1398 break;
1399 }
1400
1401 return smu_v11_0_set_performance_level(smu, level);
1402 }
1403
arcturus_dump_pptable(struct smu_context * smu)1404 static void arcturus_dump_pptable(struct smu_context *smu)
1405 {
1406 struct smu_table_context *table_context = &smu->smu_table;
1407 PPTable_t *pptable = table_context->driver_pptable;
1408 int i;
1409
1410 dev_info(smu->adev->dev, "Dumped PPTable:\n");
1411
1412 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1413
1414 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1415 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1416
1417 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1418 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1419 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1420 }
1421
1422 dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1423 dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1424 dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1425 dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1426
1427 dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit);
1428 dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit);
1429 dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit);
1430 dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1431 dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1432 dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1433 dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit);
1434
1435 dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1436 dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1437
1438 dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1439
1440 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1441 dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding);
1442
1443 dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1444 dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1445 dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1446 dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1447
1448 dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1449 dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1450 dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1451 dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1452
1453 dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1454 dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1455
1456 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1457 " .VoltageMode = 0x%02x\n"
1458 " .SnapToDiscrete = 0x%02x\n"
1459 " .NumDiscreteLevels = 0x%02x\n"
1460 " .padding = 0x%02x\n"
1461 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1462 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1463 " .SsFmin = 0x%04x\n"
1464 " .Padding_16 = 0x%04x\n",
1465 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1466 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1467 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1468 pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1469 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1470 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1471 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1472 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1473 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1474 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1475 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1476
1477 dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"
1478 " .VoltageMode = 0x%02x\n"
1479 " .SnapToDiscrete = 0x%02x\n"
1480 " .NumDiscreteLevels = 0x%02x\n"
1481 " .padding = 0x%02x\n"
1482 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1483 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1484 " .SsFmin = 0x%04x\n"
1485 " .Padding_16 = 0x%04x\n",
1486 pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1487 pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1488 pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1489 pptable->DpmDescriptor[PPCLK_VCLK].padding,
1490 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1491 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1492 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1493 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1494 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1495 pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1496 pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1497
1498 dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"
1499 " .VoltageMode = 0x%02x\n"
1500 " .SnapToDiscrete = 0x%02x\n"
1501 " .NumDiscreteLevels = 0x%02x\n"
1502 " .padding = 0x%02x\n"
1503 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1504 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1505 " .SsFmin = 0x%04x\n"
1506 " .Padding_16 = 0x%04x\n",
1507 pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1508 pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1509 pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1510 pptable->DpmDescriptor[PPCLK_DCLK].padding,
1511 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1512 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1513 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1514 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1515 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1516 pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1517 pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1518
1519 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1520 " .VoltageMode = 0x%02x\n"
1521 " .SnapToDiscrete = 0x%02x\n"
1522 " .NumDiscreteLevels = 0x%02x\n"
1523 " .padding = 0x%02x\n"
1524 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1525 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1526 " .SsFmin = 0x%04x\n"
1527 " .Padding_16 = 0x%04x\n",
1528 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1529 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1530 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1531 pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1532 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1533 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1534 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1535 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1536 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1537 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1538 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1539
1540 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1541 " .VoltageMode = 0x%02x\n"
1542 " .SnapToDiscrete = 0x%02x\n"
1543 " .NumDiscreteLevels = 0x%02x\n"
1544 " .padding = 0x%02x\n"
1545 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1546 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1547 " .SsFmin = 0x%04x\n"
1548 " .Padding_16 = 0x%04x\n",
1549 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1550 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1551 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1552 pptable->DpmDescriptor[PPCLK_UCLK].padding,
1553 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1554 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1555 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1556 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1557 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1558 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1559 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1560
1561 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1562 " .VoltageMode = 0x%02x\n"
1563 " .SnapToDiscrete = 0x%02x\n"
1564 " .NumDiscreteLevels = 0x%02x\n"
1565 " .padding = 0x%02x\n"
1566 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1567 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1568 " .SsFmin = 0x%04x\n"
1569 " .Padding_16 = 0x%04x\n",
1570 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1571 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1572 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1573 pptable->DpmDescriptor[PPCLK_FCLK].padding,
1574 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1575 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1576 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1577 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1578 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1579 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1580 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1581
1582
1583 dev_info(smu->adev->dev, "FreqTableGfx\n");
1584 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1585 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1586
1587 dev_info(smu->adev->dev, "FreqTableVclk\n");
1588 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1589 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1590
1591 dev_info(smu->adev->dev, "FreqTableDclk\n");
1592 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1593 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1594
1595 dev_info(smu->adev->dev, "FreqTableSocclk\n");
1596 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1597 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1598
1599 dev_info(smu->adev->dev, "FreqTableUclk\n");
1600 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1601 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1602
1603 dev_info(smu->adev->dev, "FreqTableFclk\n");
1604 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1605 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1606
1607 dev_info(smu->adev->dev, "Mp0clkFreq\n");
1608 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1609 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1610
1611 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
1612 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1613 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1614
1615 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1616 dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1617 dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1618 dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1619 dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1620 dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1621 dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1622 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1623 dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456);
1624
1625 dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm);
1626 dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1627 dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1628 dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1629
1630 dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp);
1631 dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp);
1632
1633 dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge);
1634 dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot);
1635 dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1636 dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1637 dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem);
1638 dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm);
1639
1640 dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin);
1641 dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1642 dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1643 dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1644 dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1645 dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1646 dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1647 dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1648 dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1649
1650 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1651 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1652 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1653 dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1654
1655 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1656 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1657 dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1658 dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1659
1660 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1661 pptable->dBtcGbGfxPll.a,
1662 pptable->dBtcGbGfxPll.b,
1663 pptable->dBtcGbGfxPll.c);
1664 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1665 pptable->dBtcGbGfxAfll.a,
1666 pptable->dBtcGbGfxAfll.b,
1667 pptable->dBtcGbGfxAfll.c);
1668 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1669 pptable->dBtcGbSoc.a,
1670 pptable->dBtcGbSoc.b,
1671 pptable->dBtcGbSoc.c);
1672
1673 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1674 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1675 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1676 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1677 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1678 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1679
1680 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1681 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1682 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1683 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1684 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1685 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1686 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1687 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1688
1689 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1690 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1691
1692 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1693 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1694 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1695 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1696
1697 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1698 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1699 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1700 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1701
1702 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1703 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1704
1705 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
1706 for (i = 0; i < NUM_XGMI_LEVELS; i++)
1707 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1708 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1709 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1710
1711 dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1712 dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1713 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1714 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1715 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1716 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1717 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1718 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1719
1720 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1721 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1722 pptable->ReservedEquation0.a,
1723 pptable->ReservedEquation0.b,
1724 pptable->ReservedEquation0.c);
1725 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1726 pptable->ReservedEquation1.a,
1727 pptable->ReservedEquation1.b,
1728 pptable->ReservedEquation1.c);
1729 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1730 pptable->ReservedEquation2.a,
1731 pptable->ReservedEquation2.b,
1732 pptable->ReservedEquation2.c);
1733 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1734 pptable->ReservedEquation3.a,
1735 pptable->ReservedEquation3.b,
1736 pptable->ReservedEquation3.c);
1737
1738 dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1739 dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv);
1740
1741 dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1742 dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1743 dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1744
1745 dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow);
1746 dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1747
1748 dev_info(smu->adev->dev, "Board Parameters:\n");
1749 dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1750 dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1751
1752 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1753 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1754 dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1755 dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1756
1757 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1758 dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1759
1760 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1761 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
1762 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1763
1764 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1765 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
1766 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1767
1768 dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1769 dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset);
1770 dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1771
1772 dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1773 dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset);
1774 dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1775
1776 dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio);
1777 dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1778 dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio);
1779 dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1780
1781 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1782 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1783 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1784
1785 dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1786 dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1787 dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1788
1789 dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1790 dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1791 dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1792
1793 dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1794 dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1795 dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1796
1797 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1798 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
1799 dev_info(smu->adev->dev, " .Enabled = %d\n",
1800 pptable->I2cControllers[i].Enabled);
1801 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
1802 pptable->I2cControllers[i].SlaveAddress);
1803 dev_info(smu->adev->dev, " .ControllerPort = %d\n",
1804 pptable->I2cControllers[i].ControllerPort);
1805 dev_info(smu->adev->dev, " .ControllerName = %d\n",
1806 pptable->I2cControllers[i].ControllerName);
1807 dev_info(smu->adev->dev, " .ThermalThrottler = %d\n",
1808 pptable->I2cControllers[i].ThermalThrotter);
1809 dev_info(smu->adev->dev, " .I2cProtocol = %d\n",
1810 pptable->I2cControllers[i].I2cProtocol);
1811 dev_info(smu->adev->dev, " .Speed = %d\n",
1812 pptable->I2cControllers[i].Speed);
1813 }
1814
1815 dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1816 dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth);
1817
1818 dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower);
1819
1820 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
1821 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1822 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1823 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
1824 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1825 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1826 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
1827 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1828 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1829 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
1830 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1831 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1832
1833 }
1834
arcturus_is_dpm_running(struct smu_context * smu)1835 static bool arcturus_is_dpm_running(struct smu_context *smu)
1836 {
1837 int ret = 0;
1838 uint32_t feature_mask[2];
1839 uint64_t feature_enabled;
1840
1841 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1842 if (ret)
1843 return false;
1844
1845 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1846
1847 return !!(feature_enabled & SMC_DPM_FEATURE);
1848 }
1849
arcturus_dpm_set_vcn_enable(struct smu_context * smu,bool enable)1850 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1851 {
1852 int ret = 0;
1853
1854 if (enable) {
1855 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1856 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1857 if (ret) {
1858 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
1859 return ret;
1860 }
1861 }
1862 } else {
1863 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1864 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1865 if (ret) {
1866 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
1867 return ret;
1868 }
1869 }
1870 }
1871
1872 return ret;
1873 }
1874
arcturus_fill_i2c_req(SwI2cRequest_t * req,bool write,uint8_t address,uint32_t numbytes,uint8_t * data)1875 static void arcturus_fill_i2c_req(SwI2cRequest_t *req, bool write,
1876 uint8_t address, uint32_t numbytes,
1877 uint8_t *data)
1878 {
1879 int i;
1880
1881 req->I2CcontrollerPort = 0;
1882 req->I2CSpeed = 2;
1883 req->SlaveAddress = address;
1884 req->NumCmds = numbytes;
1885
1886 for (i = 0; i < numbytes; i++) {
1887 SwI2cCmd_t *cmd = &req->SwI2cCmds[i];
1888
1889 /* First 2 bytes are always write for lower 2b EEPROM address */
1890 if (i < 2)
1891 cmd->Cmd = 1;
1892 else
1893 cmd->Cmd = write;
1894
1895
1896 /* Add RESTART for read after address filled */
1897 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
1898
1899 /* Add STOP in the end */
1900 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
1901
1902 /* Fill with data regardless if read or write to simplify code */
1903 cmd->RegisterAddr = data[i];
1904 }
1905 }
1906
arcturus_i2c_read_data(struct i2c_adapter * control,uint8_t address,uint8_t * data,uint32_t numbytes)1907 static int arcturus_i2c_read_data(struct i2c_adapter *control,
1908 uint8_t address,
1909 uint8_t *data,
1910 uint32_t numbytes)
1911 {
1912 uint32_t i, ret = 0;
1913 SwI2cRequest_t req;
1914 struct amdgpu_device *adev = to_amdgpu_device(control);
1915 struct smu_table_context *smu_table = &adev->smu.smu_table;
1916 struct smu_table *table = &smu_table->driver_table;
1917
1918 if (numbytes > MAX_SW_I2C_COMMANDS) {
1919 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1920 numbytes, MAX_SW_I2C_COMMANDS);
1921 return -EINVAL;
1922 }
1923
1924 memset(&req, 0, sizeof(req));
1925 arcturus_fill_i2c_req(&req, false, address, numbytes, data);
1926
1927 mutex_lock(&adev->smu.mutex);
1928 /* Now read data starting with that address */
1929 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
1930 true);
1931 mutex_unlock(&adev->smu.mutex);
1932
1933 if (!ret) {
1934 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
1935
1936 /* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */
1937 for (i = 0; i < numbytes; i++)
1938 data[i] = res->SwI2cCmds[i].Data;
1939
1940 dev_dbg(adev->dev, "arcturus_i2c_read_data, address = %x, bytes = %d, data :",
1941 (uint16_t)address, numbytes);
1942
1943 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1944 8, 1, data, numbytes, false);
1945 } else
1946 dev_err(adev->dev, "arcturus_i2c_read_data - error occurred :%x", ret);
1947
1948 return ret;
1949 }
1950
arcturus_i2c_write_data(struct i2c_adapter * control,uint8_t address,uint8_t * data,uint32_t numbytes)1951 static int arcturus_i2c_write_data(struct i2c_adapter *control,
1952 uint8_t address,
1953 uint8_t *data,
1954 uint32_t numbytes)
1955 {
1956 uint32_t ret;
1957 SwI2cRequest_t req;
1958 struct amdgpu_device *adev = to_amdgpu_device(control);
1959
1960 if (numbytes > MAX_SW_I2C_COMMANDS) {
1961 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1962 numbytes, MAX_SW_I2C_COMMANDS);
1963 return -EINVAL;
1964 }
1965
1966 memset(&req, 0, sizeof(req));
1967 arcturus_fill_i2c_req(&req, true, address, numbytes, data);
1968
1969 mutex_lock(&adev->smu.mutex);
1970 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
1971 mutex_unlock(&adev->smu.mutex);
1972
1973 if (!ret) {
1974 dev_dbg(adev->dev, "arcturus_i2c_write(), address = %x, bytes = %d , data: ",
1975 (uint16_t)address, numbytes);
1976
1977 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1978 8, 1, data, numbytes, false);
1979 /*
1980 * According to EEPROM spec there is a MAX of 10 ms required for
1981 * EEPROM to flush internal RX buffer after STOP was issued at the
1982 * end of write transaction. During this time the EEPROM will not be
1983 * responsive to any more commands - so wait a bit more.
1984 */
1985 msleep(10);
1986
1987 } else
1988 dev_err(adev->dev, "arcturus_i2c_write- error occurred :%x", ret);
1989
1990 return ret;
1991 }
1992
arcturus_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msgs,int num)1993 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
1994 struct i2c_msg *msgs, int num)
1995 {
1996 uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
1997 uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
1998
1999 for (i = 0; i < num; i++) {
2000 /*
2001 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2002 * once and hence the data needs to be spliced into chunks and sent each
2003 * chunk separately
2004 */
2005 data_size = msgs[i].len - 2;
2006 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2007 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2008 data_ptr = msgs[i].buf + 2;
2009
2010 for (j = 0; j < data_size / data_chunk_size; j++) {
2011 /* Insert the EEPROM dest addess, bits 0-15 */
2012 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2013 data_chunk[1] = (next_eeprom_addr & 0xff);
2014
2015 if (msgs[i].flags & I2C_M_RD) {
2016 ret = arcturus_i2c_read_data(i2c_adap,
2017 (uint8_t)msgs[i].addr,
2018 data_chunk, MAX_SW_I2C_COMMANDS);
2019
2020 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2021 } else {
2022
2023 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2024
2025 ret = arcturus_i2c_write_data(i2c_adap,
2026 (uint8_t)msgs[i].addr,
2027 data_chunk, MAX_SW_I2C_COMMANDS);
2028 }
2029
2030 if (ret) {
2031 num = -EIO;
2032 goto fail;
2033 }
2034
2035 next_eeprom_addr += data_chunk_size;
2036 data_ptr += data_chunk_size;
2037 }
2038
2039 if (data_size % data_chunk_size) {
2040 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2041 data_chunk[1] = (next_eeprom_addr & 0xff);
2042
2043 if (msgs[i].flags & I2C_M_RD) {
2044 ret = arcturus_i2c_read_data(i2c_adap,
2045 (uint8_t)msgs[i].addr,
2046 data_chunk, (data_size % data_chunk_size) + 2);
2047
2048 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2049 } else {
2050 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2051
2052 ret = arcturus_i2c_write_data(i2c_adap,
2053 (uint8_t)msgs[i].addr,
2054 data_chunk, (data_size % data_chunk_size) + 2);
2055 }
2056
2057 if (ret) {
2058 num = -EIO;
2059 goto fail;
2060 }
2061 }
2062 }
2063
2064 fail:
2065 return num;
2066 }
2067
arcturus_i2c_func(struct i2c_adapter * adap)2068 static u32 arcturus_i2c_func(struct i2c_adapter *adap)
2069 {
2070 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2071 }
2072
2073
2074 static const struct i2c_algorithm arcturus_i2c_algo = {
2075 .master_xfer = arcturus_i2c_xfer,
2076 .functionality = arcturus_i2c_func,
2077 };
2078
arcturus_i2c_control_init(struct smu_context * smu,struct i2c_adapter * control)2079 static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2080 {
2081 struct amdgpu_device *adev = to_amdgpu_device(control);
2082 int res;
2083
2084 control->owner = THIS_MODULE;
2085 control->class = I2C_CLASS_SPD;
2086 control->dev.parent = &adev->pdev->dev;
2087 control->algo = &arcturus_i2c_algo;
2088 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2089
2090 res = i2c_add_adapter(control);
2091 if (res)
2092 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2093
2094 return res;
2095 }
2096
arcturus_i2c_control_fini(struct smu_context * smu,struct i2c_adapter * control)2097 static void arcturus_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2098 {
2099 i2c_del_adapter(control);
2100 }
2101
arcturus_get_unique_id(struct smu_context * smu)2102 static void arcturus_get_unique_id(struct smu_context *smu)
2103 {
2104 struct amdgpu_device *adev = smu->adev;
2105 uint32_t top32 = 0, bottom32 = 0, smu_version;
2106 uint64_t id;
2107
2108 if (smu_cmn_get_smc_version(smu, NULL, &smu_version)) {
2109 dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n");
2110 return;
2111 }
2112
2113 /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2114 if (smu_version < 0x361700) {
2115 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
2116 return;
2117 }
2118
2119 /* Get the SN to turn into a Unique ID */
2120 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2121 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2122
2123 id = ((uint64_t)bottom32 << 32) | top32;
2124 adev->unique_id = id;
2125 /* For Arcturus-and-later, unique_id == serial_number, so convert it to a
2126 * 16-digit HEX string for convenience and backwards-compatibility
2127 */
2128 sprintf(adev->serial, "%llx", id);
2129 }
2130
arcturus_is_baco_supported(struct smu_context * smu)2131 static bool arcturus_is_baco_supported(struct smu_context *smu)
2132 {
2133 struct amdgpu_device *adev = smu->adev;
2134 uint32_t val;
2135
2136 if (!smu_v11_0_baco_is_support(smu) || amdgpu_sriov_vf(adev))
2137 return false;
2138
2139 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
2140 return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
2141 }
2142
arcturus_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)2143 static int arcturus_set_df_cstate(struct smu_context *smu,
2144 enum pp_df_cstate state)
2145 {
2146 uint32_t smu_version;
2147 int ret;
2148
2149 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2150 if (ret) {
2151 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2152 return ret;
2153 }
2154
2155 /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2156 if (smu_version < 0x360F00) {
2157 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2158 return -EINVAL;
2159 }
2160
2161 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2162 }
2163
arcturus_allow_xgmi_power_down(struct smu_context * smu,bool en)2164 static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
2165 {
2166 uint32_t smu_version;
2167 int ret;
2168
2169 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2170 if (ret) {
2171 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2172 return ret;
2173 }
2174
2175 /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2176 if (smu_version < 0x00361700) {
2177 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
2178 return -EINVAL;
2179 }
2180
2181 if (en)
2182 return smu_cmn_send_smc_msg_with_param(smu,
2183 SMU_MSG_GmiPwrDnControl,
2184 1,
2185 NULL);
2186
2187 return smu_cmn_send_smc_msg_with_param(smu,
2188 SMU_MSG_GmiPwrDnControl,
2189 0,
2190 NULL);
2191 }
2192
2193 static const struct throttling_logging_label {
2194 uint32_t feature_mask;
2195 const char *label;
2196 } logging_label[] = {
2197 {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
2198 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
2199 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
2200 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
2201 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
2202 {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
2203 {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
2204 };
arcturus_log_thermal_throttling_event(struct smu_context * smu)2205 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2206 {
2207 int ret;
2208 int throttler_idx, throtting_events = 0, buf_idx = 0;
2209 struct amdgpu_device *adev = smu->adev;
2210 uint32_t throttler_status;
2211 char log_buf[256];
2212
2213 ret = arcturus_get_smu_metrics_data(smu,
2214 METRICS_THROTTLER_STATUS,
2215 &throttler_status);
2216 if (ret)
2217 return;
2218
2219 memset(log_buf, 0, sizeof(log_buf));
2220 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
2221 throttler_idx++) {
2222 if (throttler_status & logging_label[throttler_idx].feature_mask) {
2223 throtting_events++;
2224 buf_idx += snprintf(log_buf + buf_idx,
2225 sizeof(log_buf) - buf_idx,
2226 "%s%s",
2227 throtting_events > 1 ? " and " : "",
2228 logging_label[throttler_idx].label);
2229 if (buf_idx >= sizeof(log_buf)) {
2230 dev_err(adev->dev, "buffer overflow!\n");
2231 log_buf[sizeof(log_buf) - 1] = '\0';
2232 break;
2233 }
2234 }
2235 }
2236
2237 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
2238 log_buf);
2239 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, throttler_status);
2240 }
2241
arcturus_get_current_pcie_link_speed(struct smu_context * smu)2242 static int arcturus_get_current_pcie_link_speed(struct smu_context *smu)
2243 {
2244 struct amdgpu_device *adev = smu->adev;
2245 uint32_t esm_ctrl;
2246
2247 /* TODO: confirm this on real target */
2248 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2249 if ((esm_ctrl >> 15) & 0x1FFFF)
2250 return (((esm_ctrl >> 8) & 0x3F) + 128);
2251
2252 return smu_v11_0_get_current_pcie_link_speed(smu);
2253 }
2254
arcturus_get_gpu_metrics(struct smu_context * smu,void ** table)2255 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
2256 void **table)
2257 {
2258 struct smu_table_context *smu_table = &smu->smu_table;
2259 struct gpu_metrics_v1_0 *gpu_metrics =
2260 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2261 SmuMetrics_t metrics;
2262 int ret = 0;
2263
2264 ret = smu_cmn_get_metrics_table(smu,
2265 &metrics,
2266 true);
2267 if (ret)
2268 return ret;
2269
2270 smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
2271
2272 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2273 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2274 gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2275 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2276 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2277 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2278
2279 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2280 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2281 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2282
2283 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2284 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2285
2286 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2287 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2288 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2289 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2290 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2291
2292 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2293 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2294 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2295 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2296 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2297
2298 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2299
2300 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2301
2302 gpu_metrics->pcie_link_width =
2303 smu_v11_0_get_current_pcie_link_width(smu);
2304 gpu_metrics->pcie_link_speed =
2305 arcturus_get_current_pcie_link_speed(smu);
2306
2307 *table = (void *)gpu_metrics;
2308
2309 return sizeof(struct gpu_metrics_v1_0);
2310 }
2311
2312 static const struct pptable_funcs arcturus_ppt_funcs = {
2313 /* init dpm */
2314 .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2315 /* btc */
2316 .run_btc = arcturus_run_btc,
2317 /* dpm/clk tables */
2318 .set_default_dpm_table = arcturus_set_default_dpm_table,
2319 .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2320 .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2321 .print_clk_levels = arcturus_print_clk_levels,
2322 .force_clk_levels = arcturus_force_clk_levels,
2323 .read_sensor = arcturus_read_sensor,
2324 .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2325 .get_power_profile_mode = arcturus_get_power_profile_mode,
2326 .set_power_profile_mode = arcturus_set_power_profile_mode,
2327 .set_performance_level = arcturus_set_performance_level,
2328 /* debug (internal used) */
2329 .dump_pptable = arcturus_dump_pptable,
2330 .get_power_limit = arcturus_get_power_limit,
2331 .is_dpm_running = arcturus_is_dpm_running,
2332 .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
2333 .i2c_init = arcturus_i2c_control_init,
2334 .i2c_fini = arcturus_i2c_control_fini,
2335 .get_unique_id = arcturus_get_unique_id,
2336 .init_microcode = smu_v11_0_init_microcode,
2337 .load_microcode = smu_v11_0_load_microcode,
2338 .fini_microcode = smu_v11_0_fini_microcode,
2339 .init_smc_tables = arcturus_init_smc_tables,
2340 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2341 .init_power = smu_v11_0_init_power,
2342 .fini_power = smu_v11_0_fini_power,
2343 .check_fw_status = smu_v11_0_check_fw_status,
2344 /* pptable related */
2345 .setup_pptable = arcturus_setup_pptable,
2346 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2347 .check_fw_version = smu_v11_0_check_fw_version,
2348 .write_pptable = smu_cmn_write_pptable,
2349 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2350 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2351 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2352 .system_features_control = smu_v11_0_system_features_control,
2353 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2354 .send_smc_msg = smu_cmn_send_smc_msg,
2355 .init_display_count = NULL,
2356 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2357 .get_enabled_mask = smu_cmn_get_enabled_mask,
2358 .feature_is_enabled = smu_cmn_feature_is_enabled,
2359 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2360 .notify_display_change = NULL,
2361 .set_power_limit = smu_v11_0_set_power_limit,
2362 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2363 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2364 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2365 .set_min_dcef_deep_sleep = NULL,
2366 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2367 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2368 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2369 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2370 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2371 .gfx_off_control = smu_v11_0_gfx_off_control,
2372 .register_irq_handler = smu_v11_0_register_irq_handler,
2373 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2374 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2375 .baco_is_support= arcturus_is_baco_supported,
2376 .baco_get_state = smu_v11_0_baco_get_state,
2377 .baco_set_state = smu_v11_0_baco_set_state,
2378 .baco_enter = smu_v11_0_baco_enter,
2379 .baco_exit = smu_v11_0_baco_exit,
2380 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2381 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2382 .set_df_cstate = arcturus_set_df_cstate,
2383 .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
2384 .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2385 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2386 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2387 .get_gpu_metrics = arcturus_get_gpu_metrics,
2388 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2389 .deep_sleep_control = smu_v11_0_deep_sleep_control,
2390 .get_fan_parameters = arcturus_get_fan_parameters,
2391 .interrupt_work = smu_v11_0_interrupt_work,
2392 };
2393
arcturus_set_ppt_funcs(struct smu_context * smu)2394 void arcturus_set_ppt_funcs(struct smu_context *smu)
2395 {
2396 smu->ppt_funcs = &arcturus_ppt_funcs;
2397 smu->message_map = arcturus_message_map;
2398 smu->clock_map = arcturus_clk_map;
2399 smu->feature_map = arcturus_feature_mask_map;
2400 smu->table_map = arcturus_table_map;
2401 smu->pwr_src_map = arcturus_pwr_src_map;
2402 smu->workload_map = arcturus_workload_map;
2403 }
2404