1 /*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef ARM_CPU_H
21 #define ARM_CPU_H
22
23 #include "kvm-consts.h"
24 #include "qemu/cpu-float.h"
25 #include "hw/registerfields.h"
26 #include "cpu-qom.h"
27 #include "exec/cpu-common.h"
28 #include "exec/cpu-defs.h"
29 #include "exec/cpu-interrupt.h"
30 #include "exec/gdbstub.h"
31 #include "exec/page-protection.h"
32 #include "qapi/qapi-types-common.h"
33 #include "target/arm/multiprocessing.h"
34 #include "target/arm/gtimer.h"
35 #include "target/arm/cpu-sysregs.h"
36
37 #define EXCP_UDEF 1 /* undefined instruction */
38 #define EXCP_SWI 2 /* software interrupt */
39 #define EXCP_PREFETCH_ABORT 3
40 #define EXCP_DATA_ABORT 4
41 #define EXCP_IRQ 5
42 #define EXCP_FIQ 6
43 #define EXCP_BKPT 7
44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
46 #define EXCP_HVC 11 /* HyperVisor Call */
47 #define EXCP_HYP_TRAP 12
48 #define EXCP_SMC 13 /* Secure Monitor Call */
49 #define EXCP_VIRQ 14
50 #define EXCP_VFIQ 15
51 #define EXCP_SEMIHOST 16 /* semihosting call */
52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */
53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */
55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */
56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */
57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */
58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */
59 #define EXCP_VSERR 24
60 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */
61 #define EXCP_NMI 26
62 #define EXCP_VINMI 27
63 #define EXCP_VFNMI 28
64 #define EXCP_MON_TRAP 29 /* AArch32 trap to Monitor mode */
65 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
66
67 #define ARMV7M_EXCP_RESET 1
68 #define ARMV7M_EXCP_NMI 2
69 #define ARMV7M_EXCP_HARD 3
70 #define ARMV7M_EXCP_MEM 4
71 #define ARMV7M_EXCP_BUS 5
72 #define ARMV7M_EXCP_USAGE 6
73 #define ARMV7M_EXCP_SECURE 7
74 #define ARMV7M_EXCP_SVC 11
75 #define ARMV7M_EXCP_DEBUG 12
76 #define ARMV7M_EXCP_PENDSV 14
77 #define ARMV7M_EXCP_SYSTICK 15
78
79 /* ARM-specific interrupt pending bits. */
80 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
81 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
82 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
83 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
84 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4
85 #define CPU_INTERRUPT_VINMI CPU_INTERRUPT_TGT_EXT_0
86 #define CPU_INTERRUPT_VFNMI CPU_INTERRUPT_TGT_INT_1
87
88 /* The usual mapping for an AArch64 system register to its AArch32
89 * counterpart is for the 32 bit world to have access to the lower
90 * half only (with writes leaving the upper half untouched). It's
91 * therefore useful to be able to pass TCG the offset of the least
92 * significant half of a uint64_t struct member.
93 */
94 #if HOST_BIG_ENDIAN
95 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
96 #define offsetofhigh32(S, M) offsetof(S, M)
97 #else
98 #define offsetoflow32(S, M) offsetof(S, M)
99 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
100 #endif
101
102 /* The 2nd extra word holding syndrome info for data aborts does not use
103 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to
104 * help the sleb128 encoder do a better job.
105 * When restoring the CPU state, we shift it back up.
106 */
107 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
108 #define ARM_INSN_START_WORD2_SHIFT 13
109
110 /* We currently assume float and double are IEEE single and double
111 precision respectively.
112 Doing runtime conversions is tricky because VFP registers may contain
113 integer values (eg. as the result of a FTOSI instruction).
114 s<2n> maps to the least significant half of d<n>
115 s<2n+1> maps to the most significant half of d<n>
116 */
117
118 /**
119 * DynamicGDBFeatureInfo:
120 * @desc: Contains the feature descriptions.
121 * @data: A union with data specific to the set of registers
122 * @cpregs_keys: Array that contains the corresponding Key of
123 * a given cpreg with the same order of the cpreg
124 * in the XML description.
125 */
126 typedef struct DynamicGDBFeatureInfo {
127 GDBFeature desc;
128 union {
129 struct {
130 uint32_t *keys;
131 } cpregs;
132 } data;
133 } DynamicGDBFeatureInfo;
134
135 /* CPU state for each instance of a generic timer (in cp15 c14) */
136 typedef struct ARMGenericTimer {
137 uint64_t cval; /* Timer CompareValue register */
138 uint64_t ctl; /* Timer Control register */
139 } ARMGenericTimer;
140
141 /* Define a maximum sized vector register.
142 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
143 * For 64-bit, this is a 2048-bit SVE register.
144 *
145 * Note that the mapping between S, D, and Q views of the register bank
146 * differs between AArch64 and AArch32.
147 * In AArch32:
148 * Qn = regs[n].d[1]:regs[n].d[0]
149 * Dn = regs[n / 2].d[n & 1]
150 * Sn = regs[n / 4].d[n % 4 / 2],
151 * bits 31..0 for even n, and bits 63..32 for odd n
152 * (and regs[16] to regs[31] are inaccessible)
153 * In AArch64:
154 * Zn = regs[n].d[*]
155 * Qn = regs[n].d[1]:regs[n].d[0]
156 * Dn = regs[n].d[0]
157 * Sn = regs[n].d[0] bits 31..0
158 * Hn = regs[n].d[0] bits 15..0
159 *
160 * This corresponds to the architecturally defined mapping between
161 * the two execution states, and means we do not need to explicitly
162 * map these registers when changing states.
163 *
164 * Align the data for use with TCG host vector operations.
165 */
166
167 #define ARM_MAX_VQ 16
168
169 typedef struct ARMVectorReg {
170 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
171 } ARMVectorReg;
172
173 /* In AArch32 mode, predicate registers do not exist at all. */
174 typedef struct ARMPredicateReg {
175 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
176 } ARMPredicateReg;
177
178 /* In AArch32 mode, PAC keys do not exist at all. */
179 typedef struct ARMPACKey {
180 uint64_t lo, hi;
181 } ARMPACKey;
182
183 /* See the commentary above the TBFLAG field definitions. */
184 typedef struct CPUARMTBFlags {
185 uint32_t flags;
186 uint64_t flags2;
187 } CPUARMTBFlags;
188
189 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
190
191 typedef struct NVICState NVICState;
192
193 /*
194 * Enum for indexing vfp.fp_status[].
195 *
196 * FPST_A32: is the "normal" fp status for AArch32 insns
197 * FPST_A64: is the "normal" fp status for AArch64 insns
198 * FPST_A32_F16: used for AArch32 half-precision calculations
199 * FPST_A64_F16: used for AArch64 half-precision calculations
200 * FPST_STD: the ARM "Standard FPSCR Value"
201 * FPST_STD_F16: used for half-precision
202 * calculations with the ARM "Standard FPSCR Value"
203 * FPST_AH: used for the A64 insns which change behaviour
204 * when FPCR.AH == 1 (bfloat16 conversions and multiplies,
205 * and the reciprocal and square root estimate/step insns)
206 * FPST_AH_F16: used for the A64 insns which change behaviour
207 * when FPCR.AH == 1 (bfloat16 conversions and multiplies,
208 * and the reciprocal and square root estimate/step insns);
209 * for half-precision
210 *
211 * Half-precision operations are governed by a separate
212 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
213 * status structure to control this.
214 *
215 * The "Standard FPSCR", ie default-NaN, flush-to-zero,
216 * round-to-nearest and is used by any operations (generally
217 * Neon) which the architecture defines as controlled by the
218 * standard FPSCR value rather than the FPSCR.
219 *
220 * The "standard FPSCR but for fp16 ops" is needed because
221 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than
222 * using a fixed value for it.
223 *
224 * FPST_AH is needed because some insns have different
225 * behaviour when FPCR.AH == 1: they don't update cumulative
226 * exception flags, they act like FPCR.{FZ,FIZ} = {1,1} and
227 * they ignore FPCR.RMode. But they don't ignore FPCR.FZ16,
228 * which means we need an FPST_AH_F16 as well.
229 *
230 * To avoid having to transfer exception bits around, we simply
231 * say that the FPSCR cumulative exception flags are the logical
232 * OR of the flags in the four fp statuses. This relies on the
233 * only thing which needs to read the exception flags being
234 * an explicit FPSCR read.
235 */
236 typedef enum ARMFPStatusFlavour {
237 FPST_A32,
238 FPST_A64,
239 FPST_A32_F16,
240 FPST_A64_F16,
241 FPST_AH,
242 FPST_AH_F16,
243 FPST_STD,
244 FPST_STD_F16,
245 } ARMFPStatusFlavour;
246 #define FPST_COUNT 8
247
248 typedef struct CPUArchState {
249 /* Regs for current mode. */
250 uint32_t regs[16];
251
252 /* 32/64 switch only happens when taking and returning from
253 * exceptions so the overlap semantics are taken care of then
254 * instead of having a complicated union.
255 */
256 /* Regs for A64 mode. */
257 uint64_t xregs[32];
258 uint64_t pc;
259 /* PSTATE isn't an architectural register for ARMv8. However, it is
260 * convenient for us to assemble the underlying state into a 32 bit format
261 * identical to the architectural format used for the SPSR. (This is also
262 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
263 * 'pstate' register are.) Of the PSTATE bits:
264 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
265 * semantics as for AArch32, as described in the comments on each field)
266 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
267 * DAIF (exception masks) are kept in env->daif
268 * BTYPE is kept in env->btype
269 * SM and ZA are kept in env->svcr
270 * all other bits are stored in their correct places in env->pstate
271 */
272 uint32_t pstate;
273 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */
274 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */
275
276 /* Cached TBFLAGS state. See below for which bits are included. */
277 CPUARMTBFlags hflags;
278
279 /* Frequently accessed CPSR bits are stored separately for efficiency.
280 This contains all the other bits. Use cpsr_{read,write} to access
281 the whole CPSR. */
282 uint32_t uncached_cpsr;
283 uint32_t spsr;
284
285 /* Banked registers. */
286 uint64_t banked_spsr[8];
287 uint32_t banked_r13[8];
288 uint32_t banked_r14[8];
289
290 /* These hold r8-r12. */
291 uint32_t usr_regs[5];
292 uint32_t fiq_regs[5];
293
294 /* cpsr flag cache for faster execution */
295 uint32_t CF; /* 0 or 1 */
296 uint32_t VF; /* V is the bit 31. All other bits are undefined */
297 uint32_t NF; /* N is bit 31. All other bits are undefined. */
298 uint32_t ZF; /* Z set if zero. */
299 uint32_t QF; /* 0 or 1 */
300 uint32_t GE; /* cpsr[19:16] */
301 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
302 uint32_t btype; /* BTI branch type. spsr[11:10]. */
303 uint64_t daif; /* exception masks, in the bits they are in PSTATE */
304 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */
305
306 uint64_t elr_el[4]; /* AArch64 exception link regs */
307 uint64_t sp_el[4]; /* AArch64 banked stack pointers */
308
309 /* System control coprocessor (cp15) */
310 struct {
311 uint32_t c0_cpuid;
312 union { /* Cache size selection */
313 struct {
314 uint64_t _unused_csselr0;
315 uint64_t csselr_ns;
316 uint64_t _unused_csselr1;
317 uint64_t csselr_s;
318 };
319 uint64_t csselr_el[4];
320 };
321 union { /* System control register. */
322 struct {
323 uint64_t _unused_sctlr;
324 uint64_t sctlr_ns;
325 uint64_t hsctlr;
326 uint64_t sctlr_s;
327 };
328 uint64_t sctlr_el[4];
329 };
330 uint64_t vsctlr; /* Virtualization System control register. */
331 uint64_t cpacr_el1; /* Architectural feature access control register */
332 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
333 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
334 uint64_t sder; /* Secure debug enable register. */
335 uint32_t nsacr; /* Non-secure access control register. */
336 union { /* MMU translation table base 0. */
337 struct {
338 uint64_t _unused_ttbr0_0;
339 uint64_t ttbr0_ns;
340 uint64_t _unused_ttbr0_1;
341 uint64_t ttbr0_s;
342 };
343 uint64_t ttbr0_el[4];
344 };
345 union { /* MMU translation table base 1. */
346 struct {
347 uint64_t _unused_ttbr1_0;
348 uint64_t ttbr1_ns;
349 uint64_t _unused_ttbr1_1;
350 uint64_t ttbr1_s;
351 };
352 uint64_t ttbr1_el[4];
353 };
354 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */
355 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */
356 /* MMU translation table base control. */
357 uint64_t tcr_el[4];
358 uint64_t vtcr_el2; /* Virtualization Translation Control. */
359 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */
360 uint32_t c2_data; /* MPU data cacheable bits. */
361 uint32_t c2_insn; /* MPU instruction cacheable bits. */
362 union { /* MMU domain access control register
363 * MPU write buffer control.
364 */
365 struct {
366 uint64_t dacr_ns;
367 uint64_t dacr_s;
368 };
369 struct {
370 uint64_t dacr32_el2;
371 };
372 };
373 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
374 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
375 uint64_t hcr_el2; /* Hypervisor configuration register */
376 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */
377 uint64_t scr_el3; /* Secure configuration register. */
378 union { /* Fault status registers. */
379 struct {
380 uint64_t ifsr_ns;
381 uint64_t ifsr_s;
382 };
383 struct {
384 uint64_t ifsr32_el2;
385 };
386 };
387 union {
388 struct {
389 uint64_t _unused_dfsr;
390 uint64_t dfsr_ns;
391 uint64_t hsr;
392 uint64_t dfsr_s;
393 };
394 uint64_t esr_el[4];
395 };
396 uint32_t c6_region[8]; /* MPU base/size registers. */
397 union { /* Fault address registers. */
398 struct {
399 uint64_t _unused_far0;
400 #if HOST_BIG_ENDIAN
401 uint32_t ifar_ns;
402 uint32_t dfar_ns;
403 uint32_t ifar_s;
404 uint32_t dfar_s;
405 #else
406 uint32_t dfar_ns;
407 uint32_t ifar_ns;
408 uint32_t dfar_s;
409 uint32_t ifar_s;
410 #endif
411 uint64_t _unused_far3;
412 };
413 uint64_t far_el[4];
414 };
415 uint64_t hpfar_el2;
416 uint64_t hstr_el2;
417 union { /* Translation result. */
418 struct {
419 uint64_t _unused_par_0;
420 uint64_t par_ns;
421 uint64_t _unused_par_1;
422 uint64_t par_s;
423 };
424 uint64_t par_el[4];
425 };
426
427 uint32_t c9_insn; /* Cache lockdown registers. */
428 uint32_t c9_data;
429 uint64_t c9_pmcr; /* performance monitor control register */
430 uint64_t c9_pmcnten; /* perf monitor counter enables */
431 uint64_t c9_pmovsr; /* perf monitor overflow status */
432 uint64_t c9_pmuserenr; /* perf monitor user enable */
433 uint64_t c9_pmselr; /* perf monitor counter selection register */
434 uint64_t c9_pminten; /* perf monitor interrupt enables */
435 union { /* Memory attribute redirection */
436 struct {
437 #if HOST_BIG_ENDIAN
438 uint64_t _unused_mair_0;
439 uint32_t mair1_ns;
440 uint32_t mair0_ns;
441 uint64_t _unused_mair_1;
442 uint32_t mair1_s;
443 uint32_t mair0_s;
444 #else
445 uint64_t _unused_mair_0;
446 uint32_t mair0_ns;
447 uint32_t mair1_ns;
448 uint64_t _unused_mair_1;
449 uint32_t mair0_s;
450 uint32_t mair1_s;
451 #endif
452 };
453 uint64_t mair_el[4];
454 };
455 union { /* vector base address register */
456 struct {
457 uint64_t _unused_vbar;
458 uint64_t vbar_ns;
459 uint64_t hvbar;
460 uint64_t vbar_s;
461 };
462 uint64_t vbar_el[4];
463 };
464 uint32_t mvbar; /* (monitor) vector base address register */
465 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */
466 struct { /* FCSE PID. */
467 uint32_t fcseidr_ns;
468 uint32_t fcseidr_s;
469 };
470 union { /* Context ID. */
471 struct {
472 uint64_t _unused_contextidr_0;
473 uint64_t contextidr_ns;
474 uint64_t _unused_contextidr_1;
475 uint64_t contextidr_s;
476 };
477 uint64_t contextidr_el[4];
478 };
479 union { /* User RW Thread register. */
480 struct {
481 uint64_t tpidrurw_ns;
482 uint64_t tpidrprw_ns;
483 uint64_t htpidr;
484 uint64_t _tpidr_el3;
485 };
486 uint64_t tpidr_el[4];
487 };
488 uint64_t tpidr2_el0;
489 /* The secure banks of these registers don't map anywhere */
490 uint64_t tpidrurw_s;
491 uint64_t tpidrprw_s;
492 uint64_t tpidruro_s;
493
494 union { /* User RO Thread register. */
495 uint64_t tpidruro_ns;
496 uint64_t tpidrro_el[1];
497 };
498 uint64_t c14_cntfrq; /* Counter Frequency register */
499 uint64_t c14_cntkctl; /* Timer Control register */
500 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */
501 uint64_t cntvoff_el2; /* Counter Virtual Offset register */
502 uint64_t cntpoff_el2; /* Counter Physical Offset register */
503 ARMGenericTimer c14_timer[NUM_GTIMERS];
504 uint32_t c15_cpar; /* XScale Coprocessor Access Register */
505 uint32_t c15_ticonfig; /* TI925T configuration byte. */
506 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
507 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
508 uint32_t c15_threadid; /* TI debugger thread-ID. */
509 uint32_t c15_config_base_address; /* SCU base address. */
510 uint32_t c15_diagnostic; /* diagnostic register */
511 uint32_t c15_power_diagnostic;
512 uint32_t c15_power_control; /* power control */
513 uint64_t dbgbvr[16]; /* breakpoint value registers */
514 uint64_t dbgbcr[16]; /* breakpoint control registers */
515 uint64_t dbgwvr[16]; /* watchpoint value registers */
516 uint64_t dbgwcr[16]; /* watchpoint control registers */
517 uint64_t dbgclaim; /* DBGCLAIM bits */
518 uint64_t mdscr_el1;
519 uint64_t oslsr_el1; /* OS Lock Status */
520 uint64_t osdlr_el1; /* OS DoubleLock status */
521 uint64_t mdcr_el2;
522 uint64_t mdcr_el3;
523 /* Stores the architectural value of the counter *the last time it was
524 * updated* by pmccntr_op_start. Accesses should always be surrounded
525 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest
526 * architecturally-correct value is being read/set.
527 */
528 uint64_t c15_ccnt;
529 /* Stores the delta between the architectural value and the underlying
530 * cycle count during normal operation. It is used to update c15_ccnt
531 * to be the correct architectural value before accesses. During
532 * accesses, c15_ccnt_delta contains the underlying count being used
533 * for the access, after which it reverts to the delta value in
534 * pmccntr_op_finish.
535 */
536 uint64_t c15_ccnt_delta;
537 uint64_t c14_pmevcntr[31];
538 uint64_t c14_pmevcntr_delta[31];
539 uint64_t c14_pmevtyper[31];
540 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
541 uint64_t vpidr_el2; /* Virtualization Processor ID Register */
542 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
543 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */
544 uint64_t gcr_el1;
545 uint64_t rgsr_el1;
546
547 /* Minimal RAS registers */
548 uint64_t disr_el1;
549 uint64_t vdisr_el2;
550 uint64_t vsesr_el2;
551
552 /*
553 * Fine-Grained Trap registers. We store these as arrays so the
554 * access checking code doesn't have to manually select
555 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test.
556 * FEAT_FGT2 will add more elements to these arrays.
557 */
558 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */
559 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */
560 uint64_t fgt_exec[1]; /* HFGITR */
561
562 /* RME registers */
563 uint64_t gpccr_el3;
564 uint64_t gptbr_el3;
565 uint64_t mfar_el3;
566
567 /* NV2 register */
568 uint64_t vncr_el2;
569 } cp15;
570
571 struct {
572 /* M profile has up to 4 stack pointers:
573 * a Main Stack Pointer and a Process Stack Pointer for each
574 * of the Secure and Non-Secure states. (If the CPU doesn't support
575 * the security extension then it has only two SPs.)
576 * In QEMU we always store the currently active SP in regs[13],
577 * and the non-active SP for the current security state in
578 * v7m.other_sp. The stack pointers for the inactive security state
579 * are stored in other_ss_msp and other_ss_psp.
580 * switch_v7m_security_state() is responsible for rearranging them
581 * when we change security state.
582 */
583 uint32_t other_sp;
584 uint32_t other_ss_msp;
585 uint32_t other_ss_psp;
586 uint32_t vecbase[M_REG_NUM_BANKS];
587 uint32_t basepri[M_REG_NUM_BANKS];
588 uint32_t control[M_REG_NUM_BANKS];
589 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
590 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
591 uint32_t hfsr; /* HardFault Status */
592 uint32_t dfsr; /* Debug Fault Status Register */
593 uint32_t sfsr; /* Secure Fault Status Register */
594 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
595 uint32_t bfar; /* BusFault Address */
596 uint32_t sfar; /* Secure Fault Address Register */
597 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
598 int exception;
599 uint32_t primask[M_REG_NUM_BANKS];
600 uint32_t faultmask[M_REG_NUM_BANKS];
601 uint32_t aircr; /* only holds r/w state if security extn implemented */
602 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
603 uint32_t csselr[M_REG_NUM_BANKS];
604 uint32_t scr[M_REG_NUM_BANKS];
605 uint32_t msplim[M_REG_NUM_BANKS];
606 uint32_t psplim[M_REG_NUM_BANKS];
607 uint32_t fpcar[M_REG_NUM_BANKS];
608 uint32_t fpccr[M_REG_NUM_BANKS];
609 uint32_t fpdscr[M_REG_NUM_BANKS];
610 uint32_t cpacr[M_REG_NUM_BANKS];
611 uint32_t nsacr;
612 uint32_t ltpsize;
613 uint32_t vpr;
614 } v7m;
615
616 /* Information associated with an exception about to be taken:
617 * code which raises an exception must set cs->exception_index and
618 * the relevant parts of this structure; the cpu_do_interrupt function
619 * will then set the guest-visible registers as part of the exception
620 * entry process.
621 */
622 struct {
623 uint32_t syndrome; /* AArch64 format syndrome register */
624 uint32_t fsr; /* AArch32 format fault status register info */
625 uint64_t vaddress; /* virtual addr associated with exception, if any */
626 uint32_t target_el; /* EL the exception should be targeted for */
627 /* If we implement EL2 we will also need to store information
628 * about the intermediate physical address for stage 2 faults.
629 */
630 } exception;
631
632 /* Information associated with an SError */
633 struct {
634 uint8_t pending;
635 uint8_t has_esr;
636 uint64_t esr;
637 } serror;
638
639 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
640
641 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
642 uint32_t irq_line_state;
643
644 /* Thumb-2 EE state. */
645 uint32_t teecr;
646 uint32_t teehbr;
647
648 /* VFP coprocessor state. */
649 struct {
650 ARMVectorReg zregs[32];
651
652 /* Store FFR as pregs[16] to make it easier to treat as any other. */
653 #define FFR_PRED_NUM 16
654 ARMPredicateReg pregs[17];
655 /* Scratch space for aa64 sve predicate temporary. */
656 ARMPredicateReg preg_tmp;
657
658 /* We store these fpcsr fields separately for convenience. */
659 uint32_t qc[4] QEMU_ALIGNED(16);
660 int vec_len;
661 int vec_stride;
662
663 /*
664 * Floating point status and control registers. Some bits are
665 * stored separately in other fields or in the float_status below.
666 */
667 uint64_t fpsr;
668 uint64_t fpcr;
669
670 uint32_t xregs[16];
671
672 /* Scratch space for aa32 neon expansion. */
673 uint32_t scratch[8];
674
675 /* There are a number of distinct float control structures. */
676 float_status fp_status[FPST_COUNT];
677
678 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */
679 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */
680 } vfp;
681
682 uint64_t exclusive_addr;
683 uint64_t exclusive_val;
684 /*
685 * Contains the 'val' for the second 64-bit register of LDXP, which comes
686 * from the higher address, not the high part of a complete 128-bit value.
687 * In some ways it might be more convenient to record the exclusive value
688 * as the low and high halves of a 128 bit data value, but the current
689 * semantics of these fields are baked into the migration format.
690 */
691 uint64_t exclusive_high;
692
693 /* iwMMXt coprocessor state. */
694 struct {
695 uint64_t regs[16];
696 uint64_t val;
697
698 uint32_t cregs[16];
699 } iwmmxt;
700
701 struct {
702 ARMPACKey apia;
703 ARMPACKey apib;
704 ARMPACKey apda;
705 ARMPACKey apdb;
706 ARMPACKey apga;
707 } keys;
708
709 uint64_t scxtnum_el[4];
710
711 /*
712 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order,
713 * as we do with vfp.zregs[]. This corresponds to the architectural ZA
714 * array, where ZA[N] is in the least-significant bytes of env->zarray[N].
715 * When SVL is less than the architectural maximum, the accessible
716 * storage is restricted, such that if the SVL is X bytes the guest can
717 * see only the bottom X elements of zarray[], and only the least
718 * significant X bytes of each element of the array. (In other words,
719 * the observable part is always square.)
720 *
721 * The ZA storage can also be considered as a set of square tiles of
722 * elements of different sizes. The mapping from tiles to the ZA array
723 * is architecturally defined, such that for tiles of elements of esz
724 * bytes, the Nth row (or "horizontal slice") of tile T is in
725 * ZA[T + N * esz]. Note that this means that each tile is not contiguous
726 * in the ZA storage, because its rows are striped through the ZA array.
727 *
728 * Because this is so large, keep this toward the end of the reset area,
729 * to keep the offsets into the rest of the structure smaller.
730 */
731 ARMVectorReg zarray[ARM_MAX_VQ * 16];
732
733 struct CPUBreakpoint *cpu_breakpoint[16];
734 struct CPUWatchpoint *cpu_watchpoint[16];
735
736 /* Optional fault info across tlb lookup. */
737 ARMMMUFaultInfo *tlb_fi;
738
739 /* Fields up to this point are cleared by a CPU reset */
740 struct {} end_reset_fields;
741
742 /* Fields after this point are preserved across CPU reset. */
743
744 /* Internal CPU feature flags. */
745 uint64_t features;
746
747 /* PMSAv7 MPU */
748 struct {
749 uint32_t *drbar;
750 uint32_t *drsr;
751 uint32_t *dracr;
752 uint32_t rnr[M_REG_NUM_BANKS];
753 } pmsav7;
754
755 /* PMSAv8 MPU */
756 struct {
757 /* The PMSAv8 implementation also shares some PMSAv7 config
758 * and state:
759 * pmsav7.rnr (region number register)
760 * pmsav7_dregion (number of configured regions)
761 */
762 uint32_t *rbar[M_REG_NUM_BANKS];
763 uint32_t *rlar[M_REG_NUM_BANKS];
764 uint32_t *hprbar;
765 uint32_t *hprlar;
766 uint32_t mair0[M_REG_NUM_BANKS];
767 uint32_t mair1[M_REG_NUM_BANKS];
768 uint32_t hprselr;
769 } pmsav8;
770
771 /* v8M SAU */
772 struct {
773 uint32_t *rbar;
774 uint32_t *rlar;
775 uint32_t rnr;
776 uint32_t ctrl;
777 } sau;
778
779 #if !defined(CONFIG_USER_ONLY)
780 NVICState *nvic;
781 const struct arm_boot_info *boot_info;
782 /* Store GICv3CPUState to access from this struct */
783 void *gicv3state;
784 #else /* CONFIG_USER_ONLY */
785 /* For usermode syscall translation. */
786 bool eabi;
787 /* Linux syscall tagged address support */
788 bool tagged_addr_enable;
789 #endif /* CONFIG_USER_ONLY */
790 } CPUARMState;
791
set_feature(CPUARMState * env,int feature)792 static inline void set_feature(CPUARMState *env, int feature)
793 {
794 env->features |= 1ULL << feature;
795 }
796
unset_feature(CPUARMState * env,int feature)797 static inline void unset_feature(CPUARMState *env, int feature)
798 {
799 env->features &= ~(1ULL << feature);
800 }
801
802 /**
803 * ARMELChangeHookFn:
804 * type of a function which can be registered via arm_register_el_change_hook()
805 * to get callbacks when the CPU changes its exception level or mode.
806 */
807 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
808 typedef struct ARMELChangeHook ARMELChangeHook;
809 struct ARMELChangeHook {
810 ARMELChangeHookFn *hook;
811 void *opaque;
812 QLIST_ENTRY(ARMELChangeHook) node;
813 };
814
815 /* These values map onto the return values for
816 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
817 typedef enum ARMPSCIState {
818 PSCI_ON = 0,
819 PSCI_OFF = 1,
820 PSCI_ON_PENDING = 2
821 } ARMPSCIState;
822
823 typedef struct ARMISARegisters ARMISARegisters;
824
825 /*
826 * In map, each set bit is a supported vector length of (bit-number + 1) * 16
827 * bytes, i.e. each bit number + 1 is the vector length in quadwords.
828 *
829 * While processing properties during initialization, corresponding init bits
830 * are set for bits in sve_vq_map that have been set by properties.
831 *
832 * Bits set in supported represent valid vector lengths for the CPU type.
833 */
834 typedef struct {
835 uint32_t map, init, supported;
836 } ARMVQMap;
837
838 /* REG is ID_XXX */
839 #define FIELD_DP64_IDREG(ISAR, REG, FIELD, VALUE) \
840 ({ \
841 ARMISARegisters *i_ = (ISAR); \
842 uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \
843 regval = FIELD_DP64(regval, REG, FIELD, VALUE); \
844 i_->idregs[REG ## _EL1_IDX] = regval; \
845 })
846
847 #define FIELD_DP32_IDREG(ISAR, REG, FIELD, VALUE) \
848 ({ \
849 ARMISARegisters *i_ = (ISAR); \
850 uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \
851 regval = FIELD_DP32(regval, REG, FIELD, VALUE); \
852 i_->idregs[REG ## _EL1_IDX] = regval; \
853 })
854
855 #define FIELD_EX64_IDREG(ISAR, REG, FIELD) \
856 ({ \
857 const ARMISARegisters *i_ = (ISAR); \
858 FIELD_EX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
859 })
860
861 #define FIELD_EX32_IDREG(ISAR, REG, FIELD) \
862 ({ \
863 const ARMISARegisters *i_ = (ISAR); \
864 FIELD_EX32(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
865 })
866
867 #define FIELD_SEX64_IDREG(ISAR, REG, FIELD) \
868 ({ \
869 const ARMISARegisters *i_ = (ISAR); \
870 FIELD_SEX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
871 })
872
873 #define SET_IDREG(ISAR, REG, VALUE) \
874 ({ \
875 ARMISARegisters *i_ = (ISAR); \
876 i_->idregs[REG ## _EL1_IDX] = VALUE; \
877 })
878
879 #define GET_IDREG(ISAR, REG) \
880 ({ \
881 const ARMISARegisters *i_ = (ISAR); \
882 i_->idregs[REG ## _EL1_IDX]; \
883 })
884
885 /**
886 * ARMCPU:
887 * @env: #CPUARMState
888 *
889 * An ARM CPU core.
890 */
891 struct ArchCPU {
892 CPUState parent_obj;
893
894 CPUARMState env;
895
896 /* Coprocessor information */
897 GHashTable *cp_regs;
898 /* For marshalling (mostly coprocessor) register state between the
899 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
900 * we use these arrays.
901 */
902 /* List of register indexes managed via these arrays; (full KVM style
903 * 64 bit indexes, not CPRegInfo 32 bit indexes)
904 */
905 uint64_t *cpreg_indexes;
906 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
907 uint64_t *cpreg_values;
908 /* Length of the indexes, values, reset_values arrays */
909 int32_t cpreg_array_len;
910 /* These are used only for migration: incoming data arrives in
911 * these fields and is sanity checked in post_load before copying
912 * to the working data structures above.
913 */
914 uint64_t *cpreg_vmstate_indexes;
915 uint64_t *cpreg_vmstate_values;
916 int32_t cpreg_vmstate_array_len;
917
918 DynamicGDBFeatureInfo dyn_sysreg_feature;
919 DynamicGDBFeatureInfo dyn_svereg_feature;
920 DynamicGDBFeatureInfo dyn_m_systemreg_feature;
921 DynamicGDBFeatureInfo dyn_m_secextreg_feature;
922
923 /* Timers used by the generic (architected) timer */
924 QEMUTimer *gt_timer[NUM_GTIMERS];
925 /*
926 * Timer used by the PMU. Its state is restored after migration by
927 * pmu_op_finish() - it does not need other handling during migration
928 */
929 QEMUTimer *pmu_timer;
930 /* Timer used for WFxT timeouts */
931 QEMUTimer *wfxt_timer;
932
933 /* GPIO outputs for generic timer */
934 qemu_irq gt_timer_outputs[NUM_GTIMERS];
935 /* GPIO output for GICv3 maintenance interrupt signal */
936 qemu_irq gicv3_maintenance_interrupt;
937 /* GPIO output for the PMU interrupt */
938 qemu_irq pmu_interrupt;
939
940 /* MemoryRegion to use for secure physical accesses */
941 MemoryRegion *secure_memory;
942
943 /* MemoryRegion to use for allocation tag accesses */
944 MemoryRegion *tag_memory;
945 MemoryRegion *secure_tag_memory;
946
947 /* For v8M, pointer to the IDAU interface provided by board/SoC */
948 Object *idau;
949
950 /* 'compatible' string for this CPU for Linux device trees */
951 const char *dtb_compatible;
952
953 /* PSCI version for this CPU
954 * Bits[31:16] = Major Version
955 * Bits[15:0] = Minor Version
956 */
957 uint32_t psci_version;
958
959 /* Current power state, access guarded by BQL */
960 ARMPSCIState power_state;
961
962 /* CPU has virtualization extension */
963 bool has_el2;
964 /* CPU has security extension */
965 bool has_el3;
966 /* CPU has PMU (Performance Monitor Unit) */
967 bool has_pmu;
968 /* CPU has VFP */
969 bool has_vfp;
970 /* CPU has 32 VFP registers */
971 bool has_vfp_d32;
972 /* CPU has Neon */
973 bool has_neon;
974 /* CPU has M-profile DSP extension */
975 bool has_dsp;
976
977 /* CPU has memory protection unit */
978 bool has_mpu;
979 /* CPU has MTE enabled in KVM mode */
980 bool kvm_mte;
981 /* PMSAv7 MPU number of supported regions */
982 uint32_t pmsav7_dregion;
983 /* PMSAv8 MPU number of supported hyp regions */
984 uint32_t pmsav8r_hdregion;
985 /* v8M SAU number of supported regions */
986 uint32_t sau_sregion;
987
988 /* PSCI conduit used to invoke PSCI methods
989 * 0 - disabled, 1 - smc, 2 - hvc
990 */
991 uint32_t psci_conduit;
992
993 /* For v8M, initial value of the Secure VTOR */
994 uint32_t init_svtor;
995 /* For v8M, initial value of the Non-secure VTOR */
996 uint32_t init_nsvtor;
997
998 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
999 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
1000 */
1001 uint32_t kvm_target;
1002
1003 /* KVM init features for this CPU */
1004 uint32_t kvm_init_features[7];
1005
1006 /* KVM CPU state */
1007
1008 /* KVM virtual time adjustment */
1009 bool kvm_adjvtime;
1010 bool kvm_vtime_dirty;
1011 uint64_t kvm_vtime;
1012
1013 /* KVM steal time */
1014 OnOffAuto kvm_steal_time;
1015
1016 /* Uniprocessor system with MP extensions */
1017 bool mp_is_up;
1018
1019 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init
1020 * and the probe failed (so we need to report the error in realize)
1021 */
1022 bool host_cpu_probe_failed;
1023
1024 /* QOM property to indicate we should use the back-compat CNTFRQ default */
1025 bool backcompat_cntfrq;
1026
1027 /* QOM property to indicate we should use the back-compat QARMA5 default */
1028 bool backcompat_pauth_default_use_qarma5;
1029
1030 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
1031 * register.
1032 */
1033 int32_t core_count;
1034
1035 /* The instance init functions for implementation-specific subclasses
1036 * set these fields to specify the implementation-dependent values of
1037 * various constant registers and reset values of non-constant
1038 * registers.
1039 * Some of these might become QOM properties eventually.
1040 * Field names match the official register names as defined in the
1041 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
1042 * is used for reset values of non-constant registers; no reset_
1043 * prefix means a constant register.
1044 * Some of these registers are split out into a substructure that
1045 * is shared with the translators to control the ISA.
1046 *
1047 * Note that if you add an ID register to the ARMISARegisters struct
1048 * you need to also update the 32-bit and 64-bit versions of the
1049 * kvm_arm_get_host_cpu_features() function to correctly populate the
1050 * field by reading the value from the KVM vCPU.
1051 */
1052 struct ARMISARegisters {
1053 uint32_t mvfr0;
1054 uint32_t mvfr1;
1055 uint32_t mvfr2;
1056 uint32_t dbgdidr;
1057 uint32_t dbgdevid;
1058 uint32_t dbgdevid1;
1059 uint64_t reset_pmcr_el0;
1060 uint64_t idregs[NUM_ID_IDX];
1061 } isar;
1062 uint64_t midr;
1063 uint32_t revidr;
1064 uint32_t reset_fpsid;
1065 uint64_t ctr;
1066 uint32_t reset_sctlr;
1067 uint64_t pmceid0;
1068 uint64_t pmceid1;
1069 uint32_t id_afr0;
1070 uint64_t id_aa64afr0;
1071 uint64_t id_aa64afr1;
1072 uint64_t clidr;
1073 uint64_t mp_affinity; /* MP ID without feature bits */
1074 /* The elements of this array are the CCSIDR values for each cache,
1075 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
1076 */
1077 uint64_t ccsidr[16];
1078 uint64_t reset_cbar;
1079 uint32_t reset_auxcr;
1080 bool reset_hivecs;
1081 uint8_t reset_l0gptsz;
1082
1083 /*
1084 * Intermediate values used during property parsing.
1085 * Once finalized, the values should be read from ID_AA64*.
1086 */
1087 bool prop_pauth;
1088 bool prop_pauth_impdef;
1089 bool prop_pauth_qarma3;
1090 bool prop_pauth_qarma5;
1091 bool prop_lpa2;
1092
1093 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
1094 uint8_t dcz_blocksize;
1095 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
1096 uint8_t gm_blocksize;
1097
1098 uint64_t rvbar_prop; /* Property/input signals. */
1099
1100 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
1101 int gic_num_lrs; /* number of list registers */
1102 int gic_vpribits; /* number of virtual priority bits */
1103 int gic_vprebits; /* number of virtual preemption bits */
1104 int gic_pribits; /* number of physical priority bits */
1105
1106 /* Whether the cfgend input is high (i.e. this CPU should reset into
1107 * big-endian mode). This setting isn't used directly: instead it modifies
1108 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
1109 * architecture version.
1110 */
1111 bool cfgend;
1112
1113 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
1114 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
1115
1116 int32_t node_id; /* NUMA node this CPU belongs to */
1117
1118 /* Used to synchronize KVM and QEMU in-kernel device levels */
1119 uint8_t device_irq_level;
1120
1121 /* Used to set the maximum vector length the cpu will support. */
1122 uint32_t sve_max_vq;
1123
1124 #ifdef CONFIG_USER_ONLY
1125 /* Used to set the default vector length at process start. */
1126 uint32_t sve_default_vq;
1127 uint32_t sme_default_vq;
1128 #endif
1129
1130 ARMVQMap sve_vq;
1131 ARMVQMap sme_vq;
1132
1133 /* Generic timer counter frequency, in Hz */
1134 uint64_t gt_cntfrq_hz;
1135 };
1136
1137 typedef struct ARMCPUInfo {
1138 const char *name;
1139 const char *deprecation_note;
1140 void (*initfn)(Object *obj);
1141 void (*class_init)(ObjectClass *oc, const void *data);
1142 } ARMCPUInfo;
1143
1144 /**
1145 * ARMCPUClass:
1146 * @parent_realize: The parent class' realize handler.
1147 * @parent_phases: The parent class' reset phase handlers.
1148 *
1149 * An ARM CPU model.
1150 */
1151 struct ARMCPUClass {
1152 CPUClass parent_class;
1153
1154 const ARMCPUInfo *info;
1155 DeviceRealize parent_realize;
1156 ResettablePhases parent_phases;
1157 };
1158
1159 /* Callback functions for the generic timer's timers. */
1160 void arm_gt_ptimer_cb(void *opaque);
1161 void arm_gt_vtimer_cb(void *opaque);
1162 void arm_gt_htimer_cb(void *opaque);
1163 void arm_gt_stimer_cb(void *opaque);
1164 void arm_gt_hvtimer_cb(void *opaque);
1165 void arm_gt_sel2timer_cb(void *opaque);
1166 void arm_gt_sel2vtimer_cb(void *opaque);
1167
1168 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
1169 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque);
1170
1171 #define ARM_AFF0_SHIFT 0
1172 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
1173 #define ARM_AFF1_SHIFT 8
1174 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
1175 #define ARM_AFF2_SHIFT 16
1176 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
1177 #define ARM_AFF3_SHIFT 32
1178 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
1179 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8
1180
1181 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK)
1182 #define ARM64_AFFINITY_MASK \
1183 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK)
1184 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
1185
1186 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz);
1187
1188 #ifndef CONFIG_USER_ONLY
1189 extern const VMStateDescription vmstate_arm_cpu;
1190
1191 void arm_cpu_do_interrupt(CPUState *cpu);
1192 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
1193
1194 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1195 MemTxAttrs *attrs);
1196 #endif /* !CONFIG_USER_ONLY */
1197
1198 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1199 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1200
1201 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1202 int cpuid, DumpState *s);
1203 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1204 int cpuid, DumpState *s);
1205
1206 /**
1207 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling
1208 * @cpu: CPU (which must have been freshly reset)
1209 * @target_el: exception level to put the CPU into
1210 * @secure: whether to put the CPU in secure state
1211 *
1212 * When QEMU is directly running a guest kernel at a lower level than
1213 * EL3 it implicitly emulates some aspects of the guest firmware.
1214 * This includes that on reset we need to configure the parts of the
1215 * CPU corresponding to EL3 so that the real guest code can run at its
1216 * lower exception level. This function does that post-reset CPU setup,
1217 * for when we do direct boot of a guest kernel, and for when we
1218 * emulate PSCI and similar firmware interfaces starting a CPU at a
1219 * lower exception level.
1220 *
1221 * @target_el must be an EL implemented by the CPU between 1 and 3.
1222 * We do not support dropping into a Secure EL other than 3.
1223 *
1224 * It is the responsibility of the caller to call arm_rebuild_hflags().
1225 */
1226 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el);
1227
1228 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1229 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1230 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
1231 void aarch64_sve_change_el(CPUARMState *env, int old_el,
1232 int new_el, bool el0_a64);
1233 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask);
1234
1235 /*
1236 * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1237 * The byte at offset i from the start of the in-memory representation contains
1238 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
1239 * lowest offsets are stored in the lowest memory addresses, then that nearly
1240 * matches QEMU's representation, which is to use an array of host-endian
1241 * uint64_t's, where the lower offsets are at the lower indices. To complete
1242 * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1243 */
sve_bswap64(uint64_t * dst,uint64_t * src,int nr)1244 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1245 {
1246 #if HOST_BIG_ENDIAN
1247 int i;
1248
1249 for (i = 0; i < nr; ++i) {
1250 dst[i] = bswap64(src[i]);
1251 }
1252
1253 return dst;
1254 #else
1255 return src;
1256 #endif
1257 }
1258
1259 void aarch64_sync_32_to_64(CPUARMState *env);
1260 void aarch64_sync_64_to_32(CPUARMState *env);
1261
1262 int fp_exception_el(CPUARMState *env, int cur_el);
1263 int sve_exception_el(CPUARMState *env, int cur_el);
1264 int sme_exception_el(CPUARMState *env, int cur_el);
1265
1266 /**
1267 * sve_vqm1_for_el_sm:
1268 * @env: CPUARMState
1269 * @el: exception level
1270 * @sm: streaming mode
1271 *
1272 * Compute the current vector length for @el & @sm, in units of
1273 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN.
1274 * If @sm, compute for SVL, otherwise NVL.
1275 */
1276 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm);
1277
1278 /* Likewise, but using @sm = PSTATE.SM. */
1279 uint32_t sve_vqm1_for_el(CPUARMState *env, int el);
1280
is_a64(CPUARMState * env)1281 static inline bool is_a64(CPUARMState *env)
1282 {
1283 return env->aarch64;
1284 }
1285
1286 /**
1287 * pmu_op_start/finish
1288 * @env: CPUARMState
1289 *
1290 * Convert all PMU counters between their delta form (the typical mode when
1291 * they are enabled) and the guest-visible values. These two calls must
1292 * surround any action which might affect the counters.
1293 */
1294 void pmu_op_start(CPUARMState *env);
1295 void pmu_op_finish(CPUARMState *env);
1296
1297 /*
1298 * Called when a PMU counter is due to overflow
1299 */
1300 void arm_pmu_timer_cb(void *opaque);
1301
1302 /**
1303 * Functions to register as EL change hooks for PMU mode filtering
1304 */
1305 void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1306 void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1307
1308 /*
1309 * pmu_init
1310 * @cpu: ARMCPU
1311 *
1312 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state
1313 * for the current configuration
1314 */
1315 void pmu_init(ARMCPU *cpu);
1316
1317 /* SCTLR bit meanings. Several bits have been reused in newer
1318 * versions of the architecture; in that case we define constants
1319 * for both old and new bit meanings. Code which tests against those
1320 * bits should probably check or otherwise arrange that the CPU
1321 * is the architectural version it expects.
1322 */
1323 #define SCTLR_M (1U << 0)
1324 #define SCTLR_A (1U << 1)
1325 #define SCTLR_C (1U << 2)
1326 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
1327 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1328 #define SCTLR_SA (1U << 3) /* AArch64 only */
1329 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
1330 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1331 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
1332 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
1333 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
1334 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
1335 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */
1336 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
1337 #define SCTLR_ITD (1U << 7) /* v8 onward */
1338 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
1339 #define SCTLR_SED (1U << 8) /* v8 onward */
1340 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
1341 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
1342 #define SCTLR_F (1U << 10) /* up to v6 */
1343 #define SCTLR_SW (1U << 10) /* v7 */
1344 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */
1345 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */
1346 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */
1347 #define SCTLR_I (1U << 12)
1348 #define SCTLR_V (1U << 13) /* AArch32 only */
1349 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */
1350 #define SCTLR_RR (1U << 14) /* up to v7 */
1351 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
1352 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
1353 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
1354 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
1355 #define SCTLR_nTWI (1U << 16) /* v8 onward */
1356 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */
1357 #define SCTLR_BR (1U << 17) /* PMSA only */
1358 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
1359 #define SCTLR_nTWE (1U << 18) /* v8 onward */
1360 #define SCTLR_WXN (1U << 19)
1361 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
1362 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
1363 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
1364 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
1365 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
1366 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
1367 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */
1368 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
1369 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */
1370 #define SCTLR_VE (1U << 24) /* up to v7 */
1371 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
1372 #define SCTLR_EE (1U << 25)
1373 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
1374 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
1375 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */
1376 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */
1377 #define SCTLR_TRE (1U << 28) /* AArch32 only */
1378 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1379 #define SCTLR_AFE (1U << 29) /* AArch32 only */
1380 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1381 #define SCTLR_TE (1U << 30) /* AArch32 only */
1382 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */
1383 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */
1384 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */
1385 #define SCTLR_CMOW (1ULL << 32) /* FEAT_CMOW */
1386 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */
1387 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
1388 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
1389 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
1390 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */
1391 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
1392 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
1393 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
1394 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */
1395 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */
1396 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */
1397 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */
1398 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */
1399 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */
1400 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */
1401 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */
1402 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */
1403 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */
1404 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */
1405 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */
1406 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */
1407 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
1408 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */
1409
1410 #define CPSR_M (0x1fU)
1411 #define CPSR_T (1U << 5)
1412 #define CPSR_F (1U << 6)
1413 #define CPSR_I (1U << 7)
1414 #define CPSR_A (1U << 8)
1415 #define CPSR_E (1U << 9)
1416 #define CPSR_IT_2_7 (0xfc00U)
1417 #define CPSR_GE (0xfU << 16)
1418 #define CPSR_IL (1U << 20)
1419 #define CPSR_DIT (1U << 21)
1420 #define CPSR_PAN (1U << 22)
1421 #define CPSR_SSBS (1U << 23)
1422 #define CPSR_J (1U << 24)
1423 #define CPSR_IT_0_1 (3U << 25)
1424 #define CPSR_Q (1U << 27)
1425 #define CPSR_V (1U << 28)
1426 #define CPSR_C (1U << 29)
1427 #define CPSR_Z (1U << 30)
1428 #define CPSR_N (1U << 31)
1429 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1430 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1431 #define ISR_FS (1U << 9)
1432 #define ISR_IS (1U << 10)
1433
1434 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1435 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1436 | CPSR_NZCV)
1437 /* Bits writable in user mode. */
1438 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1439 /* Execution state bits. MRS read as zero, MSR writes ignored. */
1440 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1441
1442 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */
1443 #define XPSR_EXCP 0x1ffU
1444 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
1445 #define XPSR_IT_2_7 CPSR_IT_2_7
1446 #define XPSR_GE CPSR_GE
1447 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
1448 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
1449 #define XPSR_IT_0_1 CPSR_IT_0_1
1450 #define XPSR_Q CPSR_Q
1451 #define XPSR_V CPSR_V
1452 #define XPSR_C CPSR_C
1453 #define XPSR_Z CPSR_Z
1454 #define XPSR_N CPSR_N
1455 #define XPSR_NZCV CPSR_NZCV
1456 #define XPSR_IT CPSR_IT
1457
1458 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
1459 * Only these are valid when in AArch64 mode; in
1460 * AArch32 mode SPSRs are basically CPSR-format.
1461 */
1462 #define PSTATE_SP (1U)
1463 #define PSTATE_M (0xFU)
1464 #define PSTATE_nRW (1U << 4)
1465 #define PSTATE_F (1U << 6)
1466 #define PSTATE_I (1U << 7)
1467 #define PSTATE_A (1U << 8)
1468 #define PSTATE_D (1U << 9)
1469 #define PSTATE_BTYPE (3U << 10)
1470 #define PSTATE_SSBS (1U << 12)
1471 #define PSTATE_ALLINT (1U << 13)
1472 #define PSTATE_IL (1U << 20)
1473 #define PSTATE_SS (1U << 21)
1474 #define PSTATE_PAN (1U << 22)
1475 #define PSTATE_UAO (1U << 23)
1476 #define PSTATE_DIT (1U << 24)
1477 #define PSTATE_TCO (1U << 25)
1478 #define PSTATE_V (1U << 28)
1479 #define PSTATE_C (1U << 29)
1480 #define PSTATE_Z (1U << 30)
1481 #define PSTATE_N (1U << 31)
1482 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1483 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1484 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1485 /* Mode values for AArch64 */
1486 #define PSTATE_MODE_EL3h 13
1487 #define PSTATE_MODE_EL3t 12
1488 #define PSTATE_MODE_EL2h 9
1489 #define PSTATE_MODE_EL2t 8
1490 #define PSTATE_MODE_EL1h 5
1491 #define PSTATE_MODE_EL1t 4
1492 #define PSTATE_MODE_EL0t 0
1493
1494 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */
1495 FIELD(SVCR, SM, 0, 1)
1496 FIELD(SVCR, ZA, 1, 1)
1497
1498 /* Fields for SMCR_ELx. */
1499 FIELD(SMCR, LEN, 0, 4)
1500 FIELD(SMCR, FA64, 31, 1)
1501
1502 /* Write a new value to v7m.exception, thus transitioning into or out
1503 * of Handler mode; this may result in a change of active stack pointer.
1504 */
1505 void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1506
1507 /* Map EL and handler into a PSTATE_MODE. */
aarch64_pstate_mode(unsigned int el,bool handler)1508 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1509 {
1510 return (el << 2) | handler;
1511 }
1512
1513 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1514 * interprocessing, so we don't attempt to sync with the cpsr state used by
1515 * the 32 bit decoder.
1516 */
pstate_read(CPUARMState * env)1517 static inline uint32_t pstate_read(CPUARMState *env)
1518 {
1519 int ZF;
1520
1521 ZF = (env->ZF == 0);
1522 return (env->NF & 0x80000000) | (ZF << 30)
1523 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1524 | env->pstate | env->daif | (env->btype << 10);
1525 }
1526
pstate_write(CPUARMState * env,uint32_t val)1527 static inline void pstate_write(CPUARMState *env, uint32_t val)
1528 {
1529 env->ZF = (~val) & PSTATE_Z;
1530 env->NF = val;
1531 env->CF = (val >> 29) & 1;
1532 env->VF = (val << 3) & 0x80000000;
1533 env->daif = val & PSTATE_DAIF;
1534 env->btype = (val >> 10) & 3;
1535 env->pstate = val & ~CACHED_PSTATE_BITS;
1536 }
1537
1538 /* Return the current CPSR value. */
1539 uint32_t cpsr_read(CPUARMState *env);
1540
1541 typedef enum CPSRWriteType {
1542 CPSRWriteByInstr = 0, /* from guest MSR or CPS */
1543 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
1544 CPSRWriteRaw = 2,
1545 /* trust values, no reg bank switch, no hflags rebuild */
1546 CPSRWriteByGDBStub = 3, /* from the GDB stub */
1547 } CPSRWriteType;
1548
1549 /*
1550 * Set the CPSR. Note that some bits of mask must be all-set or all-clear.
1551 * This will do an arm_rebuild_hflags() if any of the bits in @mask
1552 * correspond to TB flags bits cached in the hflags, unless @write_type
1553 * is CPSRWriteRaw.
1554 */
1555 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1556 CPSRWriteType write_type);
1557
1558 /* Return the current xPSR value. */
xpsr_read(CPUARMState * env)1559 static inline uint32_t xpsr_read(CPUARMState *env)
1560 {
1561 int ZF;
1562 ZF = (env->ZF == 0);
1563 return (env->NF & 0x80000000) | (ZF << 30)
1564 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1565 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1566 | ((env->condexec_bits & 0xfc) << 8)
1567 | (env->GE << 16)
1568 | env->v7m.exception;
1569 }
1570
1571 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
xpsr_write(CPUARMState * env,uint32_t val,uint32_t mask)1572 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1573 {
1574 if (mask & XPSR_NZCV) {
1575 env->ZF = (~val) & XPSR_Z;
1576 env->NF = val;
1577 env->CF = (val >> 29) & 1;
1578 env->VF = (val << 3) & 0x80000000;
1579 }
1580 if (mask & XPSR_Q) {
1581 env->QF = ((val & XPSR_Q) != 0);
1582 }
1583 if (mask & XPSR_GE) {
1584 env->GE = (val & XPSR_GE) >> 16;
1585 }
1586 #ifndef CONFIG_USER_ONLY
1587 if (mask & XPSR_T) {
1588 env->thumb = ((val & XPSR_T) != 0);
1589 }
1590 if (mask & XPSR_IT_0_1) {
1591 env->condexec_bits &= ~3;
1592 env->condexec_bits |= (val >> 25) & 3;
1593 }
1594 if (mask & XPSR_IT_2_7) {
1595 env->condexec_bits &= 3;
1596 env->condexec_bits |= (val >> 8) & 0xfc;
1597 }
1598 if (mask & XPSR_EXCP) {
1599 /* Note that this only happens on exception exit */
1600 write_v7m_exception(env, val & XPSR_EXCP);
1601 }
1602 #endif
1603 }
1604
1605 #define HCR_VM (1ULL << 0)
1606 #define HCR_SWIO (1ULL << 1)
1607 #define HCR_PTW (1ULL << 2)
1608 #define HCR_FMO (1ULL << 3)
1609 #define HCR_IMO (1ULL << 4)
1610 #define HCR_AMO (1ULL << 5)
1611 #define HCR_VF (1ULL << 6)
1612 #define HCR_VI (1ULL << 7)
1613 #define HCR_VSE (1ULL << 8)
1614 #define HCR_FB (1ULL << 9)
1615 #define HCR_BSU_MASK (3ULL << 10)
1616 #define HCR_DC (1ULL << 12)
1617 #define HCR_TWI (1ULL << 13)
1618 #define HCR_TWE (1ULL << 14)
1619 #define HCR_TID0 (1ULL << 15)
1620 #define HCR_TID1 (1ULL << 16)
1621 #define HCR_TID2 (1ULL << 17)
1622 #define HCR_TID3 (1ULL << 18)
1623 #define HCR_TSC (1ULL << 19)
1624 #define HCR_TIDCP (1ULL << 20)
1625 #define HCR_TACR (1ULL << 21)
1626 #define HCR_TSW (1ULL << 22)
1627 #define HCR_TPCP (1ULL << 23)
1628 #define HCR_TPU (1ULL << 24)
1629 #define HCR_TTLB (1ULL << 25)
1630 #define HCR_TVM (1ULL << 26)
1631 #define HCR_TGE (1ULL << 27)
1632 #define HCR_TDZ (1ULL << 28)
1633 #define HCR_HCD (1ULL << 29)
1634 #define HCR_TRVM (1ULL << 30)
1635 #define HCR_RW (1ULL << 31)
1636 #define HCR_CD (1ULL << 32)
1637 #define HCR_ID (1ULL << 33)
1638 #define HCR_E2H (1ULL << 34)
1639 #define HCR_TLOR (1ULL << 35)
1640 #define HCR_TERR (1ULL << 36)
1641 #define HCR_TEA (1ULL << 37)
1642 #define HCR_MIOCNCE (1ULL << 38)
1643 #define HCR_TME (1ULL << 39)
1644 #define HCR_APK (1ULL << 40)
1645 #define HCR_API (1ULL << 41)
1646 #define HCR_NV (1ULL << 42)
1647 #define HCR_NV1 (1ULL << 43)
1648 #define HCR_AT (1ULL << 44)
1649 #define HCR_NV2 (1ULL << 45)
1650 #define HCR_FWB (1ULL << 46)
1651 #define HCR_FIEN (1ULL << 47)
1652 #define HCR_GPF (1ULL << 48)
1653 #define HCR_TID4 (1ULL << 49)
1654 #define HCR_TICAB (1ULL << 50)
1655 #define HCR_AMVOFFEN (1ULL << 51)
1656 #define HCR_TOCU (1ULL << 52)
1657 #define HCR_ENSCXT (1ULL << 53)
1658 #define HCR_TTLBIS (1ULL << 54)
1659 #define HCR_TTLBOS (1ULL << 55)
1660 #define HCR_ATA (1ULL << 56)
1661 #define HCR_DCT (1ULL << 57)
1662 #define HCR_TID5 (1ULL << 58)
1663 #define HCR_TWEDEN (1ULL << 59)
1664 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
1665
1666 #define SCR_NS (1ULL << 0)
1667 #define SCR_IRQ (1ULL << 1)
1668 #define SCR_FIQ (1ULL << 2)
1669 #define SCR_EA (1ULL << 3)
1670 #define SCR_FW (1ULL << 4)
1671 #define SCR_AW (1ULL << 5)
1672 #define SCR_NET (1ULL << 6)
1673 #define SCR_SMD (1ULL << 7)
1674 #define SCR_HCE (1ULL << 8)
1675 #define SCR_SIF (1ULL << 9)
1676 #define SCR_RW (1ULL << 10)
1677 #define SCR_ST (1ULL << 11)
1678 #define SCR_TWI (1ULL << 12)
1679 #define SCR_TWE (1ULL << 13)
1680 #define SCR_TLOR (1ULL << 14)
1681 #define SCR_TERR (1ULL << 15)
1682 #define SCR_APK (1ULL << 16)
1683 #define SCR_API (1ULL << 17)
1684 #define SCR_EEL2 (1ULL << 18)
1685 #define SCR_EASE (1ULL << 19)
1686 #define SCR_NMEA (1ULL << 20)
1687 #define SCR_FIEN (1ULL << 21)
1688 #define SCR_ENSCXT (1ULL << 25)
1689 #define SCR_ATA (1ULL << 26)
1690 #define SCR_FGTEN (1ULL << 27)
1691 #define SCR_ECVEN (1ULL << 28)
1692 #define SCR_TWEDEN (1ULL << 29)
1693 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4)
1694 #define SCR_TME (1ULL << 34)
1695 #define SCR_AMVOFFEN (1ULL << 35)
1696 #define SCR_ENAS0 (1ULL << 36)
1697 #define SCR_ADEN (1ULL << 37)
1698 #define SCR_HXEN (1ULL << 38)
1699 #define SCR_TRNDR (1ULL << 40)
1700 #define SCR_ENTP2 (1ULL << 41)
1701 #define SCR_GPF (1ULL << 48)
1702 #define SCR_NSE (1ULL << 62)
1703
1704 /* Return the current FPSCR value. */
1705 uint32_t vfp_get_fpscr(CPUARMState *env);
1706 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1707
1708 /*
1709 * FPCR, Floating Point Control Register
1710 * FPSR, Floating Point Status Register
1711 *
1712 * For A64 floating point control and status bits are stored in
1713 * two logically distinct registers, FPCR and FPSR. We store these
1714 * in QEMU in vfp.fpcr and vfp.fpsr.
1715 * For A32 there was only one register, FPSCR. The bits are arranged
1716 * such that FPSCR bits map to FPCR or FPSR bits in the same bit positions,
1717 * so we can use appropriate masking to handle FPSCR reads and writes.
1718 * Note that the FPCR has some bits which are not visible in the
1719 * AArch32 view (for FEAT_AFP). Writing the FPSCR leaves these unchanged.
1720 */
1721
1722 /* FPCR bits */
1723 #define FPCR_FIZ (1 << 0) /* Flush Inputs to Zero (FEAT_AFP) */
1724 #define FPCR_AH (1 << 1) /* Alternate Handling (FEAT_AFP) */
1725 #define FPCR_NEP (1 << 2) /* SIMD scalar ops preserve elts (FEAT_AFP) */
1726 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */
1727 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */
1728 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */
1729 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */
1730 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */
1731 #define FPCR_EBF (1 << 13) /* Extended BFloat16 behaviors */
1732 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */
1733 #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */
1734 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
1735 #define FPCR_STRIDE_MASK (3 << 20) /* Stride */
1736 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */
1737 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
1738 #define FPCR_DN (1 << 25) /* Default NaN enable bit */
1739 #define FPCR_AHP (1 << 26) /* Alternative half-precision */
1740
1741 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */
1742 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
1743 #define FPCR_LTPSIZE_LENGTH 3
1744
1745 /* Cumulative exception trap enable bits */
1746 #define FPCR_EEXC_MASK (FPCR_IOE | FPCR_DZE | FPCR_OFE | FPCR_UFE | FPCR_IXE | FPCR_IDE)
1747
1748 /* FPSR bits */
1749 #define FPSR_IOC (1 << 0) /* Invalid Operation cumulative exception */
1750 #define FPSR_DZC (1 << 1) /* Divide by Zero cumulative exception */
1751 #define FPSR_OFC (1 << 2) /* Overflow cumulative exception */
1752 #define FPSR_UFC (1 << 3) /* Underflow cumulative exception */
1753 #define FPSR_IXC (1 << 4) /* Inexact cumulative exception */
1754 #define FPSR_IDC (1 << 7) /* Input Denormal cumulative exception */
1755 #define FPSR_QC (1 << 27) /* Cumulative saturation bit */
1756 #define FPSR_V (1 << 28) /* FP overflow flag */
1757 #define FPSR_C (1 << 29) /* FP carry flag */
1758 #define FPSR_Z (1 << 30) /* FP zero flag */
1759 #define FPSR_N (1 << 31) /* FP negative flag */
1760
1761 /* Cumulative exception status bits */
1762 #define FPSR_CEXC_MASK (FPSR_IOC | FPSR_DZC | FPSR_OFC | FPSR_UFC | FPSR_IXC | FPSR_IDC)
1763
1764 #define FPSR_NZCV_MASK (FPSR_N | FPSR_Z | FPSR_C | FPSR_V)
1765 #define FPSR_NZCVQC_MASK (FPSR_NZCV_MASK | FPSR_QC)
1766
1767 /* A32 FPSCR bits which architecturally map to FPSR bits */
1768 #define FPSCR_FPSR_MASK (FPSR_NZCVQC_MASK | FPSR_CEXC_MASK)
1769 /* A32 FPSCR bits which architecturally map to FPCR bits */
1770 #define FPSCR_FPCR_MASK (FPCR_EEXC_MASK | FPCR_LEN_MASK | FPCR_FZ16 | \
1771 FPCR_STRIDE_MASK | FPCR_RMODE_MASK | \
1772 FPCR_FZ | FPCR_DN | FPCR_AHP)
1773 /* These masks don't overlap: each bit lives in only one place */
1774 QEMU_BUILD_BUG_ON(FPSCR_FPSR_MASK & FPSCR_FPCR_MASK);
1775
1776 /**
1777 * vfp_get_fpsr: read the AArch64 FPSR
1778 * @env: CPU context
1779 *
1780 * Return the current AArch64 FPSR value
1781 */
1782 uint32_t vfp_get_fpsr(CPUARMState *env);
1783
1784 /**
1785 * vfp_get_fpcr: read the AArch64 FPCR
1786 * @env: CPU context
1787 *
1788 * Return the current AArch64 FPCR value
1789 */
1790 uint32_t vfp_get_fpcr(CPUARMState *env);
1791
1792 /**
1793 * vfp_set_fpsr: write the AArch64 FPSR
1794 * @env: CPU context
1795 * @value: new value
1796 */
1797 void vfp_set_fpsr(CPUARMState *env, uint32_t value);
1798
1799 /**
1800 * vfp_set_fpcr: write the AArch64 FPCR
1801 * @env: CPU context
1802 * @value: new value
1803 */
1804 void vfp_set_fpcr(CPUARMState *env, uint32_t value);
1805
1806 enum arm_cpu_mode {
1807 ARM_CPU_MODE_USR = 0x10,
1808 ARM_CPU_MODE_FIQ = 0x11,
1809 ARM_CPU_MODE_IRQ = 0x12,
1810 ARM_CPU_MODE_SVC = 0x13,
1811 ARM_CPU_MODE_MON = 0x16,
1812 ARM_CPU_MODE_ABT = 0x17,
1813 ARM_CPU_MODE_HYP = 0x1a,
1814 ARM_CPU_MODE_UND = 0x1b,
1815 ARM_CPU_MODE_SYS = 0x1f
1816 };
1817
1818 /* VFP system registers. */
1819 #define ARM_VFP_FPSID 0
1820 #define ARM_VFP_FPSCR 1
1821 #define ARM_VFP_MVFR2 5
1822 #define ARM_VFP_MVFR1 6
1823 #define ARM_VFP_MVFR0 7
1824 #define ARM_VFP_FPEXC 8
1825 #define ARM_VFP_FPINST 9
1826 #define ARM_VFP_FPINST2 10
1827 /* These ones are M-profile only */
1828 #define ARM_VFP_FPSCR_NZCVQC 2
1829 #define ARM_VFP_VPR 12
1830 #define ARM_VFP_P0 13
1831 #define ARM_VFP_FPCXT_NS 14
1832 #define ARM_VFP_FPCXT_S 15
1833
1834 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
1835 #define QEMU_VFP_FPSCR_NZCV 0xffff
1836
1837 /* iwMMXt coprocessor control registers. */
1838 #define ARM_IWMMXT_wCID 0
1839 #define ARM_IWMMXT_wCon 1
1840 #define ARM_IWMMXT_wCSSF 2
1841 #define ARM_IWMMXT_wCASF 3
1842 #define ARM_IWMMXT_wCGR0 8
1843 #define ARM_IWMMXT_wCGR1 9
1844 #define ARM_IWMMXT_wCGR2 10
1845 #define ARM_IWMMXT_wCGR3 11
1846
1847 /* V7M CCR bits */
1848 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1849 FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1850 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1851 FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1852 FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1853 FIELD(V7M_CCR, STKALIGN, 9, 1)
1854 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1855 FIELD(V7M_CCR, DC, 16, 1)
1856 FIELD(V7M_CCR, IC, 17, 1)
1857 FIELD(V7M_CCR, BP, 18, 1)
1858 FIELD(V7M_CCR, LOB, 19, 1)
1859 FIELD(V7M_CCR, TRD, 20, 1)
1860
1861 /* V7M SCR bits */
1862 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1863 FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1864 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1865 FIELD(V7M_SCR, SEVONPEND, 4, 1)
1866
1867 /* V7M AIRCR bits */
1868 FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1869 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1870 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1871 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1872 FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1873 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1874 FIELD(V7M_AIRCR, PRIS, 14, 1)
1875 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1876 FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1877
1878 /* V7M CFSR bits for MMFSR */
1879 FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1880 FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1881 FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1882 FIELD(V7M_CFSR, MSTKERR, 4, 1)
1883 FIELD(V7M_CFSR, MLSPERR, 5, 1)
1884 FIELD(V7M_CFSR, MMARVALID, 7, 1)
1885
1886 /* V7M CFSR bits for BFSR */
1887 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1888 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1889 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1890 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1891 FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1892 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1893 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1894
1895 /* V7M CFSR bits for UFSR */
1896 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1897 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1898 FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1899 FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1900 FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1901 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1902 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1903
1904 /* V7M CFSR bit masks covering all of the subregister bits */
1905 FIELD(V7M_CFSR, MMFSR, 0, 8)
1906 FIELD(V7M_CFSR, BFSR, 8, 8)
1907 FIELD(V7M_CFSR, UFSR, 16, 16)
1908
1909 /* V7M HFSR bits */
1910 FIELD(V7M_HFSR, VECTTBL, 1, 1)
1911 FIELD(V7M_HFSR, FORCED, 30, 1)
1912 FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1913
1914 /* V7M DFSR bits */
1915 FIELD(V7M_DFSR, HALTED, 0, 1)
1916 FIELD(V7M_DFSR, BKPT, 1, 1)
1917 FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1918 FIELD(V7M_DFSR, VCATCH, 3, 1)
1919 FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1920
1921 /* V7M SFSR bits */
1922 FIELD(V7M_SFSR, INVEP, 0, 1)
1923 FIELD(V7M_SFSR, INVIS, 1, 1)
1924 FIELD(V7M_SFSR, INVER, 2, 1)
1925 FIELD(V7M_SFSR, AUVIOL, 3, 1)
1926 FIELD(V7M_SFSR, INVTRAN, 4, 1)
1927 FIELD(V7M_SFSR, LSPERR, 5, 1)
1928 FIELD(V7M_SFSR, SFARVALID, 6, 1)
1929 FIELD(V7M_SFSR, LSERR, 7, 1)
1930
1931 /* v7M MPU_CTRL bits */
1932 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1933 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1934 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1935
1936 /* v7M CLIDR bits */
1937 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1938 FIELD(V7M_CLIDR, LOUIS, 21, 3)
1939 FIELD(V7M_CLIDR, LOC, 24, 3)
1940 FIELD(V7M_CLIDR, LOUU, 27, 3)
1941 FIELD(V7M_CLIDR, ICB, 30, 2)
1942
1943 FIELD(V7M_CSSELR, IND, 0, 1)
1944 FIELD(V7M_CSSELR, LEVEL, 1, 3)
1945 /* We use the combination of InD and Level to index into cpu->ccsidr[];
1946 * define a mask for this and check that it doesn't permit running off
1947 * the end of the array.
1948 */
1949 FIELD(V7M_CSSELR, INDEX, 0, 4)
1950
1951 /* v7M FPCCR bits */
1952 FIELD(V7M_FPCCR, LSPACT, 0, 1)
1953 FIELD(V7M_FPCCR, USER, 1, 1)
1954 FIELD(V7M_FPCCR, S, 2, 1)
1955 FIELD(V7M_FPCCR, THREAD, 3, 1)
1956 FIELD(V7M_FPCCR, HFRDY, 4, 1)
1957 FIELD(V7M_FPCCR, MMRDY, 5, 1)
1958 FIELD(V7M_FPCCR, BFRDY, 6, 1)
1959 FIELD(V7M_FPCCR, SFRDY, 7, 1)
1960 FIELD(V7M_FPCCR, MONRDY, 8, 1)
1961 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1962 FIELD(V7M_FPCCR, UFRDY, 10, 1)
1963 FIELD(V7M_FPCCR, RES0, 11, 15)
1964 FIELD(V7M_FPCCR, TS, 26, 1)
1965 FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1966 FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1967 FIELD(V7M_FPCCR, LSPENS, 29, 1)
1968 FIELD(V7M_FPCCR, LSPEN, 30, 1)
1969 FIELD(V7M_FPCCR, ASPEN, 31, 1)
1970 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */
1971 #define R_V7M_FPCCR_BANKED_MASK \
1972 (R_V7M_FPCCR_LSPACT_MASK | \
1973 R_V7M_FPCCR_USER_MASK | \
1974 R_V7M_FPCCR_THREAD_MASK | \
1975 R_V7M_FPCCR_MMRDY_MASK | \
1976 R_V7M_FPCCR_SPLIMVIOL_MASK | \
1977 R_V7M_FPCCR_UFRDY_MASK | \
1978 R_V7M_FPCCR_ASPEN_MASK)
1979
1980 /* v7M VPR bits */
1981 FIELD(V7M_VPR, P0, 0, 16)
1982 FIELD(V7M_VPR, MASK01, 16, 4)
1983 FIELD(V7M_VPR, MASK23, 20, 4)
1984
1985 /*
1986 * System register ID fields.
1987 */
1988 FIELD(CLIDR_EL1, CTYPE1, 0, 3)
1989 FIELD(CLIDR_EL1, CTYPE2, 3, 3)
1990 FIELD(CLIDR_EL1, CTYPE3, 6, 3)
1991 FIELD(CLIDR_EL1, CTYPE4, 9, 3)
1992 FIELD(CLIDR_EL1, CTYPE5, 12, 3)
1993 FIELD(CLIDR_EL1, CTYPE6, 15, 3)
1994 FIELD(CLIDR_EL1, CTYPE7, 18, 3)
1995 FIELD(CLIDR_EL1, LOUIS, 21, 3)
1996 FIELD(CLIDR_EL1, LOC, 24, 3)
1997 FIELD(CLIDR_EL1, LOUU, 27, 3)
1998 FIELD(CLIDR_EL1, ICB, 30, 3)
1999
2000 /* When FEAT_CCIDX is implemented */
2001 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
2002 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
2003 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
2004
2005 /* When FEAT_CCIDX is not implemented */
2006 FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
2007 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
2008 FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
2009
2010 FIELD(CTR_EL0, IMINLINE, 0, 4)
2011 FIELD(CTR_EL0, L1IP, 14, 2)
2012 FIELD(CTR_EL0, DMINLINE, 16, 4)
2013 FIELD(CTR_EL0, ERG, 20, 4)
2014 FIELD(CTR_EL0, CWG, 24, 4)
2015 FIELD(CTR_EL0, IDC, 28, 1)
2016 FIELD(CTR_EL0, DIC, 29, 1)
2017 FIELD(CTR_EL0, TMINLINE, 32, 6)
2018
2019 FIELD(MIDR_EL1, REVISION, 0, 4)
2020 FIELD(MIDR_EL1, PARTNUM, 4, 12)
2021 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
2022 FIELD(MIDR_EL1, VARIANT, 20, 4)
2023 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
2024
2025 FIELD(ID_ISAR0, SWAP, 0, 4)
2026 FIELD(ID_ISAR0, BITCOUNT, 4, 4)
2027 FIELD(ID_ISAR0, BITFIELD, 8, 4)
2028 FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
2029 FIELD(ID_ISAR0, COPROC, 16, 4)
2030 FIELD(ID_ISAR0, DEBUG, 20, 4)
2031 FIELD(ID_ISAR0, DIVIDE, 24, 4)
2032
2033 FIELD(ID_ISAR1, ENDIAN, 0, 4)
2034 FIELD(ID_ISAR1, EXCEPT, 4, 4)
2035 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
2036 FIELD(ID_ISAR1, EXTEND, 12, 4)
2037 FIELD(ID_ISAR1, IFTHEN, 16, 4)
2038 FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
2039 FIELD(ID_ISAR1, INTERWORK, 24, 4)
2040 FIELD(ID_ISAR1, JAZELLE, 28, 4)
2041
2042 FIELD(ID_ISAR2, LOADSTORE, 0, 4)
2043 FIELD(ID_ISAR2, MEMHINT, 4, 4)
2044 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
2045 FIELD(ID_ISAR2, MULT, 12, 4)
2046 FIELD(ID_ISAR2, MULTS, 16, 4)
2047 FIELD(ID_ISAR2, MULTU, 20, 4)
2048 FIELD(ID_ISAR2, PSR_AR, 24, 4)
2049 FIELD(ID_ISAR2, REVERSAL, 28, 4)
2050
2051 FIELD(ID_ISAR3, SATURATE, 0, 4)
2052 FIELD(ID_ISAR3, SIMD, 4, 4)
2053 FIELD(ID_ISAR3, SVC, 8, 4)
2054 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
2055 FIELD(ID_ISAR3, TABBRANCH, 16, 4)
2056 FIELD(ID_ISAR3, T32COPY, 20, 4)
2057 FIELD(ID_ISAR3, TRUENOP, 24, 4)
2058 FIELD(ID_ISAR3, T32EE, 28, 4)
2059
2060 FIELD(ID_ISAR4, UNPRIV, 0, 4)
2061 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
2062 FIELD(ID_ISAR4, WRITEBACK, 8, 4)
2063 FIELD(ID_ISAR4, SMC, 12, 4)
2064 FIELD(ID_ISAR4, BARRIER, 16, 4)
2065 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
2066 FIELD(ID_ISAR4, PSR_M, 24, 4)
2067 FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
2068
2069 FIELD(ID_ISAR5, SEVL, 0, 4)
2070 FIELD(ID_ISAR5, AES, 4, 4)
2071 FIELD(ID_ISAR5, SHA1, 8, 4)
2072 FIELD(ID_ISAR5, SHA2, 12, 4)
2073 FIELD(ID_ISAR5, CRC32, 16, 4)
2074 FIELD(ID_ISAR5, RDM, 24, 4)
2075 FIELD(ID_ISAR5, VCMA, 28, 4)
2076
2077 FIELD(ID_ISAR6, JSCVT, 0, 4)
2078 FIELD(ID_ISAR6, DP, 4, 4)
2079 FIELD(ID_ISAR6, FHM, 8, 4)
2080 FIELD(ID_ISAR6, SB, 12, 4)
2081 FIELD(ID_ISAR6, SPECRES, 16, 4)
2082 FIELD(ID_ISAR6, BF16, 20, 4)
2083 FIELD(ID_ISAR6, I8MM, 24, 4)
2084
2085 FIELD(ID_MMFR0, VMSA, 0, 4)
2086 FIELD(ID_MMFR0, PMSA, 4, 4)
2087 FIELD(ID_MMFR0, OUTERSHR, 8, 4)
2088 FIELD(ID_MMFR0, SHARELVL, 12, 4)
2089 FIELD(ID_MMFR0, TCM, 16, 4)
2090 FIELD(ID_MMFR0, AUXREG, 20, 4)
2091 FIELD(ID_MMFR0, FCSE, 24, 4)
2092 FIELD(ID_MMFR0, INNERSHR, 28, 4)
2093
2094 FIELD(ID_MMFR1, L1HVDVA, 0, 4)
2095 FIELD(ID_MMFR1, L1UNIVA, 4, 4)
2096 FIELD(ID_MMFR1, L1HVDSW, 8, 4)
2097 FIELD(ID_MMFR1, L1UNISW, 12, 4)
2098 FIELD(ID_MMFR1, L1HVD, 16, 4)
2099 FIELD(ID_MMFR1, L1UNI, 20, 4)
2100 FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
2101 FIELD(ID_MMFR1, BPRED, 28, 4)
2102
2103 FIELD(ID_MMFR2, L1HVDFG, 0, 4)
2104 FIELD(ID_MMFR2, L1HVDBG, 4, 4)
2105 FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
2106 FIELD(ID_MMFR2, HVDTLB, 12, 4)
2107 FIELD(ID_MMFR2, UNITLB, 16, 4)
2108 FIELD(ID_MMFR2, MEMBARR, 20, 4)
2109 FIELD(ID_MMFR2, WFISTALL, 24, 4)
2110 FIELD(ID_MMFR2, HWACCFLG, 28, 4)
2111
2112 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
2113 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
2114 FIELD(ID_MMFR3, BPMAINT, 8, 4)
2115 FIELD(ID_MMFR3, MAINTBCST, 12, 4)
2116 FIELD(ID_MMFR3, PAN, 16, 4)
2117 FIELD(ID_MMFR3, COHWALK, 20, 4)
2118 FIELD(ID_MMFR3, CMEMSZ, 24, 4)
2119 FIELD(ID_MMFR3, SUPERSEC, 28, 4)
2120
2121 FIELD(ID_MMFR4, SPECSEI, 0, 4)
2122 FIELD(ID_MMFR4, AC2, 4, 4)
2123 FIELD(ID_MMFR4, XNX, 8, 4)
2124 FIELD(ID_MMFR4, CNP, 12, 4)
2125 FIELD(ID_MMFR4, HPDS, 16, 4)
2126 FIELD(ID_MMFR4, LSM, 20, 4)
2127 FIELD(ID_MMFR4, CCIDX, 24, 4)
2128 FIELD(ID_MMFR4, EVT, 28, 4)
2129
2130 FIELD(ID_MMFR5, ETS, 0, 4)
2131 FIELD(ID_MMFR5, NTLBPA, 4, 4)
2132
2133 FIELD(ID_PFR0, STATE0, 0, 4)
2134 FIELD(ID_PFR0, STATE1, 4, 4)
2135 FIELD(ID_PFR0, STATE2, 8, 4)
2136 FIELD(ID_PFR0, STATE3, 12, 4)
2137 FIELD(ID_PFR0, CSV2, 16, 4)
2138 FIELD(ID_PFR0, AMU, 20, 4)
2139 FIELD(ID_PFR0, DIT, 24, 4)
2140 FIELD(ID_PFR0, RAS, 28, 4)
2141
2142 FIELD(ID_PFR1, PROGMOD, 0, 4)
2143 FIELD(ID_PFR1, SECURITY, 4, 4)
2144 FIELD(ID_PFR1, MPROGMOD, 8, 4)
2145 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
2146 FIELD(ID_PFR1, GENTIMER, 16, 4)
2147 FIELD(ID_PFR1, SEC_FRAC, 20, 4)
2148 FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
2149 FIELD(ID_PFR1, GIC, 28, 4)
2150
2151 FIELD(ID_PFR2, CSV3, 0, 4)
2152 FIELD(ID_PFR2, SSBS, 4, 4)
2153 FIELD(ID_PFR2, RAS_FRAC, 8, 4)
2154
2155 FIELD(ID_AA64ISAR0, AES, 4, 4)
2156 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
2157 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
2158 FIELD(ID_AA64ISAR0, CRC32, 16, 4)
2159 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
2160 FIELD(ID_AA64ISAR0, TME, 24, 4)
2161 FIELD(ID_AA64ISAR0, RDM, 28, 4)
2162 FIELD(ID_AA64ISAR0, SHA3, 32, 4)
2163 FIELD(ID_AA64ISAR0, SM3, 36, 4)
2164 FIELD(ID_AA64ISAR0, SM4, 40, 4)
2165 FIELD(ID_AA64ISAR0, DP, 44, 4)
2166 FIELD(ID_AA64ISAR0, FHM, 48, 4)
2167 FIELD(ID_AA64ISAR0, TS, 52, 4)
2168 FIELD(ID_AA64ISAR0, TLB, 56, 4)
2169 FIELD(ID_AA64ISAR0, RNDR, 60, 4)
2170
2171 FIELD(ID_AA64ISAR1, DPB, 0, 4)
2172 FIELD(ID_AA64ISAR1, APA, 4, 4)
2173 FIELD(ID_AA64ISAR1, API, 8, 4)
2174 FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
2175 FIELD(ID_AA64ISAR1, FCMA, 16, 4)
2176 FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
2177 FIELD(ID_AA64ISAR1, GPA, 24, 4)
2178 FIELD(ID_AA64ISAR1, GPI, 28, 4)
2179 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
2180 FIELD(ID_AA64ISAR1, SB, 36, 4)
2181 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
2182 FIELD(ID_AA64ISAR1, BF16, 44, 4)
2183 FIELD(ID_AA64ISAR1, DGH, 48, 4)
2184 FIELD(ID_AA64ISAR1, I8MM, 52, 4)
2185 FIELD(ID_AA64ISAR1, XS, 56, 4)
2186 FIELD(ID_AA64ISAR1, LS64, 60, 4)
2187
2188 FIELD(ID_AA64ISAR2, WFXT, 0, 4)
2189 FIELD(ID_AA64ISAR2, RPRES, 4, 4)
2190 FIELD(ID_AA64ISAR2, GPA3, 8, 4)
2191 FIELD(ID_AA64ISAR2, APA3, 12, 4)
2192 FIELD(ID_AA64ISAR2, MOPS, 16, 4)
2193 FIELD(ID_AA64ISAR2, BC, 20, 4)
2194 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4)
2195 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4)
2196 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4)
2197 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4)
2198 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4)
2199 FIELD(ID_AA64ISAR2, RPRFM, 48, 4)
2200 FIELD(ID_AA64ISAR2, CSSC, 52, 4)
2201 FIELD(ID_AA64ISAR2, ATS1A, 60, 4)
2202
2203 FIELD(ID_AA64PFR0, EL0, 0, 4)
2204 FIELD(ID_AA64PFR0, EL1, 4, 4)
2205 FIELD(ID_AA64PFR0, EL2, 8, 4)
2206 FIELD(ID_AA64PFR0, EL3, 12, 4)
2207 FIELD(ID_AA64PFR0, FP, 16, 4)
2208 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
2209 FIELD(ID_AA64PFR0, GIC, 24, 4)
2210 FIELD(ID_AA64PFR0, RAS, 28, 4)
2211 FIELD(ID_AA64PFR0, SVE, 32, 4)
2212 FIELD(ID_AA64PFR0, SEL2, 36, 4)
2213 FIELD(ID_AA64PFR0, MPAM, 40, 4)
2214 FIELD(ID_AA64PFR0, AMU, 44, 4)
2215 FIELD(ID_AA64PFR0, DIT, 48, 4)
2216 FIELD(ID_AA64PFR0, RME, 52, 4)
2217 FIELD(ID_AA64PFR0, CSV2, 56, 4)
2218 FIELD(ID_AA64PFR0, CSV3, 60, 4)
2219
2220 FIELD(ID_AA64PFR1, BT, 0, 4)
2221 FIELD(ID_AA64PFR1, SSBS, 4, 4)
2222 FIELD(ID_AA64PFR1, MTE, 8, 4)
2223 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
2224 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
2225 FIELD(ID_AA64PFR1, SME, 24, 4)
2226 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4)
2227 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4)
2228 FIELD(ID_AA64PFR1, NMI, 36, 4)
2229 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4)
2230 FIELD(ID_AA64PFR1, GCS, 44, 4)
2231 FIELD(ID_AA64PFR1, THE, 48, 4)
2232 FIELD(ID_AA64PFR1, MTEX, 52, 4)
2233 FIELD(ID_AA64PFR1, DF2, 56, 4)
2234 FIELD(ID_AA64PFR1, PFAR, 60, 4)
2235
2236 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
2237 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
2238 FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
2239 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
2240 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
2241 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
2242 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
2243 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
2244 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
2245 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
2246 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
2247 FIELD(ID_AA64MMFR0, EXS, 44, 4)
2248 FIELD(ID_AA64MMFR0, FGT, 56, 4)
2249 FIELD(ID_AA64MMFR0, ECV, 60, 4)
2250
2251 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
2252 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
2253 FIELD(ID_AA64MMFR1, VH, 8, 4)
2254 FIELD(ID_AA64MMFR1, HPDS, 12, 4)
2255 FIELD(ID_AA64MMFR1, LO, 16, 4)
2256 FIELD(ID_AA64MMFR1, PAN, 20, 4)
2257 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
2258 FIELD(ID_AA64MMFR1, XNX, 28, 4)
2259 FIELD(ID_AA64MMFR1, TWED, 32, 4)
2260 FIELD(ID_AA64MMFR1, ETS, 36, 4)
2261 FIELD(ID_AA64MMFR1, HCX, 40, 4)
2262 FIELD(ID_AA64MMFR1, AFP, 44, 4)
2263 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4)
2264 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4)
2265 FIELD(ID_AA64MMFR1, CMOW, 56, 4)
2266 FIELD(ID_AA64MMFR1, ECBHB, 60, 4)
2267
2268 FIELD(ID_AA64MMFR2, CNP, 0, 4)
2269 FIELD(ID_AA64MMFR2, UAO, 4, 4)
2270 FIELD(ID_AA64MMFR2, LSM, 8, 4)
2271 FIELD(ID_AA64MMFR2, IESB, 12, 4)
2272 FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
2273 FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
2274 FIELD(ID_AA64MMFR2, NV, 24, 4)
2275 FIELD(ID_AA64MMFR2, ST, 28, 4)
2276 FIELD(ID_AA64MMFR2, AT, 32, 4)
2277 FIELD(ID_AA64MMFR2, IDS, 36, 4)
2278 FIELD(ID_AA64MMFR2, FWB, 40, 4)
2279 FIELD(ID_AA64MMFR2, TTL, 48, 4)
2280 FIELD(ID_AA64MMFR2, BBM, 52, 4)
2281 FIELD(ID_AA64MMFR2, EVT, 56, 4)
2282 FIELD(ID_AA64MMFR2, E0PD, 60, 4)
2283
2284 FIELD(ID_AA64MMFR3, TCRX, 0, 4)
2285 FIELD(ID_AA64MMFR3, SCTLRX, 4, 4)
2286 FIELD(ID_AA64MMFR3, S1PIE, 8, 4)
2287 FIELD(ID_AA64MMFR3, S2PIE, 12, 4)
2288 FIELD(ID_AA64MMFR3, S1POE, 16, 4)
2289 FIELD(ID_AA64MMFR3, S2POE, 20, 4)
2290 FIELD(ID_AA64MMFR3, AIE, 24, 4)
2291 FIELD(ID_AA64MMFR3, MEC, 28, 4)
2292 FIELD(ID_AA64MMFR3, D128, 32, 4)
2293 FIELD(ID_AA64MMFR3, D128_2, 36, 4)
2294 FIELD(ID_AA64MMFR3, SNERR, 40, 4)
2295 FIELD(ID_AA64MMFR3, ANERR, 44, 4)
2296 FIELD(ID_AA64MMFR3, SDERR, 52, 4)
2297 FIELD(ID_AA64MMFR3, ADERR, 56, 4)
2298 FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4)
2299
2300 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
2301 FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
2302 FIELD(ID_AA64DFR0, PMUVER, 8, 4)
2303 FIELD(ID_AA64DFR0, BRPS, 12, 4)
2304 FIELD(ID_AA64DFR0, PMSS, 16, 4)
2305 FIELD(ID_AA64DFR0, WRPS, 20, 4)
2306 FIELD(ID_AA64DFR0, SEBEP, 24, 4)
2307 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
2308 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
2309 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
2310 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
2311 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4)
2312 FIELD(ID_AA64DFR0, MTPMU, 48, 4)
2313 FIELD(ID_AA64DFR0, BRBE, 52, 4)
2314 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4)
2315 FIELD(ID_AA64DFR0, HPMN0, 60, 4)
2316
2317 FIELD(ID_AA64ZFR0, SVEVER, 0, 4)
2318 FIELD(ID_AA64ZFR0, AES, 4, 4)
2319 FIELD(ID_AA64ZFR0, BITPERM, 16, 4)
2320 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4)
2321 FIELD(ID_AA64ZFR0, B16B16, 24, 4)
2322 FIELD(ID_AA64ZFR0, SHA3, 32, 4)
2323 FIELD(ID_AA64ZFR0, SM4, 40, 4)
2324 FIELD(ID_AA64ZFR0, I8MM, 44, 4)
2325 FIELD(ID_AA64ZFR0, F32MM, 52, 4)
2326 FIELD(ID_AA64ZFR0, F64MM, 56, 4)
2327
2328 FIELD(ID_AA64SMFR0, F32F32, 32, 1)
2329 FIELD(ID_AA64SMFR0, BI32I32, 33, 1)
2330 FIELD(ID_AA64SMFR0, B16F32, 34, 1)
2331 FIELD(ID_AA64SMFR0, F16F32, 35, 1)
2332 FIELD(ID_AA64SMFR0, I8I32, 36, 4)
2333 FIELD(ID_AA64SMFR0, F16F16, 42, 1)
2334 FIELD(ID_AA64SMFR0, B16B16, 43, 1)
2335 FIELD(ID_AA64SMFR0, I16I32, 44, 4)
2336 FIELD(ID_AA64SMFR0, F64F64, 48, 1)
2337 FIELD(ID_AA64SMFR0, I16I64, 52, 4)
2338 FIELD(ID_AA64SMFR0, SMEVER, 56, 4)
2339 FIELD(ID_AA64SMFR0, FA64, 63, 1)
2340
2341 FIELD(ID_DFR0, COPDBG, 0, 4)
2342 FIELD(ID_DFR0, COPSDBG, 4, 4)
2343 FIELD(ID_DFR0, MMAPDBG, 8, 4)
2344 FIELD(ID_DFR0, COPTRC, 12, 4)
2345 FIELD(ID_DFR0, MMAPTRC, 16, 4)
2346 FIELD(ID_DFR0, MPROFDBG, 20, 4)
2347 FIELD(ID_DFR0, PERFMON, 24, 4)
2348 FIELD(ID_DFR0, TRACEFILT, 28, 4)
2349
2350 FIELD(ID_DFR1, MTPMU, 0, 4)
2351 FIELD(ID_DFR1, HPMN0, 4, 4)
2352
2353 FIELD(DBGDIDR, SE_IMP, 12, 1)
2354 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
2355 FIELD(DBGDIDR, VERSION, 16, 4)
2356 FIELD(DBGDIDR, CTX_CMPS, 20, 4)
2357 FIELD(DBGDIDR, BRPS, 24, 4)
2358 FIELD(DBGDIDR, WRPS, 28, 4)
2359
2360 FIELD(DBGDEVID, PCSAMPLE, 0, 4)
2361 FIELD(DBGDEVID, WPADDRMASK, 4, 4)
2362 FIELD(DBGDEVID, BPADDRMASK, 8, 4)
2363 FIELD(DBGDEVID, VECTORCATCH, 12, 4)
2364 FIELD(DBGDEVID, VIRTEXTNS, 16, 4)
2365 FIELD(DBGDEVID, DOUBLELOCK, 20, 4)
2366 FIELD(DBGDEVID, AUXREGS, 24, 4)
2367 FIELD(DBGDEVID, CIDMASK, 28, 4)
2368
2369 FIELD(DBGDEVID1, PCSROFFSET, 0, 4)
2370
2371 FIELD(MVFR0, SIMDREG, 0, 4)
2372 FIELD(MVFR0, FPSP, 4, 4)
2373 FIELD(MVFR0, FPDP, 8, 4)
2374 FIELD(MVFR0, FPTRAP, 12, 4)
2375 FIELD(MVFR0, FPDIVIDE, 16, 4)
2376 FIELD(MVFR0, FPSQRT, 20, 4)
2377 FIELD(MVFR0, FPSHVEC, 24, 4)
2378 FIELD(MVFR0, FPROUND, 28, 4)
2379
2380 FIELD(MVFR1, FPFTZ, 0, 4)
2381 FIELD(MVFR1, FPDNAN, 4, 4)
2382 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
2383 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
2384 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
2385 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
2386 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
2387 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
2388 FIELD(MVFR1, FPHP, 24, 4)
2389 FIELD(MVFR1, SIMDFMAC, 28, 4)
2390
2391 FIELD(MVFR2, SIMDMISC, 0, 4)
2392 FIELD(MVFR2, FPMISC, 4, 4)
2393
2394 FIELD(GPCCR, PPS, 0, 3)
2395 FIELD(GPCCR, IRGN, 8, 2)
2396 FIELD(GPCCR, ORGN, 10, 2)
2397 FIELD(GPCCR, SH, 12, 2)
2398 FIELD(GPCCR, PGS, 14, 2)
2399 FIELD(GPCCR, GPC, 16, 1)
2400 FIELD(GPCCR, GPCP, 17, 1)
2401 FIELD(GPCCR, L0GPTSZ, 20, 4)
2402
2403 FIELD(MFAR, FPA, 12, 40)
2404 FIELD(MFAR, NSE, 62, 1)
2405 FIELD(MFAR, NS, 63, 1)
2406
2407 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2408
2409 /* If adding a feature bit which corresponds to a Linux ELF
2410 * HWCAP bit, remember to update the feature-bit-to-hwcap
2411 * mapping in linux-user/elfload.c:get_elf_hwcap().
2412 */
2413 enum arm_features {
2414 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
2415 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
2416 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
2417 ARM_FEATURE_V6,
2418 ARM_FEATURE_V6K,
2419 ARM_FEATURE_V7,
2420 ARM_FEATURE_THUMB2,
2421 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
2422 ARM_FEATURE_NEON,
2423 ARM_FEATURE_M, /* Microcontroller profile. */
2424 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
2425 ARM_FEATURE_THUMB2EE,
2426 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
2427 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
2428 ARM_FEATURE_V4T,
2429 ARM_FEATURE_V5,
2430 ARM_FEATURE_STRONGARM,
2431 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
2432 ARM_FEATURE_GENERIC_TIMER,
2433 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
2434 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
2435 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
2436 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
2437 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
2438 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
2439 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
2440 ARM_FEATURE_V8,
2441 ARM_FEATURE_AARCH64, /* supports 64 bit mode */
2442 ARM_FEATURE_CBAR, /* has cp15 CBAR */
2443 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
2444 ARM_FEATURE_EL2, /* has EL2 Virtualization support */
2445 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
2446 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
2447 ARM_FEATURE_PMU, /* has PMU support */
2448 ARM_FEATURE_VBAR, /* has cp15 VBAR */
2449 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
2450 ARM_FEATURE_M_MAIN, /* M profile Main Extension */
2451 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
2452 /*
2453 * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz
2454 * if the board doesn't set a value, instead of 1GHz. It is for backwards
2455 * compatibility and used only with CPU definitions that were already
2456 * in QEMU before we changed the default. It should not be set on any
2457 * CPU types added in future.
2458 */
2459 ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */
2460 };
2461
arm_feature(CPUARMState * env,int feature)2462 static inline int arm_feature(CPUARMState *env, int feature)
2463 {
2464 return (env->features & (1ULL << feature)) != 0;
2465 }
2466
2467 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
2468
2469 /*
2470 * ARM v9 security states.
2471 * The ordering of the enumeration corresponds to the low 2 bits
2472 * of the GPI value, and (except for Root) the concat of NSE:NS.
2473 */
2474
2475 typedef enum ARMSecuritySpace {
2476 ARMSS_Secure = 0,
2477 ARMSS_NonSecure = 1,
2478 ARMSS_Root = 2,
2479 ARMSS_Realm = 3,
2480 } ARMSecuritySpace;
2481
2482 /* Return true if @space is secure, in the pre-v9 sense. */
arm_space_is_secure(ARMSecuritySpace space)2483 static inline bool arm_space_is_secure(ARMSecuritySpace space)
2484 {
2485 return space == ARMSS_Secure || space == ARMSS_Root;
2486 }
2487
2488 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */
arm_secure_to_space(bool secure)2489 static inline ARMSecuritySpace arm_secure_to_space(bool secure)
2490 {
2491 return secure ? ARMSS_Secure : ARMSS_NonSecure;
2492 }
2493
2494 #if !defined(CONFIG_USER_ONLY)
2495 /**
2496 * arm_security_space_below_el3:
2497 * @env: cpu context
2498 *
2499 * Return the security space of exception levels below EL3, following
2500 * an exception return to those levels. Unlike arm_security_space,
2501 * this doesn't care about the current EL.
2502 */
2503 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env);
2504
2505 /**
2506 * arm_is_secure_below_el3:
2507 * @env: cpu context
2508 *
2509 * Return true if exception levels below EL3 are in secure state,
2510 * or would be following an exception return to those levels.
2511 */
arm_is_secure_below_el3(CPUARMState * env)2512 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2513 {
2514 ARMSecuritySpace ss = arm_security_space_below_el3(env);
2515 return ss == ARMSS_Secure;
2516 }
2517
2518 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
arm_is_el3_or_mon(CPUARMState * env)2519 static inline bool arm_is_el3_or_mon(CPUARMState *env)
2520 {
2521 assert(!arm_feature(env, ARM_FEATURE_M));
2522 if (arm_feature(env, ARM_FEATURE_EL3)) {
2523 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
2524 /* CPU currently in AArch64 state and EL3 */
2525 return true;
2526 } else if (!is_a64(env) &&
2527 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
2528 /* CPU currently in AArch32 state and monitor mode */
2529 return true;
2530 }
2531 }
2532 return false;
2533 }
2534
2535 /**
2536 * arm_security_space:
2537 * @env: cpu context
2538 *
2539 * Return the current security space of the cpu.
2540 */
2541 ARMSecuritySpace arm_security_space(CPUARMState *env);
2542
2543 /**
2544 * arm_is_secure:
2545 * @env: cpu context
2546 *
2547 * Return true if the processor is in secure state.
2548 */
arm_is_secure(CPUARMState * env)2549 static inline bool arm_is_secure(CPUARMState *env)
2550 {
2551 return arm_space_is_secure(arm_security_space(env));
2552 }
2553
2554 /*
2555 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
2556 * This corresponds to the pseudocode EL2Enabled().
2557 */
arm_is_el2_enabled_secstate(CPUARMState * env,ARMSecuritySpace space)2558 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env,
2559 ARMSecuritySpace space)
2560 {
2561 assert(space != ARMSS_Root);
2562 return arm_feature(env, ARM_FEATURE_EL2)
2563 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2));
2564 }
2565
arm_is_el2_enabled(CPUARMState * env)2566 static inline bool arm_is_el2_enabled(CPUARMState *env)
2567 {
2568 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env));
2569 }
2570
2571 #else
arm_security_space_below_el3(CPUARMState * env)2572 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env)
2573 {
2574 return ARMSS_NonSecure;
2575 }
2576
arm_is_secure_below_el3(CPUARMState * env)2577 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2578 {
2579 return false;
2580 }
2581
arm_is_el3_or_mon(CPUARMState * env)2582 static inline bool arm_is_el3_or_mon(CPUARMState *env)
2583 {
2584 return false;
2585 }
2586
arm_security_space(CPUARMState * env)2587 static inline ARMSecuritySpace arm_security_space(CPUARMState *env)
2588 {
2589 return ARMSS_NonSecure;
2590 }
2591
arm_is_secure(CPUARMState * env)2592 static inline bool arm_is_secure(CPUARMState *env)
2593 {
2594 return false;
2595 }
2596
arm_is_el2_enabled_secstate(CPUARMState * env,ARMSecuritySpace space)2597 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env,
2598 ARMSecuritySpace space)
2599 {
2600 return false;
2601 }
2602
arm_is_el2_enabled(CPUARMState * env)2603 static inline bool arm_is_el2_enabled(CPUARMState *env)
2604 {
2605 return false;
2606 }
2607 #endif
2608
2609 /**
2610 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2.
2611 * E.g. when in secure state, fields in HCR_EL2 are suppressed,
2612 * "for all purposes other than a direct read or write access of HCR_EL2."
2613 * Not included here is HCR_RW.
2614 */
2615 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space);
2616 uint64_t arm_hcr_el2_eff(CPUARMState *env);
2617 uint64_t arm_hcrx_el2_eff(CPUARMState *env);
2618
2619 /*
2620 * Function for determining whether guest cp register reads and writes should
2621 * access the secure or non-secure bank of a cp register. When EL3 is
2622 * operating in AArch32 state, the NS-bit determines whether the secure
2623 * instance of a cp register should be used. When EL3 is AArch64 (or if
2624 * it doesn't exist at all) then there is no register banking, and all
2625 * accesses are to the non-secure version.
2626 */
2627 bool access_secure_reg(CPUARMState *env);
2628
2629 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2630 uint32_t cur_el, bool secure);
2631
2632 /* Return the highest implemented Exception Level */
arm_highest_el(CPUARMState * env)2633 static inline int arm_highest_el(CPUARMState *env)
2634 {
2635 if (arm_feature(env, ARM_FEATURE_EL3)) {
2636 return 3;
2637 }
2638 if (arm_feature(env, ARM_FEATURE_EL2)) {
2639 return 2;
2640 }
2641 return 1;
2642 }
2643
2644 /* Return true if a v7M CPU is in Handler mode */
arm_v7m_is_handler_mode(CPUARMState * env)2645 static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2646 {
2647 return env->v7m.exception != 0;
2648 }
2649
2650 /**
2651 * write_list_to_cpustate
2652 * @cpu: ARMCPU
2653 *
2654 * For each register listed in the ARMCPU cpreg_indexes list, write
2655 * its value from the cpreg_values list into the ARMCPUState structure.
2656 * This updates TCG's working data structures from KVM data or
2657 * from incoming migration state.
2658 *
2659 * Returns: true if all register values were updated correctly,
2660 * false if some register was unknown or could not be written.
2661 * Note that we do not stop early on failure -- we will attempt
2662 * writing all registers in the list.
2663 */
2664 bool write_list_to_cpustate(ARMCPU *cpu);
2665
2666 /**
2667 * write_cpustate_to_list:
2668 * @cpu: ARMCPU
2669 * @kvm_sync: true if this is for syncing back to KVM
2670 *
2671 * For each register listed in the ARMCPU cpreg_indexes list, write
2672 * its value from the ARMCPUState structure into the cpreg_values list.
2673 * This is used to copy info from TCG's working data structures into
2674 * KVM or for outbound migration.
2675 *
2676 * @kvm_sync is true if we are doing this in order to sync the
2677 * register state back to KVM. In this case we will only update
2678 * values in the list if the previous list->cpustate sync actually
2679 * successfully wrote the CPU state. Otherwise we will keep the value
2680 * that is in the list.
2681 *
2682 * Returns: true if all register values were read correctly,
2683 * false if some register was unknown or could not be read.
2684 * Note that we do not stop early on failure -- we will attempt
2685 * reading all registers in the list.
2686 */
2687 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
2688
2689 #define ARM_CPUID_TI915T 0x54029152
2690 #define ARM_CPUID_TI925T 0x54029252
2691
2692 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2693
2694 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
2695
2696 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
2697 *
2698 * If EL3 is 64-bit:
2699 * + NonSecure EL1 & 0 stage 1
2700 * + NonSecure EL1 & 0 stage 2
2701 * + NonSecure EL2
2702 * + NonSecure EL2 & 0 (ARMv8.1-VHE)
2703 * + Secure EL1 & 0 stage 1
2704 * + Secure EL1 & 0 stage 2 (FEAT_SEL2)
2705 * + Secure EL2 (FEAT_SEL2)
2706 * + Secure EL2 & 0 (FEAT_SEL2)
2707 * + Realm EL1 & 0 stage 1 (FEAT_RME)
2708 * + Realm EL1 & 0 stage 2 (FEAT_RME)
2709 * + Realm EL2 (FEAT_RME)
2710 * + EL3
2711 * If EL3 is 32-bit:
2712 * + NonSecure PL1 & 0 stage 1
2713 * + NonSecure PL1 & 0 stage 2
2714 * + NonSecure PL2
2715 * + Secure PL1 & 0
2716 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
2717 *
2718 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
2719 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes,
2720 * because they may differ in access permissions even if the VA->PA map is
2721 * the same
2722 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2723 * translation, which means that we have one mmu_idx that deals with two
2724 * concatenated translation regimes [this sort of combined s1+2 TLB is
2725 * architecturally permitted]
2726 * 3. we don't need to allocate an mmu_idx to translations that we won't be
2727 * handling via the TLB. The only way to do a stage 1 translation without
2728 * the immediate stage 2 translation is via the ATS or AT system insns,
2729 * which can be slow-pathed and always do a page table walk.
2730 * The only use of stage 2 translations is either as part of an s1+2
2731 * lookup or when loading the descriptors during a stage 1 page table walk,
2732 * and in both those cases we don't use the TLB.
2733 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
2734 * translation regimes, because they map reasonably well to each other
2735 * and they can't both be active at the same time.
2736 * 5. we want to be able to use the TLB for accesses done as part of a
2737 * stage1 page table walk, rather than having to walk the stage2 page
2738 * table over and over.
2739 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
2740 * Never (PAN) bit within PSTATE.
2741 * 7. we fold together most secure and non-secure regimes for A-profile,
2742 * because there are no banked system registers for aarch64, so the
2743 * process of switching between secure and non-secure is
2744 * already heavyweight.
2745 * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure,
2746 * because both are in use simultaneously for Secure EL2.
2747 *
2748 * This gives us the following list of cases:
2749 *
2750 * EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2)
2751 * EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2)
2752 * EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN)
2753 * EL0 EL2&0
2754 * EL2 EL2&0
2755 * EL2 EL2&0 +PAN
2756 * EL2 (aka NS PL2)
2757 * EL3 (aka AArch32 S PL1 PL1&0)
2758 * AArch32 S PL0 PL1&0 (we call this EL30_0)
2759 * AArch32 S PL1 PL1&0 +PAN (we call this EL30_3_PAN)
2760 * Stage2 Secure
2761 * Stage2 NonSecure
2762 * plus one TLB per Physical address space: S, NS, Realm, Root
2763 *
2764 * for a total of 16 different mmu_idx.
2765 *
2766 * R profile CPUs have an MPU, but can use the same set of MMU indexes
2767 * as A profile. They only need to distinguish EL0 and EL1 (and
2768 * EL2 for cores like the Cortex-R52).
2769 *
2770 * M profile CPUs are rather different as they do not have a true MMU.
2771 * They have the following different MMU indexes:
2772 * User
2773 * Privileged
2774 * User, execution priority negative (ie the MPU HFNMIENA bit may apply)
2775 * Privileged, execution priority negative (ditto)
2776 * If the CPU supports the v8M Security Extension then there are also:
2777 * Secure User
2778 * Secure Privileged
2779 * Secure User, execution priority negative
2780 * Secure Privileged, execution priority negative
2781 *
2782 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
2783 * are not quite the same -- different CPU types (most notably M profile
2784 * vs A/R profile) would like to use MMU indexes with different semantics,
2785 * but since we don't ever need to use all of those in a single CPU we
2786 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU
2787 * modes + total number of M profile MMU modes". The lower bits of
2788 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
2789 * the same for any particular CPU.
2790 * Variables of type ARMMUIdx are always full values, and the core
2791 * index values are in variables of type 'int'.
2792 *
2793 * Our enumeration includes at the end some entries which are not "true"
2794 * mmu_idx values in that they don't have corresponding TLBs and are only
2795 * valid for doing slow path page table walks.
2796 *
2797 * The constant names here are patterned after the general style of the names
2798 * of the AT/ATS operations.
2799 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
2800 * For M profile we arrange them to have a bit for priv, a bit for negpri
2801 * and a bit for secure.
2802 */
2803 #define ARM_MMU_IDX_A 0x10 /* A profile */
2804 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
2805 #define ARM_MMU_IDX_M 0x40 /* M profile */
2806
2807 /* Meanings of the bits for M profile mmu idx values */
2808 #define ARM_MMU_IDX_M_PRIV 0x1
2809 #define ARM_MMU_IDX_M_NEGPRI 0x2
2810 #define ARM_MMU_IDX_M_S 0x4 /* Secure */
2811
2812 #define ARM_MMU_IDX_TYPE_MASK \
2813 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
2814 #define ARM_MMU_IDX_COREIDX_MASK 0xf
2815
2816 typedef enum ARMMMUIdx {
2817 /*
2818 * A-profile.
2819 */
2820 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
2821 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A,
2822 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A,
2823 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A,
2824 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A,
2825 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A,
2826 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A,
2827 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A,
2828 ARMMMUIdx_E30_0 = 8 | ARM_MMU_IDX_A,
2829 ARMMMUIdx_E30_3_PAN = 9 | ARM_MMU_IDX_A,
2830
2831 /*
2832 * Used for second stage of an S12 page table walk, or for descriptor
2833 * loads during first stage of an S1 page table walk. Note that both
2834 * are in use simultaneously for SecureEL2: the security state for
2835 * the S2 ptw is selected by the NS bit from the S1 ptw.
2836 */
2837 ARMMMUIdx_Stage2_S = 10 | ARM_MMU_IDX_A,
2838 ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A,
2839
2840 /* TLBs with 1-1 mapping to the physical address spaces. */
2841 ARMMMUIdx_Phys_S = 12 | ARM_MMU_IDX_A,
2842 ARMMMUIdx_Phys_NS = 13 | ARM_MMU_IDX_A,
2843 ARMMMUIdx_Phys_Root = 14 | ARM_MMU_IDX_A,
2844 ARMMMUIdx_Phys_Realm = 15 | ARM_MMU_IDX_A,
2845
2846 /*
2847 * These are not allocated TLBs and are used only for AT system
2848 * instructions or for the first stage of an S12 page table walk.
2849 */
2850 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
2851 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
2852 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
2853
2854 /*
2855 * M-profile.
2856 */
2857 ARMMMUIdx_MUser = ARM_MMU_IDX_M,
2858 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
2859 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
2860 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
2861 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
2862 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
2863 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
2864 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
2865 } ARMMMUIdx;
2866
2867 /*
2868 * Bit macros for the core-mmu-index values for each index,
2869 * for use when calling tlb_flush_by_mmuidx() and friends.
2870 */
2871 #define TO_CORE_BIT(NAME) \
2872 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
2873
2874 typedef enum ARMMMUIdxBit {
2875 TO_CORE_BIT(E10_0),
2876 TO_CORE_BIT(E20_0),
2877 TO_CORE_BIT(E10_1),
2878 TO_CORE_BIT(E10_1_PAN),
2879 TO_CORE_BIT(E2),
2880 TO_CORE_BIT(E20_2),
2881 TO_CORE_BIT(E20_2_PAN),
2882 TO_CORE_BIT(E3),
2883 TO_CORE_BIT(E30_0),
2884 TO_CORE_BIT(E30_3_PAN),
2885 TO_CORE_BIT(Stage2),
2886 TO_CORE_BIT(Stage2_S),
2887
2888 TO_CORE_BIT(MUser),
2889 TO_CORE_BIT(MPriv),
2890 TO_CORE_BIT(MUserNegPri),
2891 TO_CORE_BIT(MPrivNegPri),
2892 TO_CORE_BIT(MSUser),
2893 TO_CORE_BIT(MSPriv),
2894 TO_CORE_BIT(MSUserNegPri),
2895 TO_CORE_BIT(MSPrivNegPri),
2896 } ARMMMUIdxBit;
2897
2898 #undef TO_CORE_BIT
2899
2900 #define MMU_USER_IDX 0
2901
2902 /* Indexes used when registering address spaces with cpu_address_space_init */
2903 typedef enum ARMASIdx {
2904 ARMASIdx_NS = 0,
2905 ARMASIdx_S = 1,
2906 ARMASIdx_TagNS = 2,
2907 ARMASIdx_TagS = 3,
2908 } ARMASIdx;
2909
arm_space_to_phys(ARMSecuritySpace space)2910 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space)
2911 {
2912 /* Assert the relative order of the physical mmu indexes. */
2913 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0);
2914 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure);
2915 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root);
2916 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm);
2917
2918 return ARMMMUIdx_Phys_S + space;
2919 }
2920
arm_phys_to_space(ARMMMUIdx idx)2921 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx)
2922 {
2923 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm);
2924 return idx - ARMMMUIdx_Phys_S;
2925 }
2926
arm_v7m_csselr_razwi(ARMCPU * cpu)2927 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
2928 {
2929 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and
2930 * CSSELR is RAZ/WI.
2931 */
2932 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
2933 }
2934
arm_sctlr_b(CPUARMState * env)2935 static inline bool arm_sctlr_b(CPUARMState *env)
2936 {
2937 return
2938 /* We need not implement SCTLR.ITD in user-mode emulation, so
2939 * let linux-user ignore the fact that it conflicts with SCTLR_B.
2940 * This lets people run BE32 binaries with "-cpu any".
2941 */
2942 #ifndef CONFIG_USER_ONLY
2943 !arm_feature(env, ARM_FEATURE_V7) &&
2944 #endif
2945 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
2946 }
2947
2948 uint64_t arm_sctlr(CPUARMState *env, int el);
2949
2950 /*
2951 * We have more than 32-bits worth of state per TB, so we split the data
2952 * between tb->flags and tb->cs_base, which is otherwise unused for ARM.
2953 * We collect these two parts in CPUARMTBFlags where they are named
2954 * flags and flags2 respectively.
2955 *
2956 * The flags that are shared between all execution modes, TBFLAG_ANY, are stored
2957 * in flags. The flags that are specific to a given mode are stored in flags2.
2958 * flags2 always has 64-bits, even though only 32-bits are used for A32 and M32.
2959 *
2960 * The bits for 32-bit A-profile and M-profile partially overlap:
2961 *
2962 * 31 23 11 10 0
2963 * +-------------+----------+----------------+
2964 * | | | TBFLAG_A32 |
2965 * | TBFLAG_AM32 | +-----+----------+
2966 * | | |TBFLAG_M32|
2967 * +-------------+----------------+----------+
2968 * 31 23 6 5 0
2969 *
2970 * Unless otherwise noted, these bits are cached in env->hflags.
2971 */
2972 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1)
2973 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1)
2974 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */
2975 FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
2976 FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
2977 /* Target EL if we take a floating-point-disabled exception */
2978 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
2979 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
2980 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
2981 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
2982 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
2983 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1)
2984
2985 /*
2986 * Bit usage when in AArch32 state, both A- and M-profile.
2987 */
2988 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */
2989 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */
2990
2991 /*
2992 * Bit usage when in AArch32 state, for A-profile only.
2993 */
2994 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */
2995 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */
2996 /*
2997 * We store the bottom two bits of the CPAR as TB flags and handle
2998 * checks on the other bits at runtime. This shares the same bits as
2999 * VECSTRIDE, which is OK as no XScale CPU has VFP.
3000 * Not cached, because VECLEN+VECSTRIDE are not cached.
3001 */
3002 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2)
3003 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */
3004 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */
3005 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
3006 /*
3007 * Indicates whether cp register reads and writes by guest code should access
3008 * the secure or nonsecure bank of banked registers; note that this is not
3009 * the same thing as the current security state of the processor!
3010 */
3011 FIELD(TBFLAG_A32, NS, 10, 1)
3012 /*
3013 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not.
3014 * This requires an SME trap from AArch32 mode when using NEON.
3015 */
3016 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1)
3017
3018 /*
3019 * Bit usage when in AArch32 state, for M-profile only.
3020 */
3021 /* Handler (ie not Thread) mode */
3022 FIELD(TBFLAG_M32, HANDLER, 0, 1)
3023 /* Whether we should generate stack-limit checks */
3024 FIELD(TBFLAG_M32, STACKCHECK, 1, 1)
3025 /* Set if FPCCR.LSPACT is set */
3026 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */
3027 /* Set if we must create a new FP context */
3028 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */
3029 /* Set if FPCCR.S does not match current security state */
3030 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */
3031 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */
3032 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */
3033 /* Set if in secure mode */
3034 FIELD(TBFLAG_M32, SECURE, 6, 1)
3035
3036 /*
3037 * Bit usage when in AArch64 state
3038 */
3039 FIELD(TBFLAG_A64, TBII, 0, 2)
3040 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3041 /* The current vector length, either NVL or SVL. */
3042 FIELD(TBFLAG_A64, VL, 4, 4)
3043 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3044 FIELD(TBFLAG_A64, BT, 9, 1)
3045 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */
3046 FIELD(TBFLAG_A64, TBID, 12, 2)
3047 FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3048 FIELD(TBFLAG_A64, ATA, 15, 1)
3049 FIELD(TBFLAG_A64, TCMA, 16, 2)
3050 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3051 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
3052 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
3053 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
3054 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
3055 FIELD(TBFLAG_A64, SVL, 24, 4)
3056 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */
3057 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
3058 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1)
3059 FIELD(TBFLAG_A64, NAA, 30, 1)
3060 FIELD(TBFLAG_A64, ATA0, 31, 1)
3061 FIELD(TBFLAG_A64, NV, 32, 1)
3062 FIELD(TBFLAG_A64, NV1, 33, 1)
3063 FIELD(TBFLAG_A64, NV2, 34, 1)
3064 /* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */
3065 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1)
3066 /* Set if FEAT_NV2 RAM accesses are big-endian */
3067 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1)
3068 FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */
3069 FIELD(TBFLAG_A64, NEP, 38, 1) /* FPCR.NEP */
3070
3071 /*
3072 * Helpers for using the above. Note that only the A64 accessors use
3073 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags
3074 * word either is or might be 32 bits only.
3075 */
3076 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \
3077 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
3078 #define DP_TBFLAG_A64(DST, WHICH, VAL) \
3079 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL))
3080 #define DP_TBFLAG_A32(DST, WHICH, VAL) \
3081 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL))
3082 #define DP_TBFLAG_M32(DST, WHICH, VAL) \
3083 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL))
3084 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \
3085 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
3086
3087 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH)
3088 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH)
3089 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH)
3090 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
3091 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
3092
3093 /**
3094 * sve_vq
3095 * @env: the cpu context
3096 *
3097 * Return the VL cached within env->hflags, in units of quadwords.
3098 */
sve_vq(CPUARMState * env)3099 static inline int sve_vq(CPUARMState *env)
3100 {
3101 return EX_TBFLAG_A64(env->hflags, VL) + 1;
3102 }
3103
3104 /**
3105 * sme_vq
3106 * @env: the cpu context
3107 *
3108 * Return the SVL cached within env->hflags, in units of quadwords.
3109 */
sme_vq(CPUARMState * env)3110 static inline int sme_vq(CPUARMState *env)
3111 {
3112 return EX_TBFLAG_A64(env->hflags, SVL) + 1;
3113 }
3114
bswap_code(bool sctlr_b)3115 static inline bool bswap_code(bool sctlr_b)
3116 {
3117 #ifdef CONFIG_USER_ONLY
3118 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian.
3119 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0
3120 * would also end up as a mixed-endian mode with BE code, LE data.
3121 */
3122 return TARGET_BIG_ENDIAN ^ sctlr_b;
3123 #else
3124 /* All code access in ARM is little endian, and there are no loaders
3125 * doing swaps that need to be reversed
3126 */
3127 return 0;
3128 #endif
3129 }
3130
3131 enum {
3132 QEMU_PSCI_CONDUIT_DISABLED = 0,
3133 QEMU_PSCI_CONDUIT_SMC = 1,
3134 QEMU_PSCI_CONDUIT_HVC = 2,
3135 };
3136
3137 #ifndef CONFIG_USER_ONLY
3138 /* Return the address space index to use for a memory access */
arm_asidx_from_attrs(CPUState * cs,MemTxAttrs attrs)3139 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3140 {
3141 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3142 }
3143
3144 /* Return the AddressSpace to use for a memory access
3145 * (which depends on whether the access is S or NS, and whether
3146 * the board gave us a separate AddressSpace for S accesses).
3147 */
arm_addressspace(CPUState * cs,MemTxAttrs attrs)3148 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3149 {
3150 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3151 }
3152 #endif
3153
3154 /**
3155 * arm_register_pre_el_change_hook:
3156 * Register a hook function which will be called immediately before this
3157 * CPU changes exception level or mode. The hook function will be
3158 * passed a pointer to the ARMCPU and the opaque data pointer passed
3159 * to this function when the hook was registered.
3160 *
3161 * Note that if a pre-change hook is called, any registered post-change hooks
3162 * are guaranteed to subsequently be called.
3163 */
3164 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3165 void *opaque);
3166 /**
3167 * arm_register_el_change_hook:
3168 * Register a hook function which will be called immediately after this
3169 * CPU changes exception level or mode. The hook function will be
3170 * passed a pointer to the ARMCPU and the opaque data pointer passed
3171 * to this function when the hook was registered.
3172 *
3173 * Note that any registered hooks registered here are guaranteed to be called
3174 * if pre-change hooks have been.
3175 */
3176 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3177 *opaque);
3178
3179 /**
3180 * arm_rebuild_hflags:
3181 * Rebuild the cached TBFLAGS for arbitrary changed processor state.
3182 */
3183 void arm_rebuild_hflags(CPUARMState *env);
3184
3185 /**
3186 * aa32_vfp_dreg:
3187 * Return a pointer to the Dn register within env in 32-bit mode.
3188 */
aa32_vfp_dreg(CPUARMState * env,unsigned regno)3189 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3190 {
3191 return &env->vfp.zregs[regno >> 1].d[regno & 1];
3192 }
3193
3194 /**
3195 * aa32_vfp_qreg:
3196 * Return a pointer to the Qn register within env in 32-bit mode.
3197 */
aa32_vfp_qreg(CPUARMState * env,unsigned regno)3198 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3199 {
3200 return &env->vfp.zregs[regno].d[0];
3201 }
3202
3203 /**
3204 * aa64_vfp_qreg:
3205 * Return a pointer to the Qn register within env in 64-bit mode.
3206 */
aa64_vfp_qreg(CPUARMState * env,unsigned regno)3207 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3208 {
3209 return &env->vfp.zregs[regno].d[0];
3210 }
3211
3212 /* Shared between translate-sve.c and sve_helper.c. */
3213 extern const uint64_t pred_esz_masks[5];
3214
3215 /*
3216 * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
3217 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect
3218 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR.
3219 */
3220 #define PAGE_BTI PAGE_TARGET_1
3221 #define PAGE_MTE PAGE_TARGET_2
3222 #define PAGE_TARGET_STICKY PAGE_MTE
3223
3224 /* We associate one allocation tag per 16 bytes, the minimum. */
3225 #define LOG2_TAG_GRANULE 4
3226 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE)
3227
3228 #endif
3229