1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2025 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include "amdgpu_ras_mgr.h"
26 #include "amdgpu_ras_nbio_v7_9.h"
27 #include "nbio/nbio_7_9_0_offset.h"
28 #include "nbio/nbio_7_9_0_sh_mask.h"
29 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
30
nbio_v7_9_set_ras_controller_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)31 static int nbio_v7_9_set_ras_controller_irq_state(struct amdgpu_device *adev,
32 struct amdgpu_irq_src *src,
33 unsigned int type,
34 enum amdgpu_interrupt_state state)
35 {
36 /* Dummy function, there is no initialization operation in driver */
37
38 return 0;
39 }
40
nbio_v7_9_process_ras_controller_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)41 static int nbio_v7_9_process_ras_controller_irq(struct amdgpu_device *adev,
42 struct amdgpu_irq_src *source,
43 struct amdgpu_iv_entry *entry)
44 {
45 /* By design, the ih cookie for ras_controller_irq should be written
46 * to BIFring instead of general iv ring. However, due to known bif ring
47 * hw bug, it has to be disabled. There is no chance the process function
48 * will be involked. Just left it as a dummy one.
49 */
50 return 0;
51 }
52
nbio_v7_9_set_ras_err_event_athub_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)53 static int nbio_v7_9_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
54 struct amdgpu_irq_src *src,
55 unsigned int type,
56 enum amdgpu_interrupt_state state)
57 {
58 /* Dummy function, there is no initialization operation in driver */
59
60 return 0;
61 }
62
nbio_v7_9_process_err_event_athub_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)63 static int nbio_v7_9_process_err_event_athub_irq(struct amdgpu_device *adev,
64 struct amdgpu_irq_src *source,
65 struct amdgpu_iv_entry *entry)
66 {
67 /* By design, the ih cookie for err_event_athub_irq should be written
68 * to BIFring instead of general iv ring. However, due to known bif ring
69 * hw bug, it has to be disabled. There is no chance the process function
70 * will be involked. Just left it as a dummy one.
71 */
72 return 0;
73 }
74
75 static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_controller_irq_funcs = {
76 .set = nbio_v7_9_set_ras_controller_irq_state,
77 .process = nbio_v7_9_process_ras_controller_irq,
78 };
79
80 static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_err_event_athub_irq_funcs = {
81 .set = nbio_v7_9_set_ras_err_event_athub_irq_state,
82 .process = nbio_v7_9_process_err_event_athub_irq,
83 };
84
nbio_v7_9_init_ras_controller_interrupt(struct ras_core_context * ras_core,bool state)85 static int nbio_v7_9_init_ras_controller_interrupt(struct ras_core_context *ras_core, bool state)
86 {
87 struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
88 int r;
89
90 /* init the irq funcs */
91 adev->nbio.ras_controller_irq.funcs =
92 &nbio_v7_9_ras_controller_irq_funcs;
93 adev->nbio.ras_controller_irq.num_types = 1;
94
95 /* register ras controller interrupt */
96 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
97 NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
98 &adev->nbio.ras_controller_irq);
99
100 return r;
101 }
102
nbio_v7_9_init_ras_err_event_athub_interrupt(struct ras_core_context * ras_core,bool state)103 static int nbio_v7_9_init_ras_err_event_athub_interrupt(struct ras_core_context *ras_core,
104 bool state)
105 {
106 struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
107 int r;
108
109 /* init the irq funcs */
110 adev->nbio.ras_err_event_athub_irq.funcs =
111 &nbio_v7_9_ras_err_event_athub_irq_funcs;
112 adev->nbio.ras_err_event_athub_irq.num_types = 1;
113
114 /* register ras err event athub interrupt */
115 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
116 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
117 &adev->nbio.ras_err_event_athub_irq);
118
119 return r;
120 }
121
122 const struct ras_nbio_sys_func amdgpu_ras_nbio_sys_func_v7_9 = {
123 .set_ras_controller_irq_state = nbio_v7_9_init_ras_controller_interrupt,
124 .set_ras_err_event_athub_irq_state = nbio_v7_9_init_ras_err_event_athub_interrupt,
125 };
126