1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Rafał Miłecki <zajec5@gmail.com>
23 * Alex Deucher <alexdeucher@gmail.com>
24 */
25
26 #include "amdgpu.h"
27 #include "amdgpu_drv.h"
28 #include "amdgpu_pm.h"
29 #include "amdgpu_dpm.h"
30 #include "atom.h"
31 #include <linux/pci.h>
32 #include <linux/hwmon.h>
33 #include <linux/hwmon-sysfs.h>
34 #include <linux/nospec.h>
35 #include <linux/pm_runtime.h>
36 #include <asm/processor.h>
37
38 #define MAX_NUM_OF_FEATURES_PER_SUBSET 8
39 #define MAX_NUM_OF_SUBSETS 8
40
41 #define DEVICE_ATTR_IS(_name) (attr_id == device_attr_id__##_name)
42
43 struct od_attribute {
44 struct kobj_attribute attribute;
45 struct list_head entry;
46 };
47
48 struct od_kobj {
49 struct kobject kobj;
50 struct list_head entry;
51 struct list_head attribute;
52 void *priv;
53 };
54
55 struct od_feature_ops {
56 umode_t (*is_visible)(struct amdgpu_device *adev);
57 ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
58 char *buf);
59 ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr,
60 const char *buf, size_t count);
61 };
62
63 struct od_feature_item {
64 const char *name;
65 struct od_feature_ops ops;
66 };
67
68 struct od_feature_container {
69 char *name;
70 struct od_feature_ops ops;
71 struct od_feature_item sub_feature[MAX_NUM_OF_FEATURES_PER_SUBSET];
72 };
73
74 struct od_feature_set {
75 struct od_feature_container containers[MAX_NUM_OF_SUBSETS];
76 };
77
78 static const struct hwmon_temp_label {
79 enum PP_HWMON_TEMP channel;
80 const char *label;
81 } temp_label[] = {
82 {PP_TEMP_EDGE, "edge"},
83 {PP_TEMP_JUNCTION, "junction"},
84 {PP_TEMP_MEM, "mem"},
85 };
86
87 const char * const amdgpu_pp_profile_name[] = {
88 "BOOTUP_DEFAULT",
89 "3D_FULL_SCREEN",
90 "POWER_SAVING",
91 "VIDEO",
92 "VR",
93 "COMPUTE",
94 "CUSTOM",
95 "WINDOW_3D",
96 "CAPPED",
97 "UNCAPPED",
98 };
99
100 /**
101 * amdgpu_pm_dev_state_check - Check if device can be accessed.
102 * @adev: Target device.
103 * @runpm: Check runpm status for suspend state checks.
104 *
105 * Checks the state of the @adev for access. Return 0 if the device is
106 * accessible or a negative error code otherwise.
107 */
amdgpu_pm_dev_state_check(struct amdgpu_device * adev,bool runpm)108 static int amdgpu_pm_dev_state_check(struct amdgpu_device *adev, bool runpm)
109 {
110 bool runpm_check = runpm ? adev->in_runpm : false;
111
112 if (amdgpu_in_reset(adev))
113 return -EPERM;
114 if (adev->in_suspend && !runpm_check)
115 return -EPERM;
116
117 return 0;
118 }
119
120 /**
121 * amdgpu_pm_get_access - Check if device can be accessed, resume if needed.
122 * @adev: Target device.
123 *
124 * Checks the state of the @adev for access. Use runtime pm API to resume if
125 * needed. Return 0 if the device is accessible or a negative error code
126 * otherwise.
127 */
amdgpu_pm_get_access(struct amdgpu_device * adev)128 static int amdgpu_pm_get_access(struct amdgpu_device *adev)
129 {
130 int ret;
131
132 ret = amdgpu_pm_dev_state_check(adev, true);
133 if (ret)
134 return ret;
135
136 return pm_runtime_resume_and_get(adev->dev);
137 }
138
139 /**
140 * amdgpu_pm_get_access_if_active - Check if device is active for access.
141 * @adev: Target device.
142 *
143 * Checks the state of the @adev for access. Use runtime pm API to determine
144 * if device is active. Allow access only if device is active.Return 0 if the
145 * device is accessible or a negative error code otherwise.
146 */
amdgpu_pm_get_access_if_active(struct amdgpu_device * adev)147 static int amdgpu_pm_get_access_if_active(struct amdgpu_device *adev)
148 {
149 int ret;
150
151 /* Ignore runpm status. If device is in suspended state, deny access */
152 ret = amdgpu_pm_dev_state_check(adev, false);
153 if (ret)
154 return ret;
155
156 /*
157 * Allow only if device is active. If runpm is disabled also, as in
158 * kernels without CONFIG_PM, allow access.
159 */
160 ret = pm_runtime_get_if_active(adev->dev);
161 if (!ret)
162 return -EPERM;
163
164 return 0;
165 }
166
167 /**
168 * amdgpu_pm_put_access - Put to auto suspend mode after a device access.
169 * @adev: Target device.
170 *
171 * Should be paired with amdgpu_pm_get_access* calls
172 */
amdgpu_pm_put_access(struct amdgpu_device * adev)173 static inline void amdgpu_pm_put_access(struct amdgpu_device *adev)
174 {
175 pm_runtime_mark_last_busy(adev->dev);
176 pm_runtime_put_autosuspend(adev->dev);
177 }
178
179 /**
180 * DOC: power_dpm_state
181 *
182 * The power_dpm_state file is a legacy interface and is only provided for
183 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
184 * certain power related parameters. The file power_dpm_state is used for this.
185 * It accepts the following arguments:
186 *
187 * - battery
188 *
189 * - balanced
190 *
191 * - performance
192 *
193 * battery
194 *
195 * On older GPUs, the vbios provided a special power state for battery
196 * operation. Selecting battery switched to this state. This is no
197 * longer provided on newer GPUs so the option does nothing in that case.
198 *
199 * balanced
200 *
201 * On older GPUs, the vbios provided a special power state for balanced
202 * operation. Selecting balanced switched to this state. This is no
203 * longer provided on newer GPUs so the option does nothing in that case.
204 *
205 * performance
206 *
207 * On older GPUs, the vbios provided a special power state for performance
208 * operation. Selecting performance switched to this state. This is no
209 * longer provided on newer GPUs so the option does nothing in that case.
210 *
211 */
212
amdgpu_get_power_dpm_state(struct device * dev,struct device_attribute * attr,char * buf)213 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
214 struct device_attribute *attr,
215 char *buf)
216 {
217 struct drm_device *ddev = dev_get_drvdata(dev);
218 struct amdgpu_device *adev = drm_to_adev(ddev);
219 enum amd_pm_state_type pm;
220 int ret;
221
222 ret = amdgpu_pm_get_access_if_active(adev);
223 if (ret)
224 return ret;
225
226 amdgpu_dpm_get_current_power_state(adev, &pm);
227
228 amdgpu_pm_put_access(adev);
229
230 return sysfs_emit(buf, "%s\n",
231 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
232 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
233 }
234
amdgpu_set_power_dpm_state(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)235 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
236 struct device_attribute *attr,
237 const char *buf,
238 size_t count)
239 {
240 struct drm_device *ddev = dev_get_drvdata(dev);
241 struct amdgpu_device *adev = drm_to_adev(ddev);
242 enum amd_pm_state_type state;
243 int ret;
244
245 if (strncmp("battery", buf, strlen("battery")) == 0)
246 state = POWER_STATE_TYPE_BATTERY;
247 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
248 state = POWER_STATE_TYPE_BALANCED;
249 else if (strncmp("performance", buf, strlen("performance")) == 0)
250 state = POWER_STATE_TYPE_PERFORMANCE;
251 else
252 return -EINVAL;
253
254 ret = amdgpu_pm_get_access(adev);
255 if (ret < 0)
256 return ret;
257
258 amdgpu_dpm_set_power_state(adev, state);
259
260 amdgpu_pm_put_access(adev);
261
262 return count;
263 }
264
265
266 /**
267 * DOC: power_dpm_force_performance_level
268 *
269 * The amdgpu driver provides a sysfs API for adjusting certain power
270 * related parameters. The file power_dpm_force_performance_level is
271 * used for this. It accepts the following arguments:
272 *
273 * - auto
274 *
275 * - low
276 *
277 * - high
278 *
279 * - manual
280 *
281 * - profile_standard
282 *
283 * - profile_min_sclk
284 *
285 * - profile_min_mclk
286 *
287 * - profile_peak
288 *
289 * auto
290 *
291 * When auto is selected, the driver will attempt to dynamically select
292 * the optimal power profile for current conditions in the driver.
293 *
294 * low
295 *
296 * When low is selected, the clocks are forced to the lowest power state.
297 *
298 * high
299 *
300 * When high is selected, the clocks are forced to the highest power state.
301 *
302 * manual
303 *
304 * When manual is selected, the user can manually adjust which power states
305 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
306 * and pp_dpm_pcie files and adjust the power state transition heuristics
307 * via the pp_power_profile_mode sysfs file.
308 *
309 * profile_standard
310 * profile_min_sclk
311 * profile_min_mclk
312 * profile_peak
313 *
314 * When the profiling modes are selected, clock and power gating are
315 * disabled and the clocks are set for different profiling cases. This
316 * mode is recommended for profiling specific work loads where you do
317 * not want clock or power gating for clock fluctuation to interfere
318 * with your results. profile_standard sets the clocks to a fixed clock
319 * level which varies from asic to asic. profile_min_sclk forces the sclk
320 * to the lowest level. profile_min_mclk forces the mclk to the lowest level.
321 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
322 *
323 */
324
amdgpu_get_power_dpm_force_performance_level(struct device * dev,struct device_attribute * attr,char * buf)325 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
326 struct device_attribute *attr,
327 char *buf)
328 {
329 struct drm_device *ddev = dev_get_drvdata(dev);
330 struct amdgpu_device *adev = drm_to_adev(ddev);
331 enum amd_dpm_forced_level level = 0xff;
332 int ret;
333
334 ret = amdgpu_pm_get_access_if_active(adev);
335 if (ret)
336 return ret;
337
338 level = amdgpu_dpm_get_performance_level(adev);
339
340 amdgpu_pm_put_access(adev);
341
342 return sysfs_emit(buf, "%s\n",
343 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
344 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
345 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
346 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
347 (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
348 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
349 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
350 (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
351 (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
352 "unknown");
353 }
354
amdgpu_set_power_dpm_force_performance_level(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)355 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
356 struct device_attribute *attr,
357 const char *buf,
358 size_t count)
359 {
360 struct drm_device *ddev = dev_get_drvdata(dev);
361 struct amdgpu_device *adev = drm_to_adev(ddev);
362 enum amd_dpm_forced_level level;
363 int ret = 0;
364
365 if (strncmp("low", buf, strlen("low")) == 0) {
366 level = AMD_DPM_FORCED_LEVEL_LOW;
367 } else if (strncmp("high", buf, strlen("high")) == 0) {
368 level = AMD_DPM_FORCED_LEVEL_HIGH;
369 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
370 level = AMD_DPM_FORCED_LEVEL_AUTO;
371 } else if (strncmp("manual", buf, strlen("manual")) == 0) {
372 level = AMD_DPM_FORCED_LEVEL_MANUAL;
373 } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
374 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
375 } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
376 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
377 } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
378 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
379 } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
380 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
381 } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
382 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
383 } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
384 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
385 } else {
386 return -EINVAL;
387 }
388
389 ret = amdgpu_pm_get_access(adev);
390 if (ret < 0)
391 return ret;
392
393 mutex_lock(&adev->pm.stable_pstate_ctx_lock);
394 if (amdgpu_dpm_force_performance_level(adev, level)) {
395 amdgpu_pm_put_access(adev);
396 mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
397 return -EINVAL;
398 }
399 /* override whatever a user ctx may have set */
400 adev->pm.stable_pstate_ctx = NULL;
401 mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
402
403 amdgpu_pm_put_access(adev);
404
405 return count;
406 }
407
amdgpu_get_pp_num_states(struct device * dev,struct device_attribute * attr,char * buf)408 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
409 struct device_attribute *attr,
410 char *buf)
411 {
412 struct drm_device *ddev = dev_get_drvdata(dev);
413 struct amdgpu_device *adev = drm_to_adev(ddev);
414 struct pp_states_info data;
415 uint32_t i;
416 int buf_len, ret;
417
418 ret = amdgpu_pm_get_access_if_active(adev);
419 if (ret)
420 return ret;
421
422 if (amdgpu_dpm_get_pp_num_states(adev, &data))
423 memset(&data, 0, sizeof(data));
424
425 amdgpu_pm_put_access(adev);
426
427 buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
428 for (i = 0; i < data.nums; i++)
429 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
430 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
431 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
432 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
433 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
434
435 return buf_len;
436 }
437
amdgpu_get_pp_cur_state(struct device * dev,struct device_attribute * attr,char * buf)438 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
439 struct device_attribute *attr,
440 char *buf)
441 {
442 struct drm_device *ddev = dev_get_drvdata(dev);
443 struct amdgpu_device *adev = drm_to_adev(ddev);
444 struct pp_states_info data = {0};
445 enum amd_pm_state_type pm = 0;
446 int i = 0, ret = 0;
447
448 ret = amdgpu_pm_get_access_if_active(adev);
449 if (ret)
450 return ret;
451
452 amdgpu_dpm_get_current_power_state(adev, &pm);
453
454 ret = amdgpu_dpm_get_pp_num_states(adev, &data);
455
456 amdgpu_pm_put_access(adev);
457
458 if (ret)
459 return ret;
460
461 for (i = 0; i < data.nums; i++) {
462 if (pm == data.states[i])
463 break;
464 }
465
466 if (i == data.nums)
467 i = -EINVAL;
468
469 return sysfs_emit(buf, "%d\n", i);
470 }
471
amdgpu_get_pp_force_state(struct device * dev,struct device_attribute * attr,char * buf)472 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
473 struct device_attribute *attr,
474 char *buf)
475 {
476 struct drm_device *ddev = dev_get_drvdata(dev);
477 struct amdgpu_device *adev = drm_to_adev(ddev);
478
479 if (adev->pm.pp_force_state_enabled)
480 return amdgpu_get_pp_cur_state(dev, attr, buf);
481 else
482 return sysfs_emit(buf, "\n");
483 }
484
amdgpu_set_pp_force_state(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)485 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
486 struct device_attribute *attr,
487 const char *buf,
488 size_t count)
489 {
490 struct drm_device *ddev = dev_get_drvdata(dev);
491 struct amdgpu_device *adev = drm_to_adev(ddev);
492 enum amd_pm_state_type state = 0;
493 struct pp_states_info data;
494 unsigned long idx;
495 int ret;
496
497 adev->pm.pp_force_state_enabled = false;
498
499 if (strlen(buf) == 1)
500 return count;
501
502 ret = kstrtoul(buf, 0, &idx);
503 if (ret || idx >= ARRAY_SIZE(data.states))
504 return -EINVAL;
505
506 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
507
508 ret = amdgpu_pm_get_access(adev);
509 if (ret < 0)
510 return ret;
511
512 ret = amdgpu_dpm_get_pp_num_states(adev, &data);
513 if (ret)
514 goto err_out;
515
516 state = data.states[idx];
517
518 /* only set user selected power states */
519 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
520 state != POWER_STATE_TYPE_DEFAULT) {
521 ret = amdgpu_dpm_dispatch_task(adev,
522 AMD_PP_TASK_ENABLE_USER_STATE, &state);
523 if (ret)
524 goto err_out;
525
526 adev->pm.pp_force_state_enabled = true;
527 }
528
529 amdgpu_pm_put_access(adev);
530
531 return count;
532
533 err_out:
534 amdgpu_pm_put_access(adev);
535
536 return ret;
537 }
538
539 /**
540 * DOC: pp_table
541 *
542 * The amdgpu driver provides a sysfs API for uploading new powerplay
543 * tables. The file pp_table is used for this. Reading the file
544 * will dump the current power play table. Writing to the file
545 * will attempt to upload a new powerplay table and re-initialize
546 * powerplay using that new table.
547 *
548 */
549
amdgpu_get_pp_table(struct device * dev,struct device_attribute * attr,char * buf)550 static ssize_t amdgpu_get_pp_table(struct device *dev,
551 struct device_attribute *attr,
552 char *buf)
553 {
554 struct drm_device *ddev = dev_get_drvdata(dev);
555 struct amdgpu_device *adev = drm_to_adev(ddev);
556 char *table = NULL;
557 int size, ret;
558
559 ret = amdgpu_pm_get_access_if_active(adev);
560 if (ret)
561 return ret;
562
563 size = amdgpu_dpm_get_pp_table(adev, &table);
564
565 amdgpu_pm_put_access(adev);
566
567 if (size <= 0)
568 return size;
569
570 if (size >= PAGE_SIZE)
571 size = PAGE_SIZE - 1;
572
573 memcpy(buf, table, size);
574
575 return size;
576 }
577
amdgpu_set_pp_table(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)578 static ssize_t amdgpu_set_pp_table(struct device *dev,
579 struct device_attribute *attr,
580 const char *buf,
581 size_t count)
582 {
583 struct drm_device *ddev = dev_get_drvdata(dev);
584 struct amdgpu_device *adev = drm_to_adev(ddev);
585 int ret = 0;
586
587 ret = amdgpu_pm_get_access(adev);
588 if (ret < 0)
589 return ret;
590
591 ret = amdgpu_dpm_set_pp_table(adev, buf, count);
592
593 amdgpu_pm_put_access(adev);
594
595 if (ret)
596 return ret;
597
598 return count;
599 }
600
601 /**
602 * DOC: pp_od_clk_voltage
603 *
604 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
605 * in each power level within a power state. The pp_od_clk_voltage is used for
606 * this.
607 *
608 * Note that the actual memory controller clock rate are exposed, not
609 * the effective memory clock of the DRAMs. To translate it, use the
610 * following formula:
611 *
612 * Clock conversion (Mhz):
613 *
614 * HBM: effective_memory_clock = memory_controller_clock * 1
615 *
616 * G5: effective_memory_clock = memory_controller_clock * 1
617 *
618 * G6: effective_memory_clock = memory_controller_clock * 2
619 *
620 * DRAM data rate (MT/s):
621 *
622 * HBM: effective_memory_clock * 2 = data_rate
623 *
624 * G5: effective_memory_clock * 4 = data_rate
625 *
626 * G6: effective_memory_clock * 8 = data_rate
627 *
628 * Bandwidth (MB/s):
629 *
630 * data_rate * vram_bit_width / 8 = memory_bandwidth
631 *
632 * Some examples:
633 *
634 * G5 on RX460:
635 *
636 * memory_controller_clock = 1750 Mhz
637 *
638 * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
639 *
640 * data rate = 1750 * 4 = 7000 MT/s
641 *
642 * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
643 *
644 * G6 on RX5700:
645 *
646 * memory_controller_clock = 875 Mhz
647 *
648 * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
649 *
650 * data rate = 1750 * 8 = 14000 MT/s
651 *
652 * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
653 *
654 * < For Vega10 and previous ASICs >
655 *
656 * Reading the file will display:
657 *
658 * - a list of engine clock levels and voltages labeled OD_SCLK
659 *
660 * - a list of memory clock levels and voltages labeled OD_MCLK
661 *
662 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
663 *
664 * To manually adjust these settings, first select manual using
665 * power_dpm_force_performance_level. Enter a new value for each
666 * level by writing a string that contains "s/m level clock voltage" to
667 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
668 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
669 * 810 mV. When you have edited all of the states as needed, write
670 * "c" (commit) to the file to commit your changes. If you want to reset to the
671 * default power levels, write "r" (reset) to the file to reset them.
672 *
673 *
674 * < For Vega20 and newer ASICs >
675 *
676 * Reading the file will display:
677 *
678 * - minimum and maximum engine clock labeled OD_SCLK
679 *
680 * - minimum(not available for Vega20 and Navi1x) and maximum memory
681 * clock labeled OD_MCLK
682 *
683 * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
684 * They can be used to calibrate the sclk voltage curve. This is
685 * available for Vega20 and NV1X.
686 *
687 * - voltage offset(in mV) applied on target voltage calculation.
688 * This is available for Sienna Cichlid, Navy Flounder, Dimgrey
689 * Cavefish and some later SMU13 ASICs. For these ASICs, the target
690 * voltage calculation can be illustrated by "voltage = voltage
691 * calculated from v/f curve + overdrive vddgfx offset"
692 *
693 * - a list of valid ranges for sclk, mclk, voltage curve points
694 * or voltage offset labeled OD_RANGE
695 *
696 * < For APUs >
697 *
698 * Reading the file will display:
699 *
700 * - minimum and maximum engine clock labeled OD_SCLK
701 *
702 * - a list of valid ranges for sclk labeled OD_RANGE
703 *
704 * < For VanGogh >
705 *
706 * Reading the file will display:
707 *
708 * - minimum and maximum engine clock labeled OD_SCLK
709 * - minimum and maximum core clocks labeled OD_CCLK
710 *
711 * - a list of valid ranges for sclk and cclk labeled OD_RANGE
712 *
713 * To manually adjust these settings:
714 *
715 * - First select manual using power_dpm_force_performance_level
716 *
717 * - For clock frequency setting, enter a new value by writing a
718 * string that contains "s/m index clock" to the file. The index
719 * should be 0 if to set minimum clock. And 1 if to set maximum
720 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
721 * "m 1 800" will update maximum mclk to be 800Mhz. For core
722 * clocks on VanGogh, the string contains "p core index clock".
723 * E.g., "p 2 0 800" would set the minimum core clock on core
724 * 2 to 800Mhz.
725 *
726 * For sclk voltage curve supported by Vega20 and NV1X, enter the new
727 * values by writing a string that contains "vc point clock voltage"
728 * to the file. The points are indexed by 0, 1 and 2. E.g., "vc 0 300
729 * 600" will update point1 with clock set as 300Mhz and voltage as 600mV.
730 * "vc 2 1000 1000" will update point3 with clock set as 1000Mhz and
731 * voltage 1000mV.
732 *
733 * For voltage offset supported by Sienna Cichlid, Navy Flounder, Dimgrey
734 * Cavefish and some later SMU13 ASICs, enter the new value by writing a
735 * string that contains "vo offset". E.g., "vo -10" will update the extra
736 * voltage offset applied to the whole v/f curve line as -10mv.
737 *
738 * - When you have edited all of the states as needed, write "c" (commit)
739 * to the file to commit your changes
740 *
741 * - If you want to reset to the default power levels, write "r" (reset)
742 * to the file to reset them
743 *
744 */
745
amdgpu_set_pp_od_clk_voltage(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)746 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
747 struct device_attribute *attr,
748 const char *buf,
749 size_t count)
750 {
751 struct drm_device *ddev = dev_get_drvdata(dev);
752 struct amdgpu_device *adev = drm_to_adev(ddev);
753 int ret;
754 uint32_t parameter_size = 0;
755 long parameter[64];
756 char buf_cpy[128];
757 char *tmp_str;
758 char *sub_str;
759 const char delimiter[3] = {' ', '\n', '\0'};
760 uint32_t type;
761
762 if (count > 127 || count == 0)
763 return -EINVAL;
764
765 if (*buf == 's')
766 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
767 else if (*buf == 'p')
768 type = PP_OD_EDIT_CCLK_VDDC_TABLE;
769 else if (*buf == 'm')
770 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
771 else if (*buf == 'r')
772 type = PP_OD_RESTORE_DEFAULT_TABLE;
773 else if (*buf == 'c')
774 type = PP_OD_COMMIT_DPM_TABLE;
775 else if (!strncmp(buf, "vc", 2))
776 type = PP_OD_EDIT_VDDC_CURVE;
777 else if (!strncmp(buf, "vo", 2))
778 type = PP_OD_EDIT_VDDGFX_OFFSET;
779 else
780 return -EINVAL;
781
782 memcpy(buf_cpy, buf, count);
783 buf_cpy[count] = 0;
784
785 tmp_str = buf_cpy;
786
787 if ((type == PP_OD_EDIT_VDDC_CURVE) ||
788 (type == PP_OD_EDIT_VDDGFX_OFFSET))
789 tmp_str++;
790 while (isspace(*++tmp_str));
791
792 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
793 if (strlen(sub_str) == 0)
794 continue;
795 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
796 if (ret)
797 return -EINVAL;
798 parameter_size++;
799
800 if (!tmp_str)
801 break;
802
803 while (isspace(*tmp_str))
804 tmp_str++;
805 }
806
807 ret = amdgpu_pm_get_access(adev);
808 if (ret < 0)
809 return ret;
810
811 if (amdgpu_dpm_set_fine_grain_clk_vol(adev,
812 type,
813 parameter,
814 parameter_size))
815 goto err_out;
816
817 if (amdgpu_dpm_odn_edit_dpm_table(adev, type,
818 parameter, parameter_size))
819 goto err_out;
820
821 if (type == PP_OD_COMMIT_DPM_TABLE) {
822 if (amdgpu_dpm_dispatch_task(adev,
823 AMD_PP_TASK_READJUST_POWER_STATE,
824 NULL))
825 goto err_out;
826 }
827
828 amdgpu_pm_put_access(adev);
829
830 return count;
831
832 err_out:
833 amdgpu_pm_put_access(adev);
834
835 return -EINVAL;
836 }
837
amdgpu_get_pp_od_clk_voltage(struct device * dev,struct device_attribute * attr,char * buf)838 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
839 struct device_attribute *attr,
840 char *buf)
841 {
842 struct drm_device *ddev = dev_get_drvdata(dev);
843 struct amdgpu_device *adev = drm_to_adev(ddev);
844 int size = 0;
845 int ret;
846 enum pp_clock_type od_clocks[6] = {
847 OD_SCLK,
848 OD_MCLK,
849 OD_VDDC_CURVE,
850 OD_RANGE,
851 OD_VDDGFX_OFFSET,
852 OD_CCLK,
853 };
854 uint clk_index;
855
856 ret = amdgpu_pm_get_access_if_active(adev);
857 if (ret)
858 return ret;
859
860 for (clk_index = 0 ; clk_index < 6 ; clk_index++) {
861 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size);
862 if (ret)
863 break;
864 }
865 if (ret == -ENOENT) {
866 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
867 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
868 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
869 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
870 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
871 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
872 }
873
874 if (size == 0)
875 size = sysfs_emit(buf, "\n");
876
877 amdgpu_pm_put_access(adev);
878
879 return size;
880 }
881
882 /**
883 * DOC: pp_features
884 *
885 * The amdgpu driver provides a sysfs API for adjusting what powerplay
886 * features to be enabled. The file pp_features is used for this. And
887 * this is only available for Vega10 and later dGPUs.
888 *
889 * Reading back the file will show you the followings:
890 * - Current ppfeature masks
891 * - List of the all supported powerplay features with their naming,
892 * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
893 *
894 * To manually enable or disable a specific feature, just set or clear
895 * the corresponding bit from original ppfeature masks and input the
896 * new ppfeature masks.
897 */
amdgpu_set_pp_features(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)898 static ssize_t amdgpu_set_pp_features(struct device *dev,
899 struct device_attribute *attr,
900 const char *buf,
901 size_t count)
902 {
903 struct drm_device *ddev = dev_get_drvdata(dev);
904 struct amdgpu_device *adev = drm_to_adev(ddev);
905 uint64_t featuremask;
906 int ret;
907
908 ret = kstrtou64(buf, 0, &featuremask);
909 if (ret)
910 return -EINVAL;
911
912 ret = amdgpu_pm_get_access(adev);
913 if (ret < 0)
914 return ret;
915
916 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
917
918 amdgpu_pm_put_access(adev);
919
920 if (ret)
921 return -EINVAL;
922
923 return count;
924 }
925
amdgpu_get_pp_features(struct device * dev,struct device_attribute * attr,char * buf)926 static ssize_t amdgpu_get_pp_features(struct device *dev,
927 struct device_attribute *attr,
928 char *buf)
929 {
930 struct drm_device *ddev = dev_get_drvdata(dev);
931 struct amdgpu_device *adev = drm_to_adev(ddev);
932 ssize_t size;
933 int ret;
934
935 ret = amdgpu_pm_get_access_if_active(adev);
936 if (ret)
937 return ret;
938
939 size = amdgpu_dpm_get_ppfeature_status(adev, buf);
940 if (size <= 0)
941 size = sysfs_emit(buf, "\n");
942
943 amdgpu_pm_put_access(adev);
944
945 return size;
946 }
947
948 /**
949 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
950 *
951 * The amdgpu driver provides a sysfs API for adjusting what power levels
952 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk,
953 * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
954 * this.
955 *
956 * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
957 * Vega10 and later ASICs.
958 * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
959 *
960 * Reading back the files will show you the available power levels within
961 * the power state and the clock information for those levels. If deep sleep is
962 * applied to a clock, the level will be denoted by a special level 'S:'
963 * E.g., ::
964 *
965 * S: 19Mhz *
966 * 0: 615Mhz
967 * 1: 800Mhz
968 * 2: 888Mhz
969 * 3: 1000Mhz
970 *
971 *
972 * To manually adjust these states, first select manual using
973 * power_dpm_force_performance_level.
974 * Secondly, enter a new value for each level by inputing a string that
975 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
976 * E.g.,
977 *
978 * .. code-block:: bash
979 *
980 * echo "4 5 6" > pp_dpm_sclk
981 *
982 * will enable sclk levels 4, 5, and 6.
983 *
984 * NOTE: change to the dcefclk max dpm level is not supported now
985 */
986
amdgpu_get_pp_dpm_clock(struct device * dev,enum pp_clock_type type,char * buf)987 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
988 enum pp_clock_type type,
989 char *buf)
990 {
991 struct drm_device *ddev = dev_get_drvdata(dev);
992 struct amdgpu_device *adev = drm_to_adev(ddev);
993 int size = 0;
994 int ret = 0;
995
996 ret = amdgpu_pm_get_access_if_active(adev);
997 if (ret)
998 return ret;
999
1000 ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size);
1001 if (ret == -ENOENT)
1002 size = amdgpu_dpm_print_clock_levels(adev, type, buf);
1003
1004 if (size == 0)
1005 size = sysfs_emit(buf, "\n");
1006
1007 amdgpu_pm_put_access(adev);
1008
1009 return size;
1010 }
1011
1012 /*
1013 * Worst case: 32 bits individually specified, in octal at 12 characters
1014 * per line (+1 for \n).
1015 */
1016 #define AMDGPU_MASK_BUF_MAX (32 * 13)
1017
amdgpu_read_mask(const char * buf,size_t count,uint32_t * mask)1018 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1019 {
1020 int ret;
1021 unsigned long level;
1022 char *sub_str = NULL;
1023 char *tmp;
1024 char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1025 const char delimiter[3] = {' ', '\n', '\0'};
1026 size_t bytes;
1027
1028 *mask = 0;
1029
1030 bytes = min(count, sizeof(buf_cpy) - 1);
1031 memcpy(buf_cpy, buf, bytes);
1032 buf_cpy[bytes] = '\0';
1033 tmp = buf_cpy;
1034 while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1035 if (strlen(sub_str)) {
1036 ret = kstrtoul(sub_str, 0, &level);
1037 if (ret || level > 31)
1038 return -EINVAL;
1039 *mask |= 1 << level;
1040 } else
1041 break;
1042 }
1043
1044 return 0;
1045 }
1046
amdgpu_set_pp_dpm_clock(struct device * dev,enum pp_clock_type type,const char * buf,size_t count)1047 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
1048 enum pp_clock_type type,
1049 const char *buf,
1050 size_t count)
1051 {
1052 struct drm_device *ddev = dev_get_drvdata(dev);
1053 struct amdgpu_device *adev = drm_to_adev(ddev);
1054 int ret;
1055 uint32_t mask = 0;
1056
1057 ret = amdgpu_read_mask(buf, count, &mask);
1058 if (ret)
1059 return ret;
1060
1061 ret = amdgpu_pm_get_access(adev);
1062 if (ret < 0)
1063 return ret;
1064
1065 ret = amdgpu_dpm_force_clock_level(adev, type, mask);
1066
1067 amdgpu_pm_put_access(adev);
1068
1069 if (ret)
1070 return -EINVAL;
1071
1072 return count;
1073 }
1074
amdgpu_get_pp_dpm_sclk(struct device * dev,struct device_attribute * attr,char * buf)1075 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1076 struct device_attribute *attr,
1077 char *buf)
1078 {
1079 return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
1080 }
1081
amdgpu_set_pp_dpm_sclk(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1082 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1083 struct device_attribute *attr,
1084 const char *buf,
1085 size_t count)
1086 {
1087 return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
1088 }
1089
amdgpu_get_pp_dpm_mclk(struct device * dev,struct device_attribute * attr,char * buf)1090 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1091 struct device_attribute *attr,
1092 char *buf)
1093 {
1094 return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
1095 }
1096
amdgpu_set_pp_dpm_mclk(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1097 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1098 struct device_attribute *attr,
1099 const char *buf,
1100 size_t count)
1101 {
1102 return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
1103 }
1104
amdgpu_get_pp_dpm_socclk(struct device * dev,struct device_attribute * attr,char * buf)1105 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1106 struct device_attribute *attr,
1107 char *buf)
1108 {
1109 return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
1110 }
1111
amdgpu_set_pp_dpm_socclk(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1112 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1113 struct device_attribute *attr,
1114 const char *buf,
1115 size_t count)
1116 {
1117 return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
1118 }
1119
amdgpu_get_pp_dpm_fclk(struct device * dev,struct device_attribute * attr,char * buf)1120 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1121 struct device_attribute *attr,
1122 char *buf)
1123 {
1124 return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
1125 }
1126
amdgpu_set_pp_dpm_fclk(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1127 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1128 struct device_attribute *attr,
1129 const char *buf,
1130 size_t count)
1131 {
1132 return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
1133 }
1134
amdgpu_get_pp_dpm_vclk(struct device * dev,struct device_attribute * attr,char * buf)1135 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1136 struct device_attribute *attr,
1137 char *buf)
1138 {
1139 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
1140 }
1141
amdgpu_set_pp_dpm_vclk(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1142 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1143 struct device_attribute *attr,
1144 const char *buf,
1145 size_t count)
1146 {
1147 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
1148 }
1149
amdgpu_get_pp_dpm_vclk1(struct device * dev,struct device_attribute * attr,char * buf)1150 static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev,
1151 struct device_attribute *attr,
1152 char *buf)
1153 {
1154 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf);
1155 }
1156
amdgpu_set_pp_dpm_vclk1(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1157 static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev,
1158 struct device_attribute *attr,
1159 const char *buf,
1160 size_t count)
1161 {
1162 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count);
1163 }
1164
amdgpu_get_pp_dpm_dclk(struct device * dev,struct device_attribute * attr,char * buf)1165 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1166 struct device_attribute *attr,
1167 char *buf)
1168 {
1169 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
1170 }
1171
amdgpu_set_pp_dpm_dclk(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1172 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1173 struct device_attribute *attr,
1174 const char *buf,
1175 size_t count)
1176 {
1177 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
1178 }
1179
amdgpu_get_pp_dpm_dclk1(struct device * dev,struct device_attribute * attr,char * buf)1180 static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev,
1181 struct device_attribute *attr,
1182 char *buf)
1183 {
1184 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf);
1185 }
1186
amdgpu_set_pp_dpm_dclk1(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1187 static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev,
1188 struct device_attribute *attr,
1189 const char *buf,
1190 size_t count)
1191 {
1192 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count);
1193 }
1194
amdgpu_get_pp_dpm_dcefclk(struct device * dev,struct device_attribute * attr,char * buf)1195 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1196 struct device_attribute *attr,
1197 char *buf)
1198 {
1199 return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
1200 }
1201
amdgpu_set_pp_dpm_dcefclk(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1202 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1203 struct device_attribute *attr,
1204 const char *buf,
1205 size_t count)
1206 {
1207 return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
1208 }
1209
amdgpu_get_pp_dpm_pcie(struct device * dev,struct device_attribute * attr,char * buf)1210 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1211 struct device_attribute *attr,
1212 char *buf)
1213 {
1214 return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
1215 }
1216
amdgpu_set_pp_dpm_pcie(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1217 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1218 struct device_attribute *attr,
1219 const char *buf,
1220 size_t count)
1221 {
1222 return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
1223 }
1224
amdgpu_get_pp_sclk_od(struct device * dev,struct device_attribute * attr,char * buf)1225 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1226 struct device_attribute *attr,
1227 char *buf)
1228 {
1229 struct drm_device *ddev = dev_get_drvdata(dev);
1230 struct amdgpu_device *adev = drm_to_adev(ddev);
1231 uint32_t value = 0;
1232 int ret;
1233
1234 ret = amdgpu_pm_get_access_if_active(adev);
1235 if (ret)
1236 return ret;
1237
1238 value = amdgpu_dpm_get_sclk_od(adev);
1239
1240 amdgpu_pm_put_access(adev);
1241
1242 return sysfs_emit(buf, "%d\n", value);
1243 }
1244
amdgpu_set_pp_sclk_od(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1245 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1246 struct device_attribute *attr,
1247 const char *buf,
1248 size_t count)
1249 {
1250 struct drm_device *ddev = dev_get_drvdata(dev);
1251 struct amdgpu_device *adev = drm_to_adev(ddev);
1252 int ret;
1253 long int value;
1254
1255 ret = kstrtol(buf, 0, &value);
1256
1257 if (ret)
1258 return -EINVAL;
1259
1260 ret = amdgpu_pm_get_access(adev);
1261 if (ret < 0)
1262 return ret;
1263
1264 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1265
1266 amdgpu_pm_put_access(adev);
1267
1268 return count;
1269 }
1270
amdgpu_get_pp_mclk_od(struct device * dev,struct device_attribute * attr,char * buf)1271 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1272 struct device_attribute *attr,
1273 char *buf)
1274 {
1275 struct drm_device *ddev = dev_get_drvdata(dev);
1276 struct amdgpu_device *adev = drm_to_adev(ddev);
1277 uint32_t value = 0;
1278 int ret;
1279
1280 ret = amdgpu_pm_get_access_if_active(adev);
1281 if (ret)
1282 return ret;
1283
1284 value = amdgpu_dpm_get_mclk_od(adev);
1285
1286 amdgpu_pm_put_access(adev);
1287
1288 return sysfs_emit(buf, "%d\n", value);
1289 }
1290
amdgpu_set_pp_mclk_od(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1291 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1292 struct device_attribute *attr,
1293 const char *buf,
1294 size_t count)
1295 {
1296 struct drm_device *ddev = dev_get_drvdata(dev);
1297 struct amdgpu_device *adev = drm_to_adev(ddev);
1298 int ret;
1299 long int value;
1300
1301 ret = kstrtol(buf, 0, &value);
1302
1303 if (ret)
1304 return -EINVAL;
1305
1306 ret = amdgpu_pm_get_access(adev);
1307 if (ret < 0)
1308 return ret;
1309
1310 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1311
1312 amdgpu_pm_put_access(adev);
1313
1314 return count;
1315 }
1316
1317 /**
1318 * DOC: pp_power_profile_mode
1319 *
1320 * The amdgpu driver provides a sysfs API for adjusting the heuristics
1321 * related to switching between power levels in a power state. The file
1322 * pp_power_profile_mode is used for this.
1323 *
1324 * Reading this file outputs a list of all of the predefined power profiles
1325 * and the relevant heuristics settings for that profile.
1326 *
1327 * To select a profile or create a custom profile, first select manual using
1328 * power_dpm_force_performance_level. Writing the number of a predefined
1329 * profile to pp_power_profile_mode will enable those heuristics. To
1330 * create a custom set of heuristics, write a string of numbers to the file
1331 * starting with the number of the custom profile along with a setting
1332 * for each heuristic parameter. Due to differences across asic families
1333 * the heuristic parameters vary from family to family. Additionally,
1334 * you can apply the custom heuristics to different clock domains. Each
1335 * clock domain is considered a distinct operation so if you modify the
1336 * gfxclk heuristics and then the memclk heuristics, the all of the
1337 * custom heuristics will be retained until you switch to another profile.
1338 *
1339 */
1340
amdgpu_get_pp_power_profile_mode(struct device * dev,struct device_attribute * attr,char * buf)1341 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1342 struct device_attribute *attr,
1343 char *buf)
1344 {
1345 struct drm_device *ddev = dev_get_drvdata(dev);
1346 struct amdgpu_device *adev = drm_to_adev(ddev);
1347 ssize_t size;
1348 int ret;
1349
1350 ret = amdgpu_pm_get_access_if_active(adev);
1351 if (ret)
1352 return ret;
1353
1354 size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1355 if (size <= 0)
1356 size = sysfs_emit(buf, "\n");
1357
1358 amdgpu_pm_put_access(adev);
1359
1360 return size;
1361 }
1362
1363
amdgpu_set_pp_power_profile_mode(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1364 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1365 struct device_attribute *attr,
1366 const char *buf,
1367 size_t count)
1368 {
1369 int ret;
1370 struct drm_device *ddev = dev_get_drvdata(dev);
1371 struct amdgpu_device *adev = drm_to_adev(ddev);
1372 uint32_t parameter_size = 0;
1373 long parameter[64];
1374 char *sub_str, buf_cpy[128];
1375 char *tmp_str;
1376 uint32_t i = 0;
1377 char tmp[2];
1378 long int profile_mode = 0;
1379 const char delimiter[3] = {' ', '\n', '\0'};
1380
1381 tmp[0] = *(buf);
1382 tmp[1] = '\0';
1383 ret = kstrtol(tmp, 0, &profile_mode);
1384 if (ret)
1385 return -EINVAL;
1386
1387 if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1388 if (count < 2 || count > 127)
1389 return -EINVAL;
1390 while (isspace(*++buf))
1391 i++;
1392 memcpy(buf_cpy, buf, count-i);
1393 tmp_str = buf_cpy;
1394 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1395 if (strlen(sub_str) == 0)
1396 continue;
1397 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
1398 if (ret)
1399 return -EINVAL;
1400 parameter_size++;
1401 while (isspace(*tmp_str))
1402 tmp_str++;
1403 }
1404 }
1405 parameter[parameter_size] = profile_mode;
1406
1407 ret = amdgpu_pm_get_access(adev);
1408 if (ret < 0)
1409 return ret;
1410
1411 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1412
1413 amdgpu_pm_put_access(adev);
1414
1415 if (!ret)
1416 return count;
1417
1418 return -EINVAL;
1419 }
1420
amdgpu_hwmon_get_sensor_generic(struct amdgpu_device * adev,enum amd_pp_sensors sensor,void * query)1421 static int amdgpu_hwmon_get_sensor_generic(struct amdgpu_device *adev,
1422 enum amd_pp_sensors sensor,
1423 void *query)
1424 {
1425 int r, size = sizeof(uint32_t);
1426
1427 r = amdgpu_pm_get_access_if_active(adev);
1428 if (r)
1429 return r;
1430
1431 /* get the sensor value */
1432 r = amdgpu_dpm_read_sensor(adev, sensor, query, &size);
1433
1434 amdgpu_pm_put_access(adev);
1435
1436 return r;
1437 }
1438
1439 /**
1440 * DOC: gpu_busy_percent
1441 *
1442 * The amdgpu driver provides a sysfs API for reading how busy the GPU
1443 * is as a percentage. The file gpu_busy_percent is used for this.
1444 * The SMU firmware computes a percentage of load based on the
1445 * aggregate activity level in the IP cores.
1446 */
amdgpu_get_gpu_busy_percent(struct device * dev,struct device_attribute * attr,char * buf)1447 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1448 struct device_attribute *attr,
1449 char *buf)
1450 {
1451 struct drm_device *ddev = dev_get_drvdata(dev);
1452 struct amdgpu_device *adev = drm_to_adev(ddev);
1453 unsigned int value;
1454 int r;
1455
1456 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value);
1457 if (r)
1458 return r;
1459
1460 return sysfs_emit(buf, "%d\n", value);
1461 }
1462
1463 /**
1464 * DOC: mem_busy_percent
1465 *
1466 * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1467 * is as a percentage. The file mem_busy_percent is used for this.
1468 * The SMU firmware computes a percentage of load based on the
1469 * aggregate activity level in the IP cores.
1470 */
amdgpu_get_mem_busy_percent(struct device * dev,struct device_attribute * attr,char * buf)1471 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1472 struct device_attribute *attr,
1473 char *buf)
1474 {
1475 struct drm_device *ddev = dev_get_drvdata(dev);
1476 struct amdgpu_device *adev = drm_to_adev(ddev);
1477 unsigned int value;
1478 int r;
1479
1480 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value);
1481 if (r)
1482 return r;
1483
1484 return sysfs_emit(buf, "%d\n", value);
1485 }
1486
1487 /**
1488 * DOC: vcn_busy_percent
1489 *
1490 * The amdgpu driver provides a sysfs API for reading how busy the VCN
1491 * is as a percentage. The file vcn_busy_percent is used for this.
1492 * The SMU firmware computes a percentage of load based on the
1493 * aggregate activity level in the IP cores.
1494 */
amdgpu_get_vcn_busy_percent(struct device * dev,struct device_attribute * attr,char * buf)1495 static ssize_t amdgpu_get_vcn_busy_percent(struct device *dev,
1496 struct device_attribute *attr,
1497 char *buf)
1498 {
1499 struct drm_device *ddev = dev_get_drvdata(dev);
1500 struct amdgpu_device *adev = drm_to_adev(ddev);
1501 unsigned int value;
1502 int r;
1503
1504 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VCN_LOAD, &value);
1505 if (r)
1506 return r;
1507
1508 return sysfs_emit(buf, "%d\n", value);
1509 }
1510
1511 /**
1512 * DOC: pcie_bw
1513 *
1514 * The amdgpu driver provides a sysfs API for estimating how much data
1515 * has been received and sent by the GPU in the last second through PCIe.
1516 * The file pcie_bw is used for this.
1517 * The Perf counters count the number of received and sent messages and return
1518 * those values, as well as the maximum payload size of a PCIe packet (mps).
1519 * Note that it is not possible to easily and quickly obtain the size of each
1520 * packet transmitted, so we output the max payload size (mps) to allow for
1521 * quick estimation of the PCIe bandwidth usage
1522 */
amdgpu_get_pcie_bw(struct device * dev,struct device_attribute * attr,char * buf)1523 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1524 struct device_attribute *attr,
1525 char *buf)
1526 {
1527 struct drm_device *ddev = dev_get_drvdata(dev);
1528 struct amdgpu_device *adev = drm_to_adev(ddev);
1529 uint64_t count0 = 0, count1 = 0;
1530 int ret;
1531
1532 if (adev->flags & AMD_IS_APU)
1533 return -ENODATA;
1534
1535 if (!adev->asic_funcs->get_pcie_usage)
1536 return -ENODATA;
1537
1538 ret = amdgpu_pm_get_access_if_active(adev);
1539 if (ret)
1540 return ret;
1541
1542 amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1543
1544 amdgpu_pm_put_access(adev);
1545
1546 return sysfs_emit(buf, "%llu %llu %i\n",
1547 count0, count1, pcie_get_mps(adev->pdev));
1548 }
1549
1550 /**
1551 * DOC: unique_id
1552 *
1553 * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1554 * The file unique_id is used for this.
1555 * This will provide a Unique ID that will persist from machine to machine
1556 *
1557 * NOTE: This will only work for GFX9 and newer. This file will be absent
1558 * on unsupported ASICs (GFX8 and older)
1559 */
amdgpu_get_unique_id(struct device * dev,struct device_attribute * attr,char * buf)1560 static ssize_t amdgpu_get_unique_id(struct device *dev,
1561 struct device_attribute *attr,
1562 char *buf)
1563 {
1564 struct drm_device *ddev = dev_get_drvdata(dev);
1565 struct amdgpu_device *adev = drm_to_adev(ddev);
1566
1567 if (adev->unique_id)
1568 return sysfs_emit(buf, "%016llx\n", adev->unique_id);
1569
1570 return 0;
1571 }
1572
1573 /**
1574 * DOC: thermal_throttling_logging
1575 *
1576 * Thermal throttling pulls down the clock frequency and thus the performance.
1577 * It's an useful mechanism to protect the chip from overheating. Since it
1578 * impacts performance, the user controls whether it is enabled and if so,
1579 * the log frequency.
1580 *
1581 * Reading back the file shows you the status(enabled or disabled) and
1582 * the interval(in seconds) between each thermal logging.
1583 *
1584 * Writing an integer to the file, sets a new logging interval, in seconds.
1585 * The value should be between 1 and 3600. If the value is less than 1,
1586 * thermal logging is disabled. Values greater than 3600 are ignored.
1587 */
amdgpu_get_thermal_throttling_logging(struct device * dev,struct device_attribute * attr,char * buf)1588 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1589 struct device_attribute *attr,
1590 char *buf)
1591 {
1592 struct drm_device *ddev = dev_get_drvdata(dev);
1593 struct amdgpu_device *adev = drm_to_adev(ddev);
1594
1595 return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
1596 adev_to_drm(adev)->unique,
1597 atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1598 adev->throttling_logging_rs.interval / HZ + 1);
1599 }
1600
amdgpu_set_thermal_throttling_logging(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1601 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1602 struct device_attribute *attr,
1603 const char *buf,
1604 size_t count)
1605 {
1606 struct drm_device *ddev = dev_get_drvdata(dev);
1607 struct amdgpu_device *adev = drm_to_adev(ddev);
1608 long throttling_logging_interval;
1609 unsigned long flags;
1610 int ret = 0;
1611
1612 ret = kstrtol(buf, 0, &throttling_logging_interval);
1613 if (ret)
1614 return ret;
1615
1616 if (throttling_logging_interval > 3600)
1617 return -EINVAL;
1618
1619 if (throttling_logging_interval > 0) {
1620 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1621 /*
1622 * Reset the ratelimit timer internals.
1623 * This can effectively restart the timer.
1624 */
1625 adev->throttling_logging_rs.interval =
1626 (throttling_logging_interval - 1) * HZ;
1627 adev->throttling_logging_rs.begin = 0;
1628 adev->throttling_logging_rs.printed = 0;
1629 adev->throttling_logging_rs.missed = 0;
1630 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1631
1632 atomic_set(&adev->throttling_logging_enabled, 1);
1633 } else {
1634 atomic_set(&adev->throttling_logging_enabled, 0);
1635 }
1636
1637 return count;
1638 }
1639
1640 /**
1641 * DOC: apu_thermal_cap
1642 *
1643 * The amdgpu driver provides a sysfs API for retrieving/updating thermal
1644 * limit temperature in millidegrees Celsius
1645 *
1646 * Reading back the file shows you core limit value
1647 *
1648 * Writing an integer to the file, sets a new thermal limit. The value
1649 * should be between 0 and 100. If the value is less than 0 or greater
1650 * than 100, then the write request will be ignored.
1651 */
amdgpu_get_apu_thermal_cap(struct device * dev,struct device_attribute * attr,char * buf)1652 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev,
1653 struct device_attribute *attr,
1654 char *buf)
1655 {
1656 int ret, size;
1657 u32 limit;
1658 struct drm_device *ddev = dev_get_drvdata(dev);
1659 struct amdgpu_device *adev = drm_to_adev(ddev);
1660
1661 ret = amdgpu_pm_get_access_if_active(adev);
1662 if (ret)
1663 return ret;
1664
1665 ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit);
1666 if (!ret)
1667 size = sysfs_emit(buf, "%u\n", limit);
1668 else
1669 size = sysfs_emit(buf, "failed to get thermal limit\n");
1670
1671 amdgpu_pm_put_access(adev);
1672
1673 return size;
1674 }
1675
amdgpu_set_apu_thermal_cap(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1676 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev,
1677 struct device_attribute *attr,
1678 const char *buf,
1679 size_t count)
1680 {
1681 int ret;
1682 u32 value;
1683 struct drm_device *ddev = dev_get_drvdata(dev);
1684 struct amdgpu_device *adev = drm_to_adev(ddev);
1685
1686 ret = kstrtou32(buf, 10, &value);
1687 if (ret)
1688 return ret;
1689
1690 if (value > 100) {
1691 dev_err(dev, "Invalid argument !\n");
1692 return -EINVAL;
1693 }
1694
1695 ret = amdgpu_pm_get_access(adev);
1696 if (ret < 0)
1697 return ret;
1698
1699 ret = amdgpu_dpm_set_apu_thermal_limit(adev, value);
1700 if (ret) {
1701 amdgpu_pm_put_access(adev);
1702 dev_err(dev, "failed to update thermal limit\n");
1703 return ret;
1704 }
1705
1706 amdgpu_pm_put_access(adev);
1707
1708 return count;
1709 }
1710
amdgpu_pm_metrics_attr_update(struct amdgpu_device * adev,struct amdgpu_device_attr * attr,uint32_t mask,enum amdgpu_device_attr_states * states)1711 static int amdgpu_pm_metrics_attr_update(struct amdgpu_device *adev,
1712 struct amdgpu_device_attr *attr,
1713 uint32_t mask,
1714 enum amdgpu_device_attr_states *states)
1715 {
1716 if (amdgpu_dpm_get_pm_metrics(adev, NULL, 0) == -EOPNOTSUPP)
1717 *states = ATTR_STATE_UNSUPPORTED;
1718
1719 return 0;
1720 }
1721
amdgpu_get_pm_metrics(struct device * dev,struct device_attribute * attr,char * buf)1722 static ssize_t amdgpu_get_pm_metrics(struct device *dev,
1723 struct device_attribute *attr, char *buf)
1724 {
1725 struct drm_device *ddev = dev_get_drvdata(dev);
1726 struct amdgpu_device *adev = drm_to_adev(ddev);
1727 ssize_t size = 0;
1728 int ret;
1729
1730 ret = amdgpu_pm_get_access_if_active(adev);
1731 if (ret)
1732 return ret;
1733
1734 size = amdgpu_dpm_get_pm_metrics(adev, buf, PAGE_SIZE);
1735
1736 amdgpu_pm_put_access(adev);
1737
1738 return size;
1739 }
1740
1741 /**
1742 * DOC: gpu_metrics
1743 *
1744 * The amdgpu driver provides a sysfs API for retrieving current gpu
1745 * metrics data. The file gpu_metrics is used for this. Reading the
1746 * file will dump all the current gpu metrics data.
1747 *
1748 * These data include temperature, frequency, engines utilization,
1749 * power consume, throttler status, fan speed and cpu core statistics(
1750 * available for APU only). That's it will give a snapshot of all sensors
1751 * at the same time.
1752 */
amdgpu_get_gpu_metrics(struct device * dev,struct device_attribute * attr,char * buf)1753 static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1754 struct device_attribute *attr,
1755 char *buf)
1756 {
1757 struct drm_device *ddev = dev_get_drvdata(dev);
1758 struct amdgpu_device *adev = drm_to_adev(ddev);
1759 void *gpu_metrics;
1760 ssize_t size = 0;
1761 int ret;
1762
1763 ret = amdgpu_pm_get_access_if_active(adev);
1764 if (ret)
1765 return ret;
1766
1767 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
1768 if (size <= 0)
1769 goto out;
1770
1771 if (size >= PAGE_SIZE)
1772 size = PAGE_SIZE - 1;
1773
1774 memcpy(buf, gpu_metrics, size);
1775
1776 out:
1777 amdgpu_pm_put_access(adev);
1778
1779 return size;
1780 }
1781
amdgpu_show_powershift_percent(struct device * dev,char * buf,enum amd_pp_sensors sensor)1782 static int amdgpu_show_powershift_percent(struct device *dev,
1783 char *buf, enum amd_pp_sensors sensor)
1784 {
1785 struct drm_device *ddev = dev_get_drvdata(dev);
1786 struct amdgpu_device *adev = drm_to_adev(ddev);
1787 uint32_t ss_power;
1788 int r = 0, i;
1789
1790 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power);
1791 if (r == -EOPNOTSUPP) {
1792 /* sensor not available on dGPU, try to read from APU */
1793 adev = NULL;
1794 mutex_lock(&mgpu_info.mutex);
1795 for (i = 0; i < mgpu_info.num_gpu; i++) {
1796 if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) {
1797 adev = mgpu_info.gpu_ins[i].adev;
1798 break;
1799 }
1800 }
1801 mutex_unlock(&mgpu_info.mutex);
1802 if (adev)
1803 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power);
1804 }
1805
1806 if (r)
1807 return r;
1808
1809 return sysfs_emit(buf, "%u%%\n", ss_power);
1810 }
1811
1812 /**
1813 * DOC: smartshift_apu_power
1814 *
1815 * The amdgpu driver provides a sysfs API for reporting APU power
1816 * shift in percentage if platform supports smartshift. Value 0 means that
1817 * there is no powershift and values between [1-100] means that the power
1818 * is shifted to APU, the percentage of boost is with respect to APU power
1819 * limit on the platform.
1820 */
1821
amdgpu_get_smartshift_apu_power(struct device * dev,struct device_attribute * attr,char * buf)1822 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
1823 char *buf)
1824 {
1825 return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_APU_SHARE);
1826 }
1827
1828 /**
1829 * DOC: smartshift_dgpu_power
1830 *
1831 * The amdgpu driver provides a sysfs API for reporting dGPU power
1832 * shift in percentage if platform supports smartshift. Value 0 means that
1833 * there is no powershift and values between [1-100] means that the power is
1834 * shifted to dGPU, the percentage of boost is with respect to dGPU power
1835 * limit on the platform.
1836 */
1837
amdgpu_get_smartshift_dgpu_power(struct device * dev,struct device_attribute * attr,char * buf)1838 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
1839 char *buf)
1840 {
1841 return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_DGPU_SHARE);
1842 }
1843
1844 /**
1845 * DOC: smartshift_bias
1846 *
1847 * The amdgpu driver provides a sysfs API for reporting the
1848 * smartshift(SS2.0) bias level. The value ranges from -100 to 100
1849 * and the default is 0. -100 sets maximum preference to APU
1850 * and 100 sets max perference to dGPU.
1851 */
1852
amdgpu_get_smartshift_bias(struct device * dev,struct device_attribute * attr,char * buf)1853 static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
1854 struct device_attribute *attr,
1855 char *buf)
1856 {
1857 int r = 0;
1858
1859 r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
1860
1861 return r;
1862 }
1863
amdgpu_set_smartshift_bias(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1864 static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
1865 struct device_attribute *attr,
1866 const char *buf, size_t count)
1867 {
1868 struct drm_device *ddev = dev_get_drvdata(dev);
1869 struct amdgpu_device *adev = drm_to_adev(ddev);
1870 int r = 0;
1871 int bias = 0;
1872
1873 r = kstrtoint(buf, 10, &bias);
1874 if (r)
1875 goto out;
1876
1877 r = amdgpu_pm_get_access(adev);
1878 if (r < 0)
1879 return r;
1880
1881 if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
1882 bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
1883 else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
1884 bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
1885
1886 amdgpu_smartshift_bias = bias;
1887 r = count;
1888
1889 /* TODO: update bias level with SMU message */
1890
1891 out:
1892 amdgpu_pm_put_access(adev);
1893
1894 return r;
1895 }
1896
ss_power_attr_update(struct amdgpu_device * adev,struct amdgpu_device_attr * attr,uint32_t mask,enum amdgpu_device_attr_states * states)1897 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1898 uint32_t mask, enum amdgpu_device_attr_states *states)
1899 {
1900 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1901 *states = ATTR_STATE_UNSUPPORTED;
1902
1903 return 0;
1904 }
1905
ss_bias_attr_update(struct amdgpu_device * adev,struct amdgpu_device_attr * attr,uint32_t mask,enum amdgpu_device_attr_states * states)1906 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1907 uint32_t mask, enum amdgpu_device_attr_states *states)
1908 {
1909 uint32_t ss_power;
1910
1911 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1912 *states = ATTR_STATE_UNSUPPORTED;
1913 else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1914 (void *)&ss_power))
1915 *states = ATTR_STATE_UNSUPPORTED;
1916 else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1917 (void *)&ss_power))
1918 *states = ATTR_STATE_UNSUPPORTED;
1919
1920 return 0;
1921 }
1922
pp_od_clk_voltage_attr_update(struct amdgpu_device * adev,struct amdgpu_device_attr * attr,uint32_t mask,enum amdgpu_device_attr_states * states)1923 static int pp_od_clk_voltage_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1924 uint32_t mask, enum amdgpu_device_attr_states *states)
1925 {
1926 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
1927
1928 *states = ATTR_STATE_SUPPORTED;
1929
1930 if (!amdgpu_dpm_is_overdrive_supported(adev)) {
1931 *states = ATTR_STATE_UNSUPPORTED;
1932 return 0;
1933 }
1934
1935 /* Enable pp_od_clk_voltage node for gc 9.4.3, 9.4.4, 9.5.0 SRIOV/BM support */
1936 if (gc_ver == IP_VERSION(9, 4, 3) ||
1937 gc_ver == IP_VERSION(9, 4, 4) ||
1938 gc_ver == IP_VERSION(9, 5, 0)) {
1939 if (amdgpu_sriov_multi_vf_mode(adev))
1940 *states = ATTR_STATE_UNSUPPORTED;
1941 return 0;
1942 }
1943
1944 if (!(attr->flags & mask))
1945 *states = ATTR_STATE_UNSUPPORTED;
1946
1947 return 0;
1948 }
1949
pp_dpm_dcefclk_attr_update(struct amdgpu_device * adev,struct amdgpu_device_attr * attr,uint32_t mask,enum amdgpu_device_attr_states * states)1950 static int pp_dpm_dcefclk_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1951 uint32_t mask, enum amdgpu_device_attr_states *states)
1952 {
1953 struct device_attribute *dev_attr = &attr->dev_attr;
1954 uint32_t gc_ver;
1955
1956 *states = ATTR_STATE_SUPPORTED;
1957
1958 if (!(attr->flags & mask)) {
1959 *states = ATTR_STATE_UNSUPPORTED;
1960 return 0;
1961 }
1962
1963 gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
1964 /* dcefclk node is not available on gfx 11.0.3 sriov */
1965 if ((gc_ver == IP_VERSION(11, 0, 3) && amdgpu_sriov_is_pp_one_vf(adev)) ||
1966 gc_ver < IP_VERSION(9, 0, 0) ||
1967 !amdgpu_device_has_display_hardware(adev))
1968 *states = ATTR_STATE_UNSUPPORTED;
1969
1970 /* SMU MP1 does not support dcefclk level setting,
1971 * setting should not be allowed from VF if not in one VF mode.
1972 */
1973 if (gc_ver >= IP_VERSION(10, 0, 0) ||
1974 (amdgpu_sriov_multi_vf_mode(adev))) {
1975 dev_attr->attr.mode &= ~S_IWUGO;
1976 dev_attr->store = NULL;
1977 }
1978
1979 return 0;
1980 }
1981
pp_dpm_clk_default_attr_update(struct amdgpu_device * adev,struct amdgpu_device_attr * attr,uint32_t mask,enum amdgpu_device_attr_states * states)1982 static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1983 uint32_t mask, enum amdgpu_device_attr_states *states)
1984 {
1985 struct device_attribute *dev_attr = &attr->dev_attr;
1986 enum amdgpu_device_attr_id attr_id = attr->attr_id;
1987 uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0);
1988 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
1989
1990 *states = ATTR_STATE_SUPPORTED;
1991
1992 if (!(attr->flags & mask)) {
1993 *states = ATTR_STATE_UNSUPPORTED;
1994 return 0;
1995 }
1996
1997 if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
1998 if (gc_ver < IP_VERSION(9, 0, 0))
1999 *states = ATTR_STATE_UNSUPPORTED;
2000 } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
2001 if (mp1_ver < IP_VERSION(10, 0, 0))
2002 *states = ATTR_STATE_UNSUPPORTED;
2003 } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
2004 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2005 gc_ver == IP_VERSION(10, 3, 3) ||
2006 gc_ver == IP_VERSION(10, 3, 6) ||
2007 gc_ver == IP_VERSION(10, 3, 7) ||
2008 gc_ver == IP_VERSION(10, 3, 0) ||
2009 gc_ver == IP_VERSION(10, 1, 2) ||
2010 gc_ver == IP_VERSION(11, 0, 0) ||
2011 gc_ver == IP_VERSION(11, 0, 1) ||
2012 gc_ver == IP_VERSION(11, 0, 4) ||
2013 gc_ver == IP_VERSION(11, 5, 0) ||
2014 gc_ver == IP_VERSION(11, 0, 2) ||
2015 gc_ver == IP_VERSION(11, 0, 3) ||
2016 gc_ver == IP_VERSION(9, 4, 3) ||
2017 gc_ver == IP_VERSION(9, 4, 4) ||
2018 gc_ver == IP_VERSION(9, 5, 0)))
2019 *states = ATTR_STATE_UNSUPPORTED;
2020 } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
2021 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2022 gc_ver == IP_VERSION(10, 3, 0) ||
2023 gc_ver == IP_VERSION(11, 0, 2) ||
2024 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2025 *states = ATTR_STATE_UNSUPPORTED;
2026 } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2027 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2028 gc_ver == IP_VERSION(10, 3, 3) ||
2029 gc_ver == IP_VERSION(10, 3, 6) ||
2030 gc_ver == IP_VERSION(10, 3, 7) ||
2031 gc_ver == IP_VERSION(10, 3, 0) ||
2032 gc_ver == IP_VERSION(10, 1, 2) ||
2033 gc_ver == IP_VERSION(11, 0, 0) ||
2034 gc_ver == IP_VERSION(11, 0, 1) ||
2035 gc_ver == IP_VERSION(11, 0, 4) ||
2036 gc_ver == IP_VERSION(11, 5, 0) ||
2037 gc_ver == IP_VERSION(11, 0, 2) ||
2038 gc_ver == IP_VERSION(11, 0, 3) ||
2039 gc_ver == IP_VERSION(9, 4, 3) ||
2040 gc_ver == IP_VERSION(9, 4, 4) ||
2041 gc_ver == IP_VERSION(9, 5, 0)))
2042 *states = ATTR_STATE_UNSUPPORTED;
2043 } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) {
2044 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2045 gc_ver == IP_VERSION(10, 3, 0) ||
2046 gc_ver == IP_VERSION(11, 0, 2) ||
2047 gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2048 *states = ATTR_STATE_UNSUPPORTED;
2049 } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
2050 if (gc_ver == IP_VERSION(9, 4, 2) ||
2051 gc_ver == IP_VERSION(9, 4, 3) ||
2052 gc_ver == IP_VERSION(9, 4, 4) ||
2053 gc_ver == IP_VERSION(9, 5, 0))
2054 *states = ATTR_STATE_UNSUPPORTED;
2055 }
2056
2057 switch (gc_ver) {
2058 case IP_VERSION(9, 4, 1):
2059 case IP_VERSION(9, 4, 2):
2060 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */
2061 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2062 DEVICE_ATTR_IS(pp_dpm_socclk) ||
2063 DEVICE_ATTR_IS(pp_dpm_fclk)) {
2064 dev_attr->attr.mode &= ~S_IWUGO;
2065 dev_attr->store = NULL;
2066 }
2067 break;
2068 default:
2069 break;
2070 }
2071
2072 /* setting should not be allowed from VF if not in one VF mode */
2073 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_is_pp_one_vf(adev)) {
2074 dev_attr->attr.mode &= ~S_IWUGO;
2075 dev_attr->store = NULL;
2076 }
2077
2078 return 0;
2079 }
2080
2081 /* pm policy attributes */
2082 struct amdgpu_pm_policy_attr {
2083 struct device_attribute dev_attr;
2084 enum pp_pm_policy id;
2085 };
2086
2087 /**
2088 * DOC: pm_policy
2089 *
2090 * Certain SOCs can support different power policies to optimize application
2091 * performance. However, this policy is provided only at SOC level and not at a
2092 * per-process level. This is useful especially when entire SOC is utilized for
2093 * dedicated workload.
2094 *
2095 * The amdgpu driver provides a sysfs API for selecting the policy. Presently,
2096 * only two types of policies are supported through this interface.
2097 *
2098 * Pstate Policy Selection - This is to select different Pstate profiles which
2099 * decides clock/throttling preferences.
2100 *
2101 * XGMI PLPD Policy Selection - When multiple devices are connected over XGMI,
2102 * this helps to select policy to be applied for per link power down.
2103 *
2104 * The list of available policies and policy levels vary between SOCs. They can
2105 * be viewed under pm_policy node directory. If SOC doesn't support any policy,
2106 * this node won't be available. The different policies supported will be
2107 * available as separate nodes under pm_policy.
2108 *
2109 * cat /sys/bus/pci/devices/.../pm_policy/<policy_type>
2110 *
2111 * Reading the policy file shows the different levels supported. The level which
2112 * is applied presently is denoted by * (asterisk). E.g.,
2113 *
2114 * .. code-block:: console
2115 *
2116 * cat /sys/bus/pci/devices/.../pm_policy/soc_pstate
2117 * 0 : soc_pstate_default
2118 * 1 : soc_pstate_0
2119 * 2 : soc_pstate_1*
2120 * 3 : soc_pstate_2
2121 *
2122 * cat /sys/bus/pci/devices/.../pm_policy/xgmi_plpd
2123 * 0 : plpd_disallow
2124 * 1 : plpd_default
2125 * 2 : plpd_optimized*
2126 *
2127 * To apply a specific policy
2128 *
2129 * "echo <level> > /sys/bus/pci/devices/.../pm_policy/<policy_type>"
2130 *
2131 * For the levels listed in the example above, to select "plpd_optimized" for
2132 * XGMI and "soc_pstate_2" for soc pstate policy -
2133 *
2134 * .. code-block:: console
2135 *
2136 * echo "2" > /sys/bus/pci/devices/.../pm_policy/xgmi_plpd
2137 * echo "3" > /sys/bus/pci/devices/.../pm_policy/soc_pstate
2138 *
2139 */
amdgpu_get_pm_policy_attr(struct device * dev,struct device_attribute * attr,char * buf)2140 static ssize_t amdgpu_get_pm_policy_attr(struct device *dev,
2141 struct device_attribute *attr,
2142 char *buf)
2143 {
2144 struct drm_device *ddev = dev_get_drvdata(dev);
2145 struct amdgpu_device *adev = drm_to_adev(ddev);
2146 struct amdgpu_pm_policy_attr *policy_attr;
2147
2148 policy_attr =
2149 container_of(attr, struct amdgpu_pm_policy_attr, dev_attr);
2150
2151 return amdgpu_dpm_get_pm_policy_info(adev, policy_attr->id, buf);
2152 }
2153
amdgpu_set_pm_policy_attr(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2154 static ssize_t amdgpu_set_pm_policy_attr(struct device *dev,
2155 struct device_attribute *attr,
2156 const char *buf, size_t count)
2157 {
2158 struct drm_device *ddev = dev_get_drvdata(dev);
2159 struct amdgpu_device *adev = drm_to_adev(ddev);
2160 struct amdgpu_pm_policy_attr *policy_attr;
2161 int ret, num_params = 0;
2162 char delimiter[] = " \n\t";
2163 char tmp_buf[128];
2164 char *tmp, *param;
2165 long val;
2166
2167 count = min(count, sizeof(tmp_buf));
2168 memcpy(tmp_buf, buf, count);
2169 tmp_buf[count - 1] = '\0';
2170 tmp = tmp_buf;
2171
2172 tmp = skip_spaces(tmp);
2173 while ((param = strsep(&tmp, delimiter))) {
2174 if (!strlen(param)) {
2175 tmp = skip_spaces(tmp);
2176 continue;
2177 }
2178 ret = kstrtol(param, 0, &val);
2179 if (ret)
2180 return -EINVAL;
2181 num_params++;
2182 if (num_params > 1)
2183 return -EINVAL;
2184 }
2185
2186 if (num_params != 1)
2187 return -EINVAL;
2188
2189 policy_attr =
2190 container_of(attr, struct amdgpu_pm_policy_attr, dev_attr);
2191
2192 ret = amdgpu_pm_get_access(adev);
2193 if (ret < 0)
2194 return ret;
2195
2196 ret = amdgpu_dpm_set_pm_policy(adev, policy_attr->id, val);
2197
2198 amdgpu_pm_put_access(adev);
2199
2200 if (ret)
2201 return ret;
2202
2203 return count;
2204 }
2205
2206 #define AMDGPU_PM_POLICY_ATTR(_name, _id) \
2207 static struct amdgpu_pm_policy_attr pm_policy_attr_##_name = { \
2208 .dev_attr = __ATTR(_name, 0644, amdgpu_get_pm_policy_attr, \
2209 amdgpu_set_pm_policy_attr), \
2210 .id = PP_PM_POLICY_##_id, \
2211 };
2212
2213 #define AMDGPU_PM_POLICY_ATTR_VAR(_name) pm_policy_attr_##_name.dev_attr.attr
2214
2215 AMDGPU_PM_POLICY_ATTR(soc_pstate, SOC_PSTATE)
2216 AMDGPU_PM_POLICY_ATTR(xgmi_plpd, XGMI_PLPD)
2217
2218 static struct attribute *pm_policy_attrs[] = {
2219 &AMDGPU_PM_POLICY_ATTR_VAR(soc_pstate),
2220 &AMDGPU_PM_POLICY_ATTR_VAR(xgmi_plpd),
2221 NULL
2222 };
2223
amdgpu_pm_policy_attr_visible(struct kobject * kobj,struct attribute * attr,int n)2224 static umode_t amdgpu_pm_policy_attr_visible(struct kobject *kobj,
2225 struct attribute *attr, int n)
2226 {
2227 struct device *dev = kobj_to_dev(kobj);
2228 struct drm_device *ddev = dev_get_drvdata(dev);
2229 struct amdgpu_device *adev = drm_to_adev(ddev);
2230 struct amdgpu_pm_policy_attr *policy_attr;
2231
2232 policy_attr =
2233 container_of(attr, struct amdgpu_pm_policy_attr, dev_attr.attr);
2234
2235 if (amdgpu_dpm_get_pm_policy_info(adev, policy_attr->id, NULL) ==
2236 -ENOENT)
2237 return 0;
2238
2239 return attr->mode;
2240 }
2241
2242 const struct attribute_group amdgpu_pm_policy_attr_group = {
2243 .name = "pm_policy",
2244 .attrs = pm_policy_attrs,
2245 .is_visible = amdgpu_pm_policy_attr_visible,
2246 };
2247
2248 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
2249 AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2250 AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2251 AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2252 AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2253 AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2254 AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2255 AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
2256 .attr_update = pp_dpm_clk_default_attr_update),
2257 AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
2258 .attr_update = pp_dpm_clk_default_attr_update),
2259 AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
2260 .attr_update = pp_dpm_clk_default_attr_update),
2261 AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
2262 .attr_update = pp_dpm_clk_default_attr_update),
2263 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
2264 .attr_update = pp_dpm_clk_default_attr_update),
2265 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
2266 .attr_update = pp_dpm_clk_default_attr_update),
2267 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
2268 .attr_update = pp_dpm_clk_default_attr_update),
2269 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
2270 .attr_update = pp_dpm_clk_default_attr_update),
2271 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
2272 .attr_update = pp_dpm_dcefclk_attr_update),
2273 AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
2274 .attr_update = pp_dpm_clk_default_attr_update),
2275 AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC),
2276 AMDGPU_DEVICE_ATTR_RW(pp_mclk_od, ATTR_FLAG_BASIC),
2277 AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2278 AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage, ATTR_FLAG_BASIC,
2279 .attr_update = pp_od_clk_voltage_attr_update),
2280 AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2281 AMDGPU_DEVICE_ATTR_RO(mem_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2282 AMDGPU_DEVICE_ATTR_RO(vcn_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2283 AMDGPU_DEVICE_ATTR_RO(pcie_bw, ATTR_FLAG_BASIC),
2284 AMDGPU_DEVICE_ATTR_RW(pp_features, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2285 AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2286 AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2287 AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2288 AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2289 AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power, ATTR_FLAG_BASIC,
2290 .attr_update = ss_power_attr_update),
2291 AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power, ATTR_FLAG_BASIC,
2292 .attr_update = ss_power_attr_update),
2293 AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC,
2294 .attr_update = ss_bias_attr_update),
2295 AMDGPU_DEVICE_ATTR_RO(pm_metrics, ATTR_FLAG_BASIC,
2296 .attr_update = amdgpu_pm_metrics_attr_update),
2297 };
2298
default_attr_update(struct amdgpu_device * adev,struct amdgpu_device_attr * attr,uint32_t mask,enum amdgpu_device_attr_states * states)2299 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2300 uint32_t mask, enum amdgpu_device_attr_states *states)
2301 {
2302 struct device_attribute *dev_attr = &attr->dev_attr;
2303 enum amdgpu_device_attr_id attr_id = attr->attr_id;
2304 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
2305
2306 if (!(attr->flags & mask)) {
2307 *states = ATTR_STATE_UNSUPPORTED;
2308 return 0;
2309 }
2310
2311 if (DEVICE_ATTR_IS(mem_busy_percent)) {
2312 if ((adev->flags & AMD_IS_APU &&
2313 gc_ver != IP_VERSION(9, 4, 3)) ||
2314 gc_ver == IP_VERSION(9, 0, 1))
2315 *states = ATTR_STATE_UNSUPPORTED;
2316 } else if (DEVICE_ATTR_IS(vcn_busy_percent)) {
2317 if (!(gc_ver == IP_VERSION(9, 3, 0) ||
2318 gc_ver == IP_VERSION(10, 3, 1) ||
2319 gc_ver == IP_VERSION(10, 3, 3) ||
2320 gc_ver == IP_VERSION(10, 3, 6) ||
2321 gc_ver == IP_VERSION(10, 3, 7) ||
2322 gc_ver == IP_VERSION(11, 0, 0) ||
2323 gc_ver == IP_VERSION(11, 0, 1) ||
2324 gc_ver == IP_VERSION(11, 0, 2) ||
2325 gc_ver == IP_VERSION(11, 0, 3) ||
2326 gc_ver == IP_VERSION(11, 0, 4) ||
2327 gc_ver == IP_VERSION(11, 5, 0) ||
2328 gc_ver == IP_VERSION(11, 5, 1) ||
2329 gc_ver == IP_VERSION(11, 5, 2) ||
2330 gc_ver == IP_VERSION(11, 5, 3) ||
2331 gc_ver == IP_VERSION(12, 0, 0) ||
2332 gc_ver == IP_VERSION(12, 0, 1)))
2333 *states = ATTR_STATE_UNSUPPORTED;
2334 } else if (DEVICE_ATTR_IS(pcie_bw)) {
2335 /* PCIe Perf counters won't work on APU nodes */
2336 if (adev->flags & AMD_IS_APU ||
2337 !adev->asic_funcs->get_pcie_usage)
2338 *states = ATTR_STATE_UNSUPPORTED;
2339 } else if (DEVICE_ATTR_IS(unique_id)) {
2340 switch (gc_ver) {
2341 case IP_VERSION(9, 0, 1):
2342 case IP_VERSION(9, 4, 0):
2343 case IP_VERSION(9, 4, 1):
2344 case IP_VERSION(9, 4, 2):
2345 case IP_VERSION(9, 4, 3):
2346 case IP_VERSION(9, 4, 4):
2347 case IP_VERSION(9, 5, 0):
2348 case IP_VERSION(10, 3, 0):
2349 case IP_VERSION(11, 0, 0):
2350 case IP_VERSION(11, 0, 1):
2351 case IP_VERSION(11, 0, 2):
2352 case IP_VERSION(11, 0, 3):
2353 case IP_VERSION(12, 0, 0):
2354 case IP_VERSION(12, 0, 1):
2355 *states = ATTR_STATE_SUPPORTED;
2356 break;
2357 default:
2358 *states = ATTR_STATE_UNSUPPORTED;
2359 }
2360 } else if (DEVICE_ATTR_IS(pp_features)) {
2361 if ((adev->flags & AMD_IS_APU &&
2362 gc_ver != IP_VERSION(9, 4, 3)) ||
2363 gc_ver < IP_VERSION(9, 0, 0))
2364 *states = ATTR_STATE_UNSUPPORTED;
2365 } else if (DEVICE_ATTR_IS(gpu_metrics)) {
2366 if (gc_ver < IP_VERSION(9, 1, 0))
2367 *states = ATTR_STATE_UNSUPPORTED;
2368 } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
2369 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
2370 *states = ATTR_STATE_UNSUPPORTED;
2371 else if ((gc_ver == IP_VERSION(10, 3, 0) ||
2372 gc_ver == IP_VERSION(11, 0, 3)) && amdgpu_sriov_vf(adev))
2373 *states = ATTR_STATE_UNSUPPORTED;
2374 } else if (DEVICE_ATTR_IS(pp_mclk_od)) {
2375 if (amdgpu_dpm_get_mclk_od(adev) == -EOPNOTSUPP)
2376 *states = ATTR_STATE_UNSUPPORTED;
2377 } else if (DEVICE_ATTR_IS(pp_sclk_od)) {
2378 if (amdgpu_dpm_get_sclk_od(adev) == -EOPNOTSUPP)
2379 *states = ATTR_STATE_UNSUPPORTED;
2380 } else if (DEVICE_ATTR_IS(apu_thermal_cap)) {
2381 u32 limit;
2382
2383 if (amdgpu_dpm_get_apu_thermal_limit(adev, &limit) ==
2384 -EOPNOTSUPP)
2385 *states = ATTR_STATE_UNSUPPORTED;
2386 }
2387
2388 switch (gc_ver) {
2389 case IP_VERSION(10, 3, 0):
2390 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) &&
2391 amdgpu_sriov_vf(adev)) {
2392 dev_attr->attr.mode &= ~0222;
2393 dev_attr->store = NULL;
2394 }
2395 break;
2396 default:
2397 break;
2398 }
2399
2400 return 0;
2401 }
2402
2403
amdgpu_device_attr_create(struct amdgpu_device * adev,struct amdgpu_device_attr * attr,uint32_t mask,struct list_head * attr_list)2404 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2405 struct amdgpu_device_attr *attr,
2406 uint32_t mask, struct list_head *attr_list)
2407 {
2408 int ret = 0;
2409 enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2410 struct amdgpu_device_attr_entry *attr_entry;
2411 struct device_attribute *dev_attr;
2412 const char *name;
2413
2414 int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2415 uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2416
2417 if (!attr)
2418 return -EINVAL;
2419
2420 dev_attr = &attr->dev_attr;
2421 name = dev_attr->attr.name;
2422
2423 attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
2424
2425 ret = attr_update(adev, attr, mask, &attr_states);
2426 if (ret) {
2427 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2428 name, ret);
2429 return ret;
2430 }
2431
2432 if (attr_states == ATTR_STATE_UNSUPPORTED)
2433 return 0;
2434
2435 ret = device_create_file(adev->dev, dev_attr);
2436 if (ret) {
2437 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2438 name, ret);
2439 }
2440
2441 attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2442 if (!attr_entry)
2443 return -ENOMEM;
2444
2445 attr_entry->attr = attr;
2446 INIT_LIST_HEAD(&attr_entry->entry);
2447
2448 list_add_tail(&attr_entry->entry, attr_list);
2449
2450 return ret;
2451 }
2452
amdgpu_device_attr_remove(struct amdgpu_device * adev,struct amdgpu_device_attr * attr)2453 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2454 {
2455 struct device_attribute *dev_attr = &attr->dev_attr;
2456
2457 device_remove_file(adev->dev, dev_attr);
2458 }
2459
2460 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2461 struct list_head *attr_list);
2462
amdgpu_device_attr_create_groups(struct amdgpu_device * adev,struct amdgpu_device_attr * attrs,uint32_t counts,uint32_t mask,struct list_head * attr_list)2463 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2464 struct amdgpu_device_attr *attrs,
2465 uint32_t counts,
2466 uint32_t mask,
2467 struct list_head *attr_list)
2468 {
2469 int ret = 0;
2470 uint32_t i = 0;
2471
2472 for (i = 0; i < counts; i++) {
2473 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2474 if (ret)
2475 goto failed;
2476 }
2477
2478 return 0;
2479
2480 failed:
2481 amdgpu_device_attr_remove_groups(adev, attr_list);
2482
2483 return ret;
2484 }
2485
amdgpu_device_attr_remove_groups(struct amdgpu_device * adev,struct list_head * attr_list)2486 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2487 struct list_head *attr_list)
2488 {
2489 struct amdgpu_device_attr_entry *entry, *entry_tmp;
2490
2491 if (list_empty(attr_list))
2492 return ;
2493
2494 list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2495 amdgpu_device_attr_remove(adev, entry->attr);
2496 list_del(&entry->entry);
2497 kfree(entry);
2498 }
2499 }
2500
amdgpu_hwmon_show_temp(struct device * dev,struct device_attribute * attr,char * buf)2501 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2502 struct device_attribute *attr,
2503 char *buf)
2504 {
2505 struct amdgpu_device *adev = dev_get_drvdata(dev);
2506 int channel = to_sensor_dev_attr(attr)->index;
2507 int r, temp = 0;
2508
2509 if (channel >= PP_TEMP_MAX)
2510 return -EINVAL;
2511
2512 switch (channel) {
2513 case PP_TEMP_JUNCTION:
2514 /* get current junction temperature */
2515 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2516 (void *)&temp);
2517 break;
2518 case PP_TEMP_EDGE:
2519 /* get current edge temperature */
2520 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2521 (void *)&temp);
2522 break;
2523 case PP_TEMP_MEM:
2524 /* get current memory temperature */
2525 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2526 (void *)&temp);
2527 break;
2528 default:
2529 r = -EINVAL;
2530 break;
2531 }
2532
2533 if (r)
2534 return r;
2535
2536 return sysfs_emit(buf, "%d\n", temp);
2537 }
2538
amdgpu_hwmon_show_temp_thresh(struct device * dev,struct device_attribute * attr,char * buf)2539 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2540 struct device_attribute *attr,
2541 char *buf)
2542 {
2543 struct amdgpu_device *adev = dev_get_drvdata(dev);
2544 int hyst = to_sensor_dev_attr(attr)->index;
2545 int temp;
2546
2547 if (hyst)
2548 temp = adev->pm.dpm.thermal.min_temp;
2549 else
2550 temp = adev->pm.dpm.thermal.max_temp;
2551
2552 return sysfs_emit(buf, "%d\n", temp);
2553 }
2554
amdgpu_hwmon_show_hotspot_temp_thresh(struct device * dev,struct device_attribute * attr,char * buf)2555 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2556 struct device_attribute *attr,
2557 char *buf)
2558 {
2559 struct amdgpu_device *adev = dev_get_drvdata(dev);
2560 int hyst = to_sensor_dev_attr(attr)->index;
2561 int temp;
2562
2563 if (hyst)
2564 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2565 else
2566 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2567
2568 return sysfs_emit(buf, "%d\n", temp);
2569 }
2570
amdgpu_hwmon_show_mem_temp_thresh(struct device * dev,struct device_attribute * attr,char * buf)2571 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2572 struct device_attribute *attr,
2573 char *buf)
2574 {
2575 struct amdgpu_device *adev = dev_get_drvdata(dev);
2576 int hyst = to_sensor_dev_attr(attr)->index;
2577 int temp;
2578
2579 if (hyst)
2580 temp = adev->pm.dpm.thermal.min_mem_temp;
2581 else
2582 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2583
2584 return sysfs_emit(buf, "%d\n", temp);
2585 }
2586
amdgpu_hwmon_show_temp_label(struct device * dev,struct device_attribute * attr,char * buf)2587 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2588 struct device_attribute *attr,
2589 char *buf)
2590 {
2591 int channel = to_sensor_dev_attr(attr)->index;
2592
2593 if (channel >= PP_TEMP_MAX)
2594 return -EINVAL;
2595
2596 return sysfs_emit(buf, "%s\n", temp_label[channel].label);
2597 }
2598
amdgpu_hwmon_show_temp_emergency(struct device * dev,struct device_attribute * attr,char * buf)2599 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2600 struct device_attribute *attr,
2601 char *buf)
2602 {
2603 struct amdgpu_device *adev = dev_get_drvdata(dev);
2604 int channel = to_sensor_dev_attr(attr)->index;
2605 int temp = 0;
2606
2607 if (channel >= PP_TEMP_MAX)
2608 return -EINVAL;
2609
2610 switch (channel) {
2611 case PP_TEMP_JUNCTION:
2612 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2613 break;
2614 case PP_TEMP_EDGE:
2615 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2616 break;
2617 case PP_TEMP_MEM:
2618 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2619 break;
2620 }
2621
2622 return sysfs_emit(buf, "%d\n", temp);
2623 }
2624
amdgpu_hwmon_get_pwm1_enable(struct device * dev,struct device_attribute * attr,char * buf)2625 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2626 struct device_attribute *attr,
2627 char *buf)
2628 {
2629 struct amdgpu_device *adev = dev_get_drvdata(dev);
2630 u32 pwm_mode = 0;
2631 int ret;
2632
2633 ret = amdgpu_pm_get_access_if_active(adev);
2634 if (ret)
2635 return ret;
2636
2637 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2638
2639 amdgpu_pm_put_access(adev);
2640
2641 if (ret)
2642 return -EINVAL;
2643
2644 return sysfs_emit(buf, "%u\n", pwm_mode);
2645 }
2646
amdgpu_hwmon_set_pwm1_enable(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2647 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2648 struct device_attribute *attr,
2649 const char *buf,
2650 size_t count)
2651 {
2652 struct amdgpu_device *adev = dev_get_drvdata(dev);
2653 int err, ret;
2654 u32 pwm_mode;
2655 int value;
2656
2657 err = kstrtoint(buf, 10, &value);
2658 if (err)
2659 return err;
2660
2661 if (value == 0)
2662 pwm_mode = AMD_FAN_CTRL_NONE;
2663 else if (value == 1)
2664 pwm_mode = AMD_FAN_CTRL_MANUAL;
2665 else if (value == 2)
2666 pwm_mode = AMD_FAN_CTRL_AUTO;
2667 else
2668 return -EINVAL;
2669
2670 ret = amdgpu_pm_get_access(adev);
2671 if (ret < 0)
2672 return ret;
2673
2674 ret = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2675
2676 amdgpu_pm_put_access(adev);
2677
2678 if (ret)
2679 return -EINVAL;
2680
2681 return count;
2682 }
2683
amdgpu_hwmon_get_pwm1_min(struct device * dev,struct device_attribute * attr,char * buf)2684 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2685 struct device_attribute *attr,
2686 char *buf)
2687 {
2688 return sysfs_emit(buf, "%i\n", 0);
2689 }
2690
amdgpu_hwmon_get_pwm1_max(struct device * dev,struct device_attribute * attr,char * buf)2691 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2692 struct device_attribute *attr,
2693 char *buf)
2694 {
2695 return sysfs_emit(buf, "%i\n", 255);
2696 }
2697
amdgpu_hwmon_set_pwm1(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2698 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2699 struct device_attribute *attr,
2700 const char *buf, size_t count)
2701 {
2702 struct amdgpu_device *adev = dev_get_drvdata(dev);
2703 int err;
2704 u32 value;
2705 u32 pwm_mode;
2706
2707 err = kstrtou32(buf, 10, &value);
2708 if (err)
2709 return err;
2710
2711 err = amdgpu_pm_get_access(adev);
2712 if (err < 0)
2713 return err;
2714
2715 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2716 if (err)
2717 goto out;
2718
2719 if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2720 pr_info("manual fan speed control should be enabled first\n");
2721 err = -EINVAL;
2722 goto out;
2723 }
2724
2725 err = amdgpu_dpm_set_fan_speed_pwm(adev, value);
2726
2727 out:
2728 amdgpu_pm_put_access(adev);
2729
2730 if (err)
2731 return err;
2732
2733 return count;
2734 }
2735
amdgpu_hwmon_get_pwm1(struct device * dev,struct device_attribute * attr,char * buf)2736 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2737 struct device_attribute *attr,
2738 char *buf)
2739 {
2740 struct amdgpu_device *adev = dev_get_drvdata(dev);
2741 int err;
2742 u32 speed = 0;
2743
2744 err = amdgpu_pm_get_access_if_active(adev);
2745 if (err)
2746 return err;
2747
2748 err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed);
2749
2750 amdgpu_pm_put_access(adev);
2751
2752 if (err)
2753 return err;
2754
2755 return sysfs_emit(buf, "%i\n", speed);
2756 }
2757
amdgpu_hwmon_get_fan1_input(struct device * dev,struct device_attribute * attr,char * buf)2758 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2759 struct device_attribute *attr,
2760 char *buf)
2761 {
2762 struct amdgpu_device *adev = dev_get_drvdata(dev);
2763 int err;
2764 u32 speed = 0;
2765
2766 err = amdgpu_pm_get_access_if_active(adev);
2767 if (err)
2768 return err;
2769
2770 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2771
2772 amdgpu_pm_put_access(adev);
2773
2774 if (err)
2775 return err;
2776
2777 return sysfs_emit(buf, "%i\n", speed);
2778 }
2779
amdgpu_hwmon_get_fan1_min(struct device * dev,struct device_attribute * attr,char * buf)2780 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2781 struct device_attribute *attr,
2782 char *buf)
2783 {
2784 struct amdgpu_device *adev = dev_get_drvdata(dev);
2785 u32 min_rpm = 0;
2786 int r;
2787
2788 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2789 (void *)&min_rpm);
2790
2791 if (r)
2792 return r;
2793
2794 return sysfs_emit(buf, "%d\n", min_rpm);
2795 }
2796
amdgpu_hwmon_get_fan1_max(struct device * dev,struct device_attribute * attr,char * buf)2797 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2798 struct device_attribute *attr,
2799 char *buf)
2800 {
2801 struct amdgpu_device *adev = dev_get_drvdata(dev);
2802 u32 max_rpm = 0;
2803 int r;
2804
2805 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2806 (void *)&max_rpm);
2807
2808 if (r)
2809 return r;
2810
2811 return sysfs_emit(buf, "%d\n", max_rpm);
2812 }
2813
amdgpu_hwmon_get_fan1_target(struct device * dev,struct device_attribute * attr,char * buf)2814 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2815 struct device_attribute *attr,
2816 char *buf)
2817 {
2818 struct amdgpu_device *adev = dev_get_drvdata(dev);
2819 int err;
2820 u32 rpm = 0;
2821
2822 err = amdgpu_pm_get_access_if_active(adev);
2823 if (err)
2824 return err;
2825
2826 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2827
2828 amdgpu_pm_put_access(adev);
2829
2830 if (err)
2831 return err;
2832
2833 return sysfs_emit(buf, "%i\n", rpm);
2834 }
2835
amdgpu_hwmon_set_fan1_target(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2836 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2837 struct device_attribute *attr,
2838 const char *buf, size_t count)
2839 {
2840 struct amdgpu_device *adev = dev_get_drvdata(dev);
2841 int err;
2842 u32 value;
2843 u32 pwm_mode;
2844
2845 err = kstrtou32(buf, 10, &value);
2846 if (err)
2847 return err;
2848
2849 err = amdgpu_pm_get_access(adev);
2850 if (err < 0)
2851 return err;
2852
2853 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2854 if (err)
2855 goto out;
2856
2857 if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2858 err = -ENODATA;
2859 goto out;
2860 }
2861
2862 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2863
2864 out:
2865 amdgpu_pm_put_access(adev);
2866
2867 if (err)
2868 return err;
2869
2870 return count;
2871 }
2872
amdgpu_hwmon_get_fan1_enable(struct device * dev,struct device_attribute * attr,char * buf)2873 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2874 struct device_attribute *attr,
2875 char *buf)
2876 {
2877 struct amdgpu_device *adev = dev_get_drvdata(dev);
2878 u32 pwm_mode = 0;
2879 int ret;
2880
2881 ret = amdgpu_pm_get_access_if_active(adev);
2882 if (ret)
2883 return ret;
2884
2885 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2886
2887 amdgpu_pm_put_access(adev);
2888
2889 if (ret)
2890 return -EINVAL;
2891
2892 return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2893 }
2894
amdgpu_hwmon_set_fan1_enable(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2895 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2896 struct device_attribute *attr,
2897 const char *buf,
2898 size_t count)
2899 {
2900 struct amdgpu_device *adev = dev_get_drvdata(dev);
2901 int err;
2902 int value;
2903 u32 pwm_mode;
2904
2905 err = kstrtoint(buf, 10, &value);
2906 if (err)
2907 return err;
2908
2909 if (value == 0)
2910 pwm_mode = AMD_FAN_CTRL_AUTO;
2911 else if (value == 1)
2912 pwm_mode = AMD_FAN_CTRL_MANUAL;
2913 else
2914 return -EINVAL;
2915
2916 err = amdgpu_pm_get_access(adev);
2917 if (err < 0)
2918 return err;
2919
2920 err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2921
2922 amdgpu_pm_put_access(adev);
2923
2924 if (err)
2925 return -EINVAL;
2926
2927 return count;
2928 }
2929
amdgpu_hwmon_show_vddgfx(struct device * dev,struct device_attribute * attr,char * buf)2930 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2931 struct device_attribute *attr,
2932 char *buf)
2933 {
2934 struct amdgpu_device *adev = dev_get_drvdata(dev);
2935 u32 vddgfx;
2936 int r;
2937
2938 /* get the voltage */
2939 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX,
2940 (void *)&vddgfx);
2941 if (r)
2942 return r;
2943
2944 return sysfs_emit(buf, "%d\n", vddgfx);
2945 }
2946
amdgpu_hwmon_show_vddgfx_label(struct device * dev,struct device_attribute * attr,char * buf)2947 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2948 struct device_attribute *attr,
2949 char *buf)
2950 {
2951 return sysfs_emit(buf, "vddgfx\n");
2952 }
2953
amdgpu_hwmon_show_vddnb(struct device * dev,struct device_attribute * attr,char * buf)2954 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2955 struct device_attribute *attr,
2956 char *buf)
2957 {
2958 struct amdgpu_device *adev = dev_get_drvdata(dev);
2959 u32 vddnb;
2960 int r;
2961
2962 /* only APUs have vddnb */
2963 if (!(adev->flags & AMD_IS_APU))
2964 return -EINVAL;
2965
2966 /* get the voltage */
2967 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB,
2968 (void *)&vddnb);
2969 if (r)
2970 return r;
2971
2972 return sysfs_emit(buf, "%d\n", vddnb);
2973 }
2974
amdgpu_hwmon_show_vddnb_label(struct device * dev,struct device_attribute * attr,char * buf)2975 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2976 struct device_attribute *attr,
2977 char *buf)
2978 {
2979 return sysfs_emit(buf, "vddnb\n");
2980 }
2981
amdgpu_hwmon_get_power(struct device * dev,enum amd_pp_sensors sensor)2982 static int amdgpu_hwmon_get_power(struct device *dev,
2983 enum amd_pp_sensors sensor)
2984 {
2985 struct amdgpu_device *adev = dev_get_drvdata(dev);
2986 unsigned int uw;
2987 u32 query = 0;
2988 int r;
2989
2990 r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&query);
2991 if (r)
2992 return r;
2993
2994 /* convert to microwatts */
2995 uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2996
2997 return uw;
2998 }
2999
amdgpu_hwmon_show_power_avg(struct device * dev,struct device_attribute * attr,char * buf)3000 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
3001 struct device_attribute *attr,
3002 char *buf)
3003 {
3004 ssize_t val;
3005
3006 val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_AVG_POWER);
3007 if (val < 0)
3008 return val;
3009
3010 return sysfs_emit(buf, "%zd\n", val);
3011 }
3012
amdgpu_hwmon_show_power_input(struct device * dev,struct device_attribute * attr,char * buf)3013 static ssize_t amdgpu_hwmon_show_power_input(struct device *dev,
3014 struct device_attribute *attr,
3015 char *buf)
3016 {
3017 ssize_t val;
3018
3019 val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER);
3020 if (val < 0)
3021 return val;
3022
3023 return sysfs_emit(buf, "%zd\n", val);
3024 }
3025
amdgpu_hwmon_show_power_cap_generic(struct device * dev,struct device_attribute * attr,char * buf,enum pp_power_limit_level pp_limit_level)3026 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev,
3027 struct device_attribute *attr,
3028 char *buf,
3029 enum pp_power_limit_level pp_limit_level)
3030 {
3031 struct amdgpu_device *adev = dev_get_drvdata(dev);
3032 enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
3033 uint32_t limit;
3034 ssize_t size;
3035 int r;
3036
3037 r = amdgpu_pm_get_access_if_active(adev);
3038 if (r)
3039 return r;
3040
3041 r = amdgpu_dpm_get_power_limit(adev, &limit,
3042 pp_limit_level, power_type);
3043
3044 if (!r)
3045 size = sysfs_emit(buf, "%u\n", limit * 1000000);
3046 else
3047 size = sysfs_emit(buf, "\n");
3048
3049 amdgpu_pm_put_access(adev);
3050
3051 return size;
3052 }
3053
amdgpu_hwmon_show_power_cap_min(struct device * dev,struct device_attribute * attr,char * buf)3054 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
3055 struct device_attribute *attr,
3056 char *buf)
3057 {
3058 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MIN);
3059 }
3060
amdgpu_hwmon_show_power_cap_max(struct device * dev,struct device_attribute * attr,char * buf)3061 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
3062 struct device_attribute *attr,
3063 char *buf)
3064 {
3065 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX);
3066
3067 }
3068
amdgpu_hwmon_show_power_cap(struct device * dev,struct device_attribute * attr,char * buf)3069 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
3070 struct device_attribute *attr,
3071 char *buf)
3072 {
3073 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT);
3074
3075 }
3076
amdgpu_hwmon_show_power_cap_default(struct device * dev,struct device_attribute * attr,char * buf)3077 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
3078 struct device_attribute *attr,
3079 char *buf)
3080 {
3081 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT);
3082
3083 }
3084
amdgpu_hwmon_show_power_label(struct device * dev,struct device_attribute * attr,char * buf)3085 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
3086 struct device_attribute *attr,
3087 char *buf)
3088 {
3089 struct amdgpu_device *adev = dev_get_drvdata(dev);
3090 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
3091
3092 if (gc_ver == IP_VERSION(10, 3, 1))
3093 return sysfs_emit(buf, "%s\n",
3094 to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ?
3095 "fastPPT" : "slowPPT");
3096 else
3097 return sysfs_emit(buf, "PPT\n");
3098 }
3099
amdgpu_hwmon_set_power_cap(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3100 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
3101 struct device_attribute *attr,
3102 const char *buf,
3103 size_t count)
3104 {
3105 struct amdgpu_device *adev = dev_get_drvdata(dev);
3106 int limit_type = to_sensor_dev_attr(attr)->index;
3107 int err;
3108 u32 value;
3109
3110 if (amdgpu_sriov_vf(adev))
3111 return -EINVAL;
3112
3113 err = kstrtou32(buf, 10, &value);
3114 if (err)
3115 return err;
3116
3117 value = value / 1000000; /* convert to Watt */
3118 value |= limit_type << 24;
3119
3120 err = amdgpu_pm_get_access(adev);
3121 if (err < 0)
3122 return err;
3123
3124 err = amdgpu_dpm_set_power_limit(adev, value);
3125
3126 amdgpu_pm_put_access(adev);
3127
3128 if (err)
3129 return err;
3130
3131 return count;
3132 }
3133
amdgpu_hwmon_show_sclk(struct device * dev,struct device_attribute * attr,char * buf)3134 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
3135 struct device_attribute *attr,
3136 char *buf)
3137 {
3138 struct amdgpu_device *adev = dev_get_drvdata(dev);
3139 uint32_t sclk;
3140 int r;
3141
3142 /* get the sclk */
3143 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
3144 (void *)&sclk);
3145 if (r)
3146 return r;
3147
3148 return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
3149 }
3150
amdgpu_hwmon_show_sclk_label(struct device * dev,struct device_attribute * attr,char * buf)3151 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
3152 struct device_attribute *attr,
3153 char *buf)
3154 {
3155 return sysfs_emit(buf, "sclk\n");
3156 }
3157
amdgpu_hwmon_show_mclk(struct device * dev,struct device_attribute * attr,char * buf)3158 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
3159 struct device_attribute *attr,
3160 char *buf)
3161 {
3162 struct amdgpu_device *adev = dev_get_drvdata(dev);
3163 uint32_t mclk;
3164 int r;
3165
3166 /* get the sclk */
3167 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
3168 (void *)&mclk);
3169 if (r)
3170 return r;
3171
3172 return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
3173 }
3174
amdgpu_hwmon_show_mclk_label(struct device * dev,struct device_attribute * attr,char * buf)3175 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
3176 struct device_attribute *attr,
3177 char *buf)
3178 {
3179 return sysfs_emit(buf, "mclk\n");
3180 }
3181
3182 /**
3183 * DOC: hwmon
3184 *
3185 * The amdgpu driver exposes the following sensor interfaces:
3186 *
3187 * - GPU temperature (via the on-die sensor)
3188 *
3189 * - GPU voltage
3190 *
3191 * - Northbridge voltage (APUs only)
3192 *
3193 * - GPU power
3194 *
3195 * - GPU fan
3196 *
3197 * - GPU gfx/compute engine clock
3198 *
3199 * - GPU memory clock (dGPU only)
3200 *
3201 * hwmon interfaces for GPU temperature:
3202 *
3203 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3204 * - temp2_input and temp3_input are supported on SOC15 dGPUs only
3205 *
3206 * - temp[1-3]_label: temperature channel label
3207 * - temp2_label and temp3_label are supported on SOC15 dGPUs only
3208 *
3209 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3210 * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3211 *
3212 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3213 * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3214 *
3215 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3216 * - these are supported on SOC15 dGPUs only
3217 *
3218 * hwmon interfaces for GPU voltage:
3219 *
3220 * - in0_input: the voltage on the GPU in millivolts
3221 *
3222 * - in1_input: the voltage on the Northbridge in millivolts
3223 *
3224 * hwmon interfaces for GPU power:
3225 *
3226 * - power1_average: average power used by the SoC in microWatts. On APUs this includes the CPU.
3227 *
3228 * - power1_input: instantaneous power used by the SoC in microWatts. On APUs this includes the CPU.
3229 *
3230 * - power1_cap_min: minimum cap supported in microWatts
3231 *
3232 * - power1_cap_max: maximum cap supported in microWatts
3233 *
3234 * - power1_cap: selected power cap in microWatts
3235 *
3236 * hwmon interfaces for GPU fan:
3237 *
3238 * - pwm1: pulse width modulation fan level (0-255)
3239 *
3240 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3241 *
3242 * - pwm1_min: pulse width modulation fan control minimum level (0)
3243 *
3244 * - pwm1_max: pulse width modulation fan control maximum level (255)
3245 *
3246 * - fan1_min: a minimum value Unit: revolution/min (RPM)
3247 *
3248 * - fan1_max: a maximum value Unit: revolution/max (RPM)
3249 *
3250 * - fan1_input: fan speed in RPM
3251 *
3252 * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3253 *
3254 * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3255 *
3256 * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time.
3257 * That will get the former one overridden.
3258 *
3259 * hwmon interfaces for GPU clocks:
3260 *
3261 * - freq1_input: the gfx/compute clock in hertz
3262 *
3263 * - freq2_input: the memory clock in hertz
3264 *
3265 * You can use hwmon tools like sensors to view this information on your system.
3266 *
3267 */
3268
3269 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3270 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3271 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3272 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3273 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3274 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3275 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3276 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3277 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3278 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3279 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3280 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3281 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3282 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3283 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3284 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3285 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3286 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3287 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3288 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3289 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3290 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3291 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3292 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3293 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3294 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3295 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3296 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3297 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3298 static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, amdgpu_hwmon_show_power_input, NULL, 0);
3299 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3300 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3301 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3302 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
3303 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
3304 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1);
3305 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
3306 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
3307 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
3308 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
3309 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
3310 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3311 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3312 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3313 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3314
3315 static struct attribute *hwmon_attributes[] = {
3316 &sensor_dev_attr_temp1_input.dev_attr.attr,
3317 &sensor_dev_attr_temp1_crit.dev_attr.attr,
3318 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3319 &sensor_dev_attr_temp2_input.dev_attr.attr,
3320 &sensor_dev_attr_temp2_crit.dev_attr.attr,
3321 &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3322 &sensor_dev_attr_temp3_input.dev_attr.attr,
3323 &sensor_dev_attr_temp3_crit.dev_attr.attr,
3324 &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3325 &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3326 &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3327 &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3328 &sensor_dev_attr_temp1_label.dev_attr.attr,
3329 &sensor_dev_attr_temp2_label.dev_attr.attr,
3330 &sensor_dev_attr_temp3_label.dev_attr.attr,
3331 &sensor_dev_attr_pwm1.dev_attr.attr,
3332 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3333 &sensor_dev_attr_pwm1_min.dev_attr.attr,
3334 &sensor_dev_attr_pwm1_max.dev_attr.attr,
3335 &sensor_dev_attr_fan1_input.dev_attr.attr,
3336 &sensor_dev_attr_fan1_min.dev_attr.attr,
3337 &sensor_dev_attr_fan1_max.dev_attr.attr,
3338 &sensor_dev_attr_fan1_target.dev_attr.attr,
3339 &sensor_dev_attr_fan1_enable.dev_attr.attr,
3340 &sensor_dev_attr_in0_input.dev_attr.attr,
3341 &sensor_dev_attr_in0_label.dev_attr.attr,
3342 &sensor_dev_attr_in1_input.dev_attr.attr,
3343 &sensor_dev_attr_in1_label.dev_attr.attr,
3344 &sensor_dev_attr_power1_average.dev_attr.attr,
3345 &sensor_dev_attr_power1_input.dev_attr.attr,
3346 &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3347 &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3348 &sensor_dev_attr_power1_cap.dev_attr.attr,
3349 &sensor_dev_attr_power1_cap_default.dev_attr.attr,
3350 &sensor_dev_attr_power1_label.dev_attr.attr,
3351 &sensor_dev_attr_power2_average.dev_attr.attr,
3352 &sensor_dev_attr_power2_cap_max.dev_attr.attr,
3353 &sensor_dev_attr_power2_cap_min.dev_attr.attr,
3354 &sensor_dev_attr_power2_cap.dev_attr.attr,
3355 &sensor_dev_attr_power2_cap_default.dev_attr.attr,
3356 &sensor_dev_attr_power2_label.dev_attr.attr,
3357 &sensor_dev_attr_freq1_input.dev_attr.attr,
3358 &sensor_dev_attr_freq1_label.dev_attr.attr,
3359 &sensor_dev_attr_freq2_input.dev_attr.attr,
3360 &sensor_dev_attr_freq2_label.dev_attr.attr,
3361 NULL
3362 };
3363
hwmon_attributes_visible(struct kobject * kobj,struct attribute * attr,int index)3364 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3365 struct attribute *attr, int index)
3366 {
3367 struct device *dev = kobj_to_dev(kobj);
3368 struct amdgpu_device *adev = dev_get_drvdata(dev);
3369 umode_t effective_mode = attr->mode;
3370 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
3371 uint32_t tmp;
3372
3373 /* under pp one vf mode manage of hwmon attributes is not supported */
3374 if (amdgpu_sriov_is_pp_one_vf(adev))
3375 effective_mode &= ~S_IWUSR;
3376
3377 /* Skip fan attributes if fan is not present */
3378 if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3379 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3380 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3381 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3382 attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3383 attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3384 attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3385 attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3386 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3387 return 0;
3388
3389 /* Skip fan attributes on APU */
3390 if ((adev->flags & AMD_IS_APU) &&
3391 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3392 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3393 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3394 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3395 attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3396 attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3397 attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3398 attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3399 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3400 return 0;
3401
3402 /* Skip crit temp on APU */
3403 if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) ||
3404 (gc_ver == IP_VERSION(9, 4, 3) || gc_ver == IP_VERSION(9, 4, 4) ||
3405 gc_ver == IP_VERSION(9, 5, 0))) &&
3406 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3407 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3408 return 0;
3409
3410 /* Skip limit attributes if DPM is not enabled */
3411 if (!adev->pm.dpm_enabled &&
3412 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3413 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3414 attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3415 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3416 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3417 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3418 attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3419 attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3420 attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3421 attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3422 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3423 return 0;
3424
3425 /* mask fan attributes if we have no bindings for this asic to expose */
3426 if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3427 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3428 ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) &&
3429 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3430 effective_mode &= ~S_IRUGO;
3431
3432 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3433 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3434 ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) &&
3435 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3436 effective_mode &= ~S_IWUSR;
3437
3438 /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */
3439 if (((adev->family == AMDGPU_FAMILY_SI) ||
3440 ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) &&
3441 (gc_ver != IP_VERSION(9, 4, 3) && gc_ver != IP_VERSION(9, 4, 4)))) &&
3442 (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3443 attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr ||
3444 attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3445 attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3446 return 0;
3447
3448 /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */
3449 if (((adev->family == AMDGPU_FAMILY_SI) ||
3450 ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) &&
3451 (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3452 return 0;
3453
3454 /* not all products support both average and instantaneous */
3455 if (attr == &sensor_dev_attr_power1_average.dev_attr.attr &&
3456 amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&tmp) == -EOPNOTSUPP)
3457 return 0;
3458 if (attr == &sensor_dev_attr_power1_input.dev_attr.attr &&
3459 amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&tmp) == -EOPNOTSUPP)
3460 return 0;
3461
3462 /* hide max/min values if we can't both query and manage the fan */
3463 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3464 (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3465 (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3466 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) &&
3467 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3468 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3469 return 0;
3470
3471 if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3472 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) &&
3473 (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3474 attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3475 return 0;
3476
3477 if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */
3478 adev->family == AMDGPU_FAMILY_KV || /* not implemented yet */
3479 (gc_ver == IP_VERSION(9, 4, 3) ||
3480 gc_ver == IP_VERSION(9, 4, 4) ||
3481 gc_ver == IP_VERSION(9, 5, 0))) &&
3482 (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3483 attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3484 return 0;
3485
3486 /* only APUs other than gc 9,4,3 have vddnb */
3487 if ((!(adev->flags & AMD_IS_APU) ||
3488 (gc_ver == IP_VERSION(9, 4, 3) ||
3489 gc_ver == IP_VERSION(9, 4, 4) ||
3490 gc_ver == IP_VERSION(9, 5, 0))) &&
3491 (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3492 attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3493 return 0;
3494
3495 /* no mclk on APUs other than gc 9,4,3*/
3496 if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) &&
3497 (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3498 attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3499 return 0;
3500
3501 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3502 (gc_ver != IP_VERSION(9, 4, 3) && gc_ver != IP_VERSION(9, 4, 4)) &&
3503 (attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3504 attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3505 attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3506 attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3507 attr == &sensor_dev_attr_temp3_label.dev_attr.attr ||
3508 attr == &sensor_dev_attr_temp3_crit.dev_attr.attr))
3509 return 0;
3510
3511 /* hotspot temperature for gc 9,4,3*/
3512 if (gc_ver == IP_VERSION(9, 4, 3) ||
3513 gc_ver == IP_VERSION(9, 4, 4) ||
3514 gc_ver == IP_VERSION(9, 5, 0)) {
3515 if (attr == &sensor_dev_attr_temp1_input.dev_attr.attr ||
3516 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3517 attr == &sensor_dev_attr_temp1_label.dev_attr.attr)
3518 return 0;
3519
3520 if (attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3521 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr)
3522 return attr->mode;
3523 }
3524
3525 /* only SOC15 dGPUs support hotspot and mem temperatures */
3526 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3527 (attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3528 attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3529 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3530 attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3531 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr))
3532 return 0;
3533
3534 /* only Vangogh has fast PPT limit and power labels */
3535 if (!(gc_ver == IP_VERSION(10, 3, 1)) &&
3536 (attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3537 attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3538 attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3539 attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3540 attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3541 attr == &sensor_dev_attr_power2_label.dev_attr.attr))
3542 return 0;
3543
3544 return effective_mode;
3545 }
3546
3547 static const struct attribute_group hwmon_attrgroup = {
3548 .attrs = hwmon_attributes,
3549 .is_visible = hwmon_attributes_visible,
3550 };
3551
3552 static const struct attribute_group *hwmon_groups[] = {
3553 &hwmon_attrgroup,
3554 NULL
3555 };
3556
amdgpu_retrieve_od_settings(struct amdgpu_device * adev,enum pp_clock_type od_type,char * buf)3557 static int amdgpu_retrieve_od_settings(struct amdgpu_device *adev,
3558 enum pp_clock_type od_type,
3559 char *buf)
3560 {
3561 int size = 0;
3562 int ret;
3563
3564 ret = amdgpu_pm_get_access_if_active(adev);
3565 if (ret)
3566 return ret;
3567
3568 size = amdgpu_dpm_print_clock_levels(adev, od_type, buf);
3569 if (size == 0)
3570 size = sysfs_emit(buf, "\n");
3571
3572 amdgpu_pm_put_access(adev);
3573
3574 return size;
3575 }
3576
parse_input_od_command_lines(const char * buf,size_t count,u32 * type,long * params,uint32_t * num_of_params)3577 static int parse_input_od_command_lines(const char *buf,
3578 size_t count,
3579 u32 *type,
3580 long *params,
3581 uint32_t *num_of_params)
3582 {
3583 const char delimiter[3] = {' ', '\n', '\0'};
3584 uint32_t parameter_size = 0;
3585 char buf_cpy[128] = {0};
3586 char *tmp_str, *sub_str;
3587 int ret;
3588
3589 if (count > sizeof(buf_cpy) - 1)
3590 return -EINVAL;
3591
3592 memcpy(buf_cpy, buf, count);
3593 tmp_str = buf_cpy;
3594
3595 /* skip heading spaces */
3596 while (isspace(*tmp_str))
3597 tmp_str++;
3598
3599 switch (*tmp_str) {
3600 case 'c':
3601 *type = PP_OD_COMMIT_DPM_TABLE;
3602 return 0;
3603 case 'r':
3604 params[parameter_size] = *type;
3605 *num_of_params = 1;
3606 *type = PP_OD_RESTORE_DEFAULT_TABLE;
3607 return 0;
3608 default:
3609 break;
3610 }
3611
3612 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
3613 if (strlen(sub_str) == 0)
3614 continue;
3615
3616 ret = kstrtol(sub_str, 0, ¶ms[parameter_size]);
3617 if (ret)
3618 return -EINVAL;
3619 parameter_size++;
3620
3621 while (isspace(*tmp_str))
3622 tmp_str++;
3623 }
3624
3625 *num_of_params = parameter_size;
3626
3627 return 0;
3628 }
3629
3630 static int
amdgpu_distribute_custom_od_settings(struct amdgpu_device * adev,enum PP_OD_DPM_TABLE_COMMAND cmd_type,const char * in_buf,size_t count)3631 amdgpu_distribute_custom_od_settings(struct amdgpu_device *adev,
3632 enum PP_OD_DPM_TABLE_COMMAND cmd_type,
3633 const char *in_buf,
3634 size_t count)
3635 {
3636 uint32_t parameter_size = 0;
3637 long parameter[64];
3638 int ret;
3639
3640 ret = parse_input_od_command_lines(in_buf,
3641 count,
3642 &cmd_type,
3643 parameter,
3644 ¶meter_size);
3645 if (ret)
3646 return ret;
3647
3648 ret = amdgpu_pm_get_access(adev);
3649 if (ret < 0)
3650 return ret;
3651
3652 ret = amdgpu_dpm_odn_edit_dpm_table(adev,
3653 cmd_type,
3654 parameter,
3655 parameter_size);
3656 if (ret)
3657 goto err_out;
3658
3659 if (cmd_type == PP_OD_COMMIT_DPM_TABLE) {
3660 ret = amdgpu_dpm_dispatch_task(adev,
3661 AMD_PP_TASK_READJUST_POWER_STATE,
3662 NULL);
3663 if (ret)
3664 goto err_out;
3665 }
3666
3667 amdgpu_pm_put_access(adev);
3668
3669 return count;
3670
3671 err_out:
3672 amdgpu_pm_put_access(adev);
3673
3674 return ret;
3675 }
3676
3677 /**
3678 * DOC: fan_curve
3679 *
3680 * The amdgpu driver provides a sysfs API for checking and adjusting the fan
3681 * control curve line.
3682 *
3683 * Reading back the file shows you the current settings(temperature in Celsius
3684 * degree and fan speed in pwm) applied to every anchor point of the curve line
3685 * and their permitted ranges if changable.
3686 *
3687 * Writing a desired string(with the format like "anchor_point_index temperature
3688 * fan_speed_in_pwm") to the file, change the settings for the specific anchor
3689 * point accordingly.
3690 *
3691 * When you have finished the editing, write "c" (commit) to the file to commit
3692 * your changes.
3693 *
3694 * If you want to reset to the default value, write "r" (reset) to the file to
3695 * reset them
3696 *
3697 * There are two fan control modes supported: auto and manual. With auto mode,
3698 * PMFW handles the fan speed control(how fan speed reacts to ASIC temperature).
3699 * While with manual mode, users can set their own fan curve line as what
3700 * described here. Normally the ASIC is booted up with auto mode. Any
3701 * settings via this interface will switch the fan control to manual mode
3702 * implicitly.
3703 */
fan_curve_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)3704 static ssize_t fan_curve_show(struct kobject *kobj,
3705 struct kobj_attribute *attr,
3706 char *buf)
3707 {
3708 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3709 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3710
3711 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_CURVE, buf);
3712 }
3713
fan_curve_store(struct kobject * kobj,struct kobj_attribute * attr,const char * buf,size_t count)3714 static ssize_t fan_curve_store(struct kobject *kobj,
3715 struct kobj_attribute *attr,
3716 const char *buf,
3717 size_t count)
3718 {
3719 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3720 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3721
3722 return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3723 PP_OD_EDIT_FAN_CURVE,
3724 buf,
3725 count);
3726 }
3727
fan_curve_visible(struct amdgpu_device * adev)3728 static umode_t fan_curve_visible(struct amdgpu_device *adev)
3729 {
3730 umode_t umode = 0000;
3731
3732 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE)
3733 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3734
3735 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_SET)
3736 umode |= S_IWUSR;
3737
3738 return umode;
3739 }
3740
3741 /**
3742 * DOC: acoustic_limit_rpm_threshold
3743 *
3744 * The amdgpu driver provides a sysfs API for checking and adjusting the
3745 * acoustic limit in RPM for fan control.
3746 *
3747 * Reading back the file shows you the current setting and the permitted
3748 * ranges if changable.
3749 *
3750 * Writing an integer to the file, change the setting accordingly.
3751 *
3752 * When you have finished the editing, write "c" (commit) to the file to commit
3753 * your changes.
3754 *
3755 * If you want to reset to the default value, write "r" (reset) to the file to
3756 * reset them
3757 *
3758 * This setting works under auto fan control mode only. It adjusts the PMFW's
3759 * behavior about the maximum speed in RPM the fan can spin. Setting via this
3760 * interface will switch the fan control to auto mode implicitly.
3761 */
acoustic_limit_threshold_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)3762 static ssize_t acoustic_limit_threshold_show(struct kobject *kobj,
3763 struct kobj_attribute *attr,
3764 char *buf)
3765 {
3766 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3767 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3768
3769 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_LIMIT, buf);
3770 }
3771
acoustic_limit_threshold_store(struct kobject * kobj,struct kobj_attribute * attr,const char * buf,size_t count)3772 static ssize_t acoustic_limit_threshold_store(struct kobject *kobj,
3773 struct kobj_attribute *attr,
3774 const char *buf,
3775 size_t count)
3776 {
3777 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3778 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3779
3780 return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3781 PP_OD_EDIT_ACOUSTIC_LIMIT,
3782 buf,
3783 count);
3784 }
3785
acoustic_limit_threshold_visible(struct amdgpu_device * adev)3786 static umode_t acoustic_limit_threshold_visible(struct amdgpu_device *adev)
3787 {
3788 umode_t umode = 0000;
3789
3790 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE)
3791 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3792
3793 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET)
3794 umode |= S_IWUSR;
3795
3796 return umode;
3797 }
3798
3799 /**
3800 * DOC: acoustic_target_rpm_threshold
3801 *
3802 * The amdgpu driver provides a sysfs API for checking and adjusting the
3803 * acoustic target in RPM for fan control.
3804 *
3805 * Reading back the file shows you the current setting and the permitted
3806 * ranges if changable.
3807 *
3808 * Writing an integer to the file, change the setting accordingly.
3809 *
3810 * When you have finished the editing, write "c" (commit) to the file to commit
3811 * your changes.
3812 *
3813 * If you want to reset to the default value, write "r" (reset) to the file to
3814 * reset them
3815 *
3816 * This setting works under auto fan control mode only. It can co-exist with
3817 * other settings which can work also under auto mode. It adjusts the PMFW's
3818 * behavior about the maximum speed in RPM the fan can spin when ASIC
3819 * temperature is not greater than target temperature. Setting via this
3820 * interface will switch the fan control to auto mode implicitly.
3821 */
acoustic_target_threshold_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)3822 static ssize_t acoustic_target_threshold_show(struct kobject *kobj,
3823 struct kobj_attribute *attr,
3824 char *buf)
3825 {
3826 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3827 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3828
3829 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_TARGET, buf);
3830 }
3831
acoustic_target_threshold_store(struct kobject * kobj,struct kobj_attribute * attr,const char * buf,size_t count)3832 static ssize_t acoustic_target_threshold_store(struct kobject *kobj,
3833 struct kobj_attribute *attr,
3834 const char *buf,
3835 size_t count)
3836 {
3837 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3838 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3839
3840 return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3841 PP_OD_EDIT_ACOUSTIC_TARGET,
3842 buf,
3843 count);
3844 }
3845
acoustic_target_threshold_visible(struct amdgpu_device * adev)3846 static umode_t acoustic_target_threshold_visible(struct amdgpu_device *adev)
3847 {
3848 umode_t umode = 0000;
3849
3850 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE)
3851 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3852
3853 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET)
3854 umode |= S_IWUSR;
3855
3856 return umode;
3857 }
3858
3859 /**
3860 * DOC: fan_target_temperature
3861 *
3862 * The amdgpu driver provides a sysfs API for checking and adjusting the
3863 * target tempeature in Celsius degree for fan control.
3864 *
3865 * Reading back the file shows you the current setting and the permitted
3866 * ranges if changable.
3867 *
3868 * Writing an integer to the file, change the setting accordingly.
3869 *
3870 * When you have finished the editing, write "c" (commit) to the file to commit
3871 * your changes.
3872 *
3873 * If you want to reset to the default value, write "r" (reset) to the file to
3874 * reset them
3875 *
3876 * This setting works under auto fan control mode only. It can co-exist with
3877 * other settings which can work also under auto mode. Paring with the
3878 * acoustic_target_rpm_threshold setting, they define the maximum speed in
3879 * RPM the fan can spin when ASIC temperature is not greater than target
3880 * temperature. Setting via this interface will switch the fan control to
3881 * auto mode implicitly.
3882 */
fan_target_temperature_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)3883 static ssize_t fan_target_temperature_show(struct kobject *kobj,
3884 struct kobj_attribute *attr,
3885 char *buf)
3886 {
3887 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3888 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3889
3890 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_TARGET_TEMPERATURE, buf);
3891 }
3892
fan_target_temperature_store(struct kobject * kobj,struct kobj_attribute * attr,const char * buf,size_t count)3893 static ssize_t fan_target_temperature_store(struct kobject *kobj,
3894 struct kobj_attribute *attr,
3895 const char *buf,
3896 size_t count)
3897 {
3898 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3899 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3900
3901 return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3902 PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
3903 buf,
3904 count);
3905 }
3906
fan_target_temperature_visible(struct amdgpu_device * adev)3907 static umode_t fan_target_temperature_visible(struct amdgpu_device *adev)
3908 {
3909 umode_t umode = 0000;
3910
3911 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE)
3912 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3913
3914 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET)
3915 umode |= S_IWUSR;
3916
3917 return umode;
3918 }
3919
3920 /**
3921 * DOC: fan_minimum_pwm
3922 *
3923 * The amdgpu driver provides a sysfs API for checking and adjusting the
3924 * minimum fan speed in PWM.
3925 *
3926 * Reading back the file shows you the current setting and the permitted
3927 * ranges if changable.
3928 *
3929 * Writing an integer to the file, change the setting accordingly.
3930 *
3931 * When you have finished the editing, write "c" (commit) to the file to commit
3932 * your changes.
3933 *
3934 * If you want to reset to the default value, write "r" (reset) to the file to
3935 * reset them
3936 *
3937 * This setting works under auto fan control mode only. It can co-exist with
3938 * other settings which can work also under auto mode. It adjusts the PMFW's
3939 * behavior about the minimum fan speed in PWM the fan should spin. Setting
3940 * via this interface will switch the fan control to auto mode implicitly.
3941 */
fan_minimum_pwm_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)3942 static ssize_t fan_minimum_pwm_show(struct kobject *kobj,
3943 struct kobj_attribute *attr,
3944 char *buf)
3945 {
3946 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3947 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3948
3949 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_MINIMUM_PWM, buf);
3950 }
3951
fan_minimum_pwm_store(struct kobject * kobj,struct kobj_attribute * attr,const char * buf,size_t count)3952 static ssize_t fan_minimum_pwm_store(struct kobject *kobj,
3953 struct kobj_attribute *attr,
3954 const char *buf,
3955 size_t count)
3956 {
3957 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3958 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3959
3960 return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3961 PP_OD_EDIT_FAN_MINIMUM_PWM,
3962 buf,
3963 count);
3964 }
3965
fan_minimum_pwm_visible(struct amdgpu_device * adev)3966 static umode_t fan_minimum_pwm_visible(struct amdgpu_device *adev)
3967 {
3968 umode_t umode = 0000;
3969
3970 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE)
3971 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3972
3973 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET)
3974 umode |= S_IWUSR;
3975
3976 return umode;
3977 }
3978
3979 /**
3980 * DOC: fan_zero_rpm_enable
3981 *
3982 * The amdgpu driver provides a sysfs API for checking and adjusting the
3983 * zero RPM feature.
3984 *
3985 * Reading back the file shows you the current setting and the permitted
3986 * ranges if changable.
3987 *
3988 * Writing an integer to the file, change the setting accordingly.
3989 *
3990 * When you have finished the editing, write "c" (commit) to the file to commit
3991 * your changes.
3992 *
3993 * If you want to reset to the default value, write "r" (reset) to the file to
3994 * reset them.
3995 */
fan_zero_rpm_enable_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)3996 static ssize_t fan_zero_rpm_enable_show(struct kobject *kobj,
3997 struct kobj_attribute *attr,
3998 char *buf)
3999 {
4000 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
4001 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
4002
4003 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_ZERO_RPM_ENABLE, buf);
4004 }
4005
fan_zero_rpm_enable_store(struct kobject * kobj,struct kobj_attribute * attr,const char * buf,size_t count)4006 static ssize_t fan_zero_rpm_enable_store(struct kobject *kobj,
4007 struct kobj_attribute *attr,
4008 const char *buf,
4009 size_t count)
4010 {
4011 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
4012 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
4013
4014 return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
4015 PP_OD_EDIT_FAN_ZERO_RPM_ENABLE,
4016 buf,
4017 count);
4018 }
4019
fan_zero_rpm_enable_visible(struct amdgpu_device * adev)4020 static umode_t fan_zero_rpm_enable_visible(struct amdgpu_device *adev)
4021 {
4022 umode_t umode = 0000;
4023
4024 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE)
4025 umode |= S_IRUSR | S_IRGRP | S_IROTH;
4026
4027 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET)
4028 umode |= S_IWUSR;
4029
4030 return umode;
4031 }
4032
4033 /**
4034 * DOC: fan_zero_rpm_stop_temperature
4035 *
4036 * The amdgpu driver provides a sysfs API for checking and adjusting the
4037 * zero RPM stop temperature feature.
4038 *
4039 * Reading back the file shows you the current setting and the permitted
4040 * ranges if changable.
4041 *
4042 * Writing an integer to the file, change the setting accordingly.
4043 *
4044 * When you have finished the editing, write "c" (commit) to the file to commit
4045 * your changes.
4046 *
4047 * If you want to reset to the default value, write "r" (reset) to the file to
4048 * reset them.
4049 *
4050 * This setting works only if the Zero RPM setting is enabled. It adjusts the
4051 * temperature below which the fan can stop.
4052 */
fan_zero_rpm_stop_temp_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)4053 static ssize_t fan_zero_rpm_stop_temp_show(struct kobject *kobj,
4054 struct kobj_attribute *attr,
4055 char *buf)
4056 {
4057 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
4058 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
4059
4060 return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_ZERO_RPM_STOP_TEMP, buf);
4061 }
4062
fan_zero_rpm_stop_temp_store(struct kobject * kobj,struct kobj_attribute * attr,const char * buf,size_t count)4063 static ssize_t fan_zero_rpm_stop_temp_store(struct kobject *kobj,
4064 struct kobj_attribute *attr,
4065 const char *buf,
4066 size_t count)
4067 {
4068 struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
4069 struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
4070
4071 return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
4072 PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP,
4073 buf,
4074 count);
4075 }
4076
fan_zero_rpm_stop_temp_visible(struct amdgpu_device * adev)4077 static umode_t fan_zero_rpm_stop_temp_visible(struct amdgpu_device *adev)
4078 {
4079 umode_t umode = 0000;
4080
4081 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE)
4082 umode |= S_IRUSR | S_IRGRP | S_IROTH;
4083
4084 if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET)
4085 umode |= S_IWUSR;
4086
4087 return umode;
4088 }
4089
4090 static struct od_feature_set amdgpu_od_set = {
4091 .containers = {
4092 [0] = {
4093 .name = "fan_ctrl",
4094 .sub_feature = {
4095 [0] = {
4096 .name = "fan_curve",
4097 .ops = {
4098 .is_visible = fan_curve_visible,
4099 .show = fan_curve_show,
4100 .store = fan_curve_store,
4101 },
4102 },
4103 [1] = {
4104 .name = "acoustic_limit_rpm_threshold",
4105 .ops = {
4106 .is_visible = acoustic_limit_threshold_visible,
4107 .show = acoustic_limit_threshold_show,
4108 .store = acoustic_limit_threshold_store,
4109 },
4110 },
4111 [2] = {
4112 .name = "acoustic_target_rpm_threshold",
4113 .ops = {
4114 .is_visible = acoustic_target_threshold_visible,
4115 .show = acoustic_target_threshold_show,
4116 .store = acoustic_target_threshold_store,
4117 },
4118 },
4119 [3] = {
4120 .name = "fan_target_temperature",
4121 .ops = {
4122 .is_visible = fan_target_temperature_visible,
4123 .show = fan_target_temperature_show,
4124 .store = fan_target_temperature_store,
4125 },
4126 },
4127 [4] = {
4128 .name = "fan_minimum_pwm",
4129 .ops = {
4130 .is_visible = fan_minimum_pwm_visible,
4131 .show = fan_minimum_pwm_show,
4132 .store = fan_minimum_pwm_store,
4133 },
4134 },
4135 [5] = {
4136 .name = "fan_zero_rpm_enable",
4137 .ops = {
4138 .is_visible = fan_zero_rpm_enable_visible,
4139 .show = fan_zero_rpm_enable_show,
4140 .store = fan_zero_rpm_enable_store,
4141 },
4142 },
4143 [6] = {
4144 .name = "fan_zero_rpm_stop_temperature",
4145 .ops = {
4146 .is_visible = fan_zero_rpm_stop_temp_visible,
4147 .show = fan_zero_rpm_stop_temp_show,
4148 .store = fan_zero_rpm_stop_temp_store,
4149 },
4150 },
4151 },
4152 },
4153 },
4154 };
4155
od_kobj_release(struct kobject * kobj)4156 static void od_kobj_release(struct kobject *kobj)
4157 {
4158 struct od_kobj *od_kobj = container_of(kobj, struct od_kobj, kobj);
4159
4160 kfree(od_kobj);
4161 }
4162
4163 static const struct kobj_type od_ktype = {
4164 .release = od_kobj_release,
4165 .sysfs_ops = &kobj_sysfs_ops,
4166 };
4167
amdgpu_od_set_fini(struct amdgpu_device * adev)4168 static void amdgpu_od_set_fini(struct amdgpu_device *adev)
4169 {
4170 struct od_kobj *container, *container_next;
4171 struct od_attribute *attribute, *attribute_next;
4172
4173 if (list_empty(&adev->pm.od_kobj_list))
4174 return;
4175
4176 list_for_each_entry_safe(container, container_next,
4177 &adev->pm.od_kobj_list, entry) {
4178 list_del(&container->entry);
4179
4180 list_for_each_entry_safe(attribute, attribute_next,
4181 &container->attribute, entry) {
4182 list_del(&attribute->entry);
4183 sysfs_remove_file(&container->kobj,
4184 &attribute->attribute.attr);
4185 kfree(attribute);
4186 }
4187
4188 kobject_put(&container->kobj);
4189 }
4190 }
4191
amdgpu_is_od_feature_supported(struct amdgpu_device * adev,struct od_feature_ops * feature_ops)4192 static bool amdgpu_is_od_feature_supported(struct amdgpu_device *adev,
4193 struct od_feature_ops *feature_ops)
4194 {
4195 umode_t mode;
4196
4197 if (!feature_ops->is_visible)
4198 return false;
4199
4200 /*
4201 * If the feature has no user read and write mode set,
4202 * we can assume the feature is actually not supported.(?)
4203 * And the revelant sysfs interface should not be exposed.
4204 */
4205 mode = feature_ops->is_visible(adev);
4206 if (mode & (S_IRUSR | S_IWUSR))
4207 return true;
4208
4209 return false;
4210 }
4211
amdgpu_od_is_self_contained(struct amdgpu_device * adev,struct od_feature_container * container)4212 static bool amdgpu_od_is_self_contained(struct amdgpu_device *adev,
4213 struct od_feature_container *container)
4214 {
4215 int i;
4216
4217 /*
4218 * If there is no valid entry within the container, the container
4219 * is recognized as a self contained container. And the valid entry
4220 * here means it has a valid naming and it is visible/supported by
4221 * the ASIC.
4222 */
4223 for (i = 0; i < ARRAY_SIZE(container->sub_feature); i++) {
4224 if (container->sub_feature[i].name &&
4225 amdgpu_is_od_feature_supported(adev,
4226 &container->sub_feature[i].ops))
4227 return false;
4228 }
4229
4230 return true;
4231 }
4232
amdgpu_od_set_init(struct amdgpu_device * adev)4233 static int amdgpu_od_set_init(struct amdgpu_device *adev)
4234 {
4235 struct od_kobj *top_set, *sub_set;
4236 struct od_attribute *attribute;
4237 struct od_feature_container *container;
4238 struct od_feature_item *feature;
4239 int i, j;
4240 int ret;
4241
4242 /* Setup the top `gpu_od` directory which holds all other OD interfaces */
4243 top_set = kzalloc(sizeof(*top_set), GFP_KERNEL);
4244 if (!top_set)
4245 return -ENOMEM;
4246 list_add(&top_set->entry, &adev->pm.od_kobj_list);
4247
4248 ret = kobject_init_and_add(&top_set->kobj,
4249 &od_ktype,
4250 &adev->dev->kobj,
4251 "%s",
4252 "gpu_od");
4253 if (ret)
4254 goto err_out;
4255 INIT_LIST_HEAD(&top_set->attribute);
4256 top_set->priv = adev;
4257
4258 for (i = 0; i < ARRAY_SIZE(amdgpu_od_set.containers); i++) {
4259 container = &amdgpu_od_set.containers[i];
4260
4261 if (!container->name)
4262 continue;
4263
4264 /*
4265 * If there is valid entries within the container, the container
4266 * will be presented as a sub directory and all its holding entries
4267 * will be presented as plain files under it.
4268 * While if there is no valid entry within the container, the container
4269 * itself will be presented as a plain file under top `gpu_od` directory.
4270 */
4271 if (amdgpu_od_is_self_contained(adev, container)) {
4272 if (!amdgpu_is_od_feature_supported(adev,
4273 &container->ops))
4274 continue;
4275
4276 /*
4277 * The container is presented as a plain file under top `gpu_od`
4278 * directory.
4279 */
4280 attribute = kzalloc(sizeof(*attribute), GFP_KERNEL);
4281 if (!attribute) {
4282 ret = -ENOMEM;
4283 goto err_out;
4284 }
4285 list_add(&attribute->entry, &top_set->attribute);
4286
4287 attribute->attribute.attr.mode =
4288 container->ops.is_visible(adev);
4289 attribute->attribute.attr.name = container->name;
4290 attribute->attribute.show =
4291 container->ops.show;
4292 attribute->attribute.store =
4293 container->ops.store;
4294 ret = sysfs_create_file(&top_set->kobj,
4295 &attribute->attribute.attr);
4296 if (ret)
4297 goto err_out;
4298 } else {
4299 /* The container is presented as a sub directory. */
4300 sub_set = kzalloc(sizeof(*sub_set), GFP_KERNEL);
4301 if (!sub_set) {
4302 ret = -ENOMEM;
4303 goto err_out;
4304 }
4305 list_add(&sub_set->entry, &adev->pm.od_kobj_list);
4306
4307 ret = kobject_init_and_add(&sub_set->kobj,
4308 &od_ktype,
4309 &top_set->kobj,
4310 "%s",
4311 container->name);
4312 if (ret)
4313 goto err_out;
4314 INIT_LIST_HEAD(&sub_set->attribute);
4315 sub_set->priv = adev;
4316
4317 for (j = 0; j < ARRAY_SIZE(container->sub_feature); j++) {
4318 feature = &container->sub_feature[j];
4319 if (!feature->name)
4320 continue;
4321
4322 if (!amdgpu_is_od_feature_supported(adev,
4323 &feature->ops))
4324 continue;
4325
4326 /*
4327 * With the container presented as a sub directory, the entry within
4328 * it is presented as a plain file under the sub directory.
4329 */
4330 attribute = kzalloc(sizeof(*attribute), GFP_KERNEL);
4331 if (!attribute) {
4332 ret = -ENOMEM;
4333 goto err_out;
4334 }
4335 list_add(&attribute->entry, &sub_set->attribute);
4336
4337 attribute->attribute.attr.mode =
4338 feature->ops.is_visible(adev);
4339 attribute->attribute.attr.name = feature->name;
4340 attribute->attribute.show =
4341 feature->ops.show;
4342 attribute->attribute.store =
4343 feature->ops.store;
4344 ret = sysfs_create_file(&sub_set->kobj,
4345 &attribute->attribute.attr);
4346 if (ret)
4347 goto err_out;
4348 }
4349 }
4350 }
4351
4352 /*
4353 * If gpu_od is the only member in the list, that means gpu_od is an
4354 * empty directory, so remove it.
4355 */
4356 if (list_is_singular(&adev->pm.od_kobj_list))
4357 goto err_out;
4358
4359 return 0;
4360
4361 err_out:
4362 amdgpu_od_set_fini(adev);
4363
4364 return ret;
4365 }
4366
amdgpu_pm_sysfs_init(struct amdgpu_device * adev)4367 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
4368 {
4369 enum amdgpu_sriov_vf_mode mode;
4370 uint32_t mask = 0;
4371 int ret;
4372
4373 if (adev->pm.sysfs_initialized)
4374 return 0;
4375
4376 INIT_LIST_HEAD(&adev->pm.pm_attr_list);
4377
4378 if (adev->pm.dpm_enabled == 0)
4379 return 0;
4380
4381 mode = amdgpu_virt_get_sriov_vf_mode(adev);
4382
4383 /* under multi-vf mode, the hwmon attributes are all not supported */
4384 if (mode != SRIOV_VF_MODE_MULTI_VF) {
4385 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
4386 DRIVER_NAME, adev,
4387 hwmon_groups);
4388 if (IS_ERR(adev->pm.int_hwmon_dev)) {
4389 ret = PTR_ERR(adev->pm.int_hwmon_dev);
4390 dev_err(adev->dev, "Unable to register hwmon device: %d\n", ret);
4391 return ret;
4392 }
4393 }
4394
4395 switch (mode) {
4396 case SRIOV_VF_MODE_ONE_VF:
4397 mask = ATTR_FLAG_ONEVF;
4398 break;
4399 case SRIOV_VF_MODE_MULTI_VF:
4400 mask = 0;
4401 break;
4402 case SRIOV_VF_MODE_BARE_METAL:
4403 default:
4404 mask = ATTR_FLAG_MASK_ALL;
4405 break;
4406 }
4407
4408 ret = amdgpu_device_attr_create_groups(adev,
4409 amdgpu_device_attrs,
4410 ARRAY_SIZE(amdgpu_device_attrs),
4411 mask,
4412 &adev->pm.pm_attr_list);
4413 if (ret)
4414 goto err_out0;
4415
4416 if (amdgpu_dpm_is_overdrive_supported(adev)) {
4417 ret = amdgpu_od_set_init(adev);
4418 if (ret)
4419 goto err_out1;
4420 } else if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) {
4421 dev_info(adev->dev, "overdrive feature is not supported\n");
4422 }
4423
4424 if (amdgpu_dpm_get_pm_policy_info(adev, PP_PM_POLICY_NONE, NULL) !=
4425 -EOPNOTSUPP) {
4426 ret = devm_device_add_group(adev->dev,
4427 &amdgpu_pm_policy_attr_group);
4428 if (ret)
4429 goto err_out0;
4430 }
4431
4432 adev->pm.sysfs_initialized = true;
4433
4434 return 0;
4435
4436 err_out1:
4437 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
4438 err_out0:
4439 if (adev->pm.int_hwmon_dev)
4440 hwmon_device_unregister(adev->pm.int_hwmon_dev);
4441
4442 return ret;
4443 }
4444
amdgpu_pm_sysfs_fini(struct amdgpu_device * adev)4445 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
4446 {
4447 amdgpu_od_set_fini(adev);
4448
4449 if (adev->pm.int_hwmon_dev)
4450 hwmon_device_unregister(adev->pm.int_hwmon_dev);
4451
4452 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
4453 }
4454
4455 /*
4456 * Debugfs info
4457 */
4458 #if defined(CONFIG_DEBUG_FS)
4459
amdgpu_debugfs_prints_cpu_info(struct seq_file * m,struct amdgpu_device * adev)4460 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
4461 struct amdgpu_device *adev)
4462 {
4463 uint16_t *p_val;
4464 uint32_t size;
4465 int i;
4466 uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev);
4467
4468 if (amdgpu_dpm_is_cclk_dpm_supported(adev)) {
4469 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t),
4470 GFP_KERNEL);
4471
4472 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
4473 (void *)p_val, &size)) {
4474 for (i = 0; i < num_cpu_cores; i++)
4475 seq_printf(m, "\t%u MHz (CPU%d)\n",
4476 *(p_val + i), i);
4477 }
4478
4479 kfree(p_val);
4480 }
4481 }
4482
amdgpu_debugfs_pm_info_pp(struct seq_file * m,struct amdgpu_device * adev)4483 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
4484 {
4485 uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0);
4486 uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
4487 uint32_t value;
4488 uint64_t value64 = 0;
4489 uint32_t query = 0;
4490 int size;
4491
4492 /* GPU Clocks */
4493 size = sizeof(value);
4494 seq_printf(m, "GFX Clocks and Power:\n");
4495
4496 amdgpu_debugfs_prints_cpu_info(m, adev);
4497
4498 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
4499 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
4500 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
4501 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
4502 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
4503 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
4504 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
4505 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
4506 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
4507 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
4508 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
4509 seq_printf(m, "\t%u mV (VDDNB)\n", value);
4510 size = sizeof(uint32_t);
4511 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&query, &size)) {
4512 if (adev->flags & AMD_IS_APU)
4513 seq_printf(m, "\t%u.%02u W (average SoC including CPU)\n", query >> 8, query & 0xff);
4514 else
4515 seq_printf(m, "\t%u.%02u W (average SoC)\n", query >> 8, query & 0xff);
4516 }
4517 size = sizeof(uint32_t);
4518 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&query, &size)) {
4519 if (adev->flags & AMD_IS_APU)
4520 seq_printf(m, "\t%u.%02u W (current SoC including CPU)\n", query >> 8, query & 0xff);
4521 else
4522 seq_printf(m, "\t%u.%02u W (current SoC)\n", query >> 8, query & 0xff);
4523 }
4524 size = sizeof(value);
4525 seq_printf(m, "\n");
4526
4527 /* GPU Temp */
4528 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
4529 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
4530
4531 /* GPU Load */
4532 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
4533 seq_printf(m, "GPU Load: %u %%\n", value);
4534 /* MEM Load */
4535 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
4536 seq_printf(m, "MEM Load: %u %%\n", value);
4537 /* VCN Load */
4538 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_LOAD, (void *)&value, &size))
4539 seq_printf(m, "VCN Load: %u %%\n", value);
4540
4541 seq_printf(m, "\n");
4542
4543 /* SMC feature mask */
4544 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
4545 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
4546
4547 /* ASICs greater than CHIP_VEGA20 supports these sensors */
4548 if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) {
4549 /* VCN clocks */
4550 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
4551 if (!value) {
4552 seq_printf(m, "VCN: Powered down\n");
4553 } else {
4554 seq_printf(m, "VCN: Powered up\n");
4555 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
4556 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
4557 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
4558 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
4559 }
4560 }
4561 seq_printf(m, "\n");
4562 } else {
4563 /* UVD clocks */
4564 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
4565 if (!value) {
4566 seq_printf(m, "UVD: Powered down\n");
4567 } else {
4568 seq_printf(m, "UVD: Powered up\n");
4569 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
4570 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
4571 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
4572 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
4573 }
4574 }
4575 seq_printf(m, "\n");
4576
4577 /* VCE clocks */
4578 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
4579 if (!value) {
4580 seq_printf(m, "VCE: Powered down\n");
4581 } else {
4582 seq_printf(m, "VCE: Powered up\n");
4583 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
4584 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
4585 }
4586 }
4587 }
4588
4589 return 0;
4590 }
4591
4592 static const struct cg_flag_name clocks[] = {
4593 {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
4594 {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
4595 {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
4596 {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
4597 {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
4598 {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
4599 {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
4600 {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
4601 {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
4602 {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
4603 {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
4604 {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
4605 {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
4606 {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
4607 {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
4608 {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
4609 {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
4610 {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
4611 {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
4612 {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
4613 {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
4614 {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
4615 {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
4616 {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
4617 {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
4618 {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
4619 {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
4620 {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
4621 {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
4622 {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
4623 {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"},
4624 {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"},
4625 {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
4626 {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
4627 {0, NULL},
4628 };
4629
amdgpu_parse_cg_state(struct seq_file * m,u64 flags)4630 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags)
4631 {
4632 int i;
4633
4634 for (i = 0; clocks[i].flag; i++)
4635 seq_printf(m, "\t%s: %s\n", clocks[i].name,
4636 (flags & clocks[i].flag) ? "On" : "Off");
4637 }
4638
amdgpu_debugfs_pm_info_show(struct seq_file * m,void * unused)4639 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
4640 {
4641 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
4642 u64 flags = 0;
4643 int r;
4644
4645 r = amdgpu_pm_get_access(adev);
4646 if (r < 0)
4647 return r;
4648
4649 if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) {
4650 r = amdgpu_debugfs_pm_info_pp(m, adev);
4651 if (r)
4652 goto out;
4653 }
4654
4655 amdgpu_device_ip_get_clockgating_state(adev, &flags);
4656
4657 seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags);
4658 amdgpu_parse_cg_state(m, flags);
4659 seq_printf(m, "\n");
4660
4661 out:
4662 amdgpu_pm_put_access(adev);
4663
4664 return r;
4665 }
4666
4667 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
4668
4669 /*
4670 * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
4671 *
4672 * Reads debug memory region allocated to PMFW
4673 */
amdgpu_pm_prv_buffer_read(struct file * f,char __user * buf,size_t size,loff_t * pos)4674 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
4675 size_t size, loff_t *pos)
4676 {
4677 struct amdgpu_device *adev = file_inode(f)->i_private;
4678 size_t smu_prv_buf_size;
4679 void *smu_prv_buf;
4680 int ret = 0;
4681
4682 ret = amdgpu_pm_dev_state_check(adev, true);
4683 if (ret)
4684 return ret;
4685
4686 ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size);
4687 if (ret)
4688 return ret;
4689
4690 if (!smu_prv_buf || !smu_prv_buf_size)
4691 return -EINVAL;
4692
4693 return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
4694 smu_prv_buf_size);
4695 }
4696
4697 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
4698 .owner = THIS_MODULE,
4699 .open = simple_open,
4700 .read = amdgpu_pm_prv_buffer_read,
4701 .llseek = default_llseek,
4702 };
4703
4704 #endif
4705
amdgpu_debugfs_pm_init(struct amdgpu_device * adev)4706 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
4707 {
4708 #if defined(CONFIG_DEBUG_FS)
4709 struct drm_minor *minor = adev_to_drm(adev)->primary;
4710 struct dentry *root = minor->debugfs_root;
4711
4712 if (!adev->pm.dpm_enabled)
4713 return;
4714
4715 debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
4716 &amdgpu_debugfs_pm_info_fops);
4717
4718 if (adev->pm.smu_prv_buffer_size > 0)
4719 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
4720 adev,
4721 &amdgpu_debugfs_pm_prv_buffer_fops,
4722 adev->pm.smu_prv_buffer_size);
4723
4724 amdgpu_dpm_stb_debug_fs_init(adev);
4725 #endif
4726 }
4727