1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 #ifndef __AMDGPU_GMC_H__ 27 #define __AMDGPU_GMC_H__ 28 29 #include <linux/types.h> 30 31 #include "amdgpu_irq.h" 32 #include "amdgpu_xgmi.h" 33 #include "amdgpu_ras.h" 34 35 /* VA hole for 48bit and 57bit addresses */ 36 #define AMDGPU_GMC_HOLE_START (adev->vm_manager.max_level == 4 ?\ 37 0x0100000000000000ULL : 0x0000800000000000ULL) 38 #define AMDGPU_GMC_HOLE_END (adev->vm_manager.max_level == 4 ?\ 39 0xff00000000000000ULL : 0xffff800000000000ULL) 40 41 /* 42 * Hardware is programmed as if the hole doesn't exists with start and end 43 * address values. 44 * 45 * This mask is used to remove the upper 16bits of the VA and so come up with 46 * the linear addr value. 47 */ 48 #define AMDGPU_GMC_HOLE_MASK (adev->vm_manager.max_level == 4 ?\ 49 0x01ffffffffffffffULL : 0x0000ffffffffffffULL) 50 51 /* 52 * Ring size as power of two for the log of recent faults. 53 */ 54 #define AMDGPU_GMC_FAULT_RING_ORDER 8 55 #define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER) 56 57 /* 58 * Hash size as power of two for the log of recent faults 59 */ 60 #define AMDGPU_GMC_FAULT_HASH_ORDER 8 61 #define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER) 62 63 /* 64 * Number of IH timestamp ticks until a fault is considered handled 65 */ 66 #define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL 67 68 /* XNACK flags */ 69 #define AMDGPU_GMC_XNACK_FLAG_CHAIN BIT(0) 70 71 struct firmware; 72 73 enum amdgpu_memory_partition { 74 UNKNOWN_MEMORY_PARTITION_MODE = 0, 75 AMDGPU_NPS1_PARTITION_MODE = 1, 76 AMDGPU_NPS2_PARTITION_MODE = 2, 77 AMDGPU_NPS3_PARTITION_MODE = 3, 78 AMDGPU_NPS4_PARTITION_MODE = 4, 79 AMDGPU_NPS6_PARTITION_MODE = 6, 80 AMDGPU_NPS8_PARTITION_MODE = 8, 81 }; 82 83 #define AMDGPU_ALL_NPS_MASK \ 84 (BIT(AMDGPU_NPS1_PARTITION_MODE) | BIT(AMDGPU_NPS2_PARTITION_MODE) | \ 85 BIT(AMDGPU_NPS3_PARTITION_MODE) | BIT(AMDGPU_NPS4_PARTITION_MODE) | \ 86 BIT(AMDGPU_NPS6_PARTITION_MODE) | BIT(AMDGPU_NPS8_PARTITION_MODE)) 87 88 #define AMDGPU_GMC_INIT_RESET_NPS BIT(0) 89 90 #define AMDGPU_MAX_MEM_RANGES 8 91 92 #define AMDGPU_GMC9_FAULT_SOURCE_DATA_RETRY 0x80 93 #define AMDGPU_GMC9_FAULT_SOURCE_DATA_READ 0x40 94 #define AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE 0x20 95 #define AMDGPU_GMC9_FAULT_SOURCE_DATA_EXE 0x10 96 97 #define AMDGPU_GMC121_FAULT_SOURCE_DATA_READ 0x400000 98 #define AMDGPU_GMC121_FAULT_SOURCE_DATA_WRITE 0x200000 99 #define AMDGPU_GMC121_FAULT_SOURCE_DATA_EXE 0x100000 100 101 /* 102 * GMC page fault information 103 */ 104 struct amdgpu_gmc_fault { 105 uint64_t timestamp:48; 106 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER; 107 atomic64_t key; 108 uint64_t timestamp_expiry:48; 109 }; 110 111 /* 112 * VMHUB structures, functions & helpers 113 */ 114 struct amdgpu_vmhub_funcs { 115 void (*print_l2_protection_fault_status)(struct amdgpu_device *adev, 116 uint32_t status); 117 uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type); 118 }; 119 120 struct amdgpu_vmhub { 121 uint32_t ctx0_ptb_addr_lo32; 122 uint32_t ctx0_ptb_addr_hi32; 123 uint32_t vm_inv_eng0_sem; 124 uint32_t vm_inv_eng0_req; 125 uint32_t vm_inv_eng0_ack; 126 uint32_t vm_context0_cntl; 127 uint32_t vm_l2_pro_fault_status; 128 uint32_t vm_l2_pro_fault_cntl; 129 130 /* 131 * store the register distances between two continuous context domain 132 * and invalidation engine. 133 */ 134 uint32_t ctx_distance; 135 uint32_t ctx_addr_distance; /* include LO32/HI32 */ 136 uint32_t eng_distance; 137 uint32_t eng_addr_distance; /* include LO32/HI32 */ 138 139 uint32_t vm_cntx_cntl; 140 uint32_t vm_cntx_cntl_vm_fault; 141 uint32_t vm_l2_bank_select_reserved_cid2; 142 143 uint32_t vm_contexts_disable; 144 145 bool sdma_invalidation_workaround; 146 147 const struct amdgpu_vmhub_funcs *vmhub_funcs; 148 }; 149 150 /* 151 * GPU MC structures, functions & helpers 152 */ 153 struct amdgpu_gmc_funcs { 154 /* flush the vm tlb via mmio */ 155 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid, 156 uint32_t vmhub, uint32_t flush_type); 157 /* flush the vm tlb via pasid */ 158 void (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid, 159 uint32_t flush_type, bool all_hub, 160 uint32_t inst); 161 /* flush the vm tlb via ring */ 162 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid, 163 uint64_t pd_addr); 164 /* Change the VMID -> PASID mapping */ 165 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid, 166 unsigned pasid); 167 /* enable/disable PRT support */ 168 void (*set_prt)(struct amdgpu_device *adev, bool enable); 169 /* get the pde for a given mc addr */ 170 void (*get_vm_pde)(struct amdgpu_device *adev, int level, 171 u64 *dst, u64 *flags); 172 /* get the pte flags to use for PTEs */ 173 void (*get_vm_pte)(struct amdgpu_device *adev, 174 struct amdgpu_vm *vm, 175 struct amdgpu_bo *bo, 176 uint32_t vm_flags, 177 uint64_t *pte_flags); 178 /* override per-page pte flags */ 179 void (*override_vm_pte_flags)(struct amdgpu_device *dev, 180 struct amdgpu_vm *vm, 181 uint64_t addr, uint64_t *flags); 182 /* get the amount of memory used by the vbios for pre-OS console */ 183 unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev); 184 /* get the DCC buffer alignment */ 185 unsigned int (*get_dcc_alignment)(struct amdgpu_device *adev); 186 187 enum amdgpu_memory_partition (*query_mem_partition_mode)( 188 struct amdgpu_device *adev); 189 /* Request NPS mode */ 190 int (*request_mem_partition_mode)(struct amdgpu_device *adev, 191 int nps_mode); 192 bool (*need_reset_on_init)(struct amdgpu_device *adev); 193 }; 194 195 struct amdgpu_mem_partition_info { 196 union { 197 struct { 198 uint32_t fpfn; 199 uint32_t lpfn; 200 } range; 201 struct { 202 int node; 203 } numa; 204 }; 205 uint64_t size; 206 }; 207 208 #define INVALID_PFN -1 209 210 struct amdgpu_gmc_memrange { 211 uint64_t base_address; 212 uint64_t limit_address; 213 uint32_t flags; 214 int nid_mask; 215 }; 216 217 enum amdgpu_gart_placement { 218 AMDGPU_GART_PLACEMENT_BEST_FIT = 0, 219 AMDGPU_GART_PLACEMENT_HIGH, 220 AMDGPU_GART_PLACEMENT_LOW, 221 }; 222 223 struct amdgpu_gmc { 224 /* FB's physical address in MMIO space (for CPU to 225 * map FB). This is different compared to the agp/ 226 * gart/vram_start/end field as the later is from 227 * GPU's view and aper_base is from CPU's view. 228 */ 229 resource_size_t aper_size; 230 resource_size_t aper_base; 231 /* for some chips with <= 32MB we need to lie 232 * about vram size near mc fb location */ 233 u64 mc_vram_size; 234 u64 visible_vram_size; 235 /* AGP aperture start and end in MC address space 236 * Driver find a hole in the MC address space 237 * to place AGP by setting MC_VM_AGP_BOT/TOP registers 238 * Under VMID0, logical address == MC address. AGP 239 * aperture maps to physical bus or IOVA addressed. 240 * AGP aperture is used to simulate FB in ZFB case. 241 * AGP aperture is also used for page table in system 242 * memory (mainly for APU). 243 * 244 */ 245 u64 agp_size; 246 u64 agp_start; 247 u64 agp_end; 248 /* GART aperture start and end in MC address space 249 * Driver find a hole in the MC address space 250 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR 251 * registers 252 * Under VMID0, logical address inside GART aperture will 253 * be translated through gpuvm gart page table to access 254 * paged system memory 255 */ 256 u64 gart_size; 257 u64 gart_start; 258 u64 gart_end; 259 /* Frame buffer aperture of this GPU device. Different from 260 * fb_start (see below), this only covers the local GPU device. 261 * If driver uses FB aperture to access FB, driver get fb_start from 262 * MC_VM_FB_LOCATION_BASE (set by vbios) and calculate vram_start 263 * of this local device by adding an offset inside the XGMI hive. 264 * If driver uses GART table for VMID0 FB access, driver finds a hole in 265 * VMID0's virtual address space to place the SYSVM aperture inside 266 * which the first part is vram and the second part is gart (covering 267 * system ram). 268 */ 269 u64 vram_start; 270 u64 vram_end; 271 /* FB region , it's same as local vram region in single GPU, in XGMI 272 * configuration, this region covers all GPUs in the same hive , 273 * each GPU in the hive has the same view of this FB region . 274 * GPU0's vram starts at offset (0 * segment size) , 275 * GPU1 starts at offset (1 * segment size), etc. 276 */ 277 u64 fb_start; 278 u64 fb_end; 279 unsigned vram_width; 280 u64 real_vram_size; 281 int vram_mtrr; 282 u64 mc_mask; 283 const struct firmware *fw; /* MC firmware */ 284 uint32_t fw_version; 285 struct amdgpu_irq_src vm_fault; 286 uint32_t vram_type; 287 uint8_t vram_vendor; 288 uint32_t srbm_soft_reset; 289 bool prt_warning; 290 uint32_t sdpif_register; 291 /* apertures */ 292 u64 shared_aperture_start; 293 u64 shared_aperture_end; 294 u64 private_aperture_start; 295 u64 private_aperture_end; 296 /* protects concurrent invalidation */ 297 spinlock_t invalidate_lock; 298 bool translate_further; 299 struct kfd_vm_fault_info *vm_fault_info; 300 atomic_t vm_fault_info_updated; 301 302 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE]; 303 struct { 304 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER; 305 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE]; 306 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER; 307 308 bool tmz_enabled; 309 bool is_app_apu; 310 311 struct amdgpu_mem_partition_info *mem_partitions; 312 uint8_t num_mem_partitions; 313 const struct amdgpu_gmc_funcs *gmc_funcs; 314 enum amdgpu_memory_partition requested_nps_mode; 315 uint32_t supported_nps_modes; 316 uint32_t reset_flags; 317 318 struct amdgpu_xgmi xgmi; 319 struct amdgpu_irq_src ecc_irq; 320 int noretry; 321 uint32_t xnack_flags; 322 323 uint32_t vmid0_page_table_block_size; 324 uint32_t vmid0_page_table_depth; 325 struct amdgpu_bo *pdb0_bo; 326 /* CPU kmapped address of pdb0*/ 327 void *ptr_pdb0; 328 329 /* MALL size */ 330 u64 mall_size; 331 uint32_t m_half_use; 332 333 /* number of UMC instances */ 334 int num_umc; 335 /* mode2 save restore */ 336 u64 VM_L2_CNTL; 337 u64 VM_L2_CNTL2; 338 u64 VM_DUMMY_PAGE_FAULT_CNTL; 339 u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32; 340 u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32; 341 u64 VM_L2_PROTECTION_FAULT_CNTL; 342 u64 VM_L2_PROTECTION_FAULT_CNTL2; 343 u64 VM_L2_PROTECTION_FAULT_MM_CNTL3; 344 u64 VM_L2_PROTECTION_FAULT_MM_CNTL4; 345 u64 VM_L2_PROTECTION_FAULT_ADDR_LO32; 346 u64 VM_L2_PROTECTION_FAULT_ADDR_HI32; 347 u64 VM_DEBUG; 348 u64 VM_L2_MM_GROUP_RT_CLASSES; 349 u64 VM_L2_BANK_SELECT_RESERVED_CID; 350 u64 VM_L2_BANK_SELECT_RESERVED_CID2; 351 u64 VM_L2_CACHE_PARITY_CNTL; 352 u64 VM_L2_IH_LOG_CNTL; 353 u64 VM_CONTEXT_CNTL[16]; 354 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16]; 355 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16]; 356 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16]; 357 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16]; 358 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16]; 359 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16]; 360 u64 MC_VM_MX_L1_TLB_CNTL; 361 362 u64 noretry_flags; 363 u64 init_pte_flags; 364 365 bool flush_tlb_needs_extra_type_0; 366 bool flush_tlb_needs_extra_type_2; 367 bool flush_pasid_uses_kiq; 368 }; 369 370 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) 371 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) 372 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) 373 #define amdgpu_gmc_get_vm_pte(adev, vm, bo, vm_flags, pte_flags) \ 374 ((adev)->gmc.gmc_funcs->get_vm_pte((adev), (vm), (bo), (vm_flags), \ 375 (pte_flags))) 376 #define amdgpu_gmc_override_vm_pte_flags(adev, vm, addr, pte_flags) \ 377 (adev)->gmc.gmc_funcs->override_vm_pte_flags \ 378 ((adev), (vm), (addr), (pte_flags)) 379 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev)) 380 #define amdgpu_gmc_get_dcc_alignment(adev) ({ \ 381 typeof(adev) _adev = (adev); \ 382 _adev->gmc.gmc_funcs->get_dcc_alignment(_adev); \ 383 }) 384 385 /** 386 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR 387 * 388 * @adev: amdgpu_device pointer 389 * 390 * Returns: 391 * True if full VRAM is visible through the BAR 392 */ 393 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) 394 { 395 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size); 396 397 return (gmc->real_vram_size == gmc->visible_vram_size); 398 } 399 400 /** 401 * amdgpu_gmc_sign_extend - sign extend the given gmc address 402 * 403 * @addr: address to extend 404 */ 405 #define amdgpu_gmc_sign_extend(addr) ((addr) >= AMDGPU_GMC_HOLE_START ?\ 406 ((addr) | AMDGPU_GMC_HOLE_END) : (addr)) 407 408 bool amdgpu_gmc_is_pdb0_enabled(struct amdgpu_device *adev); 409 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev); 410 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 411 uint64_t *addr, uint64_t *flags); 412 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 413 uint32_t gpu_page_idx, uint64_t addr, 414 uint64_t flags); 415 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo); 416 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo); 417 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc); 418 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 419 u64 base); 420 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, 421 struct amdgpu_gmc *mc, 422 enum amdgpu_gart_placement gart_placement); 423 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, 424 struct amdgpu_gmc *mc); 425 void amdgpu_gmc_set_agp_default(struct amdgpu_device *adev, 426 struct amdgpu_gmc *mc); 427 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, 428 struct amdgpu_ih_ring *ih, uint64_t addr, 429 uint16_t pasid, uint64_t timestamp); 430 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 431 uint16_t pasid); 432 int amdgpu_gmc_handle_retry_fault(struct amdgpu_device *adev, 433 struct amdgpu_iv_entry *entry, 434 u64 addr, 435 u32 cam_index, 436 u32 node_id, 437 bool write_fault); 438 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev); 439 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev); 440 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev); 441 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev); 442 void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 443 uint32_t vmhub, uint32_t flush_type); 444 int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, 445 uint32_t flush_type, bool all_hub, 446 uint32_t inst); 447 void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev, 448 uint32_t reg0, uint32_t reg1, 449 uint32_t ref, uint32_t mask, 450 uint32_t xcc_inst); 451 452 extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev); 453 extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev); 454 455 extern void 456 amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 457 bool enable); 458 459 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev); 460 461 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev); 462 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr); 463 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); 464 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev); 465 int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev); 466 void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev); 467 468 int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, 469 struct amdgpu_mem_partition_info *mem_ranges, 470 uint8_t *exp_ranges); 471 472 int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev, 473 int nps_mode); 474 void amdgpu_gmc_prepare_nps_mode_change(struct amdgpu_device *adev); 475 bool amdgpu_gmc_need_reset_on_init(struct amdgpu_device *adev); 476 enum amdgpu_memory_partition 477 amdgpu_gmc_get_vf_memory_partition(struct amdgpu_device *adev); 478 enum amdgpu_memory_partition 479 amdgpu_gmc_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes); 480 enum amdgpu_memory_partition 481 amdgpu_gmc_query_memory_partition(struct amdgpu_device *adev); 482 int amdgpu_gmc_init_mem_ranges(struct amdgpu_device *adev); 483 void amdgpu_gmc_init_sw_mem_ranges(struct amdgpu_device *adev, 484 struct amdgpu_mem_partition_info *mem_ranges); 485 int amdgpu_gmc_get_vram_info(struct amdgpu_device *adev, 486 int *vram_width, int *vram_type, int *vram_vendor); 487 #endif 488