1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * based on nouveau_prime.c
23 *
24 * Authors: Alex Deucher
25 */
26
27 /**
28 * DOC: PRIME Buffer Sharing
29 *
30 * The following callback implementations are used for :ref:`sharing GEM buffer
31 * objects between different devices via PRIME <prime_buffer_sharing>`.
32 */
33
34 #include "amdgpu.h"
35 #include "amdgpu_display.h"
36 #include "amdgpu_gem.h"
37 #include "amdgpu_dma_buf.h"
38 #include "amdgpu_xgmi.h"
39 #include <drm/amdgpu_drm.h>
40 #include <linux/dma-buf.h>
41 #include <linux/dma-fence-array.h>
42 #include <linux/pci-p2pdma.h>
43
44 /**
45 * amdgpu_gem_prime_vmap - &dma_buf_ops.vmap implementation
46 * @obj: GEM BO
47 *
48 * Sets up an in-kernel virtual mapping of the BO's memory.
49 *
50 * Returns:
51 * The virtual address of the mapping or an error pointer.
52 */
amdgpu_gem_prime_vmap(struct drm_gem_object * obj)53 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj)
54 {
55 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
56 int ret;
57
58 ret = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages,
59 &bo->dma_buf_vmap);
60 if (ret)
61 return ERR_PTR(ret);
62
63 return bo->dma_buf_vmap.virtual;
64 }
65
66 /**
67 * amdgpu_gem_prime_vunmap - &dma_buf_ops.vunmap implementation
68 * @obj: GEM BO
69 * @vaddr: Virtual address (unused)
70 *
71 * Tears down the in-kernel virtual mapping of the BO's memory.
72 */
amdgpu_gem_prime_vunmap(struct drm_gem_object * obj,void * vaddr)73 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
74 {
75 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
76
77 ttm_bo_kunmap(&bo->dma_buf_vmap);
78 }
79
80 /**
81 * amdgpu_gem_prime_mmap - &drm_driver.gem_prime_mmap implementation
82 * @obj: GEM BO
83 * @vma: Virtual memory area
84 *
85 * Sets up a userspace mapping of the BO's memory in the given
86 * virtual memory area.
87 *
88 * Returns:
89 * 0 on success or a negative error code on failure.
90 */
amdgpu_gem_prime_mmap(struct drm_gem_object * obj,struct vm_area_struct * vma)91 int amdgpu_gem_prime_mmap(struct drm_gem_object *obj,
92 struct vm_area_struct *vma)
93 {
94 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
95 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
96 unsigned asize = amdgpu_bo_size(bo);
97 int ret;
98
99 if (!vma->vm_file)
100 return -ENODEV;
101
102 if (adev == NULL)
103 return -ENODEV;
104
105 /* Check for valid size. */
106 if (asize < vma->vm_end - vma->vm_start)
107 return -EINVAL;
108
109 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
110 (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
111 return -EPERM;
112 }
113 vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT;
114
115 /* prime mmap does not need to check access, so allow here */
116 ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data);
117 if (ret)
118 return ret;
119
120 ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev);
121 drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data);
122
123 return ret;
124 }
125
126 static int
__dma_resv_make_exclusive(struct dma_resv * obj)127 __dma_resv_make_exclusive(struct dma_resv *obj)
128 {
129 struct dma_fence **fences;
130 unsigned int count;
131 int r;
132
133 if (!dma_resv_get_list(obj)) /* no shared fences to convert */
134 return 0;
135
136 r = dma_resv_get_fences_rcu(obj, NULL, &count, &fences);
137 if (r)
138 return r;
139
140 if (count == 0) {
141 /* Now that was unexpected. */
142 } else if (count == 1) {
143 dma_resv_add_excl_fence(obj, fences[0]);
144 dma_fence_put(fences[0]);
145 kfree(fences);
146 } else {
147 struct dma_fence_array *array;
148
149 array = dma_fence_array_create(count, fences,
150 dma_fence_context_alloc(1), 0,
151 false);
152 if (!array)
153 goto err_fences_put;
154
155 dma_resv_add_excl_fence(obj, &array->base);
156 dma_fence_put(&array->base);
157 }
158
159 return 0;
160
161 err_fences_put:
162 while (count--)
163 dma_fence_put(fences[count]);
164 kfree(fences);
165 return -ENOMEM;
166 }
167
168 /**
169 * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
170 *
171 * @dmabuf: DMA-buf where we attach to
172 * @attach: attachment to add
173 *
174 * Add the attachment as user to the exported DMA-buf.
175 */
amdgpu_dma_buf_attach(struct dma_buf * dmabuf,struct dma_buf_attachment * attach)176 static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
177 struct dma_buf_attachment *attach)
178 {
179 struct drm_gem_object *obj = dmabuf->priv;
180 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
181 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
182 int r;
183
184 if (pci_p2pdma_distance_many(adev->pdev, &attach->dev, 1, true) < 0)
185 attach->peer2peer = false;
186
187 if (attach->dev->driver == adev->dev->driver)
188 return 0;
189
190 r = amdgpu_bo_reserve(bo, false);
191 if (unlikely(r != 0))
192 return r;
193
194 /*
195 * We only create shared fences for internal use, but importers
196 * of the dmabuf rely on exclusive fences for implicitly
197 * tracking write hazards. As any of the current fences may
198 * correspond to a write, we need to convert all existing
199 * fences on the reservation object into a single exclusive
200 * fence.
201 */
202 r = __dma_resv_make_exclusive(bo->tbo.base.resv);
203 if (r)
204 return r;
205
206 bo->prime_shared_count++;
207 amdgpu_bo_unreserve(bo);
208 return 0;
209 }
210
211 /**
212 * amdgpu_dma_buf_detach - &dma_buf_ops.detach implementation
213 *
214 * @dmabuf: DMA-buf where we remove the attachment from
215 * @attach: the attachment to remove
216 *
217 * Called when an attachment is removed from the DMA-buf.
218 */
amdgpu_dma_buf_detach(struct dma_buf * dmabuf,struct dma_buf_attachment * attach)219 static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf,
220 struct dma_buf_attachment *attach)
221 {
222 struct drm_gem_object *obj = dmabuf->priv;
223 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
224 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
225
226 if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count)
227 bo->prime_shared_count--;
228 }
229
230 /**
231 * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation
232 *
233 * @attach: attachment to pin down
234 *
235 * Pin the BO which is backing the DMA-buf so that it can't move any more.
236 */
amdgpu_dma_buf_pin(struct dma_buf_attachment * attach)237 static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)
238 {
239 struct drm_gem_object *obj = attach->dmabuf->priv;
240 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
241
242 /* pin buffer into GTT */
243 return amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
244 }
245
246 /**
247 * amdgpu_dma_buf_unpin - &dma_buf_ops.unpin implementation
248 *
249 * @attach: attachment to unpin
250 *
251 * Unpin a previously pinned BO to make it movable again.
252 */
amdgpu_dma_buf_unpin(struct dma_buf_attachment * attach)253 static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach)
254 {
255 struct drm_gem_object *obj = attach->dmabuf->priv;
256 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
257
258 amdgpu_bo_unpin(bo);
259 }
260
261 /**
262 * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation
263 * @attach: DMA-buf attachment
264 * @dir: DMA direction
265 *
266 * Makes sure that the shared DMA buffer can be accessed by the target device.
267 * For now, simply pins it to the GTT domain, where it should be accessible by
268 * all DMA devices.
269 *
270 * Returns:
271 * sg_table filled with the DMA addresses to use or ERR_PRT with negative error
272 * code.
273 */
amdgpu_dma_buf_map(struct dma_buf_attachment * attach,enum dma_data_direction dir)274 static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
275 enum dma_data_direction dir)
276 {
277 struct dma_buf *dma_buf = attach->dmabuf;
278 struct drm_gem_object *obj = dma_buf->priv;
279 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
280 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
281 struct sg_table *sgt;
282 long r;
283
284 if (!bo->pin_count) {
285 /* move buffer into GTT or VRAM */
286 struct ttm_operation_ctx ctx = { false, false };
287 unsigned domains = AMDGPU_GEM_DOMAIN_GTT;
288
289 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
290 attach->peer2peer) {
291 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
292 domains |= AMDGPU_GEM_DOMAIN_VRAM;
293 }
294 amdgpu_bo_placement_from_domain(bo, domains);
295 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
296 if (r)
297 return ERR_PTR(r);
298
299 } else if (!(amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type) &
300 AMDGPU_GEM_DOMAIN_GTT)) {
301 return ERR_PTR(-EBUSY);
302 }
303
304 switch (bo->tbo.mem.mem_type) {
305 case TTM_PL_TT:
306 sgt = drm_prime_pages_to_sg(obj->dev,
307 bo->tbo.ttm->pages,
308 bo->tbo.num_pages);
309 if (IS_ERR(sgt))
310 return sgt;
311
312 if (dma_map_sgtable(attach->dev, sgt, dir,
313 DMA_ATTR_SKIP_CPU_SYNC))
314 goto error_free;
315 break;
316
317 case TTM_PL_VRAM:
318 r = amdgpu_vram_mgr_alloc_sgt(adev, &bo->tbo.mem, attach->dev,
319 dir, &sgt);
320 if (r)
321 return ERR_PTR(r);
322 break;
323 default:
324 return ERR_PTR(-EINVAL);
325 }
326
327 return sgt;
328
329 error_free:
330 sg_free_table(sgt);
331 kfree(sgt);
332 return ERR_PTR(-EBUSY);
333 }
334
335 /**
336 * amdgpu_dma_buf_unmap - &dma_buf_ops.unmap_dma_buf implementation
337 * @attach: DMA-buf attachment
338 * @sgt: sg_table to unmap
339 * @dir: DMA direction
340 *
341 * This is called when a shared DMA buffer no longer needs to be accessible by
342 * another device. For now, simply unpins the buffer from GTT.
343 */
amdgpu_dma_buf_unmap(struct dma_buf_attachment * attach,struct sg_table * sgt,enum dma_data_direction dir)344 static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach,
345 struct sg_table *sgt,
346 enum dma_data_direction dir)
347 {
348 struct dma_buf *dma_buf = attach->dmabuf;
349 struct drm_gem_object *obj = dma_buf->priv;
350 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
351 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
352
353 if (sgt->sgl->page_link) {
354 dma_unmap_sgtable(attach->dev, sgt, dir, 0);
355 sg_free_table(sgt);
356 kfree(sgt);
357 } else {
358 amdgpu_vram_mgr_free_sgt(adev, attach->dev, dir, sgt);
359 }
360 }
361
362 /**
363 * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
364 * @dma_buf: Shared DMA buffer
365 * @direction: Direction of DMA transfer
366 *
367 * This is called before CPU access to the shared DMA buffer's memory. If it's
368 * a read access, the buffer is moved to the GTT domain if possible, for optimal
369 * CPU read performance.
370 *
371 * Returns:
372 * 0 on success or a negative error code on failure.
373 */
amdgpu_dma_buf_begin_cpu_access(struct dma_buf * dma_buf,enum dma_data_direction direction)374 static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
375 enum dma_data_direction direction)
376 {
377 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
378 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
379 struct ttm_operation_ctx ctx = { true, false };
380 u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
381 int ret;
382 bool reads = (direction == DMA_BIDIRECTIONAL ||
383 direction == DMA_FROM_DEVICE);
384
385 if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
386 return 0;
387
388 /* move to gtt */
389 ret = amdgpu_bo_reserve(bo, false);
390 if (unlikely(ret != 0))
391 return ret;
392
393 if (!bo->pin_count && (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
394 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
395 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
396 }
397
398 amdgpu_bo_unreserve(bo);
399 return ret;
400 }
401
402 const struct dma_buf_ops amdgpu_dmabuf_ops = {
403 .attach = amdgpu_dma_buf_attach,
404 .detach = amdgpu_dma_buf_detach,
405 .pin = amdgpu_dma_buf_pin,
406 .unpin = amdgpu_dma_buf_unpin,
407 .map_dma_buf = amdgpu_dma_buf_map,
408 .unmap_dma_buf = amdgpu_dma_buf_unmap,
409 .release = drm_gem_dmabuf_release,
410 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
411 .mmap = drm_gem_dmabuf_mmap,
412 .vmap = drm_gem_dmabuf_vmap,
413 .vunmap = drm_gem_dmabuf_vunmap,
414 };
415
416 /**
417 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
418 * @gobj: GEM BO
419 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
420 *
421 * The main work is done by the &drm_gem_prime_export helper.
422 *
423 * Returns:
424 * Shared DMA buffer representing the GEM BO from the given device.
425 */
amdgpu_gem_prime_export(struct drm_gem_object * gobj,int flags)426 struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
427 int flags)
428 {
429 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
430 struct dma_buf *buf;
431
432 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
433 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
434 return ERR_PTR(-EPERM);
435
436 buf = drm_gem_prime_export(gobj, flags);
437 if (!IS_ERR(buf))
438 buf->ops = &amdgpu_dmabuf_ops;
439
440 return buf;
441 }
442
443 /**
444 * amdgpu_dma_buf_create_obj - create BO for DMA-buf import
445 *
446 * @dev: DRM device
447 * @dma_buf: DMA-buf
448 *
449 * Creates an empty SG BO for DMA-buf import.
450 *
451 * Returns:
452 * A new GEM BO of the given DRM device, representing the memory
453 * described by the given DMA-buf attachment and scatter/gather table.
454 */
455 static struct drm_gem_object *
amdgpu_dma_buf_create_obj(struct drm_device * dev,struct dma_buf * dma_buf)456 amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
457 {
458 struct dma_resv *resv = dma_buf->resv;
459 struct amdgpu_device *adev = drm_to_adev(dev);
460 struct amdgpu_bo *bo;
461 struct amdgpu_bo_param bp;
462 struct drm_gem_object *gobj;
463 int ret;
464
465 memset(&bp, 0, sizeof(bp));
466 bp.size = dma_buf->size;
467 bp.byte_align = PAGE_SIZE;
468 bp.domain = AMDGPU_GEM_DOMAIN_CPU;
469 bp.flags = 0;
470 bp.type = ttm_bo_type_sg;
471 bp.resv = resv;
472 dma_resv_lock(resv, NULL);
473 ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
474 AMDGPU_GEM_DOMAIN_CPU,
475 0, ttm_bo_type_sg, resv, &gobj);
476 if (ret)
477 goto error;
478
479 bo = gem_to_amdgpu_bo(gobj);
480 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
481 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
482 if (dma_buf->ops != &amdgpu_dmabuf_ops)
483 bo->prime_shared_count = 1;
484
485 dma_resv_unlock(resv);
486 return gobj;
487
488 error:
489 dma_resv_unlock(resv);
490 return ERR_PTR(ret);
491 }
492
493 /**
494 * amdgpu_dma_buf_move_notify - &attach.move_notify implementation
495 *
496 * @attach: the DMA-buf attachment
497 *
498 * Invalidate the DMA-buf attachment, making sure that the we re-create the
499 * mapping before the next use.
500 */
501 static void
amdgpu_dma_buf_move_notify(struct dma_buf_attachment * attach)502 amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
503 {
504 struct drm_gem_object *obj = attach->importer_priv;
505 struct ww_acquire_ctx *ticket = dma_resv_locking_ctx(obj->resv);
506 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
507 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
508 struct ttm_operation_ctx ctx = { false, false };
509 struct ttm_placement placement = {};
510 struct amdgpu_vm_bo_base *bo_base;
511 int r;
512
513 if (bo->tbo.mem.mem_type == TTM_PL_SYSTEM)
514 return;
515
516 r = ttm_bo_validate(&bo->tbo, &placement, &ctx);
517 if (r) {
518 DRM_ERROR("Failed to invalidate DMA-buf import (%d))\n", r);
519 return;
520 }
521
522 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
523 struct amdgpu_vm *vm = bo_base->vm;
524 struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
525
526 if (ticket) {
527 /* When we get an error here it means that somebody
528 * else is holding the VM lock and updating page tables
529 * So we can just continue here.
530 */
531 r = dma_resv_lock(resv, ticket);
532 if (r)
533 continue;
534
535 } else {
536 /* TODO: This is more problematic and we actually need
537 * to allow page tables updates without holding the
538 * lock.
539 */
540 if (!dma_resv_trylock(resv))
541 continue;
542 }
543
544 r = amdgpu_vm_clear_freed(adev, vm, NULL);
545 if (!r)
546 r = amdgpu_vm_handle_moved(adev, vm);
547
548 if (r && r != -EBUSY)
549 DRM_ERROR("Failed to invalidate VM page tables (%d))\n",
550 r);
551
552 dma_resv_unlock(resv);
553 }
554 }
555
556 static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = {
557 .allow_peer2peer = true,
558 .move_notify = amdgpu_dma_buf_move_notify
559 };
560
561 /**
562 * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
563 * @dev: DRM device
564 * @dma_buf: Shared DMA buffer
565 *
566 * Import a dma_buf into a the driver and potentially create a new GEM object.
567 *
568 * Returns:
569 * GEM BO representing the shared DMA buffer for the given device.
570 */
amdgpu_gem_prime_import(struct drm_device * dev,struct dma_buf * dma_buf)571 struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
572 struct dma_buf *dma_buf)
573 {
574 struct dma_buf_attachment *attach;
575 struct drm_gem_object *obj;
576
577 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
578 obj = dma_buf->priv;
579 if (obj->dev == dev) {
580 /*
581 * Importing dmabuf exported from out own gem increases
582 * refcount on gem itself instead of f_count of dmabuf.
583 */
584 drm_gem_object_get(obj);
585 return obj;
586 }
587 }
588
589 obj = amdgpu_dma_buf_create_obj(dev, dma_buf);
590 if (IS_ERR(obj))
591 return obj;
592
593 attach = dma_buf_dynamic_attach(dma_buf, dev->dev,
594 &amdgpu_dma_buf_attach_ops, obj);
595 if (IS_ERR(attach)) {
596 drm_gem_object_put(obj);
597 return ERR_CAST(attach);
598 }
599
600 get_dma_buf(dma_buf);
601 obj->import_attach = attach;
602 return obj;
603 }
604
605 /**
606 * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer
607 *
608 * @adev: amdgpu_device pointer of the importer
609 * @bo: amdgpu buffer object
610 *
611 * Returns:
612 * True if dmabuf accessible over xgmi, false otherwise.
613 */
amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device * adev,struct amdgpu_bo * bo)614 bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
615 struct amdgpu_bo *bo)
616 {
617 struct drm_gem_object *obj = &bo->tbo.base;
618 struct drm_gem_object *gobj;
619
620 if (obj->import_attach) {
621 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
622
623 if (dma_buf->ops != &amdgpu_dmabuf_ops)
624 /* No XGMI with non AMD GPUs */
625 return false;
626
627 gobj = dma_buf->priv;
628 bo = gem_to_amdgpu_bo(gobj);
629 }
630
631 if (amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
632 (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM))
633 return true;
634
635 return false;
636 }
637