1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024 AIROHA Inc
4 * Author: Lorenzo Bianconi <lorenzo@kernel.org>
5 */
6 #include <linux/of.h>
7 #include <linux/of_net.h>
8 #include <linux/of_reserved_mem.h>
9 #include <linux/platform_device.h>
10 #include <linux/tcp.h>
11 #include <linux/u64_stats_sync.h>
12 #include <net/dst_metadata.h>
13 #include <net/page_pool/helpers.h>
14 #include <net/pkt_cls.h>
15 #include <uapi/linux/ppp_defs.h>
16
17 #include "airoha_regs.h"
18 #include "airoha_eth.h"
19
airoha_rr(void __iomem * base,u32 offset)20 u32 airoha_rr(void __iomem *base, u32 offset)
21 {
22 return readl(base + offset);
23 }
24
airoha_wr(void __iomem * base,u32 offset,u32 val)25 void airoha_wr(void __iomem *base, u32 offset, u32 val)
26 {
27 writel(val, base + offset);
28 }
29
airoha_rmw(void __iomem * base,u32 offset,u32 mask,u32 val)30 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)
31 {
32 val |= (airoha_rr(base, offset) & ~mask);
33 airoha_wr(base, offset, val);
34
35 return val;
36 }
37
airoha_qdma_set_irqmask(struct airoha_irq_bank * irq_bank,int index,u32 clear,u32 set)38 static void airoha_qdma_set_irqmask(struct airoha_irq_bank *irq_bank,
39 int index, u32 clear, u32 set)
40 {
41 struct airoha_qdma *qdma = irq_bank->qdma;
42 int bank = irq_bank - &qdma->irq_banks[0];
43 unsigned long flags;
44
45 if (WARN_ON_ONCE(index >= ARRAY_SIZE(irq_bank->irqmask)))
46 return;
47
48 spin_lock_irqsave(&irq_bank->irq_lock, flags);
49
50 irq_bank->irqmask[index] &= ~clear;
51 irq_bank->irqmask[index] |= set;
52 airoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index),
53 irq_bank->irqmask[index]);
54 /* Read irq_enable register in order to guarantee the update above
55 * completes in the spinlock critical section.
56 */
57 airoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index));
58
59 spin_unlock_irqrestore(&irq_bank->irq_lock, flags);
60 }
61
airoha_qdma_irq_enable(struct airoha_irq_bank * irq_bank,int index,u32 mask)62 static void airoha_qdma_irq_enable(struct airoha_irq_bank *irq_bank,
63 int index, u32 mask)
64 {
65 airoha_qdma_set_irqmask(irq_bank, index, 0, mask);
66 }
67
airoha_qdma_irq_disable(struct airoha_irq_bank * irq_bank,int index,u32 mask)68 static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank,
69 int index, u32 mask)
70 {
71 airoha_qdma_set_irqmask(irq_bank, index, mask, 0);
72 }
73
airoha_set_macaddr(struct airoha_gdm_port * port,const u8 * addr)74 static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
75 {
76 struct airoha_eth *eth = port->qdma->eth;
77 u32 val, reg;
78
79 reg = airhoa_is_lan_gdm_port(port) ? REG_FE_LAN_MAC_H
80 : REG_FE_WAN_MAC_H;
81 val = (addr[0] << 16) | (addr[1] << 8) | addr[2];
82 airoha_fe_wr(eth, reg, val);
83
84 val = (addr[3] << 16) | (addr[4] << 8) | addr[5];
85 airoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), val);
86 airoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), val);
87
88 airoha_ppe_init_upd_mem(port);
89 }
90
airoha_set_gdm_port_fwd_cfg(struct airoha_eth * eth,u32 addr,u32 val)91 static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr,
92 u32 val)
93 {
94 airoha_fe_rmw(eth, addr, GDM_OCFQ_MASK,
95 FIELD_PREP(GDM_OCFQ_MASK, val));
96 airoha_fe_rmw(eth, addr, GDM_MCFQ_MASK,
97 FIELD_PREP(GDM_MCFQ_MASK, val));
98 airoha_fe_rmw(eth, addr, GDM_BCFQ_MASK,
99 FIELD_PREP(GDM_BCFQ_MASK, val));
100 airoha_fe_rmw(eth, addr, GDM_UCFQ_MASK,
101 FIELD_PREP(GDM_UCFQ_MASK, val));
102 }
103
airoha_set_vip_for_gdm_port(struct airoha_gdm_port * port,bool enable)104 static int airoha_set_vip_for_gdm_port(struct airoha_gdm_port *port,
105 bool enable)
106 {
107 struct airoha_eth *eth = port->qdma->eth;
108 u32 vip_port;
109
110 switch (port->id) {
111 case 3:
112 /* FIXME: handle XSI_PCIE1_PORT */
113 vip_port = XSI_PCIE0_VIP_PORT_MASK;
114 break;
115 case 4:
116 /* FIXME: handle XSI_USB_PORT */
117 vip_port = XSI_ETH_VIP_PORT_MASK;
118 break;
119 default:
120 return 0;
121 }
122
123 if (enable) {
124 airoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port);
125 airoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port);
126 } else {
127 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, vip_port);
128 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, vip_port);
129 }
130
131 return 0;
132 }
133
airoha_fe_maccr_init(struct airoha_eth * eth)134 static void airoha_fe_maccr_init(struct airoha_eth *eth)
135 {
136 int p;
137
138 for (p = 1; p <= ARRAY_SIZE(eth->ports); p++)
139 airoha_fe_set(eth, REG_GDM_FWD_CFG(p),
140 GDM_TCP_CKSUM | GDM_UDP_CKSUM | GDM_IP4_CKSUM |
141 GDM_DROP_CRC_ERR);
142
143 airoha_fe_rmw(eth, REG_CDM1_VLAN_CTRL, CDM1_VLAN_MASK,
144 FIELD_PREP(CDM1_VLAN_MASK, 0x8100));
145
146 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD);
147 }
148
airoha_fe_vip_setup(struct airoha_eth * eth)149 static void airoha_fe_vip_setup(struct airoha_eth *eth)
150 {
151 airoha_fe_wr(eth, REG_FE_VIP_PATN(3), ETH_P_PPP_DISC);
152 airoha_fe_wr(eth, REG_FE_VIP_EN(3), PATN_FCPU_EN_MASK | PATN_EN_MASK);
153
154 airoha_fe_wr(eth, REG_FE_VIP_PATN(4), PPP_LCP);
155 airoha_fe_wr(eth, REG_FE_VIP_EN(4),
156 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |
157 PATN_EN_MASK);
158
159 airoha_fe_wr(eth, REG_FE_VIP_PATN(6), PPP_IPCP);
160 airoha_fe_wr(eth, REG_FE_VIP_EN(6),
161 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |
162 PATN_EN_MASK);
163
164 airoha_fe_wr(eth, REG_FE_VIP_PATN(7), PPP_CHAP);
165 airoha_fe_wr(eth, REG_FE_VIP_EN(7),
166 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |
167 PATN_EN_MASK);
168
169 /* BOOTP (0x43) */
170 airoha_fe_wr(eth, REG_FE_VIP_PATN(8), 0x43);
171 airoha_fe_wr(eth, REG_FE_VIP_EN(8),
172 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK |
173 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK);
174
175 /* BOOTP (0x44) */
176 airoha_fe_wr(eth, REG_FE_VIP_PATN(9), 0x44);
177 airoha_fe_wr(eth, REG_FE_VIP_EN(9),
178 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK |
179 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK);
180
181 /* ISAKMP */
182 airoha_fe_wr(eth, REG_FE_VIP_PATN(10), 0x1f401f4);
183 airoha_fe_wr(eth, REG_FE_VIP_EN(10),
184 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK |
185 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK);
186
187 airoha_fe_wr(eth, REG_FE_VIP_PATN(11), PPP_IPV6CP);
188 airoha_fe_wr(eth, REG_FE_VIP_EN(11),
189 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |
190 PATN_EN_MASK);
191
192 /* DHCPv6 */
193 airoha_fe_wr(eth, REG_FE_VIP_PATN(12), 0x2220223);
194 airoha_fe_wr(eth, REG_FE_VIP_EN(12),
195 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK |
196 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK);
197
198 airoha_fe_wr(eth, REG_FE_VIP_PATN(19), PPP_PAP);
199 airoha_fe_wr(eth, REG_FE_VIP_EN(19),
200 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |
201 PATN_EN_MASK);
202
203 /* ETH->ETH_P_1905 (0x893a) */
204 airoha_fe_wr(eth, REG_FE_VIP_PATN(20), 0x893a);
205 airoha_fe_wr(eth, REG_FE_VIP_EN(20),
206 PATN_FCPU_EN_MASK | PATN_EN_MASK);
207
208 airoha_fe_wr(eth, REG_FE_VIP_PATN(21), ETH_P_LLDP);
209 airoha_fe_wr(eth, REG_FE_VIP_EN(21),
210 PATN_FCPU_EN_MASK | PATN_EN_MASK);
211 }
212
airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth * eth,u32 port,u32 queue)213 static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth *eth,
214 u32 port, u32 queue)
215 {
216 u32 val;
217
218 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR,
219 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK,
220 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) |
221 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue));
222 val = airoha_fe_rr(eth, REG_FE_PSE_QUEUE_CFG_VAL);
223
224 return FIELD_GET(PSE_CFG_OQ_RSV_MASK, val);
225 }
226
airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth * eth,u32 port,u32 queue,u32 val)227 static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth,
228 u32 port, u32 queue, u32 val)
229 {
230 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_VAL, PSE_CFG_OQ_RSV_MASK,
231 FIELD_PREP(PSE_CFG_OQ_RSV_MASK, val));
232 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR,
233 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK |
234 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK,
235 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) |
236 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue) |
237 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK);
238 }
239
airoha_fe_get_pse_all_rsv(struct airoha_eth * eth)240 static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth)
241 {
242 u32 val = airoha_fe_rr(eth, REG_FE_PSE_BUF_SET);
243
244 return FIELD_GET(PSE_ALLRSV_MASK, val);
245 }
246
airoha_fe_set_pse_oq_rsv(struct airoha_eth * eth,u32 port,u32 queue,u32 val)247 static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth,
248 u32 port, u32 queue, u32 val)
249 {
250 u32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue);
251 u32 tmp, all_rsv, fq_limit;
252
253 airoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val);
254
255 /* modify all rsv */
256 all_rsv = airoha_fe_get_pse_all_rsv(eth);
257 all_rsv += (val - orig_val);
258 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK,
259 FIELD_PREP(PSE_ALLRSV_MASK, all_rsv));
260
261 /* modify hthd */
262 tmp = airoha_fe_rr(eth, PSE_FQ_CFG);
263 fq_limit = FIELD_GET(PSE_FQ_LIMIT_MASK, tmp);
264 tmp = fq_limit - all_rsv - 0x20;
265 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD,
266 PSE_SHARE_USED_HTHD_MASK,
267 FIELD_PREP(PSE_SHARE_USED_HTHD_MASK, tmp));
268
269 tmp = fq_limit - all_rsv - 0x100;
270 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD,
271 PSE_SHARE_USED_MTHD_MASK,
272 FIELD_PREP(PSE_SHARE_USED_MTHD_MASK, tmp));
273 tmp = (3 * tmp) >> 2;
274 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET,
275 PSE_SHARE_USED_LTHD_MASK,
276 FIELD_PREP(PSE_SHARE_USED_LTHD_MASK, tmp));
277
278 return 0;
279 }
280
airoha_fe_pse_ports_init(struct airoha_eth * eth)281 static void airoha_fe_pse_ports_init(struct airoha_eth *eth)
282 {
283 const u32 pse_port_num_queues[] = {
284 [FE_PSE_PORT_CDM1] = 6,
285 [FE_PSE_PORT_GDM1] = 6,
286 [FE_PSE_PORT_GDM2] = 32,
287 [FE_PSE_PORT_GDM3] = 6,
288 [FE_PSE_PORT_PPE1] = 4,
289 [FE_PSE_PORT_CDM2] = 6,
290 [FE_PSE_PORT_CDM3] = 8,
291 [FE_PSE_PORT_CDM4] = 10,
292 [FE_PSE_PORT_PPE2] = 4,
293 [FE_PSE_PORT_GDM4] = 2,
294 [FE_PSE_PORT_CDM5] = 2,
295 };
296 u32 all_rsv;
297 int q;
298
299 all_rsv = airoha_fe_get_pse_all_rsv(eth);
300 /* hw misses PPE2 oq rsv */
301 all_rsv += PSE_RSV_PAGES * pse_port_num_queues[FE_PSE_PORT_PPE2];
302 airoha_fe_set(eth, REG_FE_PSE_BUF_SET, all_rsv);
303
304 /* CMD1 */
305 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM1]; q++)
306 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM1, q,
307 PSE_QUEUE_RSV_PAGES);
308 /* GMD1 */
309 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM1]; q++)
310 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM1, q,
311 PSE_QUEUE_RSV_PAGES);
312 /* GMD2 */
313 for (q = 6; q < pse_port_num_queues[FE_PSE_PORT_GDM2]; q++)
314 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM2, q, 0);
315 /* GMD3 */
316 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM3]; q++)
317 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM3, q,
318 PSE_QUEUE_RSV_PAGES);
319 /* PPE1 */
320 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE1]; q++) {
321 if (q < pse_port_num_queues[FE_PSE_PORT_PPE1])
322 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q,
323 PSE_QUEUE_RSV_PAGES);
324 else
325 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 0);
326 }
327 /* CDM2 */
328 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM2]; q++)
329 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM2, q,
330 PSE_QUEUE_RSV_PAGES);
331 /* CDM3 */
332 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM3] - 1; q++)
333 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM3, q, 0);
334 /* CDM4 */
335 for (q = 4; q < pse_port_num_queues[FE_PSE_PORT_CDM4]; q++)
336 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM4, q,
337 PSE_QUEUE_RSV_PAGES);
338 /* PPE2 */
339 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE2]; q++) {
340 if (q < pse_port_num_queues[FE_PSE_PORT_PPE2] / 2)
341 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, q,
342 PSE_QUEUE_RSV_PAGES);
343 else
344 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, q, 0);
345 }
346 /* GMD4 */
347 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM4]; q++)
348 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM4, q,
349 PSE_QUEUE_RSV_PAGES);
350 /* CDM5 */
351 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM5]; q++)
352 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM5, q,
353 PSE_QUEUE_RSV_PAGES);
354 }
355
airoha_fe_mc_vlan_clear(struct airoha_eth * eth)356 static int airoha_fe_mc_vlan_clear(struct airoha_eth *eth)
357 {
358 int i;
359
360 for (i = 0; i < AIROHA_FE_MC_MAX_VLAN_TABLE; i++) {
361 int err, j;
362 u32 val;
363
364 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0);
365
366 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) |
367 MC_VLAN_CFG_TABLE_SEL_MASK | MC_VLAN_CFG_RW_MASK;
368 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val);
369 err = read_poll_timeout(airoha_fe_rr, val,
370 val & MC_VLAN_CFG_CMD_DONE_MASK,
371 USEC_PER_MSEC, 5 * USEC_PER_MSEC,
372 false, eth, REG_MC_VLAN_CFG);
373 if (err)
374 return err;
375
376 for (j = 0; j < AIROHA_FE_MC_MAX_VLAN_PORT; j++) {
377 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0);
378
379 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) |
380 FIELD_PREP(MC_VLAN_CFG_PORT_ID_MASK, j) |
381 MC_VLAN_CFG_RW_MASK;
382 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val);
383 err = read_poll_timeout(airoha_fe_rr, val,
384 val & MC_VLAN_CFG_CMD_DONE_MASK,
385 USEC_PER_MSEC,
386 5 * USEC_PER_MSEC, false, eth,
387 REG_MC_VLAN_CFG);
388 if (err)
389 return err;
390 }
391 }
392
393 return 0;
394 }
395
airoha_fe_crsn_qsel_init(struct airoha_eth * eth)396 static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth)
397 {
398 /* CDM1_CRSN_QSEL */
399 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_22 >> 2),
400 CDM1_CRSN_QSEL_REASON_MASK(CRSN_22),
401 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_22),
402 CDM_CRSN_QSEL_Q1));
403 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_08 >> 2),
404 CDM1_CRSN_QSEL_REASON_MASK(CRSN_08),
405 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_08),
406 CDM_CRSN_QSEL_Q1));
407 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_21 >> 2),
408 CDM1_CRSN_QSEL_REASON_MASK(CRSN_21),
409 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_21),
410 CDM_CRSN_QSEL_Q1));
411 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_24 >> 2),
412 CDM1_CRSN_QSEL_REASON_MASK(CRSN_24),
413 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_24),
414 CDM_CRSN_QSEL_Q6));
415 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_25 >> 2),
416 CDM1_CRSN_QSEL_REASON_MASK(CRSN_25),
417 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_25),
418 CDM_CRSN_QSEL_Q1));
419 /* CDM2_CRSN_QSEL */
420 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_08 >> 2),
421 CDM2_CRSN_QSEL_REASON_MASK(CRSN_08),
422 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_08),
423 CDM_CRSN_QSEL_Q1));
424 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_21 >> 2),
425 CDM2_CRSN_QSEL_REASON_MASK(CRSN_21),
426 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_21),
427 CDM_CRSN_QSEL_Q1));
428 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_22 >> 2),
429 CDM2_CRSN_QSEL_REASON_MASK(CRSN_22),
430 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_22),
431 CDM_CRSN_QSEL_Q1));
432 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_24 >> 2),
433 CDM2_CRSN_QSEL_REASON_MASK(CRSN_24),
434 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_24),
435 CDM_CRSN_QSEL_Q6));
436 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_25 >> 2),
437 CDM2_CRSN_QSEL_REASON_MASK(CRSN_25),
438 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_25),
439 CDM_CRSN_QSEL_Q1));
440 }
441
airoha_fe_init(struct airoha_eth * eth)442 static int airoha_fe_init(struct airoha_eth *eth)
443 {
444 airoha_fe_maccr_init(eth);
445
446 /* PSE IQ reserve */
447 airoha_fe_rmw(eth, REG_PSE_IQ_REV1, PSE_IQ_RES1_P2_MASK,
448 FIELD_PREP(PSE_IQ_RES1_P2_MASK, 0x10));
449 airoha_fe_rmw(eth, REG_PSE_IQ_REV2,
450 PSE_IQ_RES2_P5_MASK | PSE_IQ_RES2_P4_MASK,
451 FIELD_PREP(PSE_IQ_RES2_P5_MASK, 0x40) |
452 FIELD_PREP(PSE_IQ_RES2_P4_MASK, 0x34));
453
454 /* enable FE copy engine for MC/KA/DPI */
455 airoha_fe_wr(eth, REG_FE_PCE_CFG,
456 PCE_DPI_EN_MASK | PCE_KA_EN_MASK | PCE_MC_EN_MASK);
457 /* set vip queue selection to ring 1 */
458 airoha_fe_rmw(eth, REG_CDM1_FWD_CFG, CDM1_VIP_QSEL_MASK,
459 FIELD_PREP(CDM1_VIP_QSEL_MASK, 0x4));
460 airoha_fe_rmw(eth, REG_CDM2_FWD_CFG, CDM2_VIP_QSEL_MASK,
461 FIELD_PREP(CDM2_VIP_QSEL_MASK, 0x4));
462 /* set GDM4 source interface offset to 8 */
463 airoha_fe_rmw(eth, REG_GDM4_SRC_PORT_SET,
464 GDM4_SPORT_OFF2_MASK |
465 GDM4_SPORT_OFF1_MASK |
466 GDM4_SPORT_OFF0_MASK,
467 FIELD_PREP(GDM4_SPORT_OFF2_MASK, 8) |
468 FIELD_PREP(GDM4_SPORT_OFF1_MASK, 8) |
469 FIELD_PREP(GDM4_SPORT_OFF0_MASK, 8));
470
471 /* set PSE Page as 128B */
472 airoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG,
473 FE_DMA_GLO_L2_SPACE_MASK | FE_DMA_GLO_PG_SZ_MASK,
474 FIELD_PREP(FE_DMA_GLO_L2_SPACE_MASK, 2) |
475 FE_DMA_GLO_PG_SZ_MASK);
476 airoha_fe_wr(eth, REG_FE_RST_GLO_CFG,
477 FE_RST_CORE_MASK | FE_RST_GDM3_MBI_ARB_MASK |
478 FE_RST_GDM4_MBI_ARB_MASK);
479 usleep_range(1000, 2000);
480
481 /* connect RxRing1 and RxRing15 to PSE Port0 OQ-1
482 * connect other rings to PSE Port0 OQ-0
483 */
484 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP0, BIT(4));
485 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP1, BIT(28));
486 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP2, BIT(4));
487 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP3, BIT(28));
488
489 airoha_fe_vip_setup(eth);
490 airoha_fe_pse_ports_init(eth);
491
492 airoha_fe_set(eth, REG_GDM_MISC_CFG,
493 GDM2_RDM_ACK_WAIT_PREF_MASK |
494 GDM2_CHN_VLD_MODE_MASK);
495 airoha_fe_rmw(eth, REG_CDM2_FWD_CFG, CDM2_OAM_QSEL_MASK,
496 FIELD_PREP(CDM2_OAM_QSEL_MASK, 15));
497
498 /* init fragment and assemble Force Port */
499 /* NPU Core-3, NPU Bridge Channel-3 */
500 airoha_fe_rmw(eth, REG_IP_FRAG_FP,
501 IP_FRAGMENT_PORT_MASK | IP_FRAGMENT_NBQ_MASK,
502 FIELD_PREP(IP_FRAGMENT_PORT_MASK, 6) |
503 FIELD_PREP(IP_FRAGMENT_NBQ_MASK, 3));
504 /* QDMA LAN, RX Ring-22 */
505 airoha_fe_rmw(eth, REG_IP_FRAG_FP,
506 IP_ASSEMBLE_PORT_MASK | IP_ASSEMBLE_NBQ_MASK,
507 FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) |
508 FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22));
509
510 airoha_fe_set(eth, REG_GDM3_FWD_CFG, GDM3_PAD_EN_MASK);
511 airoha_fe_set(eth, REG_GDM4_FWD_CFG, GDM4_PAD_EN_MASK);
512
513 airoha_fe_crsn_qsel_init(eth);
514
515 airoha_fe_clear(eth, REG_FE_CPORT_CFG, FE_CPORT_QUEUE_XFC_MASK);
516 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK);
517
518 /* default aging mode for mbi unlock issue */
519 airoha_fe_rmw(eth, REG_GDM2_CHN_RLS,
520 MBI_RX_AGE_SEL_MASK | MBI_TX_AGE_SEL_MASK,
521 FIELD_PREP(MBI_RX_AGE_SEL_MASK, 3) |
522 FIELD_PREP(MBI_TX_AGE_SEL_MASK, 3));
523
524 /* disable IFC by default */
525 airoha_fe_clear(eth, REG_FE_CSR_IFC_CFG, FE_IFC_EN_MASK);
526
527 airoha_fe_wr(eth, REG_PPE_DFT_CPORT0(0),
528 FIELD_PREP(DFT_CPORT_MASK(7), FE_PSE_PORT_CDM1) |
529 FIELD_PREP(DFT_CPORT_MASK(6), FE_PSE_PORT_CDM1) |
530 FIELD_PREP(DFT_CPORT_MASK(5), FE_PSE_PORT_CDM1) |
531 FIELD_PREP(DFT_CPORT_MASK(4), FE_PSE_PORT_CDM1) |
532 FIELD_PREP(DFT_CPORT_MASK(3), FE_PSE_PORT_CDM1) |
533 FIELD_PREP(DFT_CPORT_MASK(2), FE_PSE_PORT_CDM1) |
534 FIELD_PREP(DFT_CPORT_MASK(1), FE_PSE_PORT_CDM1) |
535 FIELD_PREP(DFT_CPORT_MASK(0), FE_PSE_PORT_CDM1));
536 airoha_fe_wr(eth, REG_PPE_DFT_CPORT0(1),
537 FIELD_PREP(DFT_CPORT_MASK(7), FE_PSE_PORT_CDM2) |
538 FIELD_PREP(DFT_CPORT_MASK(6), FE_PSE_PORT_CDM2) |
539 FIELD_PREP(DFT_CPORT_MASK(5), FE_PSE_PORT_CDM2) |
540 FIELD_PREP(DFT_CPORT_MASK(4), FE_PSE_PORT_CDM2) |
541 FIELD_PREP(DFT_CPORT_MASK(3), FE_PSE_PORT_CDM2) |
542 FIELD_PREP(DFT_CPORT_MASK(2), FE_PSE_PORT_CDM2) |
543 FIELD_PREP(DFT_CPORT_MASK(1), FE_PSE_PORT_CDM2) |
544 FIELD_PREP(DFT_CPORT_MASK(0), FE_PSE_PORT_CDM2));
545
546 /* enable 1:N vlan action, init vlan table */
547 airoha_fe_set(eth, REG_MC_VLAN_EN, MC_VLAN_EN_MASK);
548
549 return airoha_fe_mc_vlan_clear(eth);
550 }
551
airoha_qdma_fill_rx_queue(struct airoha_queue * q)552 static int airoha_qdma_fill_rx_queue(struct airoha_queue *q)
553 {
554 struct airoha_qdma *qdma = q->qdma;
555 int qid = q - &qdma->q_rx[0];
556 int nframes = 0;
557
558 while (q->queued < q->ndesc - 1) {
559 struct airoha_queue_entry *e = &q->entry[q->head];
560 struct airoha_qdma_desc *desc = &q->desc[q->head];
561 struct page *page;
562 int offset;
563 u32 val;
564
565 page = page_pool_dev_alloc_frag(q->page_pool, &offset,
566 q->buf_size);
567 if (!page)
568 break;
569
570 q->head = (q->head + 1) % q->ndesc;
571 q->queued++;
572 nframes++;
573
574 e->buf = page_address(page) + offset;
575 e->dma_addr = page_pool_get_dma_addr(page) + offset;
576 e->dma_len = SKB_WITH_OVERHEAD(q->buf_size);
577
578 val = FIELD_PREP(QDMA_DESC_LEN_MASK, e->dma_len);
579 WRITE_ONCE(desc->ctrl, cpu_to_le32(val));
580 WRITE_ONCE(desc->addr, cpu_to_le32(e->dma_addr));
581 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, q->head);
582 WRITE_ONCE(desc->data, cpu_to_le32(val));
583 WRITE_ONCE(desc->msg0, 0);
584 WRITE_ONCE(desc->msg1, 0);
585 WRITE_ONCE(desc->msg2, 0);
586 WRITE_ONCE(desc->msg3, 0);
587
588 airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid),
589 RX_RING_CPU_IDX_MASK,
590 FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head));
591 }
592
593 return nframes;
594 }
595
airoha_qdma_get_gdm_port(struct airoha_eth * eth,struct airoha_qdma_desc * desc)596 static int airoha_qdma_get_gdm_port(struct airoha_eth *eth,
597 struct airoha_qdma_desc *desc)
598 {
599 u32 port, sport, msg1 = le32_to_cpu(desc->msg1);
600
601 sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK, msg1);
602 switch (sport) {
603 case 0x10 ... 0x14:
604 port = 0;
605 break;
606 case 0x2 ... 0x4:
607 port = sport - 1;
608 break;
609 default:
610 return -EINVAL;
611 }
612
613 return port >= ARRAY_SIZE(eth->ports) ? -EINVAL : port;
614 }
615
airoha_qdma_rx_process(struct airoha_queue * q,int budget)616 static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
617 {
618 enum dma_data_direction dir = page_pool_get_dma_dir(q->page_pool);
619 struct airoha_qdma *qdma = q->qdma;
620 struct airoha_eth *eth = qdma->eth;
621 int qid = q - &qdma->q_rx[0];
622 int done = 0;
623
624 while (done < budget) {
625 struct airoha_queue_entry *e = &q->entry[q->tail];
626 struct airoha_qdma_desc *desc = &q->desc[q->tail];
627 u32 hash, reason, msg1 = le32_to_cpu(desc->msg1);
628 struct page *page = virt_to_head_page(e->buf);
629 u32 desc_ctrl = le32_to_cpu(desc->ctrl);
630 struct airoha_gdm_port *port;
631 int data_len, len, p;
632
633 if (!(desc_ctrl & QDMA_DESC_DONE_MASK))
634 break;
635
636 q->tail = (q->tail + 1) % q->ndesc;
637 q->queued--;
638
639 dma_sync_single_for_cpu(eth->dev, e->dma_addr,
640 SKB_WITH_OVERHEAD(q->buf_size), dir);
641
642 len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl);
643 data_len = q->skb ? q->buf_size
644 : SKB_WITH_OVERHEAD(q->buf_size);
645 if (!len || data_len < len)
646 goto free_frag;
647
648 p = airoha_qdma_get_gdm_port(eth, desc);
649 if (p < 0 || !eth->ports[p])
650 goto free_frag;
651
652 port = eth->ports[p];
653 if (!q->skb) { /* first buffer */
654 q->skb = napi_build_skb(e->buf, q->buf_size);
655 if (!q->skb)
656 goto free_frag;
657
658 __skb_put(q->skb, len);
659 skb_mark_for_recycle(q->skb);
660 q->skb->dev = port->dev;
661 q->skb->protocol = eth_type_trans(q->skb, port->dev);
662 q->skb->ip_summed = CHECKSUM_UNNECESSARY;
663 skb_record_rx_queue(q->skb, qid);
664 } else { /* scattered frame */
665 struct skb_shared_info *shinfo = skb_shinfo(q->skb);
666 int nr_frags = shinfo->nr_frags;
667
668 if (nr_frags >= ARRAY_SIZE(shinfo->frags))
669 goto free_frag;
670
671 skb_add_rx_frag(q->skb, nr_frags, page,
672 e->buf - page_address(page), len,
673 q->buf_size);
674 }
675
676 if (FIELD_GET(QDMA_DESC_MORE_MASK, desc_ctrl))
677 continue;
678
679 if (netdev_uses_dsa(port->dev)) {
680 /* PPE module requires untagged packets to work
681 * properly and it provides DSA port index via the
682 * DMA descriptor. Report DSA tag to the DSA stack
683 * via skb dst info.
684 */
685 u32 sptag = FIELD_GET(QDMA_ETH_RXMSG_SPTAG,
686 le32_to_cpu(desc->msg0));
687
688 if (sptag < ARRAY_SIZE(port->dsa_meta) &&
689 port->dsa_meta[sptag])
690 skb_dst_set_noref(q->skb,
691 &port->dsa_meta[sptag]->dst);
692 }
693
694 hash = FIELD_GET(AIROHA_RXD4_FOE_ENTRY, msg1);
695 if (hash != AIROHA_RXD4_FOE_ENTRY)
696 skb_set_hash(q->skb, jhash_1word(hash, 0),
697 PKT_HASH_TYPE_L4);
698
699 reason = FIELD_GET(AIROHA_RXD4_PPE_CPU_REASON, msg1);
700 if (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
701 airoha_ppe_check_skb(eth->ppe, q->skb, hash);
702
703 done++;
704 napi_gro_receive(&q->napi, q->skb);
705 q->skb = NULL;
706 continue;
707 free_frag:
708 if (q->skb) {
709 dev_kfree_skb(q->skb);
710 q->skb = NULL;
711 } else {
712 page_pool_put_full_page(q->page_pool, page, true);
713 }
714 }
715 airoha_qdma_fill_rx_queue(q);
716
717 return done;
718 }
719
airoha_qdma_rx_napi_poll(struct napi_struct * napi,int budget)720 static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget)
721 {
722 struct airoha_queue *q = container_of(napi, struct airoha_queue, napi);
723 int cur, done = 0;
724
725 do {
726 cur = airoha_qdma_rx_process(q, budget - done);
727 done += cur;
728 } while (cur && done < budget);
729
730 if (done < budget && napi_complete(napi)) {
731 struct airoha_qdma *qdma = q->qdma;
732 int i, qid = q - &qdma->q_rx[0];
733 int intr_reg = qid < RX_DONE_HIGH_OFFSET ? QDMA_INT_REG_IDX1
734 : QDMA_INT_REG_IDX2;
735
736 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) {
737 if (!(BIT(qid) & RX_IRQ_BANK_PIN_MASK(i)))
738 continue;
739
740 airoha_qdma_irq_enable(&qdma->irq_banks[i], intr_reg,
741 BIT(qid % RX_DONE_HIGH_OFFSET));
742 }
743 }
744
745 return done;
746 }
747
airoha_qdma_init_rx_queue(struct airoha_queue * q,struct airoha_qdma * qdma,int ndesc)748 static int airoha_qdma_init_rx_queue(struct airoha_queue *q,
749 struct airoha_qdma *qdma, int ndesc)
750 {
751 const struct page_pool_params pp_params = {
752 .order = 0,
753 .pool_size = 256,
754 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
755 .dma_dir = DMA_FROM_DEVICE,
756 .max_len = PAGE_SIZE,
757 .nid = NUMA_NO_NODE,
758 .dev = qdma->eth->dev,
759 .napi = &q->napi,
760 };
761 struct airoha_eth *eth = qdma->eth;
762 int qid = q - &qdma->q_rx[0], thr;
763 dma_addr_t dma_addr;
764
765 q->buf_size = PAGE_SIZE / 2;
766 q->ndesc = ndesc;
767 q->qdma = qdma;
768
769 q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry),
770 GFP_KERNEL);
771 if (!q->entry)
772 return -ENOMEM;
773
774 q->page_pool = page_pool_create(&pp_params);
775 if (IS_ERR(q->page_pool)) {
776 int err = PTR_ERR(q->page_pool);
777
778 q->page_pool = NULL;
779 return err;
780 }
781
782 q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc),
783 &dma_addr, GFP_KERNEL);
784 if (!q->desc)
785 return -ENOMEM;
786
787 netif_napi_add(eth->napi_dev, &q->napi, airoha_qdma_rx_napi_poll);
788
789 airoha_qdma_wr(qdma, REG_RX_RING_BASE(qid), dma_addr);
790 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid),
791 RX_RING_SIZE_MASK,
792 FIELD_PREP(RX_RING_SIZE_MASK, ndesc));
793
794 thr = clamp(ndesc >> 3, 1, 32);
795 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), RX_RING_THR_MASK,
796 FIELD_PREP(RX_RING_THR_MASK, thr));
797 airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK,
798 FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head));
799 airoha_qdma_set(qdma, REG_RX_SCATTER_CFG(qid), RX_RING_SG_EN_MASK);
800
801 airoha_qdma_fill_rx_queue(q);
802
803 return 0;
804 }
805
airoha_qdma_cleanup_rx_queue(struct airoha_queue * q)806 static void airoha_qdma_cleanup_rx_queue(struct airoha_queue *q)
807 {
808 struct airoha_eth *eth = q->qdma->eth;
809
810 while (q->queued) {
811 struct airoha_queue_entry *e = &q->entry[q->tail];
812 struct page *page = virt_to_head_page(e->buf);
813
814 dma_sync_single_for_cpu(eth->dev, e->dma_addr, e->dma_len,
815 page_pool_get_dma_dir(q->page_pool));
816 page_pool_put_full_page(q->page_pool, page, false);
817 q->tail = (q->tail + 1) % q->ndesc;
818 q->queued--;
819 }
820 }
821
airoha_qdma_init_rx(struct airoha_qdma * qdma)822 static int airoha_qdma_init_rx(struct airoha_qdma *qdma)
823 {
824 int i;
825
826 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
827 int err;
828
829 if (!(RX_DONE_INT_MASK & BIT(i))) {
830 /* rx-queue not binded to irq */
831 continue;
832 }
833
834 err = airoha_qdma_init_rx_queue(&qdma->q_rx[i], qdma,
835 RX_DSCP_NUM(i));
836 if (err)
837 return err;
838 }
839
840 return 0;
841 }
842
airoha_qdma_tx_napi_poll(struct napi_struct * napi,int budget)843 static int airoha_qdma_tx_napi_poll(struct napi_struct *napi, int budget)
844 {
845 struct airoha_tx_irq_queue *irq_q;
846 int id, done = 0, irq_queued;
847 struct airoha_qdma *qdma;
848 struct airoha_eth *eth;
849 u32 status, head;
850
851 irq_q = container_of(napi, struct airoha_tx_irq_queue, napi);
852 qdma = irq_q->qdma;
853 id = irq_q - &qdma->q_tx_irq[0];
854 eth = qdma->eth;
855
856 status = airoha_qdma_rr(qdma, REG_IRQ_STATUS(id));
857 head = FIELD_GET(IRQ_HEAD_IDX_MASK, status);
858 head = head % irq_q->size;
859 irq_queued = FIELD_GET(IRQ_ENTRY_LEN_MASK, status);
860
861 while (irq_queued > 0 && done < budget) {
862 u32 qid, val = irq_q->q[head];
863 struct airoha_qdma_desc *desc;
864 struct airoha_queue_entry *e;
865 struct airoha_queue *q;
866 u32 index, desc_ctrl;
867 struct sk_buff *skb;
868
869 if (val == 0xff)
870 break;
871
872 irq_q->q[head] = 0xff; /* mark as done */
873 head = (head + 1) % irq_q->size;
874 irq_queued--;
875 done++;
876
877 qid = FIELD_GET(IRQ_RING_IDX_MASK, val);
878 if (qid >= ARRAY_SIZE(qdma->q_tx))
879 continue;
880
881 q = &qdma->q_tx[qid];
882 if (!q->ndesc)
883 continue;
884
885 index = FIELD_GET(IRQ_DESC_IDX_MASK, val);
886 if (index >= q->ndesc)
887 continue;
888
889 spin_lock_bh(&q->lock);
890
891 if (!q->queued)
892 goto unlock;
893
894 desc = &q->desc[index];
895 desc_ctrl = le32_to_cpu(desc->ctrl);
896
897 if (!(desc_ctrl & QDMA_DESC_DONE_MASK) &&
898 !(desc_ctrl & QDMA_DESC_DROP_MASK))
899 goto unlock;
900
901 e = &q->entry[index];
902 skb = e->skb;
903
904 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len,
905 DMA_TO_DEVICE);
906 memset(e, 0, sizeof(*e));
907 WRITE_ONCE(desc->msg0, 0);
908 WRITE_ONCE(desc->msg1, 0);
909 q->queued--;
910
911 /* completion ring can report out-of-order indexes if hw QoS
912 * is enabled and packets with different priority are queued
913 * to same DMA ring. Take into account possible out-of-order
914 * reports incrementing DMA ring tail pointer
915 */
916 while (q->tail != q->head && !q->entry[q->tail].dma_addr)
917 q->tail = (q->tail + 1) % q->ndesc;
918
919 if (skb) {
920 u16 queue = skb_get_queue_mapping(skb);
921 struct netdev_queue *txq;
922
923 txq = netdev_get_tx_queue(skb->dev, queue);
924 netdev_tx_completed_queue(txq, 1, skb->len);
925 if (netif_tx_queue_stopped(txq) &&
926 q->ndesc - q->queued >= q->free_thr)
927 netif_tx_wake_queue(txq);
928
929 dev_kfree_skb_any(skb);
930 }
931 unlock:
932 spin_unlock_bh(&q->lock);
933 }
934
935 if (done) {
936 int i, len = done >> 7;
937
938 for (i = 0; i < len; i++)
939 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id),
940 IRQ_CLEAR_LEN_MASK, 0x80);
941 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id),
942 IRQ_CLEAR_LEN_MASK, (done & 0x7f));
943 }
944
945 if (done < budget && napi_complete(napi))
946 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0,
947 TX_DONE_INT_MASK(id));
948
949 return done;
950 }
951
airoha_qdma_init_tx_queue(struct airoha_queue * q,struct airoha_qdma * qdma,int size)952 static int airoha_qdma_init_tx_queue(struct airoha_queue *q,
953 struct airoha_qdma *qdma, int size)
954 {
955 struct airoha_eth *eth = qdma->eth;
956 int i, qid = q - &qdma->q_tx[0];
957 dma_addr_t dma_addr;
958
959 spin_lock_init(&q->lock);
960 q->ndesc = size;
961 q->qdma = qdma;
962 q->free_thr = 1 + MAX_SKB_FRAGS;
963
964 q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry),
965 GFP_KERNEL);
966 if (!q->entry)
967 return -ENOMEM;
968
969 q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc),
970 &dma_addr, GFP_KERNEL);
971 if (!q->desc)
972 return -ENOMEM;
973
974 for (i = 0; i < q->ndesc; i++) {
975 u32 val;
976
977 val = FIELD_PREP(QDMA_DESC_DONE_MASK, 1);
978 WRITE_ONCE(q->desc[i].ctrl, cpu_to_le32(val));
979 }
980
981 /* xmit ring drop default setting */
982 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(qid),
983 TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK);
984
985 airoha_qdma_wr(qdma, REG_TX_RING_BASE(qid), dma_addr);
986 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK,
987 FIELD_PREP(TX_RING_CPU_IDX_MASK, q->head));
988 airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK,
989 FIELD_PREP(TX_RING_DMA_IDX_MASK, q->head));
990
991 return 0;
992 }
993
airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue * irq_q,struct airoha_qdma * qdma,int size)994 static int airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue *irq_q,
995 struct airoha_qdma *qdma, int size)
996 {
997 int id = irq_q - &qdma->q_tx_irq[0];
998 struct airoha_eth *eth = qdma->eth;
999 dma_addr_t dma_addr;
1000
1001 netif_napi_add_tx(eth->napi_dev, &irq_q->napi,
1002 airoha_qdma_tx_napi_poll);
1003 irq_q->q = dmam_alloc_coherent(eth->dev, size * sizeof(u32),
1004 &dma_addr, GFP_KERNEL);
1005 if (!irq_q->q)
1006 return -ENOMEM;
1007
1008 memset(irq_q->q, 0xff, size * sizeof(u32));
1009 irq_q->size = size;
1010 irq_q->qdma = qdma;
1011
1012 airoha_qdma_wr(qdma, REG_TX_IRQ_BASE(id), dma_addr);
1013 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_DEPTH_MASK,
1014 FIELD_PREP(TX_IRQ_DEPTH_MASK, size));
1015 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_THR_MASK,
1016 FIELD_PREP(TX_IRQ_THR_MASK, 1));
1017
1018 return 0;
1019 }
1020
airoha_qdma_init_tx(struct airoha_qdma * qdma)1021 static int airoha_qdma_init_tx(struct airoha_qdma *qdma)
1022 {
1023 int i, err;
1024
1025 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) {
1026 err = airoha_qdma_tx_irq_init(&qdma->q_tx_irq[i], qdma,
1027 IRQ_QUEUE_LEN(i));
1028 if (err)
1029 return err;
1030 }
1031
1032 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
1033 err = airoha_qdma_init_tx_queue(&qdma->q_tx[i], qdma,
1034 TX_DSCP_NUM);
1035 if (err)
1036 return err;
1037 }
1038
1039 return 0;
1040 }
1041
airoha_qdma_cleanup_tx_queue(struct airoha_queue * q)1042 static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q)
1043 {
1044 struct airoha_eth *eth = q->qdma->eth;
1045
1046 spin_lock_bh(&q->lock);
1047 while (q->queued) {
1048 struct airoha_queue_entry *e = &q->entry[q->tail];
1049
1050 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len,
1051 DMA_TO_DEVICE);
1052 dev_kfree_skb_any(e->skb);
1053 e->skb = NULL;
1054
1055 q->tail = (q->tail + 1) % q->ndesc;
1056 q->queued--;
1057 }
1058 spin_unlock_bh(&q->lock);
1059 }
1060
airoha_qdma_init_hfwd_queues(struct airoha_qdma * qdma)1061 static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
1062 {
1063 int size, index, num_desc = HW_DSCP_NUM;
1064 struct airoha_eth *eth = qdma->eth;
1065 int id = qdma - ð->qdma[0];
1066 u32 status, buf_size;
1067 dma_addr_t dma_addr;
1068 const char *name;
1069
1070 name = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d-buf", id);
1071 if (!name)
1072 return -ENOMEM;
1073
1074 buf_size = id ? AIROHA_MAX_PACKET_SIZE / 2 : AIROHA_MAX_PACKET_SIZE;
1075 index = of_property_match_string(eth->dev->of_node,
1076 "memory-region-names", name);
1077 if (index >= 0) {
1078 struct reserved_mem *rmem;
1079 struct device_node *np;
1080
1081 /* Consume reserved memory for hw forwarding buffers queue if
1082 * available in the DTS
1083 */
1084 np = of_parse_phandle(eth->dev->of_node, "memory-region",
1085 index);
1086 if (!np)
1087 return -ENODEV;
1088
1089 rmem = of_reserved_mem_lookup(np);
1090 of_node_put(np);
1091 dma_addr = rmem->base;
1092 /* Compute the number of hw descriptors according to the
1093 * reserved memory size and the payload buffer size
1094 */
1095 num_desc = div_u64(rmem->size, buf_size);
1096 } else {
1097 size = buf_size * num_desc;
1098 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr,
1099 GFP_KERNEL))
1100 return -ENOMEM;
1101 }
1102
1103 airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr);
1104
1105 size = num_desc * sizeof(struct airoha_qdma_fwd_desc);
1106 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL))
1107 return -ENOMEM;
1108
1109 airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr);
1110 /* QDMA0: 2KB. QDMA1: 1KB */
1111 airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG,
1112 HW_FWD_DSCP_PAYLOAD_SIZE_MASK,
1113 FIELD_PREP(HW_FWD_DSCP_PAYLOAD_SIZE_MASK, !!id));
1114 airoha_qdma_rmw(qdma, REG_FWD_DSCP_LOW_THR, FWD_DSCP_LOW_THR_MASK,
1115 FIELD_PREP(FWD_DSCP_LOW_THR_MASK, 128));
1116 airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG,
1117 LMGR_INIT_START | LMGR_SRAM_MODE_MASK |
1118 HW_FWD_DESC_NUM_MASK,
1119 FIELD_PREP(HW_FWD_DESC_NUM_MASK, num_desc) |
1120 LMGR_INIT_START | LMGR_SRAM_MODE_MASK);
1121
1122 return read_poll_timeout(airoha_qdma_rr, status,
1123 !(status & LMGR_INIT_START), USEC_PER_MSEC,
1124 30 * USEC_PER_MSEC, true, qdma,
1125 REG_LMGR_INIT_CFG);
1126 }
1127
airoha_qdma_init_qos(struct airoha_qdma * qdma)1128 static void airoha_qdma_init_qos(struct airoha_qdma *qdma)
1129 {
1130 airoha_qdma_clear(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_SCALE_MASK);
1131 airoha_qdma_set(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_BASE_MASK);
1132
1133 airoha_qdma_clear(qdma, REG_PSE_BUF_USAGE_CFG,
1134 PSE_BUF_ESTIMATE_EN_MASK);
1135
1136 airoha_qdma_set(qdma, REG_EGRESS_RATE_METER_CFG,
1137 EGRESS_RATE_METER_EN_MASK |
1138 EGRESS_RATE_METER_EQ_RATE_EN_MASK);
1139 /* 2047us x 31 = 63.457ms */
1140 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG,
1141 EGRESS_RATE_METER_WINDOW_SZ_MASK,
1142 FIELD_PREP(EGRESS_RATE_METER_WINDOW_SZ_MASK, 0x1f));
1143 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG,
1144 EGRESS_RATE_METER_TIMESLICE_MASK,
1145 FIELD_PREP(EGRESS_RATE_METER_TIMESLICE_MASK, 0x7ff));
1146
1147 /* ratelimit init */
1148 airoha_qdma_set(qdma, REG_GLB_TRTCM_CFG, GLB_TRTCM_EN_MASK);
1149 /* fast-tick 25us */
1150 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_FAST_TICK_MASK,
1151 FIELD_PREP(GLB_FAST_TICK_MASK, 25));
1152 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_SLOW_TICK_RATIO_MASK,
1153 FIELD_PREP(GLB_SLOW_TICK_RATIO_MASK, 40));
1154
1155 airoha_qdma_set(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_TRTCM_EN_MASK);
1156 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_FAST_TICK_MASK,
1157 FIELD_PREP(EGRESS_FAST_TICK_MASK, 25));
1158 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG,
1159 EGRESS_SLOW_TICK_RATIO_MASK,
1160 FIELD_PREP(EGRESS_SLOW_TICK_RATIO_MASK, 40));
1161
1162 airoha_qdma_set(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_TRTCM_EN_MASK);
1163 airoha_qdma_clear(qdma, REG_INGRESS_TRTCM_CFG,
1164 INGRESS_TRTCM_MODE_MASK);
1165 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_FAST_TICK_MASK,
1166 FIELD_PREP(INGRESS_FAST_TICK_MASK, 125));
1167 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG,
1168 INGRESS_SLOW_TICK_RATIO_MASK,
1169 FIELD_PREP(INGRESS_SLOW_TICK_RATIO_MASK, 8));
1170
1171 airoha_qdma_set(qdma, REG_SLA_TRTCM_CFG, SLA_TRTCM_EN_MASK);
1172 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_FAST_TICK_MASK,
1173 FIELD_PREP(SLA_FAST_TICK_MASK, 25));
1174 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_SLOW_TICK_RATIO_MASK,
1175 FIELD_PREP(SLA_SLOW_TICK_RATIO_MASK, 40));
1176 }
1177
airoha_qdma_init_qos_stats(struct airoha_qdma * qdma)1178 static void airoha_qdma_init_qos_stats(struct airoha_qdma *qdma)
1179 {
1180 int i;
1181
1182 for (i = 0; i < AIROHA_NUM_QOS_CHANNELS; i++) {
1183 /* Tx-cpu transferred count */
1184 airoha_qdma_wr(qdma, REG_CNTR_VAL(i << 1), 0);
1185 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1),
1186 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK |
1187 CNTR_ALL_DSCP_RING_EN_MASK |
1188 FIELD_PREP(CNTR_CHAN_MASK, i));
1189 /* Tx-fwd transferred count */
1190 airoha_qdma_wr(qdma, REG_CNTR_VAL((i << 1) + 1), 0);
1191 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1),
1192 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK |
1193 CNTR_ALL_DSCP_RING_EN_MASK |
1194 FIELD_PREP(CNTR_SRC_MASK, 1) |
1195 FIELD_PREP(CNTR_CHAN_MASK, i));
1196 }
1197 }
1198
airoha_qdma_hw_init(struct airoha_qdma * qdma)1199 static int airoha_qdma_hw_init(struct airoha_qdma *qdma)
1200 {
1201 int i;
1202
1203 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) {
1204 /* clear pending irqs */
1205 airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff);
1206 /* setup rx irqs */
1207 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX0,
1208 INT_RX0_MASK(RX_IRQ_BANK_PIN_MASK(i)));
1209 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX1,
1210 INT_RX1_MASK(RX_IRQ_BANK_PIN_MASK(i)));
1211 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX2,
1212 INT_RX2_MASK(RX_IRQ_BANK_PIN_MASK(i)));
1213 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX3,
1214 INT_RX3_MASK(RX_IRQ_BANK_PIN_MASK(i)));
1215 }
1216 /* setup tx irqs */
1217 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0,
1218 TX_COHERENT_LOW_INT_MASK | INT_TX_MASK);
1219 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX4,
1220 TX_COHERENT_HIGH_INT_MASK);
1221
1222 /* setup irq binding */
1223 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
1224 if (!qdma->q_tx[i].ndesc)
1225 continue;
1226
1227 if (TX_RING_IRQ_BLOCKING_MAP_MASK & BIT(i))
1228 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(i),
1229 TX_RING_IRQ_BLOCKING_CFG_MASK);
1230 else
1231 airoha_qdma_clear(qdma, REG_TX_RING_BLOCKING(i),
1232 TX_RING_IRQ_BLOCKING_CFG_MASK);
1233 }
1234
1235 airoha_qdma_wr(qdma, REG_QDMA_GLOBAL_CFG,
1236 FIELD_PREP(GLOBAL_CFG_DMA_PREFERENCE_MASK, 3) |
1237 GLOBAL_CFG_CPU_TXR_RR_MASK |
1238 GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK |
1239 GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK |
1240 GLOBAL_CFG_MULTICAST_EN_MASK |
1241 GLOBAL_CFG_IRQ0_EN_MASK | GLOBAL_CFG_IRQ1_EN_MASK |
1242 GLOBAL_CFG_TX_WB_DONE_MASK |
1243 FIELD_PREP(GLOBAL_CFG_MAX_ISSUE_NUM_MASK, 2));
1244
1245 airoha_qdma_init_qos(qdma);
1246
1247 /* disable qdma rx delay interrupt */
1248 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
1249 if (!qdma->q_rx[i].ndesc)
1250 continue;
1251
1252 airoha_qdma_clear(qdma, REG_RX_DELAY_INT_IDX(i),
1253 RX_DELAY_INT_MASK);
1254 }
1255
1256 airoha_qdma_set(qdma, REG_TXQ_CNGST_CFG,
1257 TXQ_CNGST_DROP_EN | TXQ_CNGST_DEI_DROP_EN);
1258 airoha_qdma_init_qos_stats(qdma);
1259
1260 return 0;
1261 }
1262
airoha_irq_handler(int irq,void * dev_instance)1263 static irqreturn_t airoha_irq_handler(int irq, void *dev_instance)
1264 {
1265 struct airoha_irq_bank *irq_bank = dev_instance;
1266 struct airoha_qdma *qdma = irq_bank->qdma;
1267 u32 rx_intr_mask = 0, rx_intr1, rx_intr2;
1268 u32 intr[ARRAY_SIZE(irq_bank->irqmask)];
1269 int i;
1270
1271 for (i = 0; i < ARRAY_SIZE(intr); i++) {
1272 intr[i] = airoha_qdma_rr(qdma, REG_INT_STATUS(i));
1273 intr[i] &= irq_bank->irqmask[i];
1274 airoha_qdma_wr(qdma, REG_INT_STATUS(i), intr[i]);
1275 }
1276
1277 if (!test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state))
1278 return IRQ_NONE;
1279
1280 rx_intr1 = intr[1] & RX_DONE_LOW_INT_MASK;
1281 if (rx_intr1) {
1282 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX1, rx_intr1);
1283 rx_intr_mask |= rx_intr1;
1284 }
1285
1286 rx_intr2 = intr[2] & RX_DONE_HIGH_INT_MASK;
1287 if (rx_intr2) {
1288 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX2, rx_intr2);
1289 rx_intr_mask |= (rx_intr2 << 16);
1290 }
1291
1292 for (i = 0; rx_intr_mask && i < ARRAY_SIZE(qdma->q_rx); i++) {
1293 if (!qdma->q_rx[i].ndesc)
1294 continue;
1295
1296 if (rx_intr_mask & BIT(i))
1297 napi_schedule(&qdma->q_rx[i].napi);
1298 }
1299
1300 if (intr[0] & INT_TX_MASK) {
1301 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) {
1302 if (!(intr[0] & TX_DONE_INT_MASK(i)))
1303 continue;
1304
1305 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX0,
1306 TX_DONE_INT_MASK(i));
1307 napi_schedule(&qdma->q_tx_irq[i].napi);
1308 }
1309 }
1310
1311 return IRQ_HANDLED;
1312 }
1313
airoha_qdma_init_irq_banks(struct platform_device * pdev,struct airoha_qdma * qdma)1314 static int airoha_qdma_init_irq_banks(struct platform_device *pdev,
1315 struct airoha_qdma *qdma)
1316 {
1317 struct airoha_eth *eth = qdma->eth;
1318 int i, id = qdma - ð->qdma[0];
1319
1320 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) {
1321 struct airoha_irq_bank *irq_bank = &qdma->irq_banks[i];
1322 int err, irq_index = 4 * id + i;
1323 const char *name;
1324
1325 spin_lock_init(&irq_bank->irq_lock);
1326 irq_bank->qdma = qdma;
1327
1328 irq_bank->irq = platform_get_irq(pdev, irq_index);
1329 if (irq_bank->irq < 0)
1330 return irq_bank->irq;
1331
1332 name = devm_kasprintf(eth->dev, GFP_KERNEL,
1333 KBUILD_MODNAME ".%d", irq_index);
1334 if (!name)
1335 return -ENOMEM;
1336
1337 err = devm_request_irq(eth->dev, irq_bank->irq,
1338 airoha_irq_handler, IRQF_SHARED, name,
1339 irq_bank);
1340 if (err)
1341 return err;
1342 }
1343
1344 return 0;
1345 }
1346
airoha_qdma_init(struct platform_device * pdev,struct airoha_eth * eth,struct airoha_qdma * qdma)1347 static int airoha_qdma_init(struct platform_device *pdev,
1348 struct airoha_eth *eth,
1349 struct airoha_qdma *qdma)
1350 {
1351 int err, id = qdma - ð->qdma[0];
1352 const char *res;
1353
1354 qdma->eth = eth;
1355 res = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d", id);
1356 if (!res)
1357 return -ENOMEM;
1358
1359 qdma->regs = devm_platform_ioremap_resource_byname(pdev, res);
1360 if (IS_ERR(qdma->regs))
1361 return dev_err_probe(eth->dev, PTR_ERR(qdma->regs),
1362 "failed to iomap qdma%d regs\n", id);
1363
1364 err = airoha_qdma_init_irq_banks(pdev, qdma);
1365 if (err)
1366 return err;
1367
1368 err = airoha_qdma_init_rx(qdma);
1369 if (err)
1370 return err;
1371
1372 err = airoha_qdma_init_tx(qdma);
1373 if (err)
1374 return err;
1375
1376 err = airoha_qdma_init_hfwd_queues(qdma);
1377 if (err)
1378 return err;
1379
1380 return airoha_qdma_hw_init(qdma);
1381 }
1382
airoha_hw_init(struct platform_device * pdev,struct airoha_eth * eth)1383 static int airoha_hw_init(struct platform_device *pdev,
1384 struct airoha_eth *eth)
1385 {
1386 int err, i;
1387
1388 /* disable xsi */
1389 err = reset_control_bulk_assert(ARRAY_SIZE(eth->xsi_rsts),
1390 eth->xsi_rsts);
1391 if (err)
1392 return err;
1393
1394 err = reset_control_bulk_assert(ARRAY_SIZE(eth->rsts), eth->rsts);
1395 if (err)
1396 return err;
1397
1398 msleep(20);
1399 err = reset_control_bulk_deassert(ARRAY_SIZE(eth->rsts), eth->rsts);
1400 if (err)
1401 return err;
1402
1403 msleep(20);
1404 err = airoha_fe_init(eth);
1405 if (err)
1406 return err;
1407
1408 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) {
1409 err = airoha_qdma_init(pdev, eth, ð->qdma[i]);
1410 if (err)
1411 return err;
1412 }
1413
1414 err = airoha_ppe_init(eth);
1415 if (err)
1416 return err;
1417
1418 set_bit(DEV_STATE_INITIALIZED, ð->state);
1419
1420 return 0;
1421 }
1422
airoha_hw_cleanup(struct airoha_qdma * qdma)1423 static void airoha_hw_cleanup(struct airoha_qdma *qdma)
1424 {
1425 int i;
1426
1427 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
1428 if (!qdma->q_rx[i].ndesc)
1429 continue;
1430
1431 netif_napi_del(&qdma->q_rx[i].napi);
1432 airoha_qdma_cleanup_rx_queue(&qdma->q_rx[i]);
1433 if (qdma->q_rx[i].page_pool)
1434 page_pool_destroy(qdma->q_rx[i].page_pool);
1435 }
1436
1437 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++)
1438 netif_napi_del(&qdma->q_tx_irq[i].napi);
1439
1440 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
1441 if (!qdma->q_tx[i].ndesc)
1442 continue;
1443
1444 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]);
1445 }
1446 }
1447
airoha_qdma_start_napi(struct airoha_qdma * qdma)1448 static void airoha_qdma_start_napi(struct airoha_qdma *qdma)
1449 {
1450 int i;
1451
1452 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++)
1453 napi_enable(&qdma->q_tx_irq[i].napi);
1454
1455 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
1456 if (!qdma->q_rx[i].ndesc)
1457 continue;
1458
1459 napi_enable(&qdma->q_rx[i].napi);
1460 }
1461 }
1462
airoha_qdma_stop_napi(struct airoha_qdma * qdma)1463 static void airoha_qdma_stop_napi(struct airoha_qdma *qdma)
1464 {
1465 int i;
1466
1467 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++)
1468 napi_disable(&qdma->q_tx_irq[i].napi);
1469
1470 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
1471 if (!qdma->q_rx[i].ndesc)
1472 continue;
1473
1474 napi_disable(&qdma->q_rx[i].napi);
1475 }
1476 }
1477
airoha_update_hw_stats(struct airoha_gdm_port * port)1478 static void airoha_update_hw_stats(struct airoha_gdm_port *port)
1479 {
1480 struct airoha_eth *eth = port->qdma->eth;
1481 u32 val, i = 0;
1482
1483 spin_lock(&port->stats.lock);
1484 u64_stats_update_begin(&port->stats.syncp);
1485
1486 /* TX */
1487 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_H(port->id));
1488 port->stats.tx_ok_pkts += ((u64)val << 32);
1489 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_L(port->id));
1490 port->stats.tx_ok_pkts += val;
1491
1492 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_H(port->id));
1493 port->stats.tx_ok_bytes += ((u64)val << 32);
1494 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_L(port->id));
1495 port->stats.tx_ok_bytes += val;
1496
1497 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_DROP_CNT(port->id));
1498 port->stats.tx_drops += val;
1499
1500 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_BC_CNT(port->id));
1501 port->stats.tx_broadcast += val;
1502
1503 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_MC_CNT(port->id));
1504 port->stats.tx_multicast += val;
1505
1506 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_RUNT_CNT(port->id));
1507 port->stats.tx_len[i] += val;
1508
1509 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_H(port->id));
1510 port->stats.tx_len[i] += ((u64)val << 32);
1511 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_L(port->id));
1512 port->stats.tx_len[i++] += val;
1513
1514 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_H(port->id));
1515 port->stats.tx_len[i] += ((u64)val << 32);
1516 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_L(port->id));
1517 port->stats.tx_len[i++] += val;
1518
1519 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_H(port->id));
1520 port->stats.tx_len[i] += ((u64)val << 32);
1521 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_L(port->id));
1522 port->stats.tx_len[i++] += val;
1523
1524 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_H(port->id));
1525 port->stats.tx_len[i] += ((u64)val << 32);
1526 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_L(port->id));
1527 port->stats.tx_len[i++] += val;
1528
1529 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_H(port->id));
1530 port->stats.tx_len[i] += ((u64)val << 32);
1531 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_L(port->id));
1532 port->stats.tx_len[i++] += val;
1533
1534 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_H(port->id));
1535 port->stats.tx_len[i] += ((u64)val << 32);
1536 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_L(port->id));
1537 port->stats.tx_len[i++] += val;
1538
1539 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_LONG_CNT(port->id));
1540 port->stats.tx_len[i++] += val;
1541
1542 /* RX */
1543 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_H(port->id));
1544 port->stats.rx_ok_pkts += ((u64)val << 32);
1545 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_L(port->id));
1546 port->stats.rx_ok_pkts += val;
1547
1548 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_H(port->id));
1549 port->stats.rx_ok_bytes += ((u64)val << 32);
1550 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_L(port->id));
1551 port->stats.rx_ok_bytes += val;
1552
1553 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_DROP_CNT(port->id));
1554 port->stats.rx_drops += val;
1555
1556 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_BC_CNT(port->id));
1557 port->stats.rx_broadcast += val;
1558
1559 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_MC_CNT(port->id));
1560 port->stats.rx_multicast += val;
1561
1562 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ERROR_DROP_CNT(port->id));
1563 port->stats.rx_errors += val;
1564
1565 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_CRC_ERR_CNT(port->id));
1566 port->stats.rx_crc_error += val;
1567
1568 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OVERFLOW_DROP_CNT(port->id));
1569 port->stats.rx_over_errors += val;
1570
1571 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_FRAG_CNT(port->id));
1572 port->stats.rx_fragment += val;
1573
1574 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_JABBER_CNT(port->id));
1575 port->stats.rx_jabber += val;
1576
1577 i = 0;
1578 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_RUNT_CNT(port->id));
1579 port->stats.rx_len[i] += val;
1580
1581 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_H(port->id));
1582 port->stats.rx_len[i] += ((u64)val << 32);
1583 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_L(port->id));
1584 port->stats.rx_len[i++] += val;
1585
1586 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_H(port->id));
1587 port->stats.rx_len[i] += ((u64)val << 32);
1588 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_L(port->id));
1589 port->stats.rx_len[i++] += val;
1590
1591 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_H(port->id));
1592 port->stats.rx_len[i] += ((u64)val << 32);
1593 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_L(port->id));
1594 port->stats.rx_len[i++] += val;
1595
1596 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_H(port->id));
1597 port->stats.rx_len[i] += ((u64)val << 32);
1598 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_L(port->id));
1599 port->stats.rx_len[i++] += val;
1600
1601 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_H(port->id));
1602 port->stats.rx_len[i] += ((u64)val << 32);
1603 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_L(port->id));
1604 port->stats.rx_len[i++] += val;
1605
1606 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_H(port->id));
1607 port->stats.rx_len[i] += ((u64)val << 32);
1608 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_L(port->id));
1609 port->stats.rx_len[i++] += val;
1610
1611 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_LONG_CNT(port->id));
1612 port->stats.rx_len[i++] += val;
1613
1614 /* reset mib counters */
1615 airoha_fe_set(eth, REG_FE_GDM_MIB_CLEAR(port->id),
1616 FE_GDM_MIB_RX_CLEAR_MASK | FE_GDM_MIB_TX_CLEAR_MASK);
1617
1618 u64_stats_update_end(&port->stats.syncp);
1619 spin_unlock(&port->stats.lock);
1620 }
1621
airoha_dev_open(struct net_device * dev)1622 static int airoha_dev_open(struct net_device *dev)
1623 {
1624 int err, len = ETH_HLEN + dev->mtu + ETH_FCS_LEN;
1625 struct airoha_gdm_port *port = netdev_priv(dev);
1626 struct airoha_qdma *qdma = port->qdma;
1627
1628 netif_tx_start_all_queues(dev);
1629 err = airoha_set_vip_for_gdm_port(port, true);
1630 if (err)
1631 return err;
1632
1633 if (netdev_uses_dsa(dev))
1634 airoha_fe_set(qdma->eth, REG_GDM_INGRESS_CFG(port->id),
1635 GDM_STAG_EN_MASK);
1636 else
1637 airoha_fe_clear(qdma->eth, REG_GDM_INGRESS_CFG(port->id),
1638 GDM_STAG_EN_MASK);
1639
1640 airoha_fe_rmw(qdma->eth, REG_GDM_LEN_CFG(port->id),
1641 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK,
1642 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) |
1643 FIELD_PREP(GDM_LONG_LEN_MASK, len));
1644
1645 airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG,
1646 GLOBAL_CFG_TX_DMA_EN_MASK |
1647 GLOBAL_CFG_RX_DMA_EN_MASK);
1648 atomic_inc(&qdma->users);
1649
1650 return 0;
1651 }
1652
airoha_dev_stop(struct net_device * dev)1653 static int airoha_dev_stop(struct net_device *dev)
1654 {
1655 struct airoha_gdm_port *port = netdev_priv(dev);
1656 struct airoha_qdma *qdma = port->qdma;
1657 int i, err;
1658
1659 netif_tx_disable(dev);
1660 err = airoha_set_vip_for_gdm_port(port, false);
1661 if (err)
1662 return err;
1663
1664 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++)
1665 netdev_tx_reset_subqueue(dev, i);
1666
1667 if (atomic_dec_and_test(&qdma->users)) {
1668 airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG,
1669 GLOBAL_CFG_TX_DMA_EN_MASK |
1670 GLOBAL_CFG_RX_DMA_EN_MASK);
1671
1672 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
1673 if (!qdma->q_tx[i].ndesc)
1674 continue;
1675
1676 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]);
1677 }
1678 }
1679
1680 return 0;
1681 }
1682
airoha_dev_set_macaddr(struct net_device * dev,void * p)1683 static int airoha_dev_set_macaddr(struct net_device *dev, void *p)
1684 {
1685 struct airoha_gdm_port *port = netdev_priv(dev);
1686 int err;
1687
1688 err = eth_mac_addr(dev, p);
1689 if (err)
1690 return err;
1691
1692 airoha_set_macaddr(port, dev->dev_addr);
1693
1694 return 0;
1695 }
1696
airhoha_set_gdm2_loopback(struct airoha_gdm_port * port)1697 static void airhoha_set_gdm2_loopback(struct airoha_gdm_port *port)
1698 {
1699 u32 pse_port = port->id == 3 ? FE_PSE_PORT_GDM3 : FE_PSE_PORT_GDM4;
1700 struct airoha_eth *eth = port->qdma->eth;
1701 u32 chan = port->id == 3 ? 4 : 0;
1702
1703 /* Forward the traffic to the proper GDM port */
1704 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(2), pse_port);
1705 airoha_fe_clear(eth, REG_GDM_FWD_CFG(2), GDM_STRIP_CRC);
1706
1707 /* Enable GDM2 loopback */
1708 airoha_fe_wr(eth, REG_GDM_TXCHN_EN(2), 0xffffffff);
1709 airoha_fe_wr(eth, REG_GDM_RXCHN_EN(2), 0xffff);
1710 airoha_fe_rmw(eth, REG_GDM_LPBK_CFG(2),
1711 LPBK_CHAN_MASK | LPBK_MODE_MASK | LPBK_EN_MASK,
1712 FIELD_PREP(LPBK_CHAN_MASK, chan) | LPBK_EN_MASK);
1713 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(2),
1714 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK,
1715 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) |
1716 FIELD_PREP(GDM_LONG_LEN_MASK, AIROHA_MAX_MTU));
1717
1718 /* Disable VIP and IFC for GDM2 */
1719 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(2));
1720 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(2));
1721
1722 if (port->id == 3) {
1723 /* FIXME: handle XSI_PCE1_PORT */
1724 airoha_fe_rmw(eth, REG_FE_WAN_PORT,
1725 WAN1_EN_MASK | WAN1_MASK | WAN0_MASK,
1726 FIELD_PREP(WAN0_MASK, HSGMII_LAN_PCIE0_SRCPORT));
1727 airoha_fe_rmw(eth,
1728 REG_SP_DFT_CPORT(HSGMII_LAN_PCIE0_SRCPORT >> 3),
1729 SP_CPORT_PCIE0_MASK,
1730 FIELD_PREP(SP_CPORT_PCIE0_MASK,
1731 FE_PSE_PORT_CDM2));
1732 } else {
1733 /* FIXME: handle XSI_USB_PORT */
1734 airoha_fe_rmw(eth, REG_SRC_PORT_FC_MAP6,
1735 FC_ID_OF_SRC_PORT24_MASK,
1736 FIELD_PREP(FC_ID_OF_SRC_PORT24_MASK, 2));
1737 airoha_fe_rmw(eth, REG_FE_WAN_PORT,
1738 WAN1_EN_MASK | WAN1_MASK | WAN0_MASK,
1739 FIELD_PREP(WAN0_MASK, HSGMII_LAN_ETH_SRCPORT));
1740 airoha_fe_rmw(eth,
1741 REG_SP_DFT_CPORT(HSGMII_LAN_ETH_SRCPORT >> 3),
1742 SP_CPORT_ETH_MASK,
1743 FIELD_PREP(SP_CPORT_ETH_MASK, FE_PSE_PORT_CDM2));
1744 }
1745 }
1746
airoha_dev_init(struct net_device * dev)1747 static int airoha_dev_init(struct net_device *dev)
1748 {
1749 struct airoha_gdm_port *port = netdev_priv(dev);
1750 struct airoha_eth *eth = port->qdma->eth;
1751 u32 pse_port;
1752
1753 airoha_set_macaddr(port, dev->dev_addr);
1754
1755 switch (port->id) {
1756 case 3:
1757 case 4:
1758 /* If GDM2 is active we can't enable loopback */
1759 if (!eth->ports[1])
1760 airhoha_set_gdm2_loopback(port);
1761 fallthrough;
1762 case 2:
1763 pse_port = FE_PSE_PORT_PPE2;
1764 break;
1765 default:
1766 pse_port = FE_PSE_PORT_PPE1;
1767 break;
1768 }
1769
1770 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(port->id), pse_port);
1771
1772 return 0;
1773 }
1774
airoha_dev_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * storage)1775 static void airoha_dev_get_stats64(struct net_device *dev,
1776 struct rtnl_link_stats64 *storage)
1777 {
1778 struct airoha_gdm_port *port = netdev_priv(dev);
1779 unsigned int start;
1780
1781 airoha_update_hw_stats(port);
1782 do {
1783 start = u64_stats_fetch_begin(&port->stats.syncp);
1784 storage->rx_packets = port->stats.rx_ok_pkts;
1785 storage->tx_packets = port->stats.tx_ok_pkts;
1786 storage->rx_bytes = port->stats.rx_ok_bytes;
1787 storage->tx_bytes = port->stats.tx_ok_bytes;
1788 storage->multicast = port->stats.rx_multicast;
1789 storage->rx_errors = port->stats.rx_errors;
1790 storage->rx_dropped = port->stats.rx_drops;
1791 storage->tx_dropped = port->stats.tx_drops;
1792 storage->rx_crc_errors = port->stats.rx_crc_error;
1793 storage->rx_over_errors = port->stats.rx_over_errors;
1794 } while (u64_stats_fetch_retry(&port->stats.syncp, start));
1795 }
1796
airoha_dev_change_mtu(struct net_device * dev,int mtu)1797 static int airoha_dev_change_mtu(struct net_device *dev, int mtu)
1798 {
1799 struct airoha_gdm_port *port = netdev_priv(dev);
1800 struct airoha_eth *eth = port->qdma->eth;
1801 u32 len = ETH_HLEN + mtu + ETH_FCS_LEN;
1802
1803 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(port->id),
1804 GDM_LONG_LEN_MASK,
1805 FIELD_PREP(GDM_LONG_LEN_MASK, len));
1806 WRITE_ONCE(dev->mtu, mtu);
1807
1808 return 0;
1809 }
1810
airoha_dev_select_queue(struct net_device * dev,struct sk_buff * skb,struct net_device * sb_dev)1811 static u16 airoha_dev_select_queue(struct net_device *dev, struct sk_buff *skb,
1812 struct net_device *sb_dev)
1813 {
1814 struct airoha_gdm_port *port = netdev_priv(dev);
1815 int queue, channel;
1816
1817 /* For dsa device select QoS channel according to the dsa user port
1818 * index, rely on port id otherwise. Select QoS queue based on the
1819 * skb priority.
1820 */
1821 channel = netdev_uses_dsa(dev) ? skb_get_queue_mapping(skb) : port->id;
1822 channel = channel % AIROHA_NUM_QOS_CHANNELS;
1823 queue = (skb->priority - 1) % AIROHA_NUM_QOS_QUEUES; /* QoS queue */
1824 queue = channel * AIROHA_NUM_QOS_QUEUES + queue;
1825
1826 return queue < dev->num_tx_queues ? queue : 0;
1827 }
1828
airoha_get_dsa_tag(struct sk_buff * skb,struct net_device * dev)1829 static u32 airoha_get_dsa_tag(struct sk_buff *skb, struct net_device *dev)
1830 {
1831 #if IS_ENABLED(CONFIG_NET_DSA)
1832 struct ethhdr *ehdr;
1833 u8 xmit_tpid;
1834 u16 tag;
1835
1836 if (!netdev_uses_dsa(dev))
1837 return 0;
1838
1839 if (dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK)
1840 return 0;
1841
1842 if (skb_cow_head(skb, 0))
1843 return 0;
1844
1845 ehdr = (struct ethhdr *)skb->data;
1846 tag = be16_to_cpu(ehdr->h_proto);
1847 xmit_tpid = tag >> 8;
1848
1849 switch (xmit_tpid) {
1850 case MTK_HDR_XMIT_TAGGED_TPID_8100:
1851 ehdr->h_proto = cpu_to_be16(ETH_P_8021Q);
1852 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_8100 << 8);
1853 break;
1854 case MTK_HDR_XMIT_TAGGED_TPID_88A8:
1855 ehdr->h_proto = cpu_to_be16(ETH_P_8021AD);
1856 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_88A8 << 8);
1857 break;
1858 default:
1859 /* PPE module requires untagged DSA packets to work properly,
1860 * so move DSA tag to DMA descriptor.
1861 */
1862 memmove(skb->data + MTK_HDR_LEN, skb->data, 2 * ETH_ALEN);
1863 __skb_pull(skb, MTK_HDR_LEN);
1864 break;
1865 }
1866
1867 return tag;
1868 #else
1869 return 0;
1870 #endif
1871 }
1872
airoha_dev_xmit(struct sk_buff * skb,struct net_device * dev)1873 static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb,
1874 struct net_device *dev)
1875 {
1876 struct airoha_gdm_port *port = netdev_priv(dev);
1877 struct airoha_qdma *qdma = port->qdma;
1878 u32 nr_frags, tag, msg0, msg1, len;
1879 struct netdev_queue *txq;
1880 struct airoha_queue *q;
1881 void *data;
1882 int i, qid;
1883 u16 index;
1884 u8 fport;
1885
1886 qid = skb_get_queue_mapping(skb) % ARRAY_SIZE(qdma->q_tx);
1887 tag = airoha_get_dsa_tag(skb, dev);
1888
1889 msg0 = FIELD_PREP(QDMA_ETH_TXMSG_CHAN_MASK,
1890 qid / AIROHA_NUM_QOS_QUEUES) |
1891 FIELD_PREP(QDMA_ETH_TXMSG_QUEUE_MASK,
1892 qid % AIROHA_NUM_QOS_QUEUES) |
1893 FIELD_PREP(QDMA_ETH_TXMSG_SP_TAG_MASK, tag);
1894 if (skb->ip_summed == CHECKSUM_PARTIAL)
1895 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TCO_MASK, 1) |
1896 FIELD_PREP(QDMA_ETH_TXMSG_UCO_MASK, 1) |
1897 FIELD_PREP(QDMA_ETH_TXMSG_ICO_MASK, 1);
1898
1899 /* TSO: fill MSS info in tcp checksum field */
1900 if (skb_is_gso(skb)) {
1901 if (skb_cow_head(skb, 0))
1902 goto error;
1903
1904 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 |
1905 SKB_GSO_TCPV6)) {
1906 __be16 csum = cpu_to_be16(skb_shinfo(skb)->gso_size);
1907
1908 tcp_hdr(skb)->check = (__force __sum16)csum;
1909 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TSO_MASK, 1);
1910 }
1911 }
1912
1913 fport = port->id == 4 ? FE_PSE_PORT_GDM4 : port->id;
1914 msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) |
1915 FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f);
1916
1917 q = &qdma->q_tx[qid];
1918 if (WARN_ON_ONCE(!q->ndesc))
1919 goto error;
1920
1921 spin_lock_bh(&q->lock);
1922
1923 txq = netdev_get_tx_queue(dev, qid);
1924 nr_frags = 1 + skb_shinfo(skb)->nr_frags;
1925
1926 if (q->queued + nr_frags > q->ndesc) {
1927 /* not enough space in the queue */
1928 netif_tx_stop_queue(txq);
1929 spin_unlock_bh(&q->lock);
1930 return NETDEV_TX_BUSY;
1931 }
1932
1933 len = skb_headlen(skb);
1934 data = skb->data;
1935 index = q->head;
1936
1937 for (i = 0; i < nr_frags; i++) {
1938 struct airoha_qdma_desc *desc = &q->desc[index];
1939 struct airoha_queue_entry *e = &q->entry[index];
1940 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1941 dma_addr_t addr;
1942 u32 val;
1943
1944 addr = dma_map_single(dev->dev.parent, data, len,
1945 DMA_TO_DEVICE);
1946 if (unlikely(dma_mapping_error(dev->dev.parent, addr)))
1947 goto error_unmap;
1948
1949 index = (index + 1) % q->ndesc;
1950
1951 val = FIELD_PREP(QDMA_DESC_LEN_MASK, len);
1952 if (i < nr_frags - 1)
1953 val |= FIELD_PREP(QDMA_DESC_MORE_MASK, 1);
1954 WRITE_ONCE(desc->ctrl, cpu_to_le32(val));
1955 WRITE_ONCE(desc->addr, cpu_to_le32(addr));
1956 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, index);
1957 WRITE_ONCE(desc->data, cpu_to_le32(val));
1958 WRITE_ONCE(desc->msg0, cpu_to_le32(msg0));
1959 WRITE_ONCE(desc->msg1, cpu_to_le32(msg1));
1960 WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff));
1961
1962 e->skb = i ? NULL : skb;
1963 e->dma_addr = addr;
1964 e->dma_len = len;
1965
1966 data = skb_frag_address(frag);
1967 len = skb_frag_size(frag);
1968 }
1969
1970 q->head = index;
1971 q->queued += i;
1972
1973 skb_tx_timestamp(skb);
1974 netdev_tx_sent_queue(txq, skb->len);
1975
1976 if (netif_xmit_stopped(txq) || !netdev_xmit_more())
1977 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid),
1978 TX_RING_CPU_IDX_MASK,
1979 FIELD_PREP(TX_RING_CPU_IDX_MASK, q->head));
1980
1981 if (q->ndesc - q->queued < q->free_thr)
1982 netif_tx_stop_queue(txq);
1983
1984 spin_unlock_bh(&q->lock);
1985
1986 return NETDEV_TX_OK;
1987
1988 error_unmap:
1989 for (i--; i >= 0; i--) {
1990 index = (q->head + i) % q->ndesc;
1991 dma_unmap_single(dev->dev.parent, q->entry[index].dma_addr,
1992 q->entry[index].dma_len, DMA_TO_DEVICE);
1993 }
1994
1995 spin_unlock_bh(&q->lock);
1996 error:
1997 dev_kfree_skb_any(skb);
1998 dev->stats.tx_dropped++;
1999
2000 return NETDEV_TX_OK;
2001 }
2002
airoha_ethtool_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)2003 static void airoha_ethtool_get_drvinfo(struct net_device *dev,
2004 struct ethtool_drvinfo *info)
2005 {
2006 struct airoha_gdm_port *port = netdev_priv(dev);
2007 struct airoha_eth *eth = port->qdma->eth;
2008
2009 strscpy(info->driver, eth->dev->driver->name, sizeof(info->driver));
2010 strscpy(info->bus_info, dev_name(eth->dev), sizeof(info->bus_info));
2011 }
2012
airoha_ethtool_get_mac_stats(struct net_device * dev,struct ethtool_eth_mac_stats * stats)2013 static void airoha_ethtool_get_mac_stats(struct net_device *dev,
2014 struct ethtool_eth_mac_stats *stats)
2015 {
2016 struct airoha_gdm_port *port = netdev_priv(dev);
2017 unsigned int start;
2018
2019 airoha_update_hw_stats(port);
2020 do {
2021 start = u64_stats_fetch_begin(&port->stats.syncp);
2022 stats->MulticastFramesXmittedOK = port->stats.tx_multicast;
2023 stats->BroadcastFramesXmittedOK = port->stats.tx_broadcast;
2024 stats->BroadcastFramesReceivedOK = port->stats.rx_broadcast;
2025 } while (u64_stats_fetch_retry(&port->stats.syncp, start));
2026 }
2027
2028 static const struct ethtool_rmon_hist_range airoha_ethtool_rmon_ranges[] = {
2029 { 0, 64 },
2030 { 65, 127 },
2031 { 128, 255 },
2032 { 256, 511 },
2033 { 512, 1023 },
2034 { 1024, 1518 },
2035 { 1519, 10239 },
2036 {},
2037 };
2038
2039 static void
airoha_ethtool_get_rmon_stats(struct net_device * dev,struct ethtool_rmon_stats * stats,const struct ethtool_rmon_hist_range ** ranges)2040 airoha_ethtool_get_rmon_stats(struct net_device *dev,
2041 struct ethtool_rmon_stats *stats,
2042 const struct ethtool_rmon_hist_range **ranges)
2043 {
2044 struct airoha_gdm_port *port = netdev_priv(dev);
2045 struct airoha_hw_stats *hw_stats = &port->stats;
2046 unsigned int start;
2047
2048 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) !=
2049 ARRAY_SIZE(hw_stats->tx_len) + 1);
2050 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) !=
2051 ARRAY_SIZE(hw_stats->rx_len) + 1);
2052
2053 *ranges = airoha_ethtool_rmon_ranges;
2054 airoha_update_hw_stats(port);
2055 do {
2056 int i;
2057
2058 start = u64_stats_fetch_begin(&port->stats.syncp);
2059 stats->fragments = hw_stats->rx_fragment;
2060 stats->jabbers = hw_stats->rx_jabber;
2061 for (i = 0; i < ARRAY_SIZE(airoha_ethtool_rmon_ranges) - 1;
2062 i++) {
2063 stats->hist[i] = hw_stats->rx_len[i];
2064 stats->hist_tx[i] = hw_stats->tx_len[i];
2065 }
2066 } while (u64_stats_fetch_retry(&port->stats.syncp, start));
2067 }
2068
airoha_qdma_set_chan_tx_sched(struct airoha_gdm_port * port,int channel,enum tx_sched_mode mode,const u16 * weights,u8 n_weights)2069 static int airoha_qdma_set_chan_tx_sched(struct airoha_gdm_port *port,
2070 int channel, enum tx_sched_mode mode,
2071 const u16 *weights, u8 n_weights)
2072 {
2073 int i;
2074
2075 for (i = 0; i < AIROHA_NUM_TX_RING; i++)
2076 airoha_qdma_clear(port->qdma, REG_QUEUE_CLOSE_CFG(channel),
2077 TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i));
2078
2079 for (i = 0; i < n_weights; i++) {
2080 u32 status;
2081 int err;
2082
2083 airoha_qdma_wr(port->qdma, REG_TXWRR_WEIGHT_CFG,
2084 TWRR_RW_CMD_MASK |
2085 FIELD_PREP(TWRR_CHAN_IDX_MASK, channel) |
2086 FIELD_PREP(TWRR_QUEUE_IDX_MASK, i) |
2087 FIELD_PREP(TWRR_VALUE_MASK, weights[i]));
2088 err = read_poll_timeout(airoha_qdma_rr, status,
2089 status & TWRR_RW_CMD_DONE,
2090 USEC_PER_MSEC, 10 * USEC_PER_MSEC,
2091 true, port->qdma,
2092 REG_TXWRR_WEIGHT_CFG);
2093 if (err)
2094 return err;
2095 }
2096
2097 airoha_qdma_rmw(port->qdma, REG_CHAN_QOS_MODE(channel >> 3),
2098 CHAN_QOS_MODE_MASK(channel),
2099 mode << __ffs(CHAN_QOS_MODE_MASK(channel)));
2100
2101 return 0;
2102 }
2103
airoha_qdma_set_tx_prio_sched(struct airoha_gdm_port * port,int channel)2104 static int airoha_qdma_set_tx_prio_sched(struct airoha_gdm_port *port,
2105 int channel)
2106 {
2107 static const u16 w[AIROHA_NUM_QOS_QUEUES] = {};
2108
2109 return airoha_qdma_set_chan_tx_sched(port, channel, TC_SCH_SP, w,
2110 ARRAY_SIZE(w));
2111 }
2112
airoha_qdma_set_tx_ets_sched(struct airoha_gdm_port * port,int channel,struct tc_ets_qopt_offload * opt)2113 static int airoha_qdma_set_tx_ets_sched(struct airoha_gdm_port *port,
2114 int channel,
2115 struct tc_ets_qopt_offload *opt)
2116 {
2117 struct tc_ets_qopt_offload_replace_params *p = &opt->replace_params;
2118 enum tx_sched_mode mode = TC_SCH_SP;
2119 u16 w[AIROHA_NUM_QOS_QUEUES] = {};
2120 int i, nstrict = 0;
2121
2122 if (p->bands > AIROHA_NUM_QOS_QUEUES)
2123 return -EINVAL;
2124
2125 for (i = 0; i < p->bands; i++) {
2126 if (!p->quanta[i])
2127 nstrict++;
2128 }
2129
2130 /* this configuration is not supported by the hw */
2131 if (nstrict == AIROHA_NUM_QOS_QUEUES - 1)
2132 return -EINVAL;
2133
2134 /* EN7581 SoC supports fixed QoS band priority where WRR queues have
2135 * lowest priorities with respect to SP ones.
2136 * e.g: WRR0, WRR1, .., WRRm, SP0, SP1, .., SPn
2137 */
2138 for (i = 0; i < nstrict; i++) {
2139 if (p->priomap[p->bands - i - 1] != i)
2140 return -EINVAL;
2141 }
2142
2143 for (i = 0; i < p->bands - nstrict; i++) {
2144 if (p->priomap[i] != nstrict + i)
2145 return -EINVAL;
2146
2147 w[i] = p->weights[nstrict + i];
2148 }
2149
2150 if (!nstrict)
2151 mode = TC_SCH_WRR8;
2152 else if (nstrict < AIROHA_NUM_QOS_QUEUES - 1)
2153 mode = nstrict + 1;
2154
2155 return airoha_qdma_set_chan_tx_sched(port, channel, mode, w,
2156 ARRAY_SIZE(w));
2157 }
2158
airoha_qdma_get_tx_ets_stats(struct airoha_gdm_port * port,int channel,struct tc_ets_qopt_offload * opt)2159 static int airoha_qdma_get_tx_ets_stats(struct airoha_gdm_port *port,
2160 int channel,
2161 struct tc_ets_qopt_offload *opt)
2162 {
2163 u64 cpu_tx_packets = airoha_qdma_rr(port->qdma,
2164 REG_CNTR_VAL(channel << 1));
2165 u64 fwd_tx_packets = airoha_qdma_rr(port->qdma,
2166 REG_CNTR_VAL((channel << 1) + 1));
2167 u64 tx_packets = (cpu_tx_packets - port->cpu_tx_packets) +
2168 (fwd_tx_packets - port->fwd_tx_packets);
2169 _bstats_update(opt->stats.bstats, 0, tx_packets);
2170
2171 port->cpu_tx_packets = cpu_tx_packets;
2172 port->fwd_tx_packets = fwd_tx_packets;
2173
2174 return 0;
2175 }
2176
airoha_tc_setup_qdisc_ets(struct airoha_gdm_port * port,struct tc_ets_qopt_offload * opt)2177 static int airoha_tc_setup_qdisc_ets(struct airoha_gdm_port *port,
2178 struct tc_ets_qopt_offload *opt)
2179 {
2180 int channel;
2181
2182 if (opt->parent == TC_H_ROOT)
2183 return -EINVAL;
2184
2185 channel = TC_H_MAJ(opt->handle) >> 16;
2186 channel = channel % AIROHA_NUM_QOS_CHANNELS;
2187
2188 switch (opt->command) {
2189 case TC_ETS_REPLACE:
2190 return airoha_qdma_set_tx_ets_sched(port, channel, opt);
2191 case TC_ETS_DESTROY:
2192 /* PRIO is default qdisc scheduler */
2193 return airoha_qdma_set_tx_prio_sched(port, channel);
2194 case TC_ETS_STATS:
2195 return airoha_qdma_get_tx_ets_stats(port, channel, opt);
2196 default:
2197 return -EOPNOTSUPP;
2198 }
2199 }
2200
airoha_qdma_get_rl_param(struct airoha_qdma * qdma,int queue_id,u32 addr,enum trtcm_param_type param,u32 * val_low,u32 * val_high)2201 static int airoha_qdma_get_rl_param(struct airoha_qdma *qdma, int queue_id,
2202 u32 addr, enum trtcm_param_type param,
2203 u32 *val_low, u32 *val_high)
2204 {
2205 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id);
2206 u32 val, config = FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) |
2207 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) |
2208 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx);
2209
2210 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config);
2211 if (read_poll_timeout(airoha_qdma_rr, val,
2212 val & RATE_LIMIT_PARAM_RW_DONE_MASK,
2213 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, qdma,
2214 REG_TRTCM_CFG_PARAM(addr)))
2215 return -ETIMEDOUT;
2216
2217 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr));
2218 if (val_high)
2219 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr));
2220
2221 return 0;
2222 }
2223
airoha_qdma_set_rl_param(struct airoha_qdma * qdma,int queue_id,u32 addr,enum trtcm_param_type param,u32 val)2224 static int airoha_qdma_set_rl_param(struct airoha_qdma *qdma, int queue_id,
2225 u32 addr, enum trtcm_param_type param,
2226 u32 val)
2227 {
2228 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id);
2229 u32 config = RATE_LIMIT_PARAM_RW_MASK |
2230 FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) |
2231 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) |
2232 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx);
2233
2234 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val);
2235 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config);
2236
2237 return read_poll_timeout(airoha_qdma_rr, val,
2238 val & RATE_LIMIT_PARAM_RW_DONE_MASK,
2239 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true,
2240 qdma, REG_TRTCM_CFG_PARAM(addr));
2241 }
2242
airoha_qdma_set_rl_config(struct airoha_qdma * qdma,int queue_id,u32 addr,bool enable,u32 enable_mask)2243 static int airoha_qdma_set_rl_config(struct airoha_qdma *qdma, int queue_id,
2244 u32 addr, bool enable, u32 enable_mask)
2245 {
2246 u32 val;
2247 int err;
2248
2249 err = airoha_qdma_get_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE,
2250 &val, NULL);
2251 if (err)
2252 return err;
2253
2254 val = enable ? val | enable_mask : val & ~enable_mask;
2255
2256 return airoha_qdma_set_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE,
2257 val);
2258 }
2259
airoha_qdma_set_rl_token_bucket(struct airoha_qdma * qdma,int queue_id,u32 rate_val,u32 bucket_size)2260 static int airoha_qdma_set_rl_token_bucket(struct airoha_qdma *qdma,
2261 int queue_id, u32 rate_val,
2262 u32 bucket_size)
2263 {
2264 u32 val, config, tick, unit, rate, rate_frac;
2265 int err;
2266
2267 err = airoha_qdma_get_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG,
2268 TRTCM_MISC_MODE, &config, NULL);
2269 if (err)
2270 return err;
2271
2272 val = airoha_qdma_rr(qdma, REG_INGRESS_TRTCM_CFG);
2273 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val);
2274 if (config & TRTCM_TICK_SEL)
2275 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val);
2276 if (!tick)
2277 return -EINVAL;
2278
2279 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick;
2280 if (!unit)
2281 return -EINVAL;
2282
2283 rate = rate_val / unit;
2284 rate_frac = rate_val % unit;
2285 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit;
2286 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) |
2287 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac);
2288
2289 err = airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG,
2290 TRTCM_TOKEN_RATE_MODE, rate);
2291 if (err)
2292 return err;
2293
2294 val = bucket_size;
2295 if (!(config & TRTCM_PKT_MODE))
2296 val = max_t(u32, val, MIN_TOKEN_SIZE);
2297 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET);
2298
2299 return airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG,
2300 TRTCM_BUCKETSIZE_SHIFT_MODE, val);
2301 }
2302
airoha_qdma_init_rl_config(struct airoha_qdma * qdma,int queue_id,bool enable,enum trtcm_unit_type unit)2303 static int airoha_qdma_init_rl_config(struct airoha_qdma *qdma, int queue_id,
2304 bool enable, enum trtcm_unit_type unit)
2305 {
2306 bool tick_sel = queue_id == 0 || queue_id == 2 || queue_id == 8;
2307 enum trtcm_param mode = TRTCM_METER_MODE;
2308 int err;
2309
2310 mode |= unit == TRTCM_PACKET_UNIT ? TRTCM_PKT_MODE : 0;
2311 err = airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG,
2312 enable, mode);
2313 if (err)
2314 return err;
2315
2316 return airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG,
2317 tick_sel, TRTCM_TICK_SEL);
2318 }
2319
airoha_qdma_get_trtcm_param(struct airoha_qdma * qdma,int channel,u32 addr,enum trtcm_param_type param,enum trtcm_mode_type mode,u32 * val_low,u32 * val_high)2320 static int airoha_qdma_get_trtcm_param(struct airoha_qdma *qdma, int channel,
2321 u32 addr, enum trtcm_param_type param,
2322 enum trtcm_mode_type mode,
2323 u32 *val_low, u32 *val_high)
2324 {
2325 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel);
2326 u32 val, config = FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) |
2327 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) |
2328 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) |
2329 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode);
2330
2331 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config);
2332 if (read_poll_timeout(airoha_qdma_rr, val,
2333 val & TRTCM_PARAM_RW_DONE_MASK,
2334 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true,
2335 qdma, REG_TRTCM_CFG_PARAM(addr)))
2336 return -ETIMEDOUT;
2337
2338 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr));
2339 if (val_high)
2340 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr));
2341
2342 return 0;
2343 }
2344
airoha_qdma_set_trtcm_param(struct airoha_qdma * qdma,int channel,u32 addr,enum trtcm_param_type param,enum trtcm_mode_type mode,u32 val)2345 static int airoha_qdma_set_trtcm_param(struct airoha_qdma *qdma, int channel,
2346 u32 addr, enum trtcm_param_type param,
2347 enum trtcm_mode_type mode, u32 val)
2348 {
2349 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel);
2350 u32 config = TRTCM_PARAM_RW_MASK |
2351 FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) |
2352 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) |
2353 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) |
2354 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode);
2355
2356 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val);
2357 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config);
2358
2359 return read_poll_timeout(airoha_qdma_rr, val,
2360 val & TRTCM_PARAM_RW_DONE_MASK,
2361 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true,
2362 qdma, REG_TRTCM_CFG_PARAM(addr));
2363 }
2364
airoha_qdma_set_trtcm_config(struct airoha_qdma * qdma,int channel,u32 addr,enum trtcm_mode_type mode,bool enable,u32 enable_mask)2365 static int airoha_qdma_set_trtcm_config(struct airoha_qdma *qdma, int channel,
2366 u32 addr, enum trtcm_mode_type mode,
2367 bool enable, u32 enable_mask)
2368 {
2369 u32 val;
2370
2371 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE,
2372 mode, &val, NULL))
2373 return -EINVAL;
2374
2375 val = enable ? val | enable_mask : val & ~enable_mask;
2376
2377 return airoha_qdma_set_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE,
2378 mode, val);
2379 }
2380
airoha_qdma_set_trtcm_token_bucket(struct airoha_qdma * qdma,int channel,u32 addr,enum trtcm_mode_type mode,u32 rate_val,u32 bucket_size)2381 static int airoha_qdma_set_trtcm_token_bucket(struct airoha_qdma *qdma,
2382 int channel, u32 addr,
2383 enum trtcm_mode_type mode,
2384 u32 rate_val, u32 bucket_size)
2385 {
2386 u32 val, config, tick, unit, rate, rate_frac;
2387 int err;
2388
2389 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE,
2390 mode, &config, NULL))
2391 return -EINVAL;
2392
2393 val = airoha_qdma_rr(qdma, addr);
2394 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val);
2395 if (config & TRTCM_TICK_SEL)
2396 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val);
2397 if (!tick)
2398 return -EINVAL;
2399
2400 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick;
2401 if (!unit)
2402 return -EINVAL;
2403
2404 rate = rate_val / unit;
2405 rate_frac = rate_val % unit;
2406 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit;
2407 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) |
2408 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac);
2409
2410 err = airoha_qdma_set_trtcm_param(qdma, channel, addr,
2411 TRTCM_TOKEN_RATE_MODE, mode, rate);
2412 if (err)
2413 return err;
2414
2415 val = max_t(u32, bucket_size, MIN_TOKEN_SIZE);
2416 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET);
2417
2418 return airoha_qdma_set_trtcm_param(qdma, channel, addr,
2419 TRTCM_BUCKETSIZE_SHIFT_MODE,
2420 mode, val);
2421 }
2422
airoha_qdma_set_tx_rate_limit(struct airoha_gdm_port * port,int channel,u32 rate,u32 bucket_size)2423 static int airoha_qdma_set_tx_rate_limit(struct airoha_gdm_port *port,
2424 int channel, u32 rate,
2425 u32 bucket_size)
2426 {
2427 int i, err;
2428
2429 for (i = 0; i <= TRTCM_PEAK_MODE; i++) {
2430 err = airoha_qdma_set_trtcm_config(port->qdma, channel,
2431 REG_EGRESS_TRTCM_CFG, i,
2432 !!rate, TRTCM_METER_MODE);
2433 if (err)
2434 return err;
2435
2436 err = airoha_qdma_set_trtcm_token_bucket(port->qdma, channel,
2437 REG_EGRESS_TRTCM_CFG,
2438 i, rate, bucket_size);
2439 if (err)
2440 return err;
2441 }
2442
2443 return 0;
2444 }
2445
airoha_tc_htb_alloc_leaf_queue(struct airoha_gdm_port * port,struct tc_htb_qopt_offload * opt)2446 static int airoha_tc_htb_alloc_leaf_queue(struct airoha_gdm_port *port,
2447 struct tc_htb_qopt_offload *opt)
2448 {
2449 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS;
2450 u32 rate = div_u64(opt->rate, 1000) << 3; /* kbps */
2451 struct net_device *dev = port->dev;
2452 int num_tx_queues = dev->real_num_tx_queues;
2453 int err;
2454
2455 if (opt->parent_classid != TC_HTB_CLASSID_ROOT) {
2456 NL_SET_ERR_MSG_MOD(opt->extack, "invalid parent classid");
2457 return -EINVAL;
2458 }
2459
2460 err = airoha_qdma_set_tx_rate_limit(port, channel, rate, opt->quantum);
2461 if (err) {
2462 NL_SET_ERR_MSG_MOD(opt->extack,
2463 "failed configuring htb offload");
2464 return err;
2465 }
2466
2467 if (opt->command == TC_HTB_NODE_MODIFY)
2468 return 0;
2469
2470 err = netif_set_real_num_tx_queues(dev, num_tx_queues + 1);
2471 if (err) {
2472 airoha_qdma_set_tx_rate_limit(port, channel, 0, opt->quantum);
2473 NL_SET_ERR_MSG_MOD(opt->extack,
2474 "failed setting real_num_tx_queues");
2475 return err;
2476 }
2477
2478 set_bit(channel, port->qos_sq_bmap);
2479 opt->qid = AIROHA_NUM_TX_RING + channel;
2480
2481 return 0;
2482 }
2483
airoha_qdma_set_rx_meter(struct airoha_gdm_port * port,u32 rate,u32 bucket_size,enum trtcm_unit_type unit_type)2484 static int airoha_qdma_set_rx_meter(struct airoha_gdm_port *port,
2485 u32 rate, u32 bucket_size,
2486 enum trtcm_unit_type unit_type)
2487 {
2488 struct airoha_qdma *qdma = port->qdma;
2489 int i;
2490
2491 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
2492 int err;
2493
2494 if (!qdma->q_rx[i].ndesc)
2495 continue;
2496
2497 err = airoha_qdma_init_rl_config(qdma, i, !!rate, unit_type);
2498 if (err)
2499 return err;
2500
2501 err = airoha_qdma_set_rl_token_bucket(qdma, i, rate,
2502 bucket_size);
2503 if (err)
2504 return err;
2505 }
2506
2507 return 0;
2508 }
2509
airoha_tc_matchall_act_validate(struct tc_cls_matchall_offload * f)2510 static int airoha_tc_matchall_act_validate(struct tc_cls_matchall_offload *f)
2511 {
2512 const struct flow_action *actions = &f->rule->action;
2513 const struct flow_action_entry *act;
2514
2515 if (!flow_action_has_entries(actions)) {
2516 NL_SET_ERR_MSG_MOD(f->common.extack,
2517 "filter run with no actions");
2518 return -EINVAL;
2519 }
2520
2521 if (!flow_offload_has_one_action(actions)) {
2522 NL_SET_ERR_MSG_MOD(f->common.extack,
2523 "only once action per filter is supported");
2524 return -EOPNOTSUPP;
2525 }
2526
2527 act = &actions->entries[0];
2528 if (act->id != FLOW_ACTION_POLICE) {
2529 NL_SET_ERR_MSG_MOD(f->common.extack, "unsupported action");
2530 return -EOPNOTSUPP;
2531 }
2532
2533 if (act->police.exceed.act_id != FLOW_ACTION_DROP) {
2534 NL_SET_ERR_MSG_MOD(f->common.extack,
2535 "invalid exceed action id");
2536 return -EOPNOTSUPP;
2537 }
2538
2539 if (act->police.notexceed.act_id != FLOW_ACTION_ACCEPT) {
2540 NL_SET_ERR_MSG_MOD(f->common.extack,
2541 "invalid notexceed action id");
2542 return -EOPNOTSUPP;
2543 }
2544
2545 if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT &&
2546 !flow_action_is_last_entry(actions, act)) {
2547 NL_SET_ERR_MSG_MOD(f->common.extack,
2548 "action accept must be last");
2549 return -EOPNOTSUPP;
2550 }
2551
2552 if (act->police.peakrate_bytes_ps || act->police.avrate ||
2553 act->police.overhead || act->police.mtu) {
2554 NL_SET_ERR_MSG_MOD(f->common.extack,
2555 "peakrate/avrate/overhead/mtu unsupported");
2556 return -EOPNOTSUPP;
2557 }
2558
2559 return 0;
2560 }
2561
airoha_dev_tc_matchall(struct net_device * dev,struct tc_cls_matchall_offload * f)2562 static int airoha_dev_tc_matchall(struct net_device *dev,
2563 struct tc_cls_matchall_offload *f)
2564 {
2565 enum trtcm_unit_type unit_type = TRTCM_BYTE_UNIT;
2566 struct airoha_gdm_port *port = netdev_priv(dev);
2567 u32 rate = 0, bucket_size = 0;
2568
2569 switch (f->command) {
2570 case TC_CLSMATCHALL_REPLACE: {
2571 const struct flow_action_entry *act;
2572 int err;
2573
2574 err = airoha_tc_matchall_act_validate(f);
2575 if (err)
2576 return err;
2577
2578 act = &f->rule->action.entries[0];
2579 if (act->police.rate_pkt_ps) {
2580 rate = act->police.rate_pkt_ps;
2581 bucket_size = act->police.burst_pkt;
2582 unit_type = TRTCM_PACKET_UNIT;
2583 } else {
2584 rate = div_u64(act->police.rate_bytes_ps, 1000);
2585 rate = rate << 3; /* Kbps */
2586 bucket_size = act->police.burst;
2587 }
2588 fallthrough;
2589 }
2590 case TC_CLSMATCHALL_DESTROY:
2591 return airoha_qdma_set_rx_meter(port, rate, bucket_size,
2592 unit_type);
2593 default:
2594 return -EOPNOTSUPP;
2595 }
2596 }
2597
airoha_dev_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)2598 static int airoha_dev_setup_tc_block_cb(enum tc_setup_type type,
2599 void *type_data, void *cb_priv)
2600 {
2601 struct net_device *dev = cb_priv;
2602
2603 if (!tc_can_offload(dev))
2604 return -EOPNOTSUPP;
2605
2606 switch (type) {
2607 case TC_SETUP_CLSFLOWER:
2608 return airoha_ppe_setup_tc_block_cb(dev, type_data);
2609 case TC_SETUP_CLSMATCHALL:
2610 return airoha_dev_tc_matchall(dev, type_data);
2611 default:
2612 return -EOPNOTSUPP;
2613 }
2614 }
2615
airoha_dev_setup_tc_block(struct airoha_gdm_port * port,struct flow_block_offload * f)2616 static int airoha_dev_setup_tc_block(struct airoha_gdm_port *port,
2617 struct flow_block_offload *f)
2618 {
2619 flow_setup_cb_t *cb = airoha_dev_setup_tc_block_cb;
2620 static LIST_HEAD(block_cb_list);
2621 struct flow_block_cb *block_cb;
2622
2623 if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
2624 return -EOPNOTSUPP;
2625
2626 f->driver_block_list = &block_cb_list;
2627 switch (f->command) {
2628 case FLOW_BLOCK_BIND:
2629 block_cb = flow_block_cb_lookup(f->block, cb, port->dev);
2630 if (block_cb) {
2631 flow_block_cb_incref(block_cb);
2632 return 0;
2633 }
2634 block_cb = flow_block_cb_alloc(cb, port->dev, port->dev, NULL);
2635 if (IS_ERR(block_cb))
2636 return PTR_ERR(block_cb);
2637
2638 flow_block_cb_incref(block_cb);
2639 flow_block_cb_add(block_cb, f);
2640 list_add_tail(&block_cb->driver_list, &block_cb_list);
2641 return 0;
2642 case FLOW_BLOCK_UNBIND:
2643 block_cb = flow_block_cb_lookup(f->block, cb, port->dev);
2644 if (!block_cb)
2645 return -ENOENT;
2646
2647 if (!flow_block_cb_decref(block_cb)) {
2648 flow_block_cb_remove(block_cb, f);
2649 list_del(&block_cb->driver_list);
2650 }
2651 return 0;
2652 default:
2653 return -EOPNOTSUPP;
2654 }
2655 }
2656
airoha_tc_remove_htb_queue(struct airoha_gdm_port * port,int queue)2657 static void airoha_tc_remove_htb_queue(struct airoha_gdm_port *port, int queue)
2658 {
2659 struct net_device *dev = port->dev;
2660
2661 netif_set_real_num_tx_queues(dev, dev->real_num_tx_queues - 1);
2662 airoha_qdma_set_tx_rate_limit(port, queue + 1, 0, 0);
2663 clear_bit(queue, port->qos_sq_bmap);
2664 }
2665
airoha_tc_htb_delete_leaf_queue(struct airoha_gdm_port * port,struct tc_htb_qopt_offload * opt)2666 static int airoha_tc_htb_delete_leaf_queue(struct airoha_gdm_port *port,
2667 struct tc_htb_qopt_offload *opt)
2668 {
2669 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS;
2670
2671 if (!test_bit(channel, port->qos_sq_bmap)) {
2672 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id");
2673 return -EINVAL;
2674 }
2675
2676 airoha_tc_remove_htb_queue(port, channel);
2677
2678 return 0;
2679 }
2680
airoha_tc_htb_destroy(struct airoha_gdm_port * port)2681 static int airoha_tc_htb_destroy(struct airoha_gdm_port *port)
2682 {
2683 int q;
2684
2685 for_each_set_bit(q, port->qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS)
2686 airoha_tc_remove_htb_queue(port, q);
2687
2688 return 0;
2689 }
2690
airoha_tc_get_htb_get_leaf_queue(struct airoha_gdm_port * port,struct tc_htb_qopt_offload * opt)2691 static int airoha_tc_get_htb_get_leaf_queue(struct airoha_gdm_port *port,
2692 struct tc_htb_qopt_offload *opt)
2693 {
2694 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS;
2695
2696 if (!test_bit(channel, port->qos_sq_bmap)) {
2697 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id");
2698 return -EINVAL;
2699 }
2700
2701 opt->qid = AIROHA_NUM_TX_RING + channel;
2702
2703 return 0;
2704 }
2705
airoha_tc_setup_qdisc_htb(struct airoha_gdm_port * port,struct tc_htb_qopt_offload * opt)2706 static int airoha_tc_setup_qdisc_htb(struct airoha_gdm_port *port,
2707 struct tc_htb_qopt_offload *opt)
2708 {
2709 switch (opt->command) {
2710 case TC_HTB_CREATE:
2711 break;
2712 case TC_HTB_DESTROY:
2713 return airoha_tc_htb_destroy(port);
2714 case TC_HTB_NODE_MODIFY:
2715 case TC_HTB_LEAF_ALLOC_QUEUE:
2716 return airoha_tc_htb_alloc_leaf_queue(port, opt);
2717 case TC_HTB_LEAF_DEL:
2718 case TC_HTB_LEAF_DEL_LAST:
2719 case TC_HTB_LEAF_DEL_LAST_FORCE:
2720 return airoha_tc_htb_delete_leaf_queue(port, opt);
2721 case TC_HTB_LEAF_QUERY_QUEUE:
2722 return airoha_tc_get_htb_get_leaf_queue(port, opt);
2723 default:
2724 return -EOPNOTSUPP;
2725 }
2726
2727 return 0;
2728 }
2729
airoha_dev_tc_setup(struct net_device * dev,enum tc_setup_type type,void * type_data)2730 static int airoha_dev_tc_setup(struct net_device *dev, enum tc_setup_type type,
2731 void *type_data)
2732 {
2733 struct airoha_gdm_port *port = netdev_priv(dev);
2734
2735 switch (type) {
2736 case TC_SETUP_QDISC_ETS:
2737 return airoha_tc_setup_qdisc_ets(port, type_data);
2738 case TC_SETUP_QDISC_HTB:
2739 return airoha_tc_setup_qdisc_htb(port, type_data);
2740 case TC_SETUP_BLOCK:
2741 case TC_SETUP_FT:
2742 return airoha_dev_setup_tc_block(port, type_data);
2743 default:
2744 return -EOPNOTSUPP;
2745 }
2746 }
2747
2748 static const struct net_device_ops airoha_netdev_ops = {
2749 .ndo_init = airoha_dev_init,
2750 .ndo_open = airoha_dev_open,
2751 .ndo_stop = airoha_dev_stop,
2752 .ndo_change_mtu = airoha_dev_change_mtu,
2753 .ndo_select_queue = airoha_dev_select_queue,
2754 .ndo_start_xmit = airoha_dev_xmit,
2755 .ndo_get_stats64 = airoha_dev_get_stats64,
2756 .ndo_set_mac_address = airoha_dev_set_macaddr,
2757 .ndo_setup_tc = airoha_dev_tc_setup,
2758 };
2759
2760 static const struct ethtool_ops airoha_ethtool_ops = {
2761 .get_drvinfo = airoha_ethtool_get_drvinfo,
2762 .get_eth_mac_stats = airoha_ethtool_get_mac_stats,
2763 .get_rmon_stats = airoha_ethtool_get_rmon_stats,
2764 };
2765
airoha_metadata_dst_alloc(struct airoha_gdm_port * port)2766 static int airoha_metadata_dst_alloc(struct airoha_gdm_port *port)
2767 {
2768 int i;
2769
2770 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) {
2771 struct metadata_dst *md_dst;
2772
2773 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX,
2774 GFP_KERNEL);
2775 if (!md_dst)
2776 return -ENOMEM;
2777
2778 md_dst->u.port_info.port_id = i;
2779 port->dsa_meta[i] = md_dst;
2780 }
2781
2782 return 0;
2783 }
2784
airoha_metadata_dst_free(struct airoha_gdm_port * port)2785 static void airoha_metadata_dst_free(struct airoha_gdm_port *port)
2786 {
2787 int i;
2788
2789 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) {
2790 if (!port->dsa_meta[i])
2791 continue;
2792
2793 metadata_dst_free(port->dsa_meta[i]);
2794 }
2795 }
2796
airoha_is_valid_gdm_port(struct airoha_eth * eth,struct airoha_gdm_port * port)2797 bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
2798 struct airoha_gdm_port *port)
2799 {
2800 int i;
2801
2802 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
2803 if (eth->ports[i] == port)
2804 return true;
2805 }
2806
2807 return false;
2808 }
2809
airoha_alloc_gdm_port(struct airoha_eth * eth,struct device_node * np,int index)2810 static int airoha_alloc_gdm_port(struct airoha_eth *eth,
2811 struct device_node *np, int index)
2812 {
2813 const __be32 *id_ptr = of_get_property(np, "reg", NULL);
2814 struct airoha_gdm_port *port;
2815 struct airoha_qdma *qdma;
2816 struct net_device *dev;
2817 int err, p;
2818 u32 id;
2819
2820 if (!id_ptr) {
2821 dev_err(eth->dev, "missing gdm port id\n");
2822 return -EINVAL;
2823 }
2824
2825 id = be32_to_cpup(id_ptr);
2826 p = id - 1;
2827
2828 if (!id || id > ARRAY_SIZE(eth->ports)) {
2829 dev_err(eth->dev, "invalid gdm port id: %d\n", id);
2830 return -EINVAL;
2831 }
2832
2833 if (eth->ports[p]) {
2834 dev_err(eth->dev, "duplicate gdm port id: %d\n", id);
2835 return -EINVAL;
2836 }
2837
2838 dev = devm_alloc_etherdev_mqs(eth->dev, sizeof(*port),
2839 AIROHA_NUM_NETDEV_TX_RINGS,
2840 AIROHA_NUM_RX_RING);
2841 if (!dev) {
2842 dev_err(eth->dev, "alloc_etherdev failed\n");
2843 return -ENOMEM;
2844 }
2845
2846 qdma = ð->qdma[index % AIROHA_MAX_NUM_QDMA];
2847 dev->netdev_ops = &airoha_netdev_ops;
2848 dev->ethtool_ops = &airoha_ethtool_ops;
2849 dev->max_mtu = AIROHA_MAX_MTU;
2850 dev->watchdog_timeo = 5 * HZ;
2851 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
2852 NETIF_F_TSO6 | NETIF_F_IPV6_CSUM |
2853 NETIF_F_SG | NETIF_F_TSO |
2854 NETIF_F_HW_TC;
2855 dev->features |= dev->hw_features;
2856 dev->vlan_features = dev->hw_features;
2857 dev->dev.of_node = np;
2858 dev->irq = qdma->irq_banks[0].irq;
2859 SET_NETDEV_DEV(dev, eth->dev);
2860
2861 /* reserve hw queues for HTB offloading */
2862 err = netif_set_real_num_tx_queues(dev, AIROHA_NUM_TX_RING);
2863 if (err)
2864 return err;
2865
2866 err = of_get_ethdev_address(np, dev);
2867 if (err) {
2868 if (err == -EPROBE_DEFER)
2869 return err;
2870
2871 eth_hw_addr_random(dev);
2872 dev_info(eth->dev, "generated random MAC address %pM\n",
2873 dev->dev_addr);
2874 }
2875
2876 port = netdev_priv(dev);
2877 u64_stats_init(&port->stats.syncp);
2878 spin_lock_init(&port->stats.lock);
2879 port->qdma = qdma;
2880 port->dev = dev;
2881 port->id = id;
2882 eth->ports[p] = port;
2883
2884 err = airoha_metadata_dst_alloc(port);
2885 if (err)
2886 return err;
2887
2888 err = register_netdev(dev);
2889 if (err)
2890 goto free_metadata_dst;
2891
2892 return 0;
2893
2894 free_metadata_dst:
2895 airoha_metadata_dst_free(port);
2896 return err;
2897 }
2898
airoha_probe(struct platform_device * pdev)2899 static int airoha_probe(struct platform_device *pdev)
2900 {
2901 struct device_node *np;
2902 struct airoha_eth *eth;
2903 int i, err;
2904
2905 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2906 if (!eth)
2907 return -ENOMEM;
2908
2909 eth->dev = &pdev->dev;
2910
2911 err = dma_set_mask_and_coherent(eth->dev, DMA_BIT_MASK(32));
2912 if (err) {
2913 dev_err(eth->dev, "failed configuring DMA mask\n");
2914 return err;
2915 }
2916
2917 eth->fe_regs = devm_platform_ioremap_resource_byname(pdev, "fe");
2918 if (IS_ERR(eth->fe_regs))
2919 return dev_err_probe(eth->dev, PTR_ERR(eth->fe_regs),
2920 "failed to iomap fe regs\n");
2921
2922 eth->rsts[0].id = "fe";
2923 eth->rsts[1].id = "pdma";
2924 eth->rsts[2].id = "qdma";
2925 err = devm_reset_control_bulk_get_exclusive(eth->dev,
2926 ARRAY_SIZE(eth->rsts),
2927 eth->rsts);
2928 if (err) {
2929 dev_err(eth->dev, "failed to get bulk reset lines\n");
2930 return err;
2931 }
2932
2933 eth->xsi_rsts[0].id = "xsi-mac";
2934 eth->xsi_rsts[1].id = "hsi0-mac";
2935 eth->xsi_rsts[2].id = "hsi1-mac";
2936 eth->xsi_rsts[3].id = "hsi-mac";
2937 eth->xsi_rsts[4].id = "xfp-mac";
2938 err = devm_reset_control_bulk_get_exclusive(eth->dev,
2939 ARRAY_SIZE(eth->xsi_rsts),
2940 eth->xsi_rsts);
2941 if (err) {
2942 dev_err(eth->dev, "failed to get bulk xsi reset lines\n");
2943 return err;
2944 }
2945
2946 eth->napi_dev = alloc_netdev_dummy(0);
2947 if (!eth->napi_dev)
2948 return -ENOMEM;
2949
2950 /* Enable threaded NAPI by default */
2951 eth->napi_dev->threaded = true;
2952 strscpy(eth->napi_dev->name, "qdma_eth", sizeof(eth->napi_dev->name));
2953 platform_set_drvdata(pdev, eth);
2954
2955 err = airoha_hw_init(pdev, eth);
2956 if (err)
2957 goto error_hw_cleanup;
2958
2959 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
2960 airoha_qdma_start_napi(ð->qdma[i]);
2961
2962 i = 0;
2963 for_each_child_of_node(pdev->dev.of_node, np) {
2964 if (!of_device_is_compatible(np, "airoha,eth-mac"))
2965 continue;
2966
2967 if (!of_device_is_available(np))
2968 continue;
2969
2970 err = airoha_alloc_gdm_port(eth, np, i++);
2971 if (err) {
2972 of_node_put(np);
2973 goto error_napi_stop;
2974 }
2975 }
2976
2977 return 0;
2978
2979 error_napi_stop:
2980 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
2981 airoha_qdma_stop_napi(ð->qdma[i]);
2982 airoha_ppe_deinit(eth);
2983 error_hw_cleanup:
2984 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
2985 airoha_hw_cleanup(ð->qdma[i]);
2986
2987 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
2988 struct airoha_gdm_port *port = eth->ports[i];
2989
2990 if (port && port->dev->reg_state == NETREG_REGISTERED) {
2991 unregister_netdev(port->dev);
2992 airoha_metadata_dst_free(port);
2993 }
2994 }
2995 free_netdev(eth->napi_dev);
2996 platform_set_drvdata(pdev, NULL);
2997
2998 return err;
2999 }
3000
airoha_remove(struct platform_device * pdev)3001 static void airoha_remove(struct platform_device *pdev)
3002 {
3003 struct airoha_eth *eth = platform_get_drvdata(pdev);
3004 int i;
3005
3006 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) {
3007 airoha_qdma_stop_napi(ð->qdma[i]);
3008 airoha_hw_cleanup(ð->qdma[i]);
3009 }
3010
3011 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
3012 struct airoha_gdm_port *port = eth->ports[i];
3013
3014 if (!port)
3015 continue;
3016
3017 airoha_dev_stop(port->dev);
3018 unregister_netdev(port->dev);
3019 airoha_metadata_dst_free(port);
3020 }
3021 free_netdev(eth->napi_dev);
3022
3023 airoha_ppe_deinit(eth);
3024 platform_set_drvdata(pdev, NULL);
3025 }
3026
3027 static const struct of_device_id of_airoha_match[] = {
3028 { .compatible = "airoha,en7581-eth" },
3029 { /* sentinel */ }
3030 };
3031 MODULE_DEVICE_TABLE(of, of_airoha_match);
3032
3033 static struct platform_driver airoha_driver = {
3034 .probe = airoha_probe,
3035 .remove = airoha_remove,
3036 .driver = {
3037 .name = KBUILD_MODNAME,
3038 .of_match_table = of_airoha_match,
3039 },
3040 };
3041 module_platform_driver(airoha_driver);
3042
3043 MODULE_LICENSE("GPL");
3044 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
3045 MODULE_DESCRIPTION("Ethernet driver for Airoha SoC");
3046