1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD7606 SPI ADC driver
4 *
5 * Copyright 2011 Analog Devices Inc.
6 */
7
8 #include <linux/cleanup.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/mutex.h>
17 #include <linux/property.h>
18 #include <linux/pwm.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/sched.h>
21 #include <linux/slab.h>
22 #include <linux/sysfs.h>
23 #include <linux/units.h>
24 #include <linux/util_macros.h>
25
26 #include <linux/iio/backend.h>
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/iio.h>
29 #include <linux/iio/sysfs.h>
30 #include <linux/iio/trigger.h>
31 #include <linux/iio/triggered_buffer.h>
32 #include <linux/iio/trigger_consumer.h>
33
34 #include "ad7606.h"
35
36 #define AD7606_CALIB_GAIN_MIN 0
37 #define AD7606_CALIB_GAIN_STEP 1024
38 #define AD7606_CALIB_GAIN_MAX (63 * AD7606_CALIB_GAIN_STEP)
39
40 /*
41 * Scales are computed as 5000/32768 and 10000/32768 respectively,
42 * so that when applied to the raw values they provide mV values.
43 * The scale arrays are kept as IIO_VAL_INT_PLUS_MICRO, so index
44 * X is the integer part and X + 1 is the fractional part.
45 */
46 static const unsigned int ad7606_16bit_hw_scale_avail[2][2] = {
47 { 0, 152588 }, { 0, 305176 }
48 };
49
50 static const unsigned int ad7606_18bit_hw_scale_avail[2][2] = {
51 { 0, 38147 }, { 0, 76294 }
52 };
53
54 static const unsigned int ad7606c_16bit_single_ended_unipolar_scale_avail[3][2] = {
55 { 0, 76294 }, { 0, 152588 }, { 0, 190735 }
56 };
57
58 static const unsigned int ad7606c_16bit_single_ended_bipolar_scale_avail[5][2] = {
59 { 0, 76294 }, { 0, 152588 }, { 0, 190735 }, { 0, 305176 }, { 0, 381470 }
60 };
61
62 static const unsigned int ad7606c_16bit_differential_bipolar_scale_avail[4][2] = {
63 { 0, 152588 }, { 0, 305176 }, { 0, 381470 }, { 0, 610352 }
64 };
65
66 static const unsigned int ad7606c_18bit_single_ended_unipolar_scale_avail[3][2] = {
67 { 0, 19073 }, { 0, 38147 }, { 0, 47684 }
68 };
69
70 static const unsigned int ad7606c_18bit_single_ended_bipolar_scale_avail[5][2] = {
71 { 0, 19073 }, { 0, 38147 }, { 0, 47684 }, { 0, 76294 }, { 0, 95367 }
72 };
73
74 static const unsigned int ad7606c_18bit_differential_bipolar_scale_avail[4][2] = {
75 { 0, 38147 }, { 0, 76294 }, { 0, 95367 }, { 0, 152588 }
76 };
77
78 static const unsigned int ad7606_16bit_sw_scale_avail[3][2] = {
79 { 0, 76293 }, { 0, 152588 }, { 0, 305176 }
80 };
81
82 static const unsigned int ad7607_hw_scale_avail[2][2] = {
83 { 0, 610352 }, { 1, 220703 }
84 };
85
86 static const unsigned int ad7609_hw_scale_avail[2][2] = {
87 { 0, 152588 }, { 0, 305176 }
88 };
89
90 static const unsigned int ad7606_oversampling_avail[7] = {
91 1, 2, 4, 8, 16, 32, 64,
92 };
93
94 static const unsigned int ad7606b_oversampling_avail[9] = {
95 1, 2, 4, 8, 16, 32, 64, 128, 256,
96 };
97
98 static const unsigned int ad7616_oversampling_avail[8] = {
99 1, 2, 4, 8, 16, 32, 64, 128,
100 };
101
102 static const int ad7606_calib_offset_avail[3] = {
103 -128, 1, 127,
104 };
105
106 static const int ad7606c_18bit_calib_offset_avail[3] = {
107 -512, 4, 508,
108 };
109
110 static const int ad7606b_calib_phase_avail[][2] = {
111 { 0, 0 }, { 0, 1250 }, { 0, 318750 },
112 };
113
114 static const int ad7606c_calib_phase_avail[][2] = {
115 { 0, 0 }, { 0, 1000 }, { 0, 255000 },
116 };
117
118 static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev,
119 struct iio_chan_spec *chan);
120 static int ad7606c_16bit_chan_scale_setup(struct iio_dev *indio_dev,
121 struct iio_chan_spec *chan);
122 static int ad7606_16bit_chan_scale_setup(struct iio_dev *indio_dev,
123 struct iio_chan_spec *chan);
124 static int ad7607_chan_scale_setup(struct iio_dev *indio_dev,
125 struct iio_chan_spec *chan);
126 static int ad7608_chan_scale_setup(struct iio_dev *indio_dev,
127 struct iio_chan_spec *chan);
128 static int ad7609_chan_scale_setup(struct iio_dev *indio_dev,
129 struct iio_chan_spec *chan);
130 static int ad7616_sw_mode_setup(struct iio_dev *indio_dev);
131 static int ad7606b_sw_mode_setup(struct iio_dev *indio_dev);
132
133 const struct ad7606_chip_info ad7605_4_info = {
134 .max_samplerate = 300 * KILO,
135 .name = "ad7605-4",
136 .bits = 16,
137 .num_adc_channels = 4,
138 .scale_setup_cb = ad7606_16bit_chan_scale_setup,
139 };
140 EXPORT_SYMBOL_NS_GPL(ad7605_4_info, "IIO_AD7606");
141
142 const struct ad7606_chip_info ad7606_8_info = {
143 .max_samplerate = 200 * KILO,
144 .name = "ad7606-8",
145 .bits = 16,
146 .num_adc_channels = 8,
147 .oversampling_avail = ad7606_oversampling_avail,
148 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
149 .scale_setup_cb = ad7606_16bit_chan_scale_setup,
150 };
151 EXPORT_SYMBOL_NS_GPL(ad7606_8_info, "IIO_AD7606");
152
153 const struct ad7606_chip_info ad7606_6_info = {
154 .max_samplerate = 200 * KILO,
155 .name = "ad7606-6",
156 .bits = 16,
157 .num_adc_channels = 6,
158 .oversampling_avail = ad7606_oversampling_avail,
159 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
160 .scale_setup_cb = ad7606_16bit_chan_scale_setup,
161 .offload_storagebits = 32,
162 };
163 EXPORT_SYMBOL_NS_GPL(ad7606_6_info, "IIO_AD7606");
164
165 const struct ad7606_chip_info ad7606_4_info = {
166 .max_samplerate = 200 * KILO,
167 .name = "ad7606-4",
168 .bits = 16,
169 .num_adc_channels = 4,
170 .oversampling_avail = ad7606_oversampling_avail,
171 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
172 .scale_setup_cb = ad7606_16bit_chan_scale_setup,
173 .offload_storagebits = 32,
174 };
175 EXPORT_SYMBOL_NS_GPL(ad7606_4_info, "IIO_AD7606");
176
177 const struct ad7606_chip_info ad7606b_info = {
178 .max_samplerate = 800 * KILO,
179 .name = "ad7606b",
180 .bits = 16,
181 .num_adc_channels = 8,
182 .oversampling_avail = ad7606_oversampling_avail,
183 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
184 .scale_setup_cb = ad7606_16bit_chan_scale_setup,
185 .sw_setup_cb = ad7606b_sw_mode_setup,
186 .offload_storagebits = 32,
187 .calib_gain_avail = true,
188 .calib_offset_avail = ad7606_calib_offset_avail,
189 .calib_phase_avail = ad7606b_calib_phase_avail,
190 };
191 EXPORT_SYMBOL_NS_GPL(ad7606b_info, "IIO_AD7606");
192
193 const struct ad7606_chip_info ad7606c_16_info = {
194 .max_samplerate = 1 * MEGA,
195 .name = "ad7606c16",
196 .bits = 16,
197 .num_adc_channels = 8,
198 .oversampling_avail = ad7606_oversampling_avail,
199 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
200 .scale_setup_cb = ad7606c_16bit_chan_scale_setup,
201 .sw_setup_cb = ad7606b_sw_mode_setup,
202 .offload_storagebits = 32,
203 .calib_gain_avail = true,
204 .calib_offset_avail = ad7606_calib_offset_avail,
205 .calib_phase_avail = ad7606c_calib_phase_avail,
206 };
207 EXPORT_SYMBOL_NS_GPL(ad7606c_16_info, "IIO_AD7606");
208
209 const struct ad7606_chip_info ad7607_info = {
210 .max_samplerate = 200 * KILO,
211 .name = "ad7607",
212 .bits = 14,
213 .num_adc_channels = 8,
214 .oversampling_avail = ad7606_oversampling_avail,
215 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
216 .scale_setup_cb = ad7607_chan_scale_setup,
217 .offload_storagebits = 32,
218 };
219 EXPORT_SYMBOL_NS_GPL(ad7607_info, "IIO_AD7606");
220
221 const struct ad7606_chip_info ad7608_info = {
222 .max_samplerate = 200 * KILO,
223 .name = "ad7608",
224 .bits = 18,
225 .num_adc_channels = 8,
226 .oversampling_avail = ad7606_oversampling_avail,
227 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
228 .scale_setup_cb = ad7608_chan_scale_setup,
229 .offload_storagebits = 32,
230 };
231 EXPORT_SYMBOL_NS_GPL(ad7608_info, "IIO_AD7606");
232
233 const struct ad7606_chip_info ad7609_info = {
234 .max_samplerate = 200 * KILO,
235 .name = "ad7609",
236 .bits = 18,
237 .num_adc_channels = 8,
238 .oversampling_avail = ad7606_oversampling_avail,
239 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
240 .scale_setup_cb = ad7609_chan_scale_setup,
241 .offload_storagebits = 32,
242 };
243 EXPORT_SYMBOL_NS_GPL(ad7609_info, "IIO_AD7606");
244
245 const struct ad7606_chip_info ad7606c_18_info = {
246 .max_samplerate = 1 * MEGA,
247 .name = "ad7606c18",
248 .bits = 18,
249 .num_adc_channels = 8,
250 .oversampling_avail = ad7606_oversampling_avail,
251 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
252 .scale_setup_cb = ad7606c_18bit_chan_scale_setup,
253 .sw_setup_cb = ad7606b_sw_mode_setup,
254 .offload_storagebits = 32,
255 .calib_gain_avail = true,
256 .calib_offset_avail = ad7606c_18bit_calib_offset_avail,
257 .calib_phase_avail = ad7606c_calib_phase_avail,
258 };
259 EXPORT_SYMBOL_NS_GPL(ad7606c_18_info, "IIO_AD7606");
260
261 const struct ad7606_chip_info ad7616_info = {
262 .max_samplerate = 1 * MEGA,
263 .init_delay_ms = 15,
264 .name = "ad7616",
265 .bits = 16,
266 .num_adc_channels = 16,
267 .oversampling_avail = ad7616_oversampling_avail,
268 .oversampling_num = ARRAY_SIZE(ad7616_oversampling_avail),
269 .os_req_reset = true,
270 .scale_setup_cb = ad7606_16bit_chan_scale_setup,
271 .sw_setup_cb = ad7616_sw_mode_setup,
272 .offload_storagebits = 16,
273 };
274 EXPORT_SYMBOL_NS_GPL(ad7616_info, "IIO_AD7606");
275
ad7606_reset(struct ad7606_state * st)276 int ad7606_reset(struct ad7606_state *st)
277 {
278 if (st->gpio_reset) {
279 gpiod_set_value(st->gpio_reset, 1);
280 ndelay(100); /* t_reset >= 100ns */
281 gpiod_set_value(st->gpio_reset, 0);
282 return 0;
283 }
284
285 return -ENODEV;
286 }
287 EXPORT_SYMBOL_NS_GPL(ad7606_reset, "IIO_AD7606");
288
ad7606_16bit_chan_scale_setup(struct iio_dev * indio_dev,struct iio_chan_spec * chan)289 static int ad7606_16bit_chan_scale_setup(struct iio_dev *indio_dev,
290 struct iio_chan_spec *chan)
291 {
292 struct ad7606_state *st = iio_priv(indio_dev);
293 struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index];
294
295 if (!st->sw_mode_en) {
296 /* tied to logic low, analog input range is +/- 5V */
297 ci->range = 0;
298 ci->scale_avail = ad7606_16bit_hw_scale_avail;
299 ci->num_scales = ARRAY_SIZE(ad7606_16bit_hw_scale_avail);
300 return 0;
301 }
302
303 /* Scale of 0.076293 is only available in sw mode */
304 /* After reset, in software mode, ±10 V is set by default */
305 ci->range = 2;
306 ci->scale_avail = ad7606_16bit_sw_scale_avail;
307 ci->num_scales = ARRAY_SIZE(ad7606_16bit_sw_scale_avail);
308
309 return 0;
310 }
311
ad7606_get_chan_config(struct iio_dev * indio_dev,int ch,bool * bipolar,bool * differential)312 static int ad7606_get_chan_config(struct iio_dev *indio_dev, int ch,
313 bool *bipolar, bool *differential)
314 {
315 struct ad7606_state *st = iio_priv(indio_dev);
316 struct ad7606_chan_info *ci;
317 unsigned int num_channels = st->chip_info->num_adc_channels;
318 struct device *dev = st->dev;
319 int ret;
320
321 *bipolar = false;
322 *differential = false;
323
324 device_for_each_child_node_scoped(dev, child) {
325 u32 pins[2];
326 int reg;
327
328 ret = fwnode_property_read_u32(child, "reg", ®);
329 if (ret)
330 return ret;
331
332 /* channel number (here) is from 1 to num_channels */
333 if (reg < 1 || reg > num_channels)
334 return -EINVAL;
335
336 /* Loop until we are in the right channel. */
337 if (reg != (ch + 1))
338 continue;
339
340 *bipolar = fwnode_property_read_bool(child, "bipolar");
341
342 ret = fwnode_property_read_u32_array(child, "diff-channels",
343 pins, ARRAY_SIZE(pins));
344 /* Channel is differential, if pins are the same as 'reg' */
345 if (ret == 0 && (pins[0] != reg || pins[1] != reg)) {
346 dev_err(dev,
347 "Differential pins must be the same as 'reg'");
348 return -EINVAL;
349 }
350
351 *differential = (ret == 0);
352
353 if (*differential && !*bipolar) {
354 dev_err(dev,
355 "'bipolar' must be added for diff channel %d\n",
356 reg);
357 return -EINVAL;
358 }
359
360 ci = &st->chan_info[reg - 1];
361
362 ci->r_gain = 0;
363 ret = fwnode_property_read_u32(child, "adi,rfilter-ohms",
364 &ci->r_gain);
365 if (ret == 0 && ci->r_gain > AD7606_CALIB_GAIN_MAX)
366 return -EINVAL;
367
368 return 0;
369 }
370
371 return 0;
372 }
373
ad7606c_18bit_chan_scale_setup(struct iio_dev * indio_dev,struct iio_chan_spec * chan)374 static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev,
375 struct iio_chan_spec *chan)
376 {
377 struct ad7606_state *st = iio_priv(indio_dev);
378 struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index];
379 bool bipolar, differential;
380 int ret;
381
382 if (!st->sw_mode_en) {
383 ci->range = 0;
384 ci->scale_avail = ad7606_18bit_hw_scale_avail;
385 ci->num_scales = ARRAY_SIZE(ad7606_18bit_hw_scale_avail);
386 return 0;
387 }
388
389 ret = ad7606_get_chan_config(indio_dev, chan->scan_index, &bipolar,
390 &differential);
391 if (ret)
392 return ret;
393
394 if (differential) {
395 ci->scale_avail = ad7606c_18bit_differential_bipolar_scale_avail;
396 ci->num_scales =
397 ARRAY_SIZE(ad7606c_18bit_differential_bipolar_scale_avail);
398 /* Bipolar differential ranges start at 8 (b1000) */
399 ci->reg_offset = 8;
400 ci->range = 1;
401 chan->differential = 1;
402 chan->channel2 = chan->channel;
403
404 return 0;
405 }
406
407 chan->differential = 0;
408
409 if (bipolar) {
410 ci->scale_avail = ad7606c_18bit_single_ended_bipolar_scale_avail;
411 ci->num_scales =
412 ARRAY_SIZE(ad7606c_18bit_single_ended_bipolar_scale_avail);
413 /* Bipolar single-ended ranges start at 0 (b0000) */
414 ci->reg_offset = 0;
415 ci->range = 3;
416 chan->scan_type.sign = 's';
417
418 return 0;
419 }
420
421 ci->scale_avail = ad7606c_18bit_single_ended_unipolar_scale_avail;
422 ci->num_scales =
423 ARRAY_SIZE(ad7606c_18bit_single_ended_unipolar_scale_avail);
424 /* Unipolar single-ended ranges start at 5 (b0101) */
425 ci->reg_offset = 5;
426 ci->range = 1;
427 chan->scan_type.sign = 'u';
428
429 return 0;
430 }
431
ad7606c_16bit_chan_scale_setup(struct iio_dev * indio_dev,struct iio_chan_spec * chan)432 static int ad7606c_16bit_chan_scale_setup(struct iio_dev *indio_dev,
433 struct iio_chan_spec *chan)
434 {
435 struct ad7606_state *st = iio_priv(indio_dev);
436 struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index];
437 bool bipolar, differential;
438 int ret;
439
440 if (!st->sw_mode_en) {
441 ci->range = 0;
442 ci->scale_avail = ad7606_16bit_hw_scale_avail;
443 ci->num_scales = ARRAY_SIZE(ad7606_16bit_hw_scale_avail);
444 return 0;
445 }
446
447 ret = ad7606_get_chan_config(indio_dev, chan->scan_index, &bipolar,
448 &differential);
449 if (ret)
450 return ret;
451
452 if (differential) {
453 ci->scale_avail = ad7606c_16bit_differential_bipolar_scale_avail;
454 ci->num_scales =
455 ARRAY_SIZE(ad7606c_16bit_differential_bipolar_scale_avail);
456 /* Bipolar differential ranges start at 8 (b1000) */
457 ci->reg_offset = 8;
458 ci->range = 1;
459 chan->differential = 1;
460 chan->channel2 = chan->channel;
461 chan->scan_type.sign = 's';
462
463 return 0;
464 }
465
466 chan->differential = 0;
467
468 if (bipolar) {
469 ci->scale_avail = ad7606c_16bit_single_ended_bipolar_scale_avail;
470 ci->num_scales =
471 ARRAY_SIZE(ad7606c_16bit_single_ended_bipolar_scale_avail);
472 /* Bipolar single-ended ranges start at 0 (b0000) */
473 ci->reg_offset = 0;
474 ci->range = 3;
475 chan->scan_type.sign = 's';
476
477 return 0;
478 }
479
480 ci->scale_avail = ad7606c_16bit_single_ended_unipolar_scale_avail;
481 ci->num_scales =
482 ARRAY_SIZE(ad7606c_16bit_single_ended_unipolar_scale_avail);
483 /* Unipolar single-ended ranges start at 5 (b0101) */
484 ci->reg_offset = 5;
485 ci->range = 1;
486 chan->scan_type.sign = 'u';
487
488 return 0;
489 }
490
ad7607_chan_scale_setup(struct iio_dev * indio_dev,struct iio_chan_spec * chan)491 static int ad7607_chan_scale_setup(struct iio_dev *indio_dev,
492 struct iio_chan_spec *chan)
493 {
494 struct ad7606_state *st = iio_priv(indio_dev);
495 struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index];
496
497 ci->range = 0;
498 ci->scale_avail = ad7607_hw_scale_avail;
499 ci->num_scales = ARRAY_SIZE(ad7607_hw_scale_avail);
500 return 0;
501 }
502
ad7608_chan_scale_setup(struct iio_dev * indio_dev,struct iio_chan_spec * chan)503 static int ad7608_chan_scale_setup(struct iio_dev *indio_dev,
504 struct iio_chan_spec *chan)
505 {
506 struct ad7606_state *st = iio_priv(indio_dev);
507 struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index];
508
509 ci->range = 0;
510 ci->scale_avail = ad7606_18bit_hw_scale_avail;
511 ci->num_scales = ARRAY_SIZE(ad7606_18bit_hw_scale_avail);
512 return 0;
513 }
514
ad7609_chan_scale_setup(struct iio_dev * indio_dev,struct iio_chan_spec * chan)515 static int ad7609_chan_scale_setup(struct iio_dev *indio_dev,
516 struct iio_chan_spec *chan)
517 {
518 struct ad7606_state *st = iio_priv(indio_dev);
519 struct ad7606_chan_info *ci = &st->chan_info[chan->scan_index];
520
521 ci->range = 0;
522 ci->scale_avail = ad7609_hw_scale_avail;
523 ci->num_scales = ARRAY_SIZE(ad7609_hw_scale_avail);
524 return 0;
525 }
526
ad7606_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)527 static int ad7606_reg_access(struct iio_dev *indio_dev,
528 unsigned int reg,
529 unsigned int writeval,
530 unsigned int *readval)
531 {
532 struct ad7606_state *st = iio_priv(indio_dev);
533 int ret;
534
535 guard(mutex)(&st->lock);
536
537 if (readval) {
538 ret = st->bops->reg_read(st, reg);
539 if (ret < 0)
540 return ret;
541 *readval = ret;
542 return 0;
543 } else {
544 return st->bops->reg_write(st, reg, writeval);
545 }
546 }
547
ad7606_pwm_set_high(struct ad7606_state * st)548 static int ad7606_pwm_set_high(struct ad7606_state *st)
549 {
550 struct pwm_state cnvst_pwm_state;
551 int ret;
552
553 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);
554 cnvst_pwm_state.enabled = true;
555 cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period;
556
557 ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state);
558
559 return ret;
560 }
561
ad7606_pwm_set_low(struct ad7606_state * st)562 int ad7606_pwm_set_low(struct ad7606_state *st)
563 {
564 struct pwm_state cnvst_pwm_state;
565 int ret;
566
567 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);
568 cnvst_pwm_state.enabled = true;
569 cnvst_pwm_state.duty_cycle = 0;
570
571 ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state);
572
573 return ret;
574 }
575 EXPORT_SYMBOL_NS_GPL(ad7606_pwm_set_low, "IIO_AD7606");
576
ad7606_pwm_set_swing(struct ad7606_state * st)577 int ad7606_pwm_set_swing(struct ad7606_state *st)
578 {
579 struct pwm_state cnvst_pwm_state;
580
581 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);
582 cnvst_pwm_state.enabled = true;
583 cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period / 2;
584
585 return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state);
586 }
587 EXPORT_SYMBOL_NS_GPL(ad7606_pwm_set_swing, "IIO_AD7606");
588
ad7606_pwm_is_swinging(struct ad7606_state * st)589 static bool ad7606_pwm_is_swinging(struct ad7606_state *st)
590 {
591 struct pwm_state cnvst_pwm_state;
592
593 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);
594
595 return cnvst_pwm_state.duty_cycle != cnvst_pwm_state.period &&
596 cnvst_pwm_state.duty_cycle != 0;
597 }
598
ad7606_set_sampling_freq(struct ad7606_state * st,unsigned long freq)599 static int ad7606_set_sampling_freq(struct ad7606_state *st, unsigned long freq)
600 {
601 struct pwm_state cnvst_pwm_state;
602 bool is_swinging = ad7606_pwm_is_swinging(st);
603 bool is_high;
604
605 if (freq == 0)
606 return -EINVAL;
607
608 /* Retrieve the previous state. */
609 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);
610 is_high = cnvst_pwm_state.duty_cycle == cnvst_pwm_state.period;
611
612 cnvst_pwm_state.period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, freq);
613 cnvst_pwm_state.polarity = PWM_POLARITY_NORMAL;
614 if (is_high)
615 cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period;
616 else if (is_swinging)
617 cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period / 2;
618 else
619 cnvst_pwm_state.duty_cycle = 0;
620
621 return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state);
622 }
623
ad7606_read_samples(struct ad7606_state * st)624 static int ad7606_read_samples(struct ad7606_state *st)
625 {
626 unsigned int num = st->chip_info->num_adc_channels;
627
628 return st->bops->read_block(st->dev, num, &st->data);
629 }
630
ad7606_trigger_handler(int irq,void * p)631 static irqreturn_t ad7606_trigger_handler(int irq, void *p)
632 {
633 struct iio_poll_func *pf = p;
634 struct iio_dev *indio_dev = pf->indio_dev;
635 struct ad7606_state *st = iio_priv(indio_dev);
636 int ret;
637
638 guard(mutex)(&st->lock);
639
640 ret = ad7606_read_samples(st);
641 if (ret)
642 goto error_ret;
643
644 iio_push_to_buffers_with_ts(indio_dev, &st->data, sizeof(st->data),
645 iio_get_time_ns(indio_dev));
646 error_ret:
647 iio_trigger_notify_done(indio_dev->trig);
648 /* The rising edge of the CONVST signal starts a new conversion. */
649 gpiod_set_value(st->gpio_convst, 1);
650
651 return IRQ_HANDLED;
652 }
653
ad7606_scan_direct(struct iio_dev * indio_dev,unsigned int ch,int * val)654 static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch,
655 int *val)
656 {
657 struct ad7606_state *st = iio_priv(indio_dev);
658 const struct iio_chan_spec *chan;
659 unsigned int realbits;
660 int ret;
661
662 if (st->gpio_convst) {
663 gpiod_set_value(st->gpio_convst, 1);
664 } else {
665 ret = ad7606_pwm_set_high(st);
666 if (ret < 0)
667 return ret;
668 }
669
670 /*
671 * If no backend, wait for the interruption on busy pin, otherwise just add
672 * a delay to leave time for the data to be available. For now, the latter
673 * will not happen because IIO_CHAN_INFO_RAW is not supported for the backend.
674 * TODO: Add support for reading a single value when the backend is used.
675 */
676 if (st->trig) {
677 ret = wait_for_completion_timeout(&st->completion,
678 msecs_to_jiffies(1000));
679 if (!ret) {
680 ret = -ETIMEDOUT;
681 goto error_ret;
682 }
683 } else {
684 /*
685 * If the BUSY interrupt is not available, wait enough time for
686 * the longest possible conversion (max for the whole family is
687 * around 350us).
688 */
689 fsleep(400);
690 }
691
692 ret = ad7606_read_samples(st);
693 if (ret)
694 goto error_ret;
695
696 chan = &indio_dev->channels[ch];
697 realbits = chan->scan_type.realbits;
698
699 if (realbits > 16)
700 *val = st->data.buf32[ch];
701 else
702 *val = st->data.buf16[ch];
703
704 *val &= GENMASK(realbits - 1, 0);
705
706 if (chan->scan_type.sign == 's')
707 *val = sign_extend32(*val, realbits - 1);
708
709 error_ret:
710 if (!st->gpio_convst) {
711 ret = ad7606_pwm_set_low(st);
712 if (ret < 0)
713 return ret;
714 }
715 gpiod_set_value(st->gpio_convst, 0);
716
717 return ret;
718 }
719
ad7606_get_calib_offset(struct ad7606_state * st,int ch,int * val)720 static int ad7606_get_calib_offset(struct ad7606_state *st, int ch, int *val)
721 {
722 int ret;
723
724 ret = st->bops->reg_read(st, AD7606_CALIB_OFFSET(ch));
725 if (ret < 0)
726 return ret;
727
728 *val = st->chip_info->calib_offset_avail[0] +
729 ret * st->chip_info->calib_offset_avail[1];
730
731 return 0;
732 }
733
ad7606_get_calib_phase(struct ad7606_state * st,int ch,int * val,int * val2)734 static int ad7606_get_calib_phase(struct ad7606_state *st, int ch, int *val,
735 int *val2)
736 {
737 int ret;
738
739 ret = st->bops->reg_read(st, AD7606_CALIB_PHASE(ch));
740 if (ret < 0)
741 return ret;
742
743 *val = 0;
744
745 /*
746 * ad7606b: phase delay from 0 to 318.75 μs in steps of 1.25 μs.
747 * ad7606c-16/18: phase delay from 0 µs to 255 µs in steps of 1 µs.
748 */
749 *val2 = ret * st->chip_info->calib_phase_avail[1][1];
750
751 return 0;
752 }
753
ad7606_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)754 static int ad7606_read_raw(struct iio_dev *indio_dev,
755 struct iio_chan_spec const *chan,
756 int *val,
757 int *val2,
758 long m)
759 {
760 int ret, ch = 0;
761 struct ad7606_state *st = iio_priv(indio_dev);
762 struct ad7606_chan_info *ci;
763 struct pwm_state cnvst_pwm_state;
764
765 switch (m) {
766 case IIO_CHAN_INFO_RAW:
767 if (!iio_device_claim_direct(indio_dev))
768 return -EBUSY;
769 ret = ad7606_scan_direct(indio_dev, chan->scan_index, val);
770 iio_device_release_direct(indio_dev);
771 if (ret < 0)
772 return ret;
773 return IIO_VAL_INT;
774 case IIO_CHAN_INFO_SCALE:
775 if (st->sw_mode_en)
776 ch = chan->scan_index;
777 ci = &st->chan_info[ch];
778 *val = ci->scale_avail[ci->range][0];
779 *val2 = ci->scale_avail[ci->range][1];
780 return IIO_VAL_INT_PLUS_MICRO;
781 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
782 *val = st->oversampling;
783 return IIO_VAL_INT;
784 case IIO_CHAN_INFO_SAMP_FREQ:
785 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state);
786 *val = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, cnvst_pwm_state.period);
787 return IIO_VAL_INT;
788 case IIO_CHAN_INFO_CALIBBIAS:
789 if (!iio_device_claim_direct(indio_dev))
790 return -EBUSY;
791 ret = ad7606_get_calib_offset(st, chan->scan_index, val);
792 iio_device_release_direct(indio_dev);
793 if (ret)
794 return ret;
795 return IIO_VAL_INT;
796 case IIO_CHAN_INFO_CONVDELAY:
797 if (!iio_device_claim_direct(indio_dev))
798 return -EBUSY;
799 ret = ad7606_get_calib_phase(st, chan->scan_index, val, val2);
800 iio_device_release_direct(indio_dev);
801 if (ret)
802 return ret;
803 return IIO_VAL_INT_PLUS_NANO;
804 }
805 return -EINVAL;
806 }
807
in_voltage_scale_available_show(struct device * dev,struct device_attribute * attr,char * buf)808 static ssize_t in_voltage_scale_available_show(struct device *dev,
809 struct device_attribute *attr,
810 char *buf)
811 {
812 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
813 struct ad7606_state *st = iio_priv(indio_dev);
814 struct ad7606_chan_info *ci = &st->chan_info[0];
815 const unsigned int (*vals)[2] = ci->scale_avail;
816 unsigned int i;
817 size_t len = 0;
818
819 for (i = 0; i < ci->num_scales; i++)
820 len += scnprintf(buf + len, PAGE_SIZE - len, "%u.%06u ",
821 vals[i][0], vals[i][1]);
822 buf[len - 1] = '\n';
823
824 return len;
825 }
826
827 static IIO_DEVICE_ATTR_RO(in_voltage_scale_available, 0);
828
ad7606_write_scale_hw(struct iio_dev * indio_dev,int ch,int val)829 static int ad7606_write_scale_hw(struct iio_dev *indio_dev, int ch, int val)
830 {
831 struct ad7606_state *st = iio_priv(indio_dev);
832
833 gpiod_set_value(st->gpio_range, val);
834
835 return 0;
836 }
837
ad7606_write_os_hw(struct iio_dev * indio_dev,int val)838 static int ad7606_write_os_hw(struct iio_dev *indio_dev, int val)
839 {
840 struct ad7606_state *st = iio_priv(indio_dev);
841 DECLARE_BITMAP(values, 3);
842
843 values[0] = val & GENMASK(2, 0);
844
845 gpiod_multi_set_value_cansleep(st->gpio_os, values);
846
847 /* AD7616 requires a reset to update value */
848 if (st->chip_info->os_req_reset)
849 ad7606_reset(st);
850
851 return 0;
852 }
853
ad7606_set_calib_offset(struct ad7606_state * st,int ch,int val)854 static int ad7606_set_calib_offset(struct ad7606_state *st, int ch, int val)
855 {
856 int start_val, step_val, stop_val;
857 int offset;
858
859 start_val = st->chip_info->calib_offset_avail[0];
860 step_val = st->chip_info->calib_offset_avail[1];
861 stop_val = st->chip_info->calib_offset_avail[2];
862
863 if (val < start_val || val > stop_val)
864 return -EINVAL;
865
866 offset = (val - start_val) / step_val;
867
868 return st->bops->reg_write(st, AD7606_CALIB_OFFSET(ch), offset);
869 }
870
ad7606_set_calib_phase(struct ad7606_state * st,int ch,int val,int val2)871 static int ad7606_set_calib_phase(struct ad7606_state *st, int ch, int val,
872 int val2)
873 {
874 int wreg, start_ns, step_ns, stop_ns;
875
876 if (val != 0)
877 return -EINVAL;
878
879 start_ns = st->chip_info->calib_phase_avail[0][1];
880 step_ns = st->chip_info->calib_phase_avail[1][1];
881 stop_ns = st->chip_info->calib_phase_avail[2][1];
882
883 /*
884 * ad7606b: phase delay from 0 to 318.75 μs in steps of 1.25 μs.
885 * ad7606c-16/18: phase delay from 0 µs to 255 µs in steps of 1 µs.
886 */
887 if (val2 < start_ns || val2 > stop_ns)
888 return -EINVAL;
889
890 wreg = val2 / step_ns;
891
892 return st->bops->reg_write(st, AD7606_CALIB_PHASE(ch), wreg);
893 }
894
ad7606_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long info)895 static int ad7606_write_raw_get_fmt(struct iio_dev *indio_dev,
896 struct iio_chan_spec const *chan, long info)
897 {
898 switch (info) {
899 case IIO_CHAN_INFO_SCALE:
900 return IIO_VAL_INT_PLUS_MICRO;
901 case IIO_CHAN_INFO_SAMP_FREQ:
902 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
903 case IIO_CHAN_INFO_CALIBBIAS:
904 return IIO_VAL_INT;
905 case IIO_CHAN_INFO_CONVDELAY:
906 return IIO_VAL_INT_PLUS_NANO;
907 default:
908 return -EINVAL;
909 }
910 }
911
ad7606_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)912 static int ad7606_write_raw(struct iio_dev *indio_dev,
913 struct iio_chan_spec const *chan,
914 int val,
915 int val2,
916 long mask)
917 {
918 struct ad7606_state *st = iio_priv(indio_dev);
919 unsigned int scale_avail_uv[AD760X_MAX_SCALES];
920 struct ad7606_chan_info *ci;
921 int i, ret, ch = 0;
922
923 guard(mutex)(&st->lock);
924
925 switch (mask) {
926 case IIO_CHAN_INFO_SCALE:
927 if (st->sw_mode_en)
928 ch = chan->scan_index;
929 ci = &st->chan_info[ch];
930 for (i = 0; i < ci->num_scales; i++) {
931 scale_avail_uv[i] = ci->scale_avail[i][0] * MICRO +
932 ci->scale_avail[i][1];
933 }
934 val = (val * MICRO) + val2;
935 i = find_closest(val, scale_avail_uv, ci->num_scales);
936
937 if (!iio_device_claim_direct(indio_dev))
938 return -EBUSY;
939 ret = st->write_scale(indio_dev, ch, i + ci->reg_offset);
940 iio_device_release_direct(indio_dev);
941 if (ret < 0)
942 return ret;
943 ci->range = i;
944
945 return 0;
946 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
947 if (val2)
948 return -EINVAL;
949 i = find_closest(val, st->oversampling_avail,
950 st->num_os_ratios);
951
952 if (!iio_device_claim_direct(indio_dev))
953 return -EBUSY;
954 ret = st->write_os(indio_dev, i);
955 iio_device_release_direct(indio_dev);
956 if (ret < 0)
957 return ret;
958 st->oversampling = st->oversampling_avail[i];
959
960 return 0;
961 case IIO_CHAN_INFO_SAMP_FREQ:
962 if (val < 0 && val2 != 0)
963 return -EINVAL;
964 return ad7606_set_sampling_freq(st, val);
965 case IIO_CHAN_INFO_CALIBBIAS:
966 if (!iio_device_claim_direct(indio_dev))
967 return -EBUSY;
968 ret = ad7606_set_calib_offset(st, chan->scan_index, val);
969 iio_device_release_direct(indio_dev);
970 return ret;
971 case IIO_CHAN_INFO_CONVDELAY:
972 if (!iio_device_claim_direct(indio_dev))
973 return -EBUSY;
974 ret = ad7606_set_calib_phase(st, chan->scan_index, val, val2);
975 iio_device_release_direct(indio_dev);
976 return ret;
977 default:
978 return -EINVAL;
979 }
980 }
981
ad7606_oversampling_ratio_avail(struct device * dev,struct device_attribute * attr,char * buf)982 static ssize_t ad7606_oversampling_ratio_avail(struct device *dev,
983 struct device_attribute *attr,
984 char *buf)
985 {
986 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
987 struct ad7606_state *st = iio_priv(indio_dev);
988 const unsigned int *vals = st->oversampling_avail;
989 unsigned int i;
990 size_t len = 0;
991
992 for (i = 0; i < st->num_os_ratios; i++)
993 len += scnprintf(buf + len, PAGE_SIZE - len, "%u ", vals[i]);
994 buf[len - 1] = '\n';
995
996 return len;
997 }
998
999 static IIO_DEVICE_ATTR(oversampling_ratio_available, 0444,
1000 ad7606_oversampling_ratio_avail, NULL, 0);
1001
1002 static struct attribute *ad7606_attributes_os_and_range[] = {
1003 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
1004 &iio_dev_attr_oversampling_ratio_available.dev_attr.attr,
1005 NULL,
1006 };
1007
1008 static const struct attribute_group ad7606_attribute_group_os_and_range = {
1009 .attrs = ad7606_attributes_os_and_range,
1010 };
1011
1012 static struct attribute *ad7606_attributes_os[] = {
1013 &iio_dev_attr_oversampling_ratio_available.dev_attr.attr,
1014 NULL,
1015 };
1016
1017 static const struct attribute_group ad7606_attribute_group_os = {
1018 .attrs = ad7606_attributes_os,
1019 };
1020
1021 static struct attribute *ad7606_attributes_range[] = {
1022 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
1023 NULL,
1024 };
1025
1026 static const struct attribute_group ad7606_attribute_group_range = {
1027 .attrs = ad7606_attributes_range,
1028 };
1029
ad7606_request_gpios(struct ad7606_state * st)1030 static int ad7606_request_gpios(struct ad7606_state *st)
1031 {
1032 struct device *dev = st->dev;
1033
1034 st->gpio_convst = devm_gpiod_get_optional(dev, "adi,conversion-start",
1035 GPIOD_OUT_LOW);
1036
1037 if (IS_ERR(st->gpio_convst))
1038 return PTR_ERR(st->gpio_convst);
1039
1040 st->gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1041 if (IS_ERR(st->gpio_reset))
1042 return PTR_ERR(st->gpio_reset);
1043
1044 st->gpio_range = devm_gpiod_get_optional(dev, "adi,range",
1045 GPIOD_OUT_LOW);
1046 if (IS_ERR(st->gpio_range))
1047 return PTR_ERR(st->gpio_range);
1048
1049 st->gpio_standby = devm_gpiod_get_optional(dev, "standby",
1050 GPIOD_OUT_LOW);
1051 if (IS_ERR(st->gpio_standby))
1052 return PTR_ERR(st->gpio_standby);
1053
1054 st->gpio_frstdata = devm_gpiod_get_optional(dev, "adi,first-data",
1055 GPIOD_IN);
1056 if (IS_ERR(st->gpio_frstdata))
1057 return PTR_ERR(st->gpio_frstdata);
1058
1059 if (!st->chip_info->oversampling_num)
1060 return 0;
1061
1062 st->gpio_os = devm_gpiod_get_array_optional(dev,
1063 "adi,oversampling-ratio",
1064 GPIOD_OUT_LOW);
1065 return PTR_ERR_OR_ZERO(st->gpio_os);
1066 }
1067
1068 /*
1069 * The BUSY signal indicates when conversions are in progress, so when a rising
1070 * edge of CONVST is applied, BUSY goes logic high and transitions low at the
1071 * end of the entire conversion process. The falling edge of the BUSY signal
1072 * triggers this interrupt.
1073 */
ad7606_interrupt(int irq,void * dev_id)1074 static irqreturn_t ad7606_interrupt(int irq, void *dev_id)
1075 {
1076 struct iio_dev *indio_dev = dev_id;
1077 struct ad7606_state *st = iio_priv(indio_dev);
1078 int ret;
1079
1080 if (iio_buffer_enabled(indio_dev)) {
1081 if (st->gpio_convst) {
1082 gpiod_set_value(st->gpio_convst, 0);
1083 } else {
1084 ret = ad7606_pwm_set_low(st);
1085 if (ret < 0) {
1086 dev_err(st->dev, "PWM set low failed");
1087 goto done;
1088 }
1089 }
1090 iio_trigger_poll_nested(st->trig);
1091 } else {
1092 complete(&st->completion);
1093 }
1094
1095 done:
1096 return IRQ_HANDLED;
1097 };
1098
ad7606_validate_trigger(struct iio_dev * indio_dev,struct iio_trigger * trig)1099 static int ad7606_validate_trigger(struct iio_dev *indio_dev,
1100 struct iio_trigger *trig)
1101 {
1102 struct ad7606_state *st = iio_priv(indio_dev);
1103
1104 if (st->trig != trig)
1105 return -EINVAL;
1106
1107 return 0;
1108 }
1109
ad7606_buffer_postenable(struct iio_dev * indio_dev)1110 static int ad7606_buffer_postenable(struct iio_dev *indio_dev)
1111 {
1112 struct ad7606_state *st = iio_priv(indio_dev);
1113
1114 gpiod_set_value(st->gpio_convst, 1);
1115
1116 return 0;
1117 }
1118
ad7606_buffer_predisable(struct iio_dev * indio_dev)1119 static int ad7606_buffer_predisable(struct iio_dev *indio_dev)
1120 {
1121 struct ad7606_state *st = iio_priv(indio_dev);
1122
1123 gpiod_set_value(st->gpio_convst, 0);
1124
1125 return 0;
1126 }
1127
ad7606_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)1128 static int ad7606_read_avail(struct iio_dev *indio_dev,
1129 struct iio_chan_spec const *chan,
1130 const int **vals, int *type, int *length,
1131 long info)
1132 {
1133 struct ad7606_state *st = iio_priv(indio_dev);
1134 struct ad7606_chan_info *ci;
1135 unsigned int ch = 0;
1136
1137 switch (info) {
1138 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1139 *vals = st->oversampling_avail;
1140 *length = st->num_os_ratios;
1141 *type = IIO_VAL_INT;
1142
1143 return IIO_AVAIL_LIST;
1144
1145 case IIO_CHAN_INFO_SCALE:
1146 if (st->sw_mode_en)
1147 ch = chan->scan_index;
1148
1149 ci = &st->chan_info[ch];
1150 *vals = (int *)ci->scale_avail;
1151 *length = ci->num_scales * 2;
1152 *type = IIO_VAL_INT_PLUS_MICRO;
1153
1154 return IIO_AVAIL_LIST;
1155 case IIO_CHAN_INFO_CALIBBIAS:
1156 *vals = st->chip_info->calib_offset_avail;
1157 *type = IIO_VAL_INT;
1158 return IIO_AVAIL_RANGE;
1159 case IIO_CHAN_INFO_CONVDELAY:
1160 *vals = (const int *)st->chip_info->calib_phase_avail;
1161 *type = IIO_VAL_INT_PLUS_NANO;
1162 return IIO_AVAIL_RANGE;
1163 }
1164 return -EINVAL;
1165 }
1166
ad7606_backend_buffer_postenable(struct iio_dev * indio_dev)1167 static int ad7606_backend_buffer_postenable(struct iio_dev *indio_dev)
1168 {
1169 struct ad7606_state *st = iio_priv(indio_dev);
1170
1171 return ad7606_pwm_set_swing(st);
1172 }
1173
ad7606_backend_buffer_predisable(struct iio_dev * indio_dev)1174 static int ad7606_backend_buffer_predisable(struct iio_dev *indio_dev)
1175 {
1176 struct ad7606_state *st = iio_priv(indio_dev);
1177
1178 return ad7606_pwm_set_low(st);
1179 }
1180
ad7606_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1181 static int ad7606_update_scan_mode(struct iio_dev *indio_dev,
1182 const unsigned long *scan_mask)
1183 {
1184 struct ad7606_state *st = iio_priv(indio_dev);
1185
1186 /*
1187 * The update scan mode is only for iio backend compatible drivers.
1188 * If the specific update_scan_mode is not defined in the bus ops,
1189 * just do nothing and return 0.
1190 */
1191 if (!st->bops->update_scan_mode)
1192 return 0;
1193
1194 return st->bops->update_scan_mode(indio_dev, scan_mask);
1195 }
1196
1197 static const struct iio_buffer_setup_ops ad7606_buffer_ops = {
1198 .postenable = &ad7606_buffer_postenable,
1199 .predisable = &ad7606_buffer_predisable,
1200 };
1201
1202 static const struct iio_buffer_setup_ops ad7606_backend_buffer_ops = {
1203 .postenable = &ad7606_backend_buffer_postenable,
1204 .predisable = &ad7606_backend_buffer_predisable,
1205 };
1206
1207 static const struct iio_info ad7606_info_no_os_or_range = {
1208 .read_raw = &ad7606_read_raw,
1209 .validate_trigger = &ad7606_validate_trigger,
1210 .update_scan_mode = &ad7606_update_scan_mode,
1211 };
1212
1213 static const struct iio_info ad7606_info_os_and_range = {
1214 .read_raw = &ad7606_read_raw,
1215 .write_raw = &ad7606_write_raw,
1216 .attrs = &ad7606_attribute_group_os_and_range,
1217 .validate_trigger = &ad7606_validate_trigger,
1218 .update_scan_mode = &ad7606_update_scan_mode,
1219 };
1220
1221 static const struct iio_info ad7606_info_sw_mode = {
1222 .read_raw = &ad7606_read_raw,
1223 .write_raw = &ad7606_write_raw,
1224 .read_avail = &ad7606_read_avail,
1225 .write_raw_get_fmt = ad7606_write_raw_get_fmt,
1226 .debugfs_reg_access = &ad7606_reg_access,
1227 .validate_trigger = &ad7606_validate_trigger,
1228 .update_scan_mode = &ad7606_update_scan_mode,
1229 };
1230
1231 static const struct iio_info ad7606_info_os = {
1232 .read_raw = &ad7606_read_raw,
1233 .write_raw = &ad7606_write_raw,
1234 .attrs = &ad7606_attribute_group_os,
1235 .validate_trigger = &ad7606_validate_trigger,
1236 .update_scan_mode = &ad7606_update_scan_mode,
1237 };
1238
1239 static const struct iio_info ad7606_info_range = {
1240 .read_raw = &ad7606_read_raw,
1241 .write_raw = &ad7606_write_raw,
1242 .attrs = &ad7606_attribute_group_range,
1243 .validate_trigger = &ad7606_validate_trigger,
1244 .update_scan_mode = &ad7606_update_scan_mode,
1245 };
1246
1247 static const struct iio_trigger_ops ad7606_trigger_ops = {
1248 .validate_device = iio_trigger_validate_own_device,
1249 };
1250
ad7606_write_mask(struct ad7606_state * st,unsigned int addr,unsigned long mask,unsigned int val)1251 static int ad7606_write_mask(struct ad7606_state *st, unsigned int addr,
1252 unsigned long mask, unsigned int val)
1253 {
1254 int readval;
1255
1256 readval = st->bops->reg_read(st, addr);
1257 if (readval < 0)
1258 return readval;
1259
1260 readval &= ~mask;
1261 readval |= val;
1262
1263 return st->bops->reg_write(st, addr, readval);
1264 }
1265
ad7616_write_scale_sw(struct iio_dev * indio_dev,int ch,int val)1266 static int ad7616_write_scale_sw(struct iio_dev *indio_dev, int ch, int val)
1267 {
1268 struct ad7606_state *st = iio_priv(indio_dev);
1269 unsigned int ch_addr, mode, ch_index;
1270
1271 /*
1272 * Ad7616 has 16 channels divided in group A and group B.
1273 * The range of channels from A are stored in registers with address 4
1274 * while channels from B are stored in register with address 6.
1275 * The last bit from channels determines if it is from group A or B
1276 * because the order of channels in iio is 0A, 0B, 1A, 1B...
1277 */
1278 ch_index = ch >> 1;
1279
1280 ch_addr = AD7616_RANGE_CH_ADDR(ch_index);
1281
1282 if ((ch & 0x1) == 0) /* channel A */
1283 ch_addr += AD7616_RANGE_CH_A_ADDR_OFF;
1284 else /* channel B */
1285 ch_addr += AD7616_RANGE_CH_B_ADDR_OFF;
1286
1287 /* 0b01 for 2.5v, 0b10 for 5v and 0b11 for 10v */
1288 mode = AD7616_RANGE_CH_MODE(ch_index, ((val + 1) & 0b11));
1289
1290 return ad7606_write_mask(st, ch_addr, AD7616_RANGE_CH_MSK(ch_index),
1291 mode);
1292 }
1293
ad7616_write_os_sw(struct iio_dev * indio_dev,int val)1294 static int ad7616_write_os_sw(struct iio_dev *indio_dev, int val)
1295 {
1296 struct ad7606_state *st = iio_priv(indio_dev);
1297
1298 return ad7606_write_mask(st, AD7616_CONFIGURATION_REGISTER,
1299 AD7616_OS_MASK, val << 2);
1300 }
1301
ad7606_write_scale_sw(struct iio_dev * indio_dev,int ch,int val)1302 static int ad7606_write_scale_sw(struct iio_dev *indio_dev, int ch, int val)
1303 {
1304 struct ad7606_state *st = iio_priv(indio_dev);
1305
1306 return ad7606_write_mask(st, AD7606_RANGE_CH_ADDR(ch),
1307 AD7606_RANGE_CH_MSK(ch),
1308 AD7606_RANGE_CH_MODE(ch, val));
1309 }
1310
ad7606_write_os_sw(struct iio_dev * indio_dev,int val)1311 static int ad7606_write_os_sw(struct iio_dev *indio_dev, int val)
1312 {
1313 struct ad7606_state *st = iio_priv(indio_dev);
1314
1315 return st->bops->reg_write(st, AD7606_OS_MODE, val);
1316 }
1317
ad7616_sw_mode_setup(struct iio_dev * indio_dev)1318 static int ad7616_sw_mode_setup(struct iio_dev *indio_dev)
1319 {
1320 struct ad7606_state *st = iio_priv(indio_dev);
1321 int ret;
1322
1323 /*
1324 * Scale can be configured individually for each channel
1325 * in software mode.
1326 */
1327
1328 st->write_scale = ad7616_write_scale_sw;
1329 st->write_os = &ad7616_write_os_sw;
1330
1331 if (st->bops->sw_mode_config) {
1332 ret = st->bops->sw_mode_config(indio_dev);
1333 if (ret)
1334 return ret;
1335 }
1336
1337 /* Activate Burst mode and SEQEN MODE */
1338 return ad7606_write_mask(st, AD7616_CONFIGURATION_REGISTER,
1339 AD7616_BURST_MODE | AD7616_SEQEN_MODE,
1340 AD7616_BURST_MODE | AD7616_SEQEN_MODE);
1341 }
1342
ad7606b_sw_mode_setup(struct iio_dev * indio_dev)1343 static int ad7606b_sw_mode_setup(struct iio_dev *indio_dev)
1344 {
1345 struct ad7606_state *st = iio_priv(indio_dev);
1346 DECLARE_BITMAP(os, 3);
1347
1348 bitmap_fill(os, 3);
1349 /*
1350 * Software mode is enabled when all three oversampling
1351 * pins are set to high. If oversampling gpios are defined
1352 * in the device tree, then they need to be set to high,
1353 * otherwise, they must be hardwired to VDD
1354 */
1355 if (st->gpio_os)
1356 gpiod_multi_set_value_cansleep(st->gpio_os, os);
1357
1358 /* OS of 128 and 256 are available only in software mode */
1359 st->oversampling_avail = ad7606b_oversampling_avail;
1360 st->num_os_ratios = ARRAY_SIZE(ad7606b_oversampling_avail);
1361
1362 st->write_scale = ad7606_write_scale_sw;
1363 st->write_os = &ad7606_write_os_sw;
1364
1365 if (!st->bops->sw_mode_config)
1366 return 0;
1367
1368 return st->bops->sw_mode_config(indio_dev);
1369 }
1370
ad7606_set_gain_calib(struct ad7606_state * st)1371 static int ad7606_set_gain_calib(struct ad7606_state *st)
1372 {
1373 struct ad7606_chan_info *ci;
1374 int i, ret;
1375
1376 for (i = 0; i < st->chip_info->num_adc_channels; i++) {
1377 ci = &st->chan_info[i];
1378 ret = st->bops->reg_write(st, AD7606_CALIB_GAIN(i),
1379 DIV_ROUND_CLOSEST(ci->r_gain,
1380 AD7606_CALIB_GAIN_STEP));
1381 if (ret)
1382 return ret;
1383 }
1384
1385 return 0;
1386 }
1387
ad7606_probe_channels(struct iio_dev * indio_dev)1388 static int ad7606_probe_channels(struct iio_dev *indio_dev)
1389 {
1390 struct ad7606_state *st = iio_priv(indio_dev);
1391 struct device *dev = indio_dev->dev.parent;
1392 struct iio_chan_spec *channels;
1393 bool slow_bus;
1394 int ret, i;
1395
1396 slow_bus = !(st->bops->iio_backend_config || st->offload_en);
1397 indio_dev->num_channels = st->chip_info->num_adc_channels;
1398
1399 /* Slow buses also get 1 more channel for soft timestamp */
1400 if (slow_bus)
1401 indio_dev->num_channels++;
1402
1403 channels = devm_kcalloc(dev, indio_dev->num_channels, sizeof(*channels),
1404 GFP_KERNEL);
1405 if (!channels)
1406 return -ENOMEM;
1407
1408 for (i = 0; i < st->chip_info->num_adc_channels; i++) {
1409 struct iio_chan_spec *chan = &channels[i];
1410
1411 chan->type = IIO_VOLTAGE;
1412 chan->indexed = 1;
1413 chan->channel = i;
1414 chan->scan_index = i;
1415 chan->scan_type.sign = 's';
1416 chan->scan_type.realbits = st->chip_info->bits;
1417 /*
1418 * If in SPI offload mode, storagebits are set based
1419 * on the spi-engine hw implementation.
1420 */
1421 chan->scan_type.storagebits = st->offload_en ?
1422 st->chip_info->offload_storagebits :
1423 (st->chip_info->bits > 16 ? 32 : 16);
1424
1425 chan->scan_type.endianness = IIO_CPU;
1426
1427 if (indio_dev->modes & INDIO_DIRECT_MODE)
1428 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_RAW);
1429
1430 if (st->sw_mode_en) {
1431 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_SCALE);
1432 chan->info_mask_separate_available |=
1433 BIT(IIO_CHAN_INFO_SCALE);
1434
1435 if (st->chip_info->calib_offset_avail) {
1436 chan->info_mask_separate |=
1437 BIT(IIO_CHAN_INFO_CALIBBIAS) |
1438 BIT(IIO_CHAN_INFO_CONVDELAY);
1439 chan->info_mask_separate_available |=
1440 BIT(IIO_CHAN_INFO_CALIBBIAS) |
1441 BIT(IIO_CHAN_INFO_CONVDELAY);
1442 }
1443
1444 /*
1445 * All chips with software mode support oversampling,
1446 * so we skip the oversampling_available check. And the
1447 * shared_by_type instead of shared_by_all on slow
1448 * buses is for backward compatibility.
1449 */
1450 if (slow_bus)
1451 chan->info_mask_shared_by_type |=
1452 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
1453 else
1454 chan->info_mask_shared_by_all |=
1455 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
1456
1457 chan->info_mask_shared_by_all_available |=
1458 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
1459 } else {
1460 chan->info_mask_shared_by_type |=
1461 BIT(IIO_CHAN_INFO_SCALE);
1462
1463 if (st->chip_info->oversampling_avail)
1464 chan->info_mask_shared_by_all |=
1465 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
1466 }
1467
1468 if (!slow_bus)
1469 chan->info_mask_shared_by_all |=
1470 BIT(IIO_CHAN_INFO_SAMP_FREQ);
1471
1472 ret = st->chip_info->scale_setup_cb(indio_dev, chan);
1473 if (ret)
1474 return ret;
1475 }
1476
1477 if (slow_bus)
1478 channels[i] = (struct iio_chan_spec)IIO_CHAN_SOFT_TIMESTAMP(i);
1479
1480 indio_dev->channels = channels;
1481
1482 return 0;
1483 }
1484
ad7606_pwm_disable(void * data)1485 static void ad7606_pwm_disable(void *data)
1486 {
1487 pwm_disable(data);
1488 }
1489
ad7606_probe(struct device * dev,int irq,void __iomem * base_address,const struct ad7606_chip_info * chip_info,const struct ad7606_bus_ops * bops)1490 int ad7606_probe(struct device *dev, int irq, void __iomem *base_address,
1491 const struct ad7606_chip_info *chip_info,
1492 const struct ad7606_bus_ops *bops)
1493 {
1494 struct ad7606_state *st;
1495 int ret;
1496 struct iio_dev *indio_dev;
1497
1498 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1499 if (!indio_dev)
1500 return -ENOMEM;
1501
1502 st = iio_priv(indio_dev);
1503 dev_set_drvdata(dev, indio_dev);
1504
1505 ret = devm_mutex_init(dev, &st->lock);
1506 if (ret)
1507 return ret;
1508
1509 st->dev = dev;
1510 st->bops = bops;
1511 st->base_address = base_address;
1512 st->oversampling = 1;
1513 st->sw_mode_en = device_property_read_bool(dev, "adi,sw-mode");
1514
1515 if (st->sw_mode_en && !chip_info->sw_setup_cb)
1516 return dev_err_probe(dev, -EINVAL,
1517 "Software mode is not supported for this chip\n");
1518
1519 ret = devm_regulator_get_enable(dev, "avcc");
1520 if (ret)
1521 return dev_err_probe(dev, ret,
1522 "Failed to enable specified AVcc supply\n");
1523
1524 ret = devm_regulator_get_enable(dev, "vdrive");
1525 if (ret)
1526 return dev_err_probe(dev, ret,
1527 "Failed to enable Vdrive supply\n");
1528
1529 ret = devm_regulator_get_enable_optional(dev, "refin");
1530 if (ret && ret != -ENODEV)
1531 return dev_err_probe(dev, ret,
1532 "Failed to enable REFIN supply\n");
1533
1534 st->chip_info = chip_info;
1535
1536 if (st->chip_info->oversampling_num) {
1537 st->oversampling_avail = st->chip_info->oversampling_avail;
1538 st->num_os_ratios = st->chip_info->oversampling_num;
1539 }
1540
1541 ret = ad7606_request_gpios(st);
1542 if (ret)
1543 return ret;
1544
1545 if (st->gpio_os) {
1546 if (st->gpio_range)
1547 indio_dev->info = &ad7606_info_os_and_range;
1548 else
1549 indio_dev->info = &ad7606_info_os;
1550 } else {
1551 if (st->gpio_range)
1552 indio_dev->info = &ad7606_info_range;
1553 else
1554 indio_dev->info = &ad7606_info_no_os_or_range;
1555 }
1556
1557 /* AXI ADC backend doesn't support single read. */
1558 indio_dev->modes = st->bops->iio_backend_config ? 0 : INDIO_DIRECT_MODE;
1559 indio_dev->name = chip_info->name;
1560
1561 /* Using spi-engine with offload support ? */
1562 if (st->bops->offload_config) {
1563 ret = st->bops->offload_config(dev, indio_dev);
1564 if (ret)
1565 return ret;
1566 }
1567
1568 ret = ad7606_probe_channels(indio_dev);
1569 if (ret)
1570 return ret;
1571
1572 ret = ad7606_reset(st);
1573 if (ret)
1574 dev_warn(st->dev, "failed to RESET: no RESET GPIO specified\n");
1575
1576 /* AD7616 requires al least 15ms to reconfigure after a reset */
1577 if (st->chip_info->init_delay_ms) {
1578 if (msleep_interruptible(st->chip_info->init_delay_ms))
1579 return -ERESTARTSYS;
1580 }
1581
1582 /* If convst pin is not defined, setup PWM. */
1583 if (!st->gpio_convst || st->offload_en) {
1584 st->cnvst_pwm = devm_pwm_get(dev, NULL);
1585 if (IS_ERR(st->cnvst_pwm))
1586 return PTR_ERR(st->cnvst_pwm);
1587
1588 /* The PWM is initialized at 1MHz to have a fast enough GPIO emulation. */
1589 ret = ad7606_set_sampling_freq(st, 1 * MEGA);
1590 if (ret)
1591 return ret;
1592
1593 ret = ad7606_pwm_set_low(st);
1594 if (ret)
1595 return ret;
1596
1597 /*
1598 * PWM is not disabled when sampling stops, but instead its duty cycle is set
1599 * to 0% to be sure we have a "low" state. After we unload the driver, let's
1600 * disable the PWM.
1601 */
1602 ret = devm_add_action_or_reset(dev, ad7606_pwm_disable,
1603 st->cnvst_pwm);
1604 if (ret)
1605 return ret;
1606 }
1607
1608 if (st->bops->iio_backend_config) {
1609 /*
1610 * If there is a backend, the PWM should not overpass the maximum sampling
1611 * frequency the chip supports.
1612 */
1613 ret = ad7606_set_sampling_freq(st, chip_info->max_samplerate);
1614 if (ret)
1615 return ret;
1616
1617 ret = st->bops->iio_backend_config(dev, indio_dev);
1618 if (ret)
1619 return ret;
1620
1621 indio_dev->setup_ops = &ad7606_backend_buffer_ops;
1622 } else if (!st->offload_en) {
1623 /* Reserve the PWM use only for backend (force gpio_convst definition) */
1624 if (!st->gpio_convst)
1625 return dev_err_probe(dev, -EINVAL,
1626 "No backend, connect convst to a GPIO");
1627
1628 init_completion(&st->completion);
1629 st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
1630 indio_dev->name,
1631 iio_device_id(indio_dev));
1632 if (!st->trig)
1633 return -ENOMEM;
1634
1635 st->trig->ops = &ad7606_trigger_ops;
1636 iio_trigger_set_drvdata(st->trig, indio_dev);
1637 ret = devm_iio_trigger_register(dev, st->trig);
1638 if (ret)
1639 return ret;
1640
1641 indio_dev->trig = iio_trigger_get(st->trig);
1642
1643 ret = devm_request_threaded_irq(dev, irq, NULL, &ad7606_interrupt,
1644 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1645 chip_info->name, indio_dev);
1646 if (ret)
1647 return ret;
1648
1649 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
1650 &iio_pollfunc_store_time,
1651 &ad7606_trigger_handler,
1652 &ad7606_buffer_ops);
1653 if (ret)
1654 return ret;
1655 }
1656
1657 st->write_scale = ad7606_write_scale_hw;
1658 st->write_os = ad7606_write_os_hw;
1659
1660 /* Offload needs 1 DOUT line, applying this setting in sw_setup_cb. */
1661 if (st->sw_mode_en || st->offload_en) {
1662 indio_dev->info = &ad7606_info_sw_mode;
1663 st->chip_info->sw_setup_cb(indio_dev);
1664 }
1665
1666 if (st->sw_mode_en && st->chip_info->calib_gain_avail) {
1667 ret = ad7606_set_gain_calib(st);
1668 if (ret)
1669 return ret;
1670 }
1671
1672 return devm_iio_device_register(dev, indio_dev);
1673 }
1674 EXPORT_SYMBOL_NS_GPL(ad7606_probe, "IIO_AD7606");
1675
1676 #ifdef CONFIG_PM_SLEEP
1677
ad7606_suspend(struct device * dev)1678 static int ad7606_suspend(struct device *dev)
1679 {
1680 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1681 struct ad7606_state *st = iio_priv(indio_dev);
1682
1683 if (st->gpio_standby) {
1684 gpiod_set_value(st->gpio_range, 1);
1685 gpiod_set_value(st->gpio_standby, 1);
1686 }
1687
1688 return 0;
1689 }
1690
ad7606_resume(struct device * dev)1691 static int ad7606_resume(struct device *dev)
1692 {
1693 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1694 struct ad7606_state *st = iio_priv(indio_dev);
1695
1696 if (st->gpio_standby) {
1697 gpiod_set_value(st->gpio_range, st->chan_info[0].range);
1698 gpiod_set_value(st->gpio_standby, 1);
1699 ad7606_reset(st);
1700 }
1701
1702 return 0;
1703 }
1704
1705 SIMPLE_DEV_PM_OPS(ad7606_pm_ops, ad7606_suspend, ad7606_resume);
1706 EXPORT_SYMBOL_NS_GPL(ad7606_pm_ops, "IIO_AD7606");
1707
1708 #endif
1709
1710 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1711 MODULE_DESCRIPTION("Analog Devices AD7606 ADC");
1712 MODULE_LICENSE("GPL v2");
1713