1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2021 Analog Devices, Inc.
4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
5 */
6
7 #include <linux/unaligned.h>
8 #include <linux/bitfield.h>
9 #include <linux/cleanup.h>
10 #include <linux/crc8.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/iio/buffer.h>
16 #include <linux/iio/iio.h>
17 #include <linux/iio/sysfs.h>
18 #include <linux/iio/trigger.h>
19 #include <linux/iio/trigger_consumer.h>
20 #include <linux/iio/triggered_buffer.h>
21 #include <linux/interrupt.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/property.h>
24 #include <linux/regmap.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/spi/spi.h>
27
28 #include <dt-bindings/iio/addac/adi,ad74413r.h>
29
30 #define AD74413R_CRC_POLYNOMIAL 0x7
31 DECLARE_CRC8_TABLE(ad74413r_crc8_table);
32
33 #define AD74413R_CHANNEL_MAX 4
34
35 #define AD74413R_FRAME_SIZE 4
36
37 struct ad74413r_chip_info {
38 const char *name;
39 bool hart_support;
40 };
41
42 struct ad74413r_channel_config {
43 u32 func;
44 u32 drive_strength;
45 bool gpo_comparator;
46 bool initialized;
47 };
48
49 struct ad74413r_channels {
50 const struct iio_chan_spec *channels;
51 unsigned int num_channels;
52 };
53
54 struct ad74413r_state {
55 struct ad74413r_channel_config channel_configs[AD74413R_CHANNEL_MAX];
56 unsigned int gpo_gpio_offsets[AD74413R_CHANNEL_MAX];
57 unsigned int comp_gpio_offsets[AD74413R_CHANNEL_MAX];
58 struct gpio_chip gpo_gpiochip;
59 struct gpio_chip comp_gpiochip;
60 struct completion adc_data_completion;
61 unsigned int num_gpo_gpios;
62 unsigned int num_comparator_gpios;
63 u32 sense_resistor_ohms;
64 int refin_reg_uv;
65 /*
66 * Synchronize consecutive operations when doing a one-shot
67 * conversion and when updating the ADC samples SPI message.
68 */
69 struct mutex lock;
70
71 const struct ad74413r_chip_info *chip_info;
72 struct spi_device *spi;
73 struct regmap *regmap;
74 struct device *dev;
75 struct iio_trigger *trig;
76
77 size_t adc_active_channels;
78 struct spi_message adc_samples_msg;
79 struct spi_transfer adc_samples_xfer[AD74413R_CHANNEL_MAX + 1];
80
81 /*
82 * DMA (thus cache coherency maintenance) may require the
83 * transfer buffers to live in their own cache lines.
84 */
85 struct {
86 u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
87 s64 timestamp;
88 } adc_samples_buf __aligned(IIO_DMA_MINALIGN);
89
90 u8 adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
91 u8 reg_tx_buf[AD74413R_FRAME_SIZE];
92 u8 reg_rx_buf[AD74413R_FRAME_SIZE];
93 };
94
95 #define AD74413R_REG_NOP 0x00
96
97 #define AD74413R_REG_CH_FUNC_SETUP_X(x) (0x01 + (x))
98 #define AD74413R_CH_FUNC_SETUP_MASK GENMASK(3, 0)
99
100 #define AD74413R_REG_ADC_CONFIG_X(x) (0x05 + (x))
101 #define AD74413R_ADC_CONFIG_RANGE_MASK GENMASK(7, 5)
102 #define AD74413R_ADC_CONFIG_REJECTION_MASK GENMASK(4, 3)
103 #define AD74413R_ADC_CONFIG_CH_200K_TO_GND BIT(2)
104 #define AD74413R_ADC_RANGE_10V 0b000
105 #define AD74413R_ADC_RANGE_2P5V_EXT_POW 0b001
106 #define AD74413R_ADC_RANGE_2P5V_INT_POW 0b010
107 #define AD74413R_ADC_RANGE_5V_BI_DIR 0b011
108 #define AD74413R_ADC_REJECTION_50_60 0b00
109 #define AD74413R_ADC_REJECTION_NONE 0b01
110 #define AD74413R_ADC_REJECTION_50_60_HART 0b10
111 #define AD74413R_ADC_REJECTION_HART 0b11
112
113 #define AD74413R_REG_DIN_CONFIG_X(x) (0x09 + (x))
114 #define AD74413R_DIN_DEBOUNCE_MASK GENMASK(4, 0)
115 #define AD74413R_DIN_DEBOUNCE_LEN BIT(5)
116 #define AD74413R_DIN_SINK_MASK GENMASK(9, 6)
117
118 #define AD74413R_REG_DAC_CODE_X(x) (0x16 + (x))
119 #define AD74413R_DAC_CODE_MAX GENMASK(12, 0)
120 #define AD74413R_DAC_VOLTAGE_MAX 11000
121
122 #define AD74413R_REG_GPO_PAR_DATA 0x0d
123 #define AD74413R_REG_GPO_CONFIG_X(x) (0x0e + (x))
124 #define AD74413R_GPO_CONFIG_DATA_MASK BIT(3)
125 #define AD74413R_GPO_CONFIG_SELECT_MASK GENMASK(2, 0)
126 #define AD74413R_GPO_CONFIG_100K_PULL_DOWN 0b000
127 #define AD74413R_GPO_CONFIG_LOGIC 0b001
128 #define AD74413R_GPO_CONFIG_LOGIC_PARALLEL 0b010
129 #define AD74413R_GPO_CONFIG_COMPARATOR 0b011
130 #define AD74413R_GPO_CONFIG_HIGH_IMPEDANCE 0b100
131
132 #define AD74413R_REG_ADC_CONV_CTRL 0x23
133 #define AD74413R_CONV_SEQ_MASK GENMASK(9, 8)
134 #define AD74413R_CONV_SEQ_ON 0b00
135 #define AD74413R_CONV_SEQ_SINGLE 0b01
136 #define AD74413R_CONV_SEQ_CONTINUOUS 0b10
137 #define AD74413R_CONV_SEQ_OFF 0b11
138 #define AD74413R_CH_EN_MASK(x) BIT(x)
139
140 #define AD74413R_REG_DIN_COMP_OUT 0x25
141
142 #define AD74413R_REG_ADC_RESULT_X(x) (0x26 + (x))
143 #define AD74413R_ADC_RESULT_MAX GENMASK(15, 0)
144
145 #define AD74413R_REG_READ_SELECT 0x41
146
147 #define AD74413R_REG_CMD_KEY 0x44
148 #define AD74413R_CMD_KEY_LDAC 0x953a
149 #define AD74413R_CMD_KEY_RESET1 0x15fa
150 #define AD74413R_CMD_KEY_RESET2 0xaf51
151
152 static const int ad74413r_adc_sampling_rates[] = {
153 20, 4800,
154 };
155
156 static const int ad74413r_adc_sampling_rates_hart[] = {
157 10, 20, 1200, 4800,
158 };
159
ad74413r_crc(u8 * buf)160 static int ad74413r_crc(u8 *buf)
161 {
162 return crc8(ad74413r_crc8_table, buf, 3, 0);
163 }
164
ad74413r_format_reg_write(u8 reg,u16 val,u8 * buf)165 static void ad74413r_format_reg_write(u8 reg, u16 val, u8 *buf)
166 {
167 buf[0] = reg;
168 put_unaligned_be16(val, &buf[1]);
169 buf[3] = ad74413r_crc(buf);
170 }
171
ad74413r_reg_write(void * context,unsigned int reg,unsigned int val)172 static int ad74413r_reg_write(void *context, unsigned int reg, unsigned int val)
173 {
174 struct ad74413r_state *st = context;
175
176 ad74413r_format_reg_write(reg, val, st->reg_tx_buf);
177
178 return spi_write(st->spi, st->reg_tx_buf, AD74413R_FRAME_SIZE);
179 }
180
ad74413r_crc_check(struct ad74413r_state * st,u8 * buf)181 static int ad74413r_crc_check(struct ad74413r_state *st, u8 *buf)
182 {
183 u8 expected_crc = ad74413r_crc(buf);
184
185 if (buf[3] != expected_crc) {
186 dev_err(st->dev, "Bad CRC %02x for %02x%02x%02x\n",
187 buf[3], buf[0], buf[1], buf[2]);
188 return -EINVAL;
189 }
190
191 return 0;
192 }
193
ad74413r_reg_read(void * context,unsigned int reg,unsigned int * val)194 static int ad74413r_reg_read(void *context, unsigned int reg, unsigned int *val)
195 {
196 struct ad74413r_state *st = context;
197 struct spi_transfer reg_read_xfer[] = {
198 {
199 .tx_buf = st->reg_tx_buf,
200 .len = AD74413R_FRAME_SIZE,
201 .cs_change = 1,
202 },
203 {
204 .rx_buf = st->reg_rx_buf,
205 .len = AD74413R_FRAME_SIZE,
206 },
207 };
208 int ret;
209
210 ad74413r_format_reg_write(AD74413R_REG_READ_SELECT, reg,
211 st->reg_tx_buf);
212
213 ret = spi_sync_transfer(st->spi, reg_read_xfer,
214 ARRAY_SIZE(reg_read_xfer));
215 if (ret)
216 return ret;
217
218 ret = ad74413r_crc_check(st, st->reg_rx_buf);
219 if (ret)
220 return ret;
221
222 *val = get_unaligned_be16(&st->reg_rx_buf[1]);
223
224 return 0;
225 }
226
227 static const struct regmap_config ad74413r_regmap_config = {
228 .reg_bits = 8,
229 .val_bits = 16,
230 .reg_read = ad74413r_reg_read,
231 .reg_write = ad74413r_reg_write,
232 };
233
ad74413r_set_gpo_config(struct ad74413r_state * st,unsigned int offset,u8 mode)234 static int ad74413r_set_gpo_config(struct ad74413r_state *st,
235 unsigned int offset, u8 mode)
236 {
237 return regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(offset),
238 AD74413R_GPO_CONFIG_SELECT_MASK, mode);
239 }
240
241 static const unsigned int ad74413r_debounce_map[AD74413R_DIN_DEBOUNCE_LEN] = {
242 0, 13, 18, 24, 32, 42, 56, 75,
243 100, 130, 180, 240, 320, 420, 560, 750,
244 1000, 1300, 1800, 2400, 3200, 4200, 5600, 7500,
245 10000, 13000, 18000, 24000, 32000, 42000, 56000, 75000,
246 };
247
ad74413r_set_comp_debounce(struct ad74413r_state * st,unsigned int offset,unsigned int debounce)248 static int ad74413r_set_comp_debounce(struct ad74413r_state *st,
249 unsigned int offset,
250 unsigned int debounce)
251 {
252 unsigned int val = AD74413R_DIN_DEBOUNCE_LEN - 1;
253 unsigned int i;
254
255 for (i = 0; i < AD74413R_DIN_DEBOUNCE_LEN; i++)
256 if (debounce <= ad74413r_debounce_map[i]) {
257 val = i;
258 break;
259 }
260
261 return regmap_update_bits(st->regmap,
262 AD74413R_REG_DIN_CONFIG_X(offset),
263 AD74413R_DIN_DEBOUNCE_MASK,
264 val);
265 }
266
ad74413r_set_comp_drive_strength(struct ad74413r_state * st,unsigned int offset,unsigned int strength)267 static int ad74413r_set_comp_drive_strength(struct ad74413r_state *st,
268 unsigned int offset,
269 unsigned int strength)
270 {
271 strength = min(strength, 1800U);
272
273 return regmap_update_bits(st->regmap, AD74413R_REG_DIN_CONFIG_X(offset),
274 AD74413R_DIN_SINK_MASK,
275 FIELD_PREP(AD74413R_DIN_SINK_MASK, strength / 120));
276 }
277
278
ad74413r_gpio_set(struct gpio_chip * chip,unsigned int offset,int val)279 static void ad74413r_gpio_set(struct gpio_chip *chip,
280 unsigned int offset, int val)
281 {
282 struct ad74413r_state *st = gpiochip_get_data(chip);
283 unsigned int real_offset = st->gpo_gpio_offsets[offset];
284 int ret;
285
286 ret = ad74413r_set_gpo_config(st, real_offset,
287 AD74413R_GPO_CONFIG_LOGIC);
288 if (ret)
289 return;
290
291 regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(real_offset),
292 AD74413R_GPO_CONFIG_DATA_MASK,
293 val ? AD74413R_GPO_CONFIG_DATA_MASK : 0);
294 }
295
ad74413r_gpio_set_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)296 static void ad74413r_gpio_set_multiple(struct gpio_chip *chip,
297 unsigned long *mask,
298 unsigned long *bits)
299 {
300 struct ad74413r_state *st = gpiochip_get_data(chip);
301 unsigned long real_mask = 0;
302 unsigned long real_bits = 0;
303 unsigned int offset;
304 int ret;
305
306 for_each_set_bit(offset, mask, chip->ngpio) {
307 unsigned int real_offset = st->gpo_gpio_offsets[offset];
308
309 ret = ad74413r_set_gpo_config(st, real_offset,
310 AD74413R_GPO_CONFIG_LOGIC_PARALLEL);
311 if (ret)
312 return;
313
314 real_mask |= BIT(real_offset);
315 if (*bits & offset)
316 real_bits |= BIT(real_offset);
317 }
318
319 regmap_update_bits(st->regmap, AD74413R_REG_GPO_PAR_DATA,
320 real_mask, real_bits);
321 }
322
ad74413r_gpio_get(struct gpio_chip * chip,unsigned int offset)323 static int ad74413r_gpio_get(struct gpio_chip *chip, unsigned int offset)
324 {
325 struct ad74413r_state *st = gpiochip_get_data(chip);
326 unsigned int real_offset = st->comp_gpio_offsets[offset];
327 unsigned int status;
328 int ret;
329
330 ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &status);
331 if (ret)
332 return ret;
333
334 status &= BIT(real_offset);
335
336 return status ? 1 : 0;
337 }
338
ad74413r_gpio_get_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)339 static int ad74413r_gpio_get_multiple(struct gpio_chip *chip,
340 unsigned long *mask,
341 unsigned long *bits)
342 {
343 struct ad74413r_state *st = gpiochip_get_data(chip);
344 unsigned int offset;
345 unsigned int val;
346 int ret;
347
348 ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &val);
349 if (ret)
350 return ret;
351
352 for_each_set_bit(offset, mask, chip->ngpio) {
353 unsigned int real_offset = st->comp_gpio_offsets[offset];
354
355 __assign_bit(offset, bits, val & BIT(real_offset));
356 }
357
358 return ret;
359 }
360
ad74413r_gpio_get_gpo_direction(struct gpio_chip * chip,unsigned int offset)361 static int ad74413r_gpio_get_gpo_direction(struct gpio_chip *chip,
362 unsigned int offset)
363 {
364 return GPIO_LINE_DIRECTION_OUT;
365 }
366
ad74413r_gpio_get_comp_direction(struct gpio_chip * chip,unsigned int offset)367 static int ad74413r_gpio_get_comp_direction(struct gpio_chip *chip,
368 unsigned int offset)
369 {
370 return GPIO_LINE_DIRECTION_IN;
371 }
372
ad74413r_gpio_set_gpo_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)373 static int ad74413r_gpio_set_gpo_config(struct gpio_chip *chip,
374 unsigned int offset,
375 unsigned long config)
376 {
377 struct ad74413r_state *st = gpiochip_get_data(chip);
378 unsigned int real_offset = st->gpo_gpio_offsets[offset];
379
380 switch (pinconf_to_config_param(config)) {
381 case PIN_CONFIG_BIAS_PULL_DOWN:
382 return ad74413r_set_gpo_config(st, real_offset,
383 AD74413R_GPO_CONFIG_100K_PULL_DOWN);
384 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
385 return ad74413r_set_gpo_config(st, real_offset,
386 AD74413R_GPO_CONFIG_HIGH_IMPEDANCE);
387 default:
388 return -ENOTSUPP;
389 }
390 }
391
ad74413r_gpio_set_comp_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)392 static int ad74413r_gpio_set_comp_config(struct gpio_chip *chip,
393 unsigned int offset,
394 unsigned long config)
395 {
396 struct ad74413r_state *st = gpiochip_get_data(chip);
397 unsigned int real_offset = st->comp_gpio_offsets[offset];
398
399 switch (pinconf_to_config_param(config)) {
400 case PIN_CONFIG_INPUT_DEBOUNCE:
401 return ad74413r_set_comp_debounce(st, real_offset,
402 pinconf_to_config_argument(config));
403 default:
404 return -ENOTSUPP;
405 }
406 }
407
ad74413r_reset(struct ad74413r_state * st)408 static int ad74413r_reset(struct ad74413r_state *st)
409 {
410 struct gpio_desc *reset_gpio;
411 int ret;
412
413 reset_gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_HIGH);
414 if (IS_ERR(reset_gpio))
415 return PTR_ERR(reset_gpio);
416
417 if (reset_gpio) {
418 fsleep(50);
419 gpiod_set_value_cansleep(reset_gpio, 0);
420 return 0;
421 }
422
423 ret = regmap_write(st->regmap, AD74413R_REG_CMD_KEY,
424 AD74413R_CMD_KEY_RESET1);
425 if (ret)
426 return ret;
427
428 return regmap_write(st->regmap, AD74413R_REG_CMD_KEY,
429 AD74413R_CMD_KEY_RESET2);
430 }
431
ad74413r_set_channel_dac_code(struct ad74413r_state * st,unsigned int channel,int dac_code)432 static int ad74413r_set_channel_dac_code(struct ad74413r_state *st,
433 unsigned int channel, int dac_code)
434 {
435 struct reg_sequence reg_seq[2] = {
436 { AD74413R_REG_DAC_CODE_X(channel), dac_code },
437 { AD74413R_REG_CMD_KEY, AD74413R_CMD_KEY_LDAC },
438 };
439
440 return regmap_multi_reg_write(st->regmap, reg_seq, 2);
441 }
442
ad74413r_set_channel_function(struct ad74413r_state * st,unsigned int channel,u8 func)443 static int ad74413r_set_channel_function(struct ad74413r_state *st,
444 unsigned int channel, u8 func)
445 {
446 int ret;
447
448 ret = regmap_update_bits(st->regmap,
449 AD74413R_REG_CH_FUNC_SETUP_X(channel),
450 AD74413R_CH_FUNC_SETUP_MASK,
451 CH_FUNC_HIGH_IMPEDANCE);
452 if (ret)
453 return ret;
454
455 /* Set DAC code to 0 prior to changing channel function */
456 ret = ad74413r_set_channel_dac_code(st, channel, 0);
457 if (ret)
458 return ret;
459
460 /* Delay required before transition to new desired mode */
461 usleep_range(130, 150);
462
463 ret = regmap_update_bits(st->regmap,
464 AD74413R_REG_CH_FUNC_SETUP_X(channel),
465 AD74413R_CH_FUNC_SETUP_MASK, func);
466 if (ret)
467 return ret;
468
469 /* Delay required before updating the new DAC code */
470 usleep_range(150, 170);
471
472 if (func == CH_FUNC_CURRENT_INPUT_LOOP_POWER)
473 ret = regmap_set_bits(st->regmap,
474 AD74413R_REG_ADC_CONFIG_X(channel),
475 AD74413R_ADC_CONFIG_CH_200K_TO_GND);
476
477 return ret;
478 }
479
ad74413r_set_adc_conv_seq(struct ad74413r_state * st,unsigned int status)480 static int ad74413r_set_adc_conv_seq(struct ad74413r_state *st,
481 unsigned int status)
482 {
483 int ret;
484
485 /*
486 * These bits do not clear when a conversion completes.
487 * To enable a subsequent conversion, repeat the write.
488 */
489 ret = regmap_write_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL,
490 AD74413R_CONV_SEQ_MASK,
491 FIELD_PREP(AD74413R_CONV_SEQ_MASK, status));
492 if (ret)
493 return ret;
494
495 /*
496 * Wait 100us before starting conversions.
497 */
498 usleep_range(100, 120);
499
500 return 0;
501 }
502
ad74413r_set_adc_channel_enable(struct ad74413r_state * st,unsigned int channel,bool status)503 static int ad74413r_set_adc_channel_enable(struct ad74413r_state *st,
504 unsigned int channel,
505 bool status)
506 {
507 return regmap_update_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL,
508 AD74413R_CH_EN_MASK(channel),
509 status ? AD74413R_CH_EN_MASK(channel) : 0);
510 }
511
ad74413r_get_adc_range(struct ad74413r_state * st,unsigned int channel,unsigned int * val)512 static int ad74413r_get_adc_range(struct ad74413r_state *st,
513 unsigned int channel,
514 unsigned int *val)
515 {
516 int ret;
517
518 ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val);
519 if (ret)
520 return ret;
521
522 *val = FIELD_GET(AD74413R_ADC_CONFIG_RANGE_MASK, *val);
523
524 return 0;
525 }
526
ad74413r_get_adc_rejection(struct ad74413r_state * st,unsigned int channel,unsigned int * val)527 static int ad74413r_get_adc_rejection(struct ad74413r_state *st,
528 unsigned int channel,
529 unsigned int *val)
530 {
531 int ret;
532
533 ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val);
534 if (ret)
535 return ret;
536
537 *val = FIELD_GET(AD74413R_ADC_CONFIG_REJECTION_MASK, *val);
538
539 return 0;
540 }
541
ad74413r_set_adc_rejection(struct ad74413r_state * st,unsigned int channel,unsigned int val)542 static int ad74413r_set_adc_rejection(struct ad74413r_state *st,
543 unsigned int channel,
544 unsigned int val)
545 {
546 return regmap_update_bits(st->regmap,
547 AD74413R_REG_ADC_CONFIG_X(channel),
548 AD74413R_ADC_CONFIG_REJECTION_MASK,
549 FIELD_PREP(AD74413R_ADC_CONFIG_REJECTION_MASK,
550 val));
551 }
552
ad74413r_rejection_to_rate(struct ad74413r_state * st,unsigned int rej,int * val)553 static int ad74413r_rejection_to_rate(struct ad74413r_state *st,
554 unsigned int rej, int *val)
555 {
556 switch (rej) {
557 case AD74413R_ADC_REJECTION_50_60:
558 *val = 20;
559 return 0;
560 case AD74413R_ADC_REJECTION_NONE:
561 *val = 4800;
562 return 0;
563 case AD74413R_ADC_REJECTION_50_60_HART:
564 *val = 10;
565 return 0;
566 case AD74413R_ADC_REJECTION_HART:
567 *val = 1200;
568 return 0;
569 default:
570 dev_err(st->dev, "ADC rejection invalid\n");
571 return -EINVAL;
572 }
573 }
574
ad74413r_rate_to_rejection(struct ad74413r_state * st,int rate,unsigned int * val)575 static int ad74413r_rate_to_rejection(struct ad74413r_state *st,
576 int rate, unsigned int *val)
577 {
578 switch (rate) {
579 case 20:
580 *val = AD74413R_ADC_REJECTION_50_60;
581 return 0;
582 case 4800:
583 *val = AD74413R_ADC_REJECTION_NONE;
584 return 0;
585 case 10:
586 *val = AD74413R_ADC_REJECTION_50_60_HART;
587 return 0;
588 case 1200:
589 *val = AD74413R_ADC_REJECTION_HART;
590 return 0;
591 default:
592 dev_err(st->dev, "ADC rate invalid\n");
593 return -EINVAL;
594 }
595 }
596
ad74413r_range_to_voltage_range(struct ad74413r_state * st,unsigned int range,int * val)597 static int ad74413r_range_to_voltage_range(struct ad74413r_state *st,
598 unsigned int range, int *val)
599 {
600 switch (range) {
601 case AD74413R_ADC_RANGE_10V:
602 *val = 10000;
603 return 0;
604 case AD74413R_ADC_RANGE_2P5V_EXT_POW:
605 case AD74413R_ADC_RANGE_2P5V_INT_POW:
606 *val = 2500;
607 return 0;
608 case AD74413R_ADC_RANGE_5V_BI_DIR:
609 *val = 5000;
610 return 0;
611 default:
612 dev_err(st->dev, "ADC range invalid\n");
613 return -EINVAL;
614 }
615 }
616
ad74413r_range_to_voltage_offset(struct ad74413r_state * st,unsigned int range,int * val)617 static int ad74413r_range_to_voltage_offset(struct ad74413r_state *st,
618 unsigned int range, int *val)
619 {
620 switch (range) {
621 case AD74413R_ADC_RANGE_10V:
622 case AD74413R_ADC_RANGE_2P5V_EXT_POW:
623 *val = 0;
624 return 0;
625 case AD74413R_ADC_RANGE_2P5V_INT_POW:
626 case AD74413R_ADC_RANGE_5V_BI_DIR:
627 *val = -2500;
628 return 0;
629 default:
630 dev_err(st->dev, "ADC range invalid\n");
631 return -EINVAL;
632 }
633 }
634
ad74413r_range_to_voltage_offset_raw(struct ad74413r_state * st,unsigned int range,int * val)635 static int ad74413r_range_to_voltage_offset_raw(struct ad74413r_state *st,
636 unsigned int range, int *val)
637 {
638 switch (range) {
639 case AD74413R_ADC_RANGE_10V:
640 case AD74413R_ADC_RANGE_2P5V_EXT_POW:
641 *val = 0;
642 return 0;
643 case AD74413R_ADC_RANGE_2P5V_INT_POW:
644 *val = -((int)AD74413R_ADC_RESULT_MAX);
645 return 0;
646 case AD74413R_ADC_RANGE_5V_BI_DIR:
647 *val = -((int)AD74413R_ADC_RESULT_MAX / 2);
648 return 0;
649 default:
650 dev_err(st->dev, "ADC range invalid\n");
651 return -EINVAL;
652 }
653 }
654
ad74413r_get_output_voltage_scale(struct ad74413r_state * st,int * val,int * val2)655 static int ad74413r_get_output_voltage_scale(struct ad74413r_state *st,
656 int *val, int *val2)
657 {
658 *val = AD74413R_DAC_VOLTAGE_MAX;
659 *val2 = AD74413R_DAC_CODE_MAX;
660
661 return IIO_VAL_FRACTIONAL;
662 }
663
ad74413r_get_output_current_scale(struct ad74413r_state * st,int * val,int * val2)664 static int ad74413r_get_output_current_scale(struct ad74413r_state *st,
665 int *val, int *val2)
666 {
667 *val = st->refin_reg_uv;
668 *val2 = st->sense_resistor_ohms * AD74413R_DAC_CODE_MAX * 1000;
669
670 return IIO_VAL_FRACTIONAL;
671 }
672
ad74413r_get_input_voltage_scale(struct ad74413r_state * st,unsigned int channel,int * val,int * val2)673 static int ad74413r_get_input_voltage_scale(struct ad74413r_state *st,
674 unsigned int channel,
675 int *val, int *val2)
676 {
677 unsigned int range;
678 int ret;
679
680 ret = ad74413r_get_adc_range(st, channel, &range);
681 if (ret)
682 return ret;
683
684 ret = ad74413r_range_to_voltage_range(st, range, val);
685 if (ret)
686 return ret;
687
688 *val2 = AD74413R_ADC_RESULT_MAX;
689
690 return IIO_VAL_FRACTIONAL;
691 }
692
ad74413r_get_input_voltage_offset(struct ad74413r_state * st,unsigned int channel,int * val)693 static int ad74413r_get_input_voltage_offset(struct ad74413r_state *st,
694 unsigned int channel, int *val)
695 {
696 unsigned int range;
697 int ret;
698
699 ret = ad74413r_get_adc_range(st, channel, &range);
700 if (ret)
701 return ret;
702
703 ret = ad74413r_range_to_voltage_offset_raw(st, range, val);
704 if (ret)
705 return ret;
706
707 return IIO_VAL_INT;
708 }
709
ad74413r_get_input_current_scale(struct ad74413r_state * st,unsigned int channel,int * val,int * val2)710 static int ad74413r_get_input_current_scale(struct ad74413r_state *st,
711 unsigned int channel, int *val,
712 int *val2)
713 {
714 unsigned int range;
715 int ret;
716
717 ret = ad74413r_get_adc_range(st, channel, &range);
718 if (ret)
719 return ret;
720
721 ret = ad74413r_range_to_voltage_range(st, range, val);
722 if (ret)
723 return ret;
724
725 *val2 = AD74413R_ADC_RESULT_MAX * st->sense_resistor_ohms;
726
727 return IIO_VAL_FRACTIONAL;
728 }
729
ad74413r_get_input_current_offset(struct ad74413r_state * st,unsigned int channel,int * val)730 static int ad74413r_get_input_current_offset(struct ad74413r_state *st,
731 unsigned int channel, int *val)
732 {
733 unsigned int range;
734 int voltage_range;
735 int voltage_offset;
736 int ret;
737
738 ret = ad74413r_get_adc_range(st, channel, &range);
739 if (ret)
740 return ret;
741
742 ret = ad74413r_range_to_voltage_range(st, range, &voltage_range);
743 if (ret)
744 return ret;
745
746 ret = ad74413r_range_to_voltage_offset(st, range, &voltage_offset);
747 if (ret)
748 return ret;
749
750 *val = voltage_offset * (int)AD74413R_ADC_RESULT_MAX / voltage_range;
751
752 return IIO_VAL_INT;
753 }
754
ad74413r_get_adc_rate(struct ad74413r_state * st,unsigned int channel,int * val)755 static int ad74413r_get_adc_rate(struct ad74413r_state *st,
756 unsigned int channel, int *val)
757 {
758 unsigned int rejection;
759 int ret;
760
761 ret = ad74413r_get_adc_rejection(st, channel, &rejection);
762 if (ret)
763 return ret;
764
765 ret = ad74413r_rejection_to_rate(st, rejection, val);
766 if (ret)
767 return ret;
768
769 return IIO_VAL_INT;
770 }
771
ad74413r_set_adc_rate(struct ad74413r_state * st,unsigned int channel,int val)772 static int ad74413r_set_adc_rate(struct ad74413r_state *st,
773 unsigned int channel, int val)
774 {
775 unsigned int rejection;
776 int ret;
777
778 ret = ad74413r_rate_to_rejection(st, val, &rejection);
779 if (ret)
780 return ret;
781
782 return ad74413r_set_adc_rejection(st, channel, rejection);
783 }
784
ad74413r_trigger_handler(int irq,void * p)785 static irqreturn_t ad74413r_trigger_handler(int irq, void *p)
786 {
787 struct iio_poll_func *pf = p;
788 struct iio_dev *indio_dev = pf->indio_dev;
789 struct ad74413r_state *st = iio_priv(indio_dev);
790 u8 *rx_buf = st->adc_samples_buf.rx_buf;
791 unsigned int i;
792 int ret;
793
794 ret = spi_sync(st->spi, &st->adc_samples_msg);
795 if (ret)
796 goto out;
797
798 for (i = 0; i < st->adc_active_channels; i++)
799 ad74413r_crc_check(st, &rx_buf[i * AD74413R_FRAME_SIZE]);
800
801 iio_push_to_buffers_with_timestamp(indio_dev, &st->adc_samples_buf,
802 iio_get_time_ns(indio_dev));
803
804 out:
805 iio_trigger_notify_done(indio_dev->trig);
806
807 return IRQ_HANDLED;
808 }
809
ad74413r_adc_data_interrupt(int irq,void * data)810 static irqreturn_t ad74413r_adc_data_interrupt(int irq, void *data)
811 {
812 struct iio_dev *indio_dev = data;
813 struct ad74413r_state *st = iio_priv(indio_dev);
814
815 if (iio_buffer_enabled(indio_dev))
816 iio_trigger_poll(st->trig);
817 else
818 complete(&st->adc_data_completion);
819
820 return IRQ_HANDLED;
821 }
822
_ad74413r_get_single_adc_result(struct ad74413r_state * st,unsigned int channel,int * val)823 static int _ad74413r_get_single_adc_result(struct ad74413r_state *st,
824 unsigned int channel, int *val)
825 {
826 unsigned int uval;
827 int ret;
828
829 guard(mutex)(&st->lock);
830
831 reinit_completion(&st->adc_data_completion);
832
833 ret = ad74413r_set_adc_channel_enable(st, channel, true);
834 if (ret)
835 return ret;
836
837 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_SINGLE);
838 if (ret)
839 return ret;
840
841 ret = wait_for_completion_timeout(&st->adc_data_completion,
842 msecs_to_jiffies(1000));
843 if (!ret) {
844 ret = -ETIMEDOUT;
845 return ret;
846 }
847
848 ret = regmap_read(st->regmap, AD74413R_REG_ADC_RESULT_X(channel),
849 &uval);
850 if (ret)
851 return ret;
852
853 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
854 if (ret)
855 return ret;
856
857 ret = ad74413r_set_adc_channel_enable(st, channel, false);
858 if (ret)
859 return ret;
860
861 *val = uval;
862
863 return IIO_VAL_INT;
864 }
865
ad74413r_get_single_adc_result(struct iio_dev * indio_dev,unsigned int channel,int * val)866 static int ad74413r_get_single_adc_result(struct iio_dev *indio_dev,
867 unsigned int channel, int *val)
868 {
869 struct ad74413r_state *st = iio_priv(indio_dev);
870 int ret;
871
872 if (!iio_device_claim_direct(indio_dev))
873 return -EBUSY;
874
875 ret = _ad74413r_get_single_adc_result(st, channel, val);
876 iio_device_release_direct(indio_dev);
877 return ret;
878 }
879
ad74413r_adc_to_resistance_result(int adc_result,int * val)880 static void ad74413r_adc_to_resistance_result(int adc_result, int *val)
881 {
882 if (adc_result == AD74413R_ADC_RESULT_MAX)
883 adc_result = AD74413R_ADC_RESULT_MAX - 1;
884
885 *val = DIV_ROUND_CLOSEST(adc_result * 2100,
886 AD74413R_ADC_RESULT_MAX - adc_result);
887 }
888
ad74413r_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * active_scan_mask)889 static int ad74413r_update_scan_mode(struct iio_dev *indio_dev,
890 const unsigned long *active_scan_mask)
891 {
892 struct ad74413r_state *st = iio_priv(indio_dev);
893 struct spi_transfer *xfer = st->adc_samples_xfer;
894 u8 *rx_buf = st->adc_samples_buf.rx_buf;
895 u8 *tx_buf = st->adc_samples_tx_buf;
896 unsigned int channel;
897 int ret = -EINVAL;
898
899 guard(mutex)(&st->lock);
900
901 spi_message_init(&st->adc_samples_msg);
902 st->adc_active_channels = 0;
903
904 for_each_clear_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) {
905 ret = ad74413r_set_adc_channel_enable(st, channel, false);
906 if (ret)
907 return ret;
908 }
909
910 if (*active_scan_mask == 0)
911 return ret;
912
913 /*
914 * The read select register is used to select which register's value
915 * will be sent by the slave on the next SPI frame.
916 *
917 * Create an SPI message that, on each step, writes to the read select
918 * register to select the ADC result of the next enabled channel, and
919 * reads the ADC result of the previous enabled channel.
920 *
921 * Example:
922 * W: [WCH1] [WCH2] [WCH2] [WCH3] [ ]
923 * R: [ ] [RCH1] [RCH2] [RCH3] [RCH4]
924 */
925
926 for_each_set_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) {
927 ret = ad74413r_set_adc_channel_enable(st, channel, true);
928 if (ret)
929 return ret;
930
931 st->adc_active_channels++;
932
933 if (xfer == st->adc_samples_xfer)
934 xfer->rx_buf = NULL;
935 else
936 xfer->rx_buf = rx_buf;
937
938 xfer->tx_buf = tx_buf;
939 xfer->len = AD74413R_FRAME_SIZE;
940 xfer->cs_change = 1;
941
942 ad74413r_format_reg_write(AD74413R_REG_READ_SELECT,
943 AD74413R_REG_ADC_RESULT_X(channel),
944 tx_buf);
945
946 spi_message_add_tail(xfer, &st->adc_samples_msg);
947
948 tx_buf += AD74413R_FRAME_SIZE;
949 if (xfer != st->adc_samples_xfer)
950 rx_buf += AD74413R_FRAME_SIZE;
951 xfer++;
952 }
953
954 xfer->rx_buf = rx_buf;
955 xfer->tx_buf = NULL;
956 xfer->len = AD74413R_FRAME_SIZE;
957 xfer->cs_change = 0;
958
959 spi_message_add_tail(xfer, &st->adc_samples_msg);
960 return 0;
961 }
962
ad74413r_buffer_postenable(struct iio_dev * indio_dev)963 static int ad74413r_buffer_postenable(struct iio_dev *indio_dev)
964 {
965 struct ad74413r_state *st = iio_priv(indio_dev);
966
967 return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_CONTINUOUS);
968 }
969
ad74413r_buffer_predisable(struct iio_dev * indio_dev)970 static int ad74413r_buffer_predisable(struct iio_dev *indio_dev)
971 {
972 struct ad74413r_state *st = iio_priv(indio_dev);
973
974 return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
975 }
976
ad74413r_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)977 static int ad74413r_read_raw(struct iio_dev *indio_dev,
978 struct iio_chan_spec const *chan,
979 int *val, int *val2, long info)
980 {
981 struct ad74413r_state *st = iio_priv(indio_dev);
982
983 switch (info) {
984 case IIO_CHAN_INFO_SCALE:
985 switch (chan->type) {
986 case IIO_VOLTAGE:
987 if (chan->output)
988 return ad74413r_get_output_voltage_scale(st,
989 val, val2);
990 else
991 return ad74413r_get_input_voltage_scale(st,
992 chan->channel, val, val2);
993 case IIO_CURRENT:
994 if (chan->output)
995 return ad74413r_get_output_current_scale(st,
996 val, val2);
997 else
998 return ad74413r_get_input_current_scale(st,
999 chan->channel, val, val2);
1000 default:
1001 return -EINVAL;
1002 }
1003 case IIO_CHAN_INFO_OFFSET:
1004 switch (chan->type) {
1005 case IIO_VOLTAGE:
1006 return ad74413r_get_input_voltage_offset(st,
1007 chan->channel, val);
1008 case IIO_CURRENT:
1009 return ad74413r_get_input_current_offset(st,
1010 chan->channel, val);
1011 default:
1012 return -EINVAL;
1013 }
1014 case IIO_CHAN_INFO_RAW:
1015 if (chan->output)
1016 return -EINVAL;
1017
1018 return ad74413r_get_single_adc_result(indio_dev, chan->channel,
1019 val);
1020 case IIO_CHAN_INFO_PROCESSED: {
1021 int ret;
1022
1023 ret = ad74413r_get_single_adc_result(indio_dev, chan->channel,
1024 val);
1025 if (ret < 0)
1026 return ret;
1027
1028 ad74413r_adc_to_resistance_result(*val, val);
1029
1030 return ret;
1031 }
1032 case IIO_CHAN_INFO_SAMP_FREQ:
1033 return ad74413r_get_adc_rate(st, chan->channel, val);
1034 default:
1035 return -EINVAL;
1036 }
1037 }
1038
ad74413r_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)1039 static int ad74413r_write_raw(struct iio_dev *indio_dev,
1040 struct iio_chan_spec const *chan,
1041 int val, int val2, long info)
1042 {
1043 struct ad74413r_state *st = iio_priv(indio_dev);
1044
1045 switch (info) {
1046 case IIO_CHAN_INFO_RAW:
1047 if (!chan->output)
1048 return -EINVAL;
1049
1050 if (val < 0 || val > AD74413R_DAC_CODE_MAX) {
1051 dev_err(st->dev, "Invalid DAC code\n");
1052 return -EINVAL;
1053 }
1054
1055 return ad74413r_set_channel_dac_code(st, chan->channel, val);
1056 case IIO_CHAN_INFO_SAMP_FREQ:
1057 return ad74413r_set_adc_rate(st, chan->channel, val);
1058 default:
1059 return -EINVAL;
1060 }
1061 }
1062
ad74413r_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)1063 static int ad74413r_read_avail(struct iio_dev *indio_dev,
1064 struct iio_chan_spec const *chan,
1065 const int **vals, int *type, int *length,
1066 long info)
1067 {
1068 struct ad74413r_state *st = iio_priv(indio_dev);
1069
1070 switch (info) {
1071 case IIO_CHAN_INFO_SAMP_FREQ:
1072 if (st->chip_info->hart_support) {
1073 *vals = ad74413r_adc_sampling_rates_hart;
1074 *length = ARRAY_SIZE(ad74413r_adc_sampling_rates_hart);
1075 } else {
1076 *vals = ad74413r_adc_sampling_rates;
1077 *length = ARRAY_SIZE(ad74413r_adc_sampling_rates);
1078 }
1079 *type = IIO_VAL_INT;
1080 return IIO_AVAIL_LIST;
1081 default:
1082 return -EINVAL;
1083 }
1084 }
1085
1086 static const struct iio_buffer_setup_ops ad74413r_buffer_ops = {
1087 .postenable = &ad74413r_buffer_postenable,
1088 .predisable = &ad74413r_buffer_predisable,
1089 };
1090
1091 static const struct iio_trigger_ops ad74413r_trigger_ops = {
1092 .validate_device = iio_trigger_validate_own_device,
1093 };
1094
1095 static const struct iio_info ad74413r_info = {
1096 .read_raw = &ad74413r_read_raw,
1097 .write_raw = &ad74413r_write_raw,
1098 .read_avail = &ad74413r_read_avail,
1099 .update_scan_mode = &ad74413r_update_scan_mode,
1100 };
1101
1102 #define AD74413R_DAC_CHANNEL(_type, extra_mask_separate) \
1103 { \
1104 .type = (_type), \
1105 .indexed = 1, \
1106 .output = 1, \
1107 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
1108 | (extra_mask_separate), \
1109 }
1110
1111 #define AD74413R_ADC_CHANNEL(_type, extra_mask_separate) \
1112 { \
1113 .type = (_type), \
1114 .indexed = 1, \
1115 .output = 0, \
1116 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
1117 | BIT(IIO_CHAN_INFO_SAMP_FREQ) \
1118 | (extra_mask_separate), \
1119 .info_mask_separate_available = \
1120 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1121 .scan_type = { \
1122 .sign = 'u', \
1123 .realbits = 16, \
1124 .storagebits = 32, \
1125 .shift = 8, \
1126 .endianness = IIO_BE, \
1127 }, \
1128 }
1129
1130 #define AD74413R_ADC_VOLTAGE_CHANNEL \
1131 AD74413R_ADC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE) \
1132 | BIT(IIO_CHAN_INFO_OFFSET))
1133
1134 #define AD74413R_ADC_CURRENT_CHANNEL \
1135 AD74413R_ADC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE) \
1136 | BIT(IIO_CHAN_INFO_OFFSET))
1137
1138 static const struct iio_chan_spec ad74413r_voltage_output_channels[] = {
1139 AD74413R_DAC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE)),
1140 AD74413R_ADC_CURRENT_CHANNEL,
1141 };
1142
1143 static const struct iio_chan_spec ad74413r_current_output_channels[] = {
1144 AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)),
1145 AD74413R_ADC_VOLTAGE_CHANNEL,
1146 };
1147
1148 static const struct iio_chan_spec ad74413r_voltage_input_channels[] = {
1149 AD74413R_ADC_VOLTAGE_CHANNEL,
1150 };
1151
1152 static const struct iio_chan_spec ad74413r_current_input_channels[] = {
1153 AD74413R_ADC_CURRENT_CHANNEL,
1154 };
1155
1156 static const struct iio_chan_spec ad74413r_current_input_loop_channels[] = {
1157 AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)),
1158 AD74413R_ADC_CURRENT_CHANNEL,
1159 };
1160
1161 static const struct iio_chan_spec ad74413r_resistance_input_channels[] = {
1162 AD74413R_ADC_CHANNEL(IIO_RESISTANCE, BIT(IIO_CHAN_INFO_PROCESSED)),
1163 };
1164
1165 static const struct iio_chan_spec ad74413r_digital_input_channels[] = {
1166 AD74413R_ADC_VOLTAGE_CHANNEL,
1167 };
1168
1169 #define _AD74413R_CHANNELS(_channels) \
1170 { \
1171 .channels = _channels, \
1172 .num_channels = ARRAY_SIZE(_channels), \
1173 }
1174
1175 #define AD74413R_CHANNELS(name) \
1176 _AD74413R_CHANNELS(ad74413r_ ## name ## _channels)
1177
1178 static const struct ad74413r_channels ad74413r_channels_map[] = {
1179 [CH_FUNC_HIGH_IMPEDANCE] = AD74413R_CHANNELS(voltage_input),
1180 [CH_FUNC_VOLTAGE_OUTPUT] = AD74413R_CHANNELS(voltage_output),
1181 [CH_FUNC_CURRENT_OUTPUT] = AD74413R_CHANNELS(current_output),
1182 [CH_FUNC_VOLTAGE_INPUT] = AD74413R_CHANNELS(voltage_input),
1183 [CH_FUNC_CURRENT_INPUT_EXT_POWER] = AD74413R_CHANNELS(current_input),
1184 [CH_FUNC_CURRENT_INPUT_LOOP_POWER] = AD74413R_CHANNELS(current_input_loop),
1185 [CH_FUNC_RESISTANCE_INPUT] = AD74413R_CHANNELS(resistance_input),
1186 [CH_FUNC_DIGITAL_INPUT_LOGIC] = AD74413R_CHANNELS(digital_input),
1187 [CH_FUNC_DIGITAL_INPUT_LOOP_POWER] = AD74413R_CHANNELS(digital_input),
1188 [CH_FUNC_CURRENT_INPUT_EXT_POWER_HART] = AD74413R_CHANNELS(current_input),
1189 [CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART] = AD74413R_CHANNELS(current_input),
1190 };
1191
ad74413r_parse_channel_config(struct iio_dev * indio_dev,struct fwnode_handle * channel_node)1192 static int ad74413r_parse_channel_config(struct iio_dev *indio_dev,
1193 struct fwnode_handle *channel_node)
1194 {
1195 struct ad74413r_state *st = iio_priv(indio_dev);
1196 struct ad74413r_channel_config *config;
1197 u32 index;
1198 int ret;
1199
1200 ret = fwnode_property_read_u32(channel_node, "reg", &index);
1201 if (ret) {
1202 dev_err(st->dev, "Failed to read channel reg: %d\n", ret);
1203 return ret;
1204 }
1205
1206 if (index >= AD74413R_CHANNEL_MAX) {
1207 dev_err(st->dev, "Channel index %u is too large\n", index);
1208 return -EINVAL;
1209 }
1210
1211 config = &st->channel_configs[index];
1212 if (config->initialized) {
1213 dev_err(st->dev, "Channel %u already initialized\n", index);
1214 return -EINVAL;
1215 }
1216
1217 config->func = CH_FUNC_HIGH_IMPEDANCE;
1218 fwnode_property_read_u32(channel_node, "adi,ch-func", &config->func);
1219
1220 if (config->func < CH_FUNC_MIN || config->func > CH_FUNC_MAX) {
1221 dev_err(st->dev, "Invalid channel function %u\n", config->func);
1222 return -EINVAL;
1223 }
1224
1225 if (!st->chip_info->hart_support &&
1226 (config->func == CH_FUNC_CURRENT_INPUT_EXT_POWER_HART ||
1227 config->func == CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART)) {
1228 dev_err(st->dev, "Unsupported HART function %u\n", config->func);
1229 return -EINVAL;
1230 }
1231
1232 if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC ||
1233 config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER)
1234 st->num_comparator_gpios++;
1235
1236 config->gpo_comparator = fwnode_property_read_bool(channel_node,
1237 "adi,gpo-comparator");
1238
1239 fwnode_property_read_u32(channel_node, "drive-strength-microamp",
1240 &config->drive_strength);
1241
1242 if (!config->gpo_comparator)
1243 st->num_gpo_gpios++;
1244
1245 indio_dev->num_channels += ad74413r_channels_map[config->func].num_channels;
1246
1247 config->initialized = true;
1248
1249 return 0;
1250 }
1251
ad74413r_parse_channel_configs(struct iio_dev * indio_dev)1252 static int ad74413r_parse_channel_configs(struct iio_dev *indio_dev)
1253 {
1254 struct ad74413r_state *st = iio_priv(indio_dev);
1255 int ret;
1256
1257 device_for_each_child_node_scoped(st->dev, channel_node) {
1258 ret = ad74413r_parse_channel_config(indio_dev, channel_node);
1259 if (ret)
1260 return ret;
1261 }
1262
1263 return 0;
1264 }
1265
ad74413r_setup_channels(struct iio_dev * indio_dev)1266 static int ad74413r_setup_channels(struct iio_dev *indio_dev)
1267 {
1268 struct ad74413r_state *st = iio_priv(indio_dev);
1269 struct ad74413r_channel_config *config;
1270 const struct iio_chan_spec *chans;
1271 struct iio_chan_spec *channels;
1272 unsigned int i, num_chans, chan_i;
1273 int ret;
1274
1275 channels = devm_kcalloc(st->dev, sizeof(*channels),
1276 indio_dev->num_channels, GFP_KERNEL);
1277 if (!channels)
1278 return -ENOMEM;
1279
1280 indio_dev->channels = channels;
1281
1282 for (i = 0; i < AD74413R_CHANNEL_MAX; i++) {
1283 config = &st->channel_configs[i];
1284 chans = ad74413r_channels_map[config->func].channels;
1285 num_chans = ad74413r_channels_map[config->func].num_channels;
1286
1287 memcpy(channels, chans, num_chans * sizeof(*chans));
1288
1289 for (chan_i = 0; chan_i < num_chans; chan_i++) {
1290 struct iio_chan_spec *chan = &channels[chan_i];
1291
1292 chan->channel = i;
1293 if (chan->output)
1294 chan->scan_index = -1;
1295 else
1296 chan->scan_index = i;
1297 }
1298
1299 ret = ad74413r_set_channel_function(st, i, config->func);
1300 if (ret)
1301 return ret;
1302
1303 channels += num_chans;
1304 }
1305
1306 return 0;
1307 }
1308
ad74413r_setup_gpios(struct ad74413r_state * st)1309 static int ad74413r_setup_gpios(struct ad74413r_state *st)
1310 {
1311 struct ad74413r_channel_config *config;
1312 unsigned int comp_gpio_i = 0;
1313 unsigned int gpo_gpio_i = 0;
1314 unsigned int i;
1315 u8 gpo_config;
1316 u32 strength;
1317 int ret;
1318
1319 for (i = 0; i < AD74413R_CHANNEL_MAX; i++) {
1320 config = &st->channel_configs[i];
1321
1322 if (config->gpo_comparator) {
1323 gpo_config = AD74413R_GPO_CONFIG_COMPARATOR;
1324 } else {
1325 gpo_config = AD74413R_GPO_CONFIG_LOGIC;
1326 st->gpo_gpio_offsets[gpo_gpio_i++] = i;
1327 }
1328
1329 if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC ||
1330 config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER) {
1331 st->comp_gpio_offsets[comp_gpio_i++] = i;
1332
1333 strength = config->drive_strength;
1334 ret = ad74413r_set_comp_drive_strength(st, i, strength);
1335 if (ret)
1336 return ret;
1337 }
1338
1339 ret = ad74413r_set_gpo_config(st, i, gpo_config);
1340 if (ret)
1341 return ret;
1342 }
1343
1344 return 0;
1345 }
1346
ad74413r_probe(struct spi_device * spi)1347 static int ad74413r_probe(struct spi_device *spi)
1348 {
1349 struct ad74413r_state *st;
1350 struct iio_dev *indio_dev;
1351 int ret;
1352
1353 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1354 if (!indio_dev)
1355 return -ENOMEM;
1356
1357 st = iio_priv(indio_dev);
1358
1359 st->spi = spi;
1360 st->dev = &spi->dev;
1361 st->chip_info = spi_get_device_match_data(spi);
1362 if (!st->chip_info)
1363 return -EINVAL;
1364
1365 ret = devm_mutex_init(st->dev, &st->lock);
1366 if (ret)
1367 return ret;
1368
1369 init_completion(&st->adc_data_completion);
1370
1371 st->regmap = devm_regmap_init(st->dev, NULL, st,
1372 &ad74413r_regmap_config);
1373 if (IS_ERR(st->regmap))
1374 return PTR_ERR(st->regmap);
1375
1376 ret = devm_regulator_get_enable_read_voltage(st->dev, "refin");
1377 if (ret < 0)
1378 return dev_err_probe(st->dev, ret,
1379 "Failed to get refin regulator voltage\n");
1380 st->refin_reg_uv = ret;
1381
1382 st->sense_resistor_ohms = 100000000;
1383 device_property_read_u32(st->dev, "shunt-resistor-micro-ohms",
1384 &st->sense_resistor_ohms);
1385 st->sense_resistor_ohms /= 1000000;
1386
1387 st->trig = devm_iio_trigger_alloc(st->dev, "%s-dev%d",
1388 st->chip_info->name, iio_device_id(indio_dev));
1389 if (!st->trig)
1390 return -ENOMEM;
1391
1392 st->trig->ops = &ad74413r_trigger_ops;
1393 iio_trigger_set_drvdata(st->trig, st);
1394
1395 ret = devm_iio_trigger_register(st->dev, st->trig);
1396 if (ret)
1397 return ret;
1398
1399 indio_dev->name = st->chip_info->name;
1400 indio_dev->modes = INDIO_DIRECT_MODE;
1401 indio_dev->info = &ad74413r_info;
1402 indio_dev->trig = iio_trigger_get(st->trig);
1403
1404 ret = ad74413r_reset(st);
1405 if (ret)
1406 return ret;
1407
1408 ret = ad74413r_parse_channel_configs(indio_dev);
1409 if (ret)
1410 return ret;
1411
1412 ret = ad74413r_setup_channels(indio_dev);
1413 if (ret)
1414 return ret;
1415
1416 ret = ad74413r_setup_gpios(st);
1417 if (ret)
1418 return ret;
1419
1420 if (st->num_gpo_gpios) {
1421 st->gpo_gpiochip.owner = THIS_MODULE;
1422 st->gpo_gpiochip.label = st->chip_info->name;
1423 st->gpo_gpiochip.base = -1;
1424 st->gpo_gpiochip.ngpio = st->num_gpo_gpios;
1425 st->gpo_gpiochip.parent = st->dev;
1426 st->gpo_gpiochip.can_sleep = true;
1427 st->gpo_gpiochip.set = ad74413r_gpio_set;
1428 st->gpo_gpiochip.set_multiple = ad74413r_gpio_set_multiple;
1429 st->gpo_gpiochip.set_config = ad74413r_gpio_set_gpo_config;
1430 st->gpo_gpiochip.get_direction =
1431 ad74413r_gpio_get_gpo_direction;
1432
1433 ret = devm_gpiochip_add_data(st->dev, &st->gpo_gpiochip, st);
1434 if (ret)
1435 return ret;
1436 }
1437
1438 if (st->num_comparator_gpios) {
1439 st->comp_gpiochip.owner = THIS_MODULE;
1440 st->comp_gpiochip.label = st->chip_info->name;
1441 st->comp_gpiochip.base = -1;
1442 st->comp_gpiochip.ngpio = st->num_comparator_gpios;
1443 st->comp_gpiochip.parent = st->dev;
1444 st->comp_gpiochip.can_sleep = true;
1445 st->comp_gpiochip.get = ad74413r_gpio_get;
1446 st->comp_gpiochip.get_multiple = ad74413r_gpio_get_multiple;
1447 st->comp_gpiochip.set_config = ad74413r_gpio_set_comp_config;
1448 st->comp_gpiochip.get_direction =
1449 ad74413r_gpio_get_comp_direction;
1450
1451 ret = devm_gpiochip_add_data(st->dev, &st->comp_gpiochip, st);
1452 if (ret)
1453 return ret;
1454 }
1455
1456 ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
1457 if (ret)
1458 return ret;
1459
1460 ret = devm_request_irq(st->dev, spi->irq, ad74413r_adc_data_interrupt,
1461 0, st->chip_info->name, indio_dev);
1462 if (ret)
1463 return dev_err_probe(st->dev, ret, "Failed to request irq\n");
1464
1465 ret = devm_iio_triggered_buffer_setup(st->dev, indio_dev,
1466 &iio_pollfunc_store_time,
1467 &ad74413r_trigger_handler,
1468 &ad74413r_buffer_ops);
1469 if (ret)
1470 return ret;
1471
1472 return devm_iio_device_register(st->dev, indio_dev);
1473 }
1474
ad74413r_unregister_driver(struct spi_driver * spi)1475 static int ad74413r_unregister_driver(struct spi_driver *spi)
1476 {
1477 spi_unregister_driver(spi);
1478
1479 return 0;
1480 }
1481
ad74413r_register_driver(struct spi_driver * spi)1482 static int __init ad74413r_register_driver(struct spi_driver *spi)
1483 {
1484 crc8_populate_msb(ad74413r_crc8_table, AD74413R_CRC_POLYNOMIAL);
1485
1486 return spi_register_driver(spi);
1487 }
1488
1489 static const struct ad74413r_chip_info ad74412r_chip_info_data = {
1490 .hart_support = false,
1491 .name = "ad74412r",
1492 };
1493
1494 static const struct ad74413r_chip_info ad74413r_chip_info_data = {
1495 .hart_support = true,
1496 .name = "ad74413r",
1497 };
1498
1499 static const struct of_device_id ad74413r_dt_id[] = {
1500 {
1501 .compatible = "adi,ad74412r",
1502 .data = &ad74412r_chip_info_data,
1503 },
1504 {
1505 .compatible = "adi,ad74413r",
1506 .data = &ad74413r_chip_info_data,
1507 },
1508 {},
1509 };
1510 MODULE_DEVICE_TABLE(of, ad74413r_dt_id);
1511
1512 static const struct spi_device_id ad74413r_spi_id[] = {
1513 { .name = "ad74412r", .driver_data = (kernel_ulong_t)&ad74412r_chip_info_data },
1514 { .name = "ad74413r", .driver_data = (kernel_ulong_t)&ad74413r_chip_info_data },
1515 {}
1516 };
1517 MODULE_DEVICE_TABLE(spi, ad74413r_spi_id);
1518
1519 static struct spi_driver ad74413r_driver = {
1520 .driver = {
1521 .name = "ad74413r",
1522 .of_match_table = ad74413r_dt_id,
1523 },
1524 .probe = ad74413r_probe,
1525 .id_table = ad74413r_spi_id,
1526 };
1527
1528 module_driver(ad74413r_driver,
1529 ad74413r_register_driver,
1530 ad74413r_unregister_driver);
1531
1532 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
1533 MODULE_DESCRIPTION("Analog Devices AD74413R ADDAC");
1534 MODULE_LICENSE("GPL v2");
1535