1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*******************************************************************************
3 STMMAC Common Header File
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9 *******************************************************************************/
10
11 #ifndef __COMMON_H__
12 #define __COMMON_H__
13
14 #include <linux/etherdevice.h>
15 #include <linux/netdevice.h>
16 #include <linux/stmmac.h>
17 #include <linux/phy.h>
18 #include <linux/pcs/pcs-xpcs.h>
19 #include <linux/module.h>
20 #if IS_ENABLED(CONFIG_VLAN_8021Q)
21 #define STMMAC_VLAN_TAG_USED
22 #include <linux/if_vlan.h>
23 #endif
24
25 #include "descs.h"
26 #include "hwif.h"
27 #include "mmc.h"
28
29 #define DWMAC_SNPSVER GENMASK_U32(7, 0)
30 #define DWMAC_USERVER GENMASK_U32(15, 8)
31
32 /* Synopsys Core versions */
33 #define DWMAC_CORE_3_40 0x34
34 #define DWMAC_CORE_3_50 0x35
35 #define DWMAC_CORE_3_70 0x37
36 #define DWMAC_CORE_4_00 0x40
37 #define DWMAC_CORE_4_10 0x41
38 #define DWMAC_CORE_5_00 0x50
39 #define DWMAC_CORE_5_10 0x51
40 #define DWMAC_CORE_5_20 0x52
41 #define DWXGMAC_CORE_2_10 0x21
42 #define DWXGMAC_CORE_2_20 0x22
43 #define DWXLGMAC_CORE_2_00 0x20
44
45 /* Device ID */
46 #define DWXGMAC_ID 0x76
47 #define DWXLGMAC_ID 0x27
48
dwmac_is_xmac(enum dwmac_core_type core_type)49 static inline bool dwmac_is_xmac(enum dwmac_core_type core_type)
50 {
51 return core_type == DWMAC_CORE_GMAC4 || core_type == DWMAC_CORE_XGMAC;
52 }
53
54 #define STMMAC_CHAN0 0 /* Always supported and default for all chips */
55
56 /* TX and RX Descriptor Length, these need to be power of two.
57 * TX descriptor length less than 64 may cause transmit queue timed out error.
58 * RX descriptor length less than 64 may cause inconsistent Rx chain error.
59 */
60 #define DMA_MIN_TX_SIZE 64
61 #define DMA_MAX_TX_SIZE 1024
62 #define DMA_DEFAULT_TX_SIZE 512
63 #define DMA_MIN_RX_SIZE 64
64 #define DMA_MAX_RX_SIZE 1024
65 #define DMA_DEFAULT_RX_SIZE 512
66 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
67
68 #undef FRAME_FILTER_DEBUG
69 /* #define FRAME_FILTER_DEBUG */
70
71 struct stmmac_q_tx_stats {
72 u64_stats_t tx_bytes;
73 u64_stats_t tx_set_ic_bit;
74 u64_stats_t tx_tso_frames;
75 u64_stats_t tx_tso_nfrags;
76 };
77
78 struct stmmac_napi_tx_stats {
79 u64_stats_t tx_packets;
80 u64_stats_t tx_pkt_n;
81 u64_stats_t poll;
82 u64_stats_t tx_clean;
83 u64_stats_t tx_set_ic_bit;
84 };
85
86 struct stmmac_txq_stats {
87 /* Updates protected by tx queue lock. */
88 struct u64_stats_sync q_syncp;
89 struct stmmac_q_tx_stats q;
90
91 /* Updates protected by NAPI poll logic. */
92 struct u64_stats_sync napi_syncp;
93 struct stmmac_napi_tx_stats napi;
94 } ____cacheline_aligned_in_smp;
95
96 struct stmmac_napi_rx_stats {
97 u64_stats_t rx_bytes;
98 u64_stats_t rx_packets;
99 u64_stats_t rx_pkt_n;
100 u64_stats_t poll;
101 };
102
103 struct stmmac_rxq_stats {
104 /* Updates protected by NAPI poll logic. */
105 struct u64_stats_sync napi_syncp;
106 struct stmmac_napi_rx_stats napi;
107 } ____cacheline_aligned_in_smp;
108
109 /* Updates on each CPU protected by not allowing nested irqs. */
110 struct stmmac_pcpu_stats {
111 struct u64_stats_sync syncp;
112 u64_stats_t rx_normal_irq_n[MTL_MAX_RX_QUEUES];
113 u64_stats_t tx_normal_irq_n[MTL_MAX_TX_QUEUES];
114 };
115
116 /* Extra statistic and debug information exposed by ethtool */
117 struct stmmac_extra_stats {
118 /* Transmit errors */
119 unsigned long tx_underflow ____cacheline_aligned;
120 unsigned long tx_carrier;
121 unsigned long tx_losscarrier;
122 unsigned long vlan_tag;
123 unsigned long tx_deferred;
124 unsigned long tx_vlan;
125 unsigned long tx_jabber;
126 unsigned long tx_frame_flushed;
127 unsigned long tx_payload_error;
128 unsigned long tx_ip_header_error;
129 unsigned long tx_collision;
130 /* Receive errors */
131 unsigned long rx_desc;
132 unsigned long sa_filter_fail;
133 unsigned long overflow_error;
134 unsigned long ipc_csum_error;
135 unsigned long rx_collision;
136 unsigned long rx_crc_errors;
137 unsigned long dribbling_bit;
138 unsigned long rx_length;
139 unsigned long rx_mii;
140 unsigned long rx_multicast;
141 unsigned long rx_gmac_overflow;
142 unsigned long rx_watchdog;
143 unsigned long da_rx_filter_fail;
144 unsigned long sa_rx_filter_fail;
145 unsigned long rx_missed_cntr;
146 unsigned long rx_overflow_cntr;
147 unsigned long rx_vlan;
148 unsigned long rx_split_hdr_pkt_n;
149 /* Tx/Rx IRQ error info */
150 unsigned long tx_undeflow_irq;
151 unsigned long tx_process_stopped_irq;
152 unsigned long tx_jabber_irq;
153 unsigned long rx_overflow_irq;
154 unsigned long rx_buf_unav_irq;
155 unsigned long rx_process_stopped_irq;
156 unsigned long rx_watchdog_irq;
157 unsigned long tx_early_irq;
158 unsigned long fatal_bus_error_irq;
159 /* Tx/Rx IRQ Events */
160 unsigned long rx_early_irq;
161 unsigned long threshold;
162 unsigned long irq_receive_pmt_irq_n;
163 /* MMC info */
164 unsigned long mmc_tx_irq_n;
165 unsigned long mmc_rx_irq_n;
166 unsigned long mmc_rx_csum_offload_irq_n;
167 /* EEE */
168 unsigned long irq_tx_path_in_lpi_mode_n;
169 unsigned long irq_tx_path_exit_lpi_mode_n;
170 unsigned long irq_rx_path_in_lpi_mode_n;
171 unsigned long irq_rx_path_exit_lpi_mode_n;
172 unsigned long phy_eee_wakeup_error_n;
173 /* Extended RDES status */
174 unsigned long ip_hdr_err;
175 unsigned long ip_payload_err;
176 unsigned long ip_csum_bypassed;
177 unsigned long ipv4_pkt_rcvd;
178 unsigned long ipv6_pkt_rcvd;
179 unsigned long no_ptp_rx_msg_type_ext;
180 unsigned long ptp_rx_msg_type_sync;
181 unsigned long ptp_rx_msg_type_follow_up;
182 unsigned long ptp_rx_msg_type_delay_req;
183 unsigned long ptp_rx_msg_type_delay_resp;
184 unsigned long ptp_rx_msg_type_pdelay_req;
185 unsigned long ptp_rx_msg_type_pdelay_resp;
186 unsigned long ptp_rx_msg_type_pdelay_follow_up;
187 unsigned long ptp_rx_msg_type_announce;
188 unsigned long ptp_rx_msg_type_management;
189 unsigned long ptp_rx_msg_pkt_reserved_type;
190 unsigned long ptp_frame_type;
191 unsigned long ptp_ver;
192 unsigned long timestamp_dropped;
193 unsigned long av_pkt_rcvd;
194 unsigned long av_tagged_pkt_rcvd;
195 unsigned long vlan_tag_priority_val;
196 unsigned long l3_filter_match;
197 unsigned long l4_filter_match;
198 unsigned long l3_l4_filter_no_match;
199 /* PCS */
200 unsigned long irq_pcs_ane_n;
201 unsigned long irq_pcs_link_n;
202 unsigned long irq_rgmii_n;
203 /* debug register */
204 unsigned long mtl_tx_status_fifo_full;
205 unsigned long mtl_tx_fifo_not_empty;
206 unsigned long mmtl_fifo_ctrl;
207 unsigned long mtl_tx_fifo_read_ctrl_write;
208 unsigned long mtl_tx_fifo_read_ctrl_wait;
209 unsigned long mtl_tx_fifo_read_ctrl_read;
210 unsigned long mtl_tx_fifo_read_ctrl_idle;
211 unsigned long mac_tx_in_pause;
212 unsigned long mac_tx_frame_ctrl_xfer;
213 unsigned long mac_tx_frame_ctrl_idle;
214 unsigned long mac_tx_frame_ctrl_wait;
215 unsigned long mac_tx_frame_ctrl_pause;
216 unsigned long mac_gmii_tx_proto_engine;
217 unsigned long mtl_rx_fifo_fill_level_full;
218 unsigned long mtl_rx_fifo_fill_above_thresh;
219 unsigned long mtl_rx_fifo_fill_below_thresh;
220 unsigned long mtl_rx_fifo_fill_level_empty;
221 unsigned long mtl_rx_fifo_read_ctrl_flush;
222 unsigned long mtl_rx_fifo_read_ctrl_read_data;
223 unsigned long mtl_rx_fifo_read_ctrl_status;
224 unsigned long mtl_rx_fifo_read_ctrl_idle;
225 unsigned long mtl_rx_fifo_ctrl_active;
226 unsigned long mac_rx_frame_ctrl_fifo;
227 unsigned long mac_gmii_rx_proto_engine;
228 /* EST */
229 unsigned long mtl_est_cgce;
230 unsigned long mtl_est_hlbs;
231 unsigned long mtl_est_hlbf;
232 unsigned long mtl_est_btre;
233 unsigned long mtl_est_btrlm;
234 unsigned long max_sdu_txq_drop[MTL_MAX_TX_QUEUES];
235 unsigned long mtl_est_txq_hlbf[MTL_MAX_TX_QUEUES];
236 unsigned long mtl_est_txq_hlbs[MTL_MAX_TX_QUEUES];
237 /* per queue statistics */
238 struct stmmac_txq_stats txq_stats[MTL_MAX_TX_QUEUES];
239 struct stmmac_rxq_stats rxq_stats[MTL_MAX_RX_QUEUES];
240 struct stmmac_pcpu_stats __percpu *pcpu_stats;
241 unsigned long rx_dropped;
242 unsigned long rx_errors;
243 unsigned long tx_dropped;
244 unsigned long tx_errors;
245 };
246
247 /* Safety Feature statistics exposed by ethtool */
248 struct stmmac_safety_stats {
249 unsigned long mac_errors[32];
250 unsigned long mtl_errors[32];
251 unsigned long dma_errors[32];
252 unsigned long dma_dpp_errors[32];
253 };
254
255 /* Number of fields in Safety Stats */
256 #define STMMAC_SAFETY_FEAT_SIZE \
257 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
258
259 /* CSR Frequency Access Defines*/
260 #define CSR_F_35M 35000000
261 #define CSR_F_60M 60000000
262 #define CSR_F_100M 100000000
263 #define CSR_F_150M 150000000
264 #define CSR_F_250M 250000000
265 #define CSR_F_300M 300000000
266 #define CSR_F_500M 500000000
267 #define CSR_F_800M 800000000
268
269 #define MAC_CSR_H_FRQ_MASK 0x20
270
271 #define HASH_TABLE_SIZE 64
272 #define PAUSE_TIME 0xffff
273
274 /* Flow Control defines */
275 #define FLOW_OFF 0
276 #define FLOW_RX 1
277 #define FLOW_TX 2
278 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
279
280 /* PCS defines */
281 #define STMMAC_PCS_SGMII (1 << 1)
282
283 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
284
285 /* DMA HW feature register fields */
286 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
287 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
288 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
289 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
290 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
291 #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
292 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
293 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
294 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
295 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
296 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
297 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
298 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
299 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
300 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
301 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
302 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
303 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
304 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
305 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
306 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
307 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
308 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
309 /* Timestamping with Internal System Time */
310 #define DMA_HW_FEAT_INTTSEN 0x02000000
311 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
312 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
313 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
314 #define DEFAULT_DMA_PBL 8
315
316 /* phy_intf_sel_i and ACTPHYIF encodings */
317 #define PHY_INTF_SEL_GMII_MII 0
318 #define PHY_INTF_SEL_RGMII 1
319 #define PHY_INTF_SEL_SGMII 2
320 #define PHY_INTF_SEL_TBI 3
321 #define PHY_INTF_SEL_RMII 4
322 #define PHY_INTF_SEL_RTBI 5
323 #define PHY_INTF_SEL_SMII 6
324 #define PHY_INTF_SEL_REVMII 7
325
326 /* XGMAC uses a different encoding - from the AgileX5 documentation */
327 #define PHY_INTF_GMII 0
328 #define PHY_INTF_RGMII 1
329
330 /* MSI defines */
331 #define STMMAC_MSI_VEC_MAX 32
332
333 /* PCS status and mask defines */
334 #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
335 #define PCS_LINK_IRQ BIT(1) /* PCS Link */
336 #define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
337
338 /* Max/Min RI Watchdog Timer count value */
339 #define MAX_DMA_RIWT 0xff
340 #define MIN_DMA_RIWT 0x10
341 #define DEF_DMA_RIWT 0xa0
342 /* Tx coalesce parameters */
343 #define STMMAC_COAL_TX_TIMER 5000
344 #define STMMAC_MAX_COAL_TX_TICK 100000
345 #define STMMAC_TX_MAX_FRAMES 256
346 #define STMMAC_TX_FRAMES 25
347 #define STMMAC_RX_FRAMES 0
348
349 /* Packets types */
350 enum packets_types {
351 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
352 PACKET_PTPQ = 0x2, /* PTP Packets */
353 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
354 PACKET_UPQ = 0x4, /* Untagged Packets */
355 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
356 };
357
358 /* Rx IPC status */
359 enum rx_frame_status {
360 good_frame = 0x0,
361 discard_frame = 0x1,
362 csum_none = 0x2,
363 llc_snap = 0x4,
364 dma_own = 0x8,
365 rx_not_ls = 0x10,
366 };
367
368 /* Tx status */
369 enum tx_frame_status {
370 tx_done = 0x0,
371 tx_not_ls = 0x1,
372 tx_err = 0x2,
373 tx_dma_own = 0x4,
374 tx_err_bump_tc = 0x8,
375 };
376
377 enum dma_irq_status {
378 tx_hard_error = 0x1,
379 tx_hard_error_bump_tc = 0x2,
380 handle_rx = 0x4,
381 handle_tx = 0x8,
382 };
383
384 enum dma_irq_dir {
385 DMA_DIR_RX = 0x1,
386 DMA_DIR_TX = 0x2,
387 DMA_DIR_RXTX = 0x3,
388 };
389
390 enum request_irq_err {
391 REQ_IRQ_ERR_ALL,
392 REQ_IRQ_ERR_TX,
393 REQ_IRQ_ERR_RX,
394 REQ_IRQ_ERR_SFTY,
395 REQ_IRQ_ERR_SFTY_UE,
396 REQ_IRQ_ERR_SFTY_CE,
397 REQ_IRQ_ERR_WOL,
398 REQ_IRQ_ERR_MAC,
399 REQ_IRQ_ERR_NO,
400 };
401
402 /* EEE and LPI defines */
403 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
404 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
405 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
406 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
407
408 /* FPE defines */
409 #define FPE_EVENT_UNKNOWN 0
410 #define FPE_EVENT_TRSP BIT(0)
411 #define FPE_EVENT_TVER BIT(1)
412 #define FPE_EVENT_RRSP BIT(2)
413 #define FPE_EVENT_RVER BIT(3)
414
415 #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
416
417 /* DMA HW capabilities */
418 struct dma_features {
419 unsigned int mbps_10_100;
420 unsigned int mbps_1000;
421 unsigned int half_duplex;
422 unsigned int hash_filter;
423 unsigned int multi_addr;
424 unsigned int pcs;
425 unsigned int sma_mdio;
426 unsigned int pmt_remote_wake_up;
427 unsigned int pmt_magic_frame;
428 unsigned int rmon;
429 /* IEEE 1588-2002 */
430 unsigned int time_stamp;
431 /* IEEE 1588-2008 */
432 unsigned int atime_stamp;
433 /* 802.3az - Energy-Efficient Ethernet (EEE) */
434 unsigned int eee;
435 unsigned int av;
436 unsigned int hash_tb_sz;
437 unsigned int tsoen;
438 /* TX and RX csum */
439 unsigned int tx_coe;
440 unsigned int rx_coe;
441 unsigned int rx_coe_type1;
442 unsigned int rx_coe_type2;
443 unsigned int rxfifo_over_2048;
444 /* TX and RX number of channels */
445 unsigned int number_rx_channel;
446 unsigned int number_tx_channel;
447 /* TX and RX number of queues */
448 unsigned int number_rx_queues;
449 unsigned int number_tx_queues;
450 /* PPS output */
451 unsigned int pps_out_num;
452 /* Number of Traffic Classes */
453 unsigned int numtc;
454 /* DCB Feature Enable */
455 unsigned int dcben;
456 /* IEEE 1588 High Word Register Enable */
457 unsigned int advthword;
458 /* PTP Offload Enable */
459 unsigned int ptoen;
460 /* One-Step Timestamping Enable */
461 unsigned int osten;
462 /* Priority-Based Flow Control Enable */
463 unsigned int pfcen;
464 /* Alternate (enhanced) DESC mode */
465 unsigned int enh_desc;
466 /* TX and RX FIFO sizes */
467 unsigned int tx_fifo_size;
468 unsigned int rx_fifo_size;
469 /* Automotive Safety Package */
470 unsigned int asp;
471 /* RX Parser */
472 unsigned int frpsel;
473 unsigned int frpbs;
474 unsigned int frpes;
475 unsigned int addr64;
476 unsigned int host_dma_width;
477 unsigned int rssen;
478 unsigned int vlhash;
479 unsigned int sphen;
480 unsigned int vlins;
481 unsigned int dvlan;
482 unsigned int l3l4fnum;
483 unsigned int arpoffsel;
484 /* One Step for PTP over UDP/IP Feature Enable */
485 unsigned int pou_ost_en;
486 /* Tx Timestamp FIFO Depth */
487 unsigned int ttsfd;
488 /* Queue/Channel-Based VLAN tag insertion on Tx */
489 unsigned int cbtisel;
490 /* Supported Parallel Instruction Processor Engines */
491 unsigned int frppipe_num;
492 /* Number of Extended VLAN Tag Filters */
493 unsigned int nrvf_num;
494 /* TSN Features */
495 unsigned int estwid;
496 unsigned int estdep;
497 unsigned int estsel;
498 unsigned int fpesel;
499 unsigned int tbssel;
500 /* Number of DMA channels enabled for TBS */
501 unsigned int tbs_ch_num;
502 /* Per-Stream Filtering Enable */
503 unsigned int sgfsel;
504 /* Numbers of Auxiliary Snapshot Inputs */
505 unsigned int aux_snapshot_n;
506 /* Timestamp System Time Source */
507 unsigned int tssrc;
508 /* Enhanced DMA Enable */
509 unsigned int edma;
510 /* Different Descriptor Cache Enable */
511 unsigned int ediffc;
512 /* VxLAN/NVGRE Enable */
513 unsigned int vxn;
514 /* Debug Memory Interface Enable */
515 unsigned int dbgmem;
516 /* Number of Policing Counters */
517 unsigned int pcsel;
518 /* Active PHY interface, PHY_INTF_SEL_xxx */
519 u8 actphyif;
520 };
521
522 /* RX Buffer size must be multiple of 4/8/16 bytes */
523 #define BUF_SIZE_16KiB 16368
524 #define BUF_SIZE_8KiB 8188
525 #define BUF_SIZE_4KiB 4096
526 #define BUF_SIZE_2KiB 2048
527
528 /* Power Down and WOL */
529 #define PMT_NOT_SUPPORTED 0
530 #define PMT_SUPPORTED 1
531
532 /* Common MAC defines */
533 #define MAC_CTRL_REG 0x00000000 /* MAC Control */
534 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
535 #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
536
537 /* Default LPI timers */
538 #define STMMAC_DEFAULT_LIT_LS 0x3E8
539 #define STMMAC_DEFAULT_TWT_LS 0x1E
540 #define STMMAC_ET_MAX 0xFFFFF
541
542 /* Common LPI register bits */
543 #define LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable, gmac4, xgmac2 only */
544 #define LPI_CTRL_STATUS_LPIATE BIT(20) /* LPI Timer Enable, gmac4 only */
545 #define LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */
546 #define LPI_CTRL_STATUS_PLSEN BIT(18) /* Enable PHY Link Status */
547 #define LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */
548 #define LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */
549 #define LPI_CTRL_STATUS_RLPIST BIT(9) /* Receive LPI state, gmac1000 only? */
550 #define LPI_CTRL_STATUS_TLPIST BIT(8) /* Transmit LPI state, gmac1000 only? */
551 #define LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */
552 #define LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */
553 #define LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */
554 #define LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */
555
556 /* Common definitions for AXI Master Bus Mode */
557 #define DMA_AXI_AAL BIT(12)
558 #define DMA_AXI_BLEN256 BIT(7)
559 #define DMA_AXI_BLEN128 BIT(6)
560 #define DMA_AXI_BLEN64 BIT(5)
561 #define DMA_AXI_BLEN32 BIT(4)
562 #define DMA_AXI_BLEN16 BIT(3)
563 #define DMA_AXI_BLEN8 BIT(2)
564 #define DMA_AXI_BLEN4 BIT(1)
565 #define DMA_AXI_BLEN_MASK GENMASK(7, 1)
566
567 void stmmac_axi_blen_to_mask(u32 *regval, const u32 *blen, size_t len);
568
569 #define STMMAC_CHAIN_MODE 0x1
570 #define STMMAC_RING_MODE 0x2
571
572 #define JUMBO_LEN 9000
573
574 /* Receive Side Scaling */
575 #define STMMAC_RSS_HASH_KEY_SIZE 40
576 #define STMMAC_RSS_MAX_TABLE_SIZE 256
577
578 /* VLAN */
579 #define STMMAC_VLAN_NONE 0x0
580 #define STMMAC_VLAN_REMOVE 0x1
581 #define STMMAC_VLAN_INSERT 0x2
582 #define STMMAC_VLAN_REPLACE 0x3
583
584 struct mac_device_info;
585
586 struct mac_link {
587 u32 caps;
588 u32 speed_mask;
589 u32 speed10;
590 u32 speed100;
591 u32 speed1000;
592 u32 speed2500;
593 u32 duplex;
594 struct {
595 u32 speed2500;
596 u32 speed5000;
597 u32 speed10000;
598 } xgmii;
599 struct {
600 u32 speed25000;
601 u32 speed40000;
602 u32 speed50000;
603 u32 speed100000;
604 } xlgmii;
605 };
606
607 struct mii_regs {
608 unsigned int addr; /* MII Address */
609 unsigned int data; /* MII Data */
610 unsigned int addr_shift; /* MII address shift */
611 unsigned int reg_shift; /* MII reg shift */
612 unsigned int addr_mask; /* MII address mask */
613 unsigned int reg_mask; /* MII reg mask */
614 unsigned int clk_csr_shift;
615 unsigned int clk_csr_mask;
616 };
617
618 struct mac_device_info {
619 const struct stmmac_ops *mac;
620 const struct stmmac_desc_ops *desc;
621 const struct stmmac_dma_ops *dma;
622 const struct stmmac_mode_ops *mode;
623 const struct stmmac_hwtimestamp *ptp;
624 const struct stmmac_tc_ops *tc;
625 const struct stmmac_mmc_ops *mmc;
626 const struct stmmac_est_ops *est;
627 const struct stmmac_vlan_ops *vlan;
628 struct dw_xpcs *xpcs;
629 struct phylink_pcs *phylink_pcs;
630 struct mii_regs mii; /* MII register Addresses */
631 struct mac_link link;
632 void __iomem *pcsr; /* vpointer to device CSRs */
633 unsigned int multicast_filter_bins;
634 unsigned int unicast_filter_entries;
635 unsigned int mcast_bits_log2;
636 unsigned int rx_csum;
637 unsigned int pcs;
638 unsigned int xlgmac;
639 unsigned int num_vlan;
640 u32 vlan_filter[32];
641 bool vlan_fail_q_en;
642 u8 vlan_fail_q;
643 bool hw_vlan_en;
644 bool reverse_sgmii_enable;
645
646 /* This spinlock protects read-modify-write of the interrupt
647 * mask/enable registers.
648 */
649 spinlock_t irq_ctrl_lock;
650 };
651
652 struct stmmac_rx_routing {
653 u32 reg_mask;
654 u32 reg_shift;
655 };
656
657 int dwmac100_setup(struct stmmac_priv *priv);
658 int dwmac1000_setup(struct stmmac_priv *priv);
659 int dwmac4_setup(struct stmmac_priv *priv);
660 int dwxgmac2_setup(struct stmmac_priv *priv);
661 int dwxlgmac2_setup(struct stmmac_priv *priv);
662
663 void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
664 unsigned int high, unsigned int low);
665 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
666 unsigned int high, unsigned int low);
667 void stmmac_set_mac(void __iomem *ioaddr, bool enable);
668
669 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
670 unsigned int high, unsigned int low);
671 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
672 unsigned int high, unsigned int low);
673 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
674
675 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
676
677 #endif /* __COMMON_H__ */
678