1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2023 Intel Corporation
4 */
5
6 #include "xe_reg_whitelist.h"
7
8 #include "regs/xe_engine_regs.h"
9 #include "regs/xe_gt_regs.h"
10 #include "regs/xe_oa_regs.h"
11 #include "regs/xe_regs.h"
12 #include "xe_gt_types.h"
13 #include "xe_gt_printk.h"
14 #include "xe_platform_types.h"
15 #include "xe_reg_sr.h"
16 #include "xe_rtp.h"
17 #include "xe_step.h"
18
19 #undef XE_REG_MCR
20 #define XE_REG_MCR(...) XE_REG(__VA_ARGS__, .mcr = 1)
21
match_not_render(const struct xe_gt * gt,const struct xe_hw_engine * hwe)22 static bool match_not_render(const struct xe_gt *gt,
23 const struct xe_hw_engine *hwe)
24 {
25 return hwe->class != XE_ENGINE_CLASS_RENDER;
26 }
27
28 static const struct xe_rtp_entry_sr register_whitelist[] = {
29 { XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865"),
30 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
31 XE_RTP_ACTIONS(WHITELIST(PS_INVOCATION_COUNT,
32 RING_FORCE_TO_NONPRIV_ACCESS_RD |
33 RING_FORCE_TO_NONPRIV_RANGE_4))
34 },
35 { XE_RTP_NAME("1508744258, 14012131227, 1808121037"),
36 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
37 XE_RTP_ACTIONS(WHITELIST(COMMON_SLICE_CHICKEN1, 0))
38 },
39 { XE_RTP_NAME("1806527549"),
40 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
41 XE_RTP_ACTIONS(WHITELIST(HIZ_CHICKEN, 0))
42 },
43 { XE_RTP_NAME("allow_read_ctx_timestamp"),
44 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260), FUNC(match_not_render)),
45 XE_RTP_ACTIONS(WHITELIST(RING_CTX_TIMESTAMP(0),
46 RING_FORCE_TO_NONPRIV_ACCESS_RD,
47 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
48 },
49 { XE_RTP_NAME("16014440446"),
50 XE_RTP_RULES(PLATFORM(PVC)),
51 XE_RTP_ACTIONS(WHITELIST(XE_REG(0x4400),
52 RING_FORCE_TO_NONPRIV_DENY |
53 RING_FORCE_TO_NONPRIV_RANGE_64),
54 WHITELIST(XE_REG(0x4500),
55 RING_FORCE_TO_NONPRIV_DENY |
56 RING_FORCE_TO_NONPRIV_RANGE_64))
57 },
58 { XE_RTP_NAME("16017236439"),
59 XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY)),
60 XE_RTP_ACTIONS(WHITELIST(BCS_SWCTRL(0),
61 RING_FORCE_TO_NONPRIV_DENY,
62 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
63 },
64 { XE_RTP_NAME("16020183090"),
65 XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
66 ENGINE_CLASS(RENDER)),
67 XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0))
68 },
69 { XE_RTP_NAME("oa_reg_render"),
70 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
71 ENGINE_CLASS(RENDER)),
72 XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER,
73 RING_FORCE_TO_NONPRIV_ACCESS_RW),
74 WHITELIST(OAG_OASTATUS,
75 RING_FORCE_TO_NONPRIV_ACCESS_RD),
76 WHITELIST(OAG_OAHEADPTR,
77 RING_FORCE_TO_NONPRIV_ACCESS_RD |
78 RING_FORCE_TO_NONPRIV_RANGE_4))
79 },
80 { XE_RTP_NAME("oa_reg_compute"),
81 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
82 ENGINE_CLASS(COMPUTE)),
83 XE_RTP_ACTIONS(WHITELIST(OAG_MMIOTRIGGER,
84 RING_FORCE_TO_NONPRIV_ACCESS_RW),
85 WHITELIST(OAG_OASTATUS,
86 RING_FORCE_TO_NONPRIV_ACCESS_RD),
87 WHITELIST(OAG_OAHEADPTR,
88 RING_FORCE_TO_NONPRIV_ACCESS_RD |
89 RING_FORCE_TO_NONPRIV_RANGE_4))
90 },
91 };
92
whitelist_apply_to_hwe(struct xe_hw_engine * hwe)93 static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
94 {
95 struct xe_reg_sr *sr = &hwe->reg_whitelist;
96 struct xe_reg_sr_entry *entry;
97 struct drm_printer p;
98 unsigned long reg;
99 unsigned int slot;
100
101 xe_gt_dbg(hwe->gt, "Add %s whitelist to engine\n", sr->name);
102 p = xe_gt_dbg_printer(hwe->gt);
103
104 slot = 0;
105 xa_for_each(&sr->xa, reg, entry) {
106 struct xe_reg_sr_entry hwe_entry = {
107 .reg = RING_FORCE_TO_NONPRIV(hwe->mmio_base, slot),
108 .set_bits = entry->reg.addr | entry->set_bits,
109 .clr_bits = ~0u,
110 .read_mask = entry->read_mask,
111 };
112
113 if (slot == RING_MAX_NONPRIV_SLOTS) {
114 xe_gt_err(hwe->gt,
115 "hwe %s: maximum register whitelist slots (%d) reached, refusing to add more\n",
116 hwe->name, RING_MAX_NONPRIV_SLOTS);
117 break;
118 }
119
120 xe_reg_whitelist_print_entry(&p, 0, reg, entry);
121 xe_reg_sr_add(&hwe->reg_sr, &hwe_entry, hwe->gt);
122
123 slot++;
124 }
125 }
126
127 /**
128 * xe_reg_whitelist_process_engine - process table of registers to whitelist
129 * @hwe: engine instance to process whitelist for
130 *
131 * Process wwhitelist table for this platform, saving in @hwe all the
132 * registers that need to be whitelisted by the hardware so they can be accessed
133 * by userspace.
134 */
xe_reg_whitelist_process_engine(struct xe_hw_engine * hwe)135 void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
136 {
137 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
138
139 xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist),
140 &hwe->reg_whitelist);
141 whitelist_apply_to_hwe(hwe);
142 }
143
144 /**
145 * xe_reg_whitelist_print_entry - print one whitelist entry
146 * @p: DRM printer
147 * @indent: indent level
148 * @reg: register allowed/denied
149 * @entry: save-restore entry
150 *
151 * Print details about the entry added to allow/deny access
152 */
xe_reg_whitelist_print_entry(struct drm_printer * p,unsigned int indent,u32 reg,struct xe_reg_sr_entry * entry)153 void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent,
154 u32 reg, struct xe_reg_sr_entry *entry)
155 {
156 u32 val = entry->set_bits;
157 const char *access_str = "(invalid)";
158 unsigned int range_bit = 2;
159 u32 range_start, range_end;
160 bool deny;
161
162 deny = val & RING_FORCE_TO_NONPRIV_DENY;
163
164 switch (val & RING_FORCE_TO_NONPRIV_RANGE_MASK) {
165 case RING_FORCE_TO_NONPRIV_RANGE_4:
166 range_bit = 4;
167 break;
168 case RING_FORCE_TO_NONPRIV_RANGE_16:
169 range_bit = 6;
170 break;
171 case RING_FORCE_TO_NONPRIV_RANGE_64:
172 range_bit = 8;
173 break;
174 }
175
176 range_start = reg & REG_GENMASK(25, range_bit);
177 range_end = range_start | REG_GENMASK(range_bit, 0);
178
179 switch (val & RING_FORCE_TO_NONPRIV_ACCESS_MASK) {
180 case RING_FORCE_TO_NONPRIV_ACCESS_RW:
181 access_str = "rw";
182 break;
183 case RING_FORCE_TO_NONPRIV_ACCESS_RD:
184 access_str = "read";
185 break;
186 case RING_FORCE_TO_NONPRIV_ACCESS_WR:
187 access_str = "write";
188 break;
189 }
190
191 drm_printf_indent(p, indent, "REG[0x%x-0x%x]: %s %s access\n",
192 range_start, range_end,
193 deny ? "deny" : "allow",
194 access_str);
195 }
196
197 /**
198 * xe_reg_whitelist_dump - print all whitelist entries
199 * @sr: Save/restore entries
200 * @p: DRM printer
201 */
xe_reg_whitelist_dump(struct xe_reg_sr * sr,struct drm_printer * p)202 void xe_reg_whitelist_dump(struct xe_reg_sr *sr, struct drm_printer *p)
203 {
204 struct xe_reg_sr_entry *entry;
205 unsigned long reg;
206
207 if (!sr->name || xa_empty(&sr->xa))
208 return;
209
210 drm_printf(p, "%s\n", sr->name);
211 xa_for_each(&sr->xa, reg, entry)
212 xe_reg_whitelist_print_entry(p, 1, reg, entry);
213 }
214