1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
3
4 #ifndef _A6XX_GMU_H_
5 #define _A6XX_GMU_H_
6
7 #include <linux/completion.h>
8 #include <linux/iopoll.h>
9 #include <linux/interrupt.h>
10 #include <linux/notifier.h>
11 #include <linux/soc/qcom/qcom_aoss.h>
12 #include "msm_drv.h"
13 #include "a6xx_hfi.h"
14
15 struct a6xx_gmu_bo {
16 struct drm_gem_object *obj;
17 void *virt;
18 size_t size;
19 u64 iova;
20 };
21
22 #define GMU_MAX_GX_FREQS 16
23 #define GMU_MAX_CX_FREQS 4
24 #define GMU_MAX_BCMS 3
25
26 struct a6xx_bcm {
27 char *name;
28 unsigned int buswidth;
29 bool fixed;
30 unsigned int perfmode;
31 unsigned int perfmode_bw;
32 };
33
34 /*
35 * These define the different GMU wake up options - these define how both the
36 * CPU and the GMU bring up the hardware
37 */
38
39 /* THe GMU has already been booted and the rentention registers are active */
40 #define GMU_WARM_BOOT 0
41
42 /* the GMU is coming up for the first time or back from a power collapse */
43 #define GMU_COLD_BOOT 1
44
45 /*
46 * These define the level of control that the GMU has - the higher the number
47 * the more things that the GMU hardware controls on its own.
48 */
49
50 /* The GMU does not do any idle state management */
51 #define GMU_IDLE_STATE_ACTIVE 0
52
53 /* The GMU manages SPTP power collapse */
54 #define GMU_IDLE_STATE_SPTP 2
55
56 /* The GMU does automatic IFPC (intra-frame power collapse) */
57 #define GMU_IDLE_STATE_IFPC 3
58
59 struct a6xx_gmu {
60 struct device *dev;
61
62 /* For serializing communication with the GMU: */
63 struct mutex lock;
64
65 struct drm_gpuvm *vm;
66
67 void __iomem *mmio;
68 void __iomem *rscc;
69
70 int hfi_irq;
71 int gmu_irq;
72
73 struct device *gxpd;
74 struct device *cxpd;
75
76 int idle_level;
77
78 struct a6xx_gmu_bo hfi;
79 struct a6xx_gmu_bo debug;
80 struct a6xx_gmu_bo icache;
81 struct a6xx_gmu_bo dcache;
82 struct a6xx_gmu_bo dummy;
83 struct a6xx_gmu_bo log;
84
85 int nr_clocks;
86 struct clk_bulk_data *clocks;
87 struct clk *core_clk;
88 struct clk *hub_clk;
89
90 /* current performance index set externally */
91 int current_perf_index;
92
93 int nr_gpu_freqs;
94 unsigned long gpu_freqs[GMU_MAX_GX_FREQS];
95 u32 gx_arc_votes[GMU_MAX_GX_FREQS];
96 struct a6xx_hfi_acd_table acd_table;
97
98 int nr_gpu_bws;
99 unsigned long gpu_bw_table[GMU_MAX_GX_FREQS];
100 u32 gpu_ib_votes[GMU_MAX_GX_FREQS][GMU_MAX_BCMS];
101
102 int nr_gmu_freqs;
103 unsigned long gmu_freqs[GMU_MAX_CX_FREQS];
104 u32 cx_arc_votes[GMU_MAX_CX_FREQS];
105
106 unsigned long freq;
107
108 struct a6xx_hfi_queue queues[2];
109
110 bool initialized;
111 bool hung;
112 bool legacy; /* a618 or a630 */
113
114 /* For power domain callback */
115 struct notifier_block pd_nb;
116 struct completion pd_gate;
117
118 struct qmp *qmp;
119 struct a6xx_hfi_msg_bw_table *bw_table;
120 };
121
gmu_read(struct a6xx_gmu * gmu,u32 offset)122 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
123 {
124 return readl(gmu->mmio + (offset << 2));
125 }
126
gmu_write(struct a6xx_gmu * gmu,u32 offset,u32 value)127 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
128 {
129 writel(value, gmu->mmio + (offset << 2));
130 }
131
132 static inline void
gmu_write_bulk(struct a6xx_gmu * gmu,u32 offset,const u32 * data,u32 size)133 gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size)
134 {
135 memcpy_toio(gmu->mmio + (offset << 2), data, size);
136 wmb();
137 }
138
gmu_rmw(struct a6xx_gmu * gmu,u32 reg,u32 mask,u32 or)139 static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)
140 {
141 u32 val = gmu_read(gmu, reg);
142
143 val &= ~mask;
144
145 gmu_write(gmu, reg, val | or);
146 }
147
gmu_read64(struct a6xx_gmu * gmu,u32 lo,u32 hi)148 static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
149 {
150 u64 val;
151
152 val = (u64) readl(gmu->mmio + (lo << 2));
153 val |= ((u64) readl(gmu->mmio + (hi << 2)) << 32);
154
155 return val;
156 }
157
158 #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \
159 readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
160 interval, timeout)
161
gmu_read_rscc(struct a6xx_gmu * gmu,u32 offset)162 static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)
163 {
164 return readl(gmu->rscc + (offset << 2));
165 }
166
gmu_write_rscc(struct a6xx_gmu * gmu,u32 offset,u32 value)167 static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
168 {
169 writel(value, gmu->rscc + (offset << 2));
170 }
171
172 #define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \
173 readl_poll_timeout((gmu)->rscc + ((addr) << 2), val, cond, \
174 interval, timeout)
175
176 /*
177 * These are the available OOB (out of band requests) to the GMU where "out of
178 * band" means that the CPU talks to the GMU directly and not through HFI.
179 * Normally this works by writing a ITCM/DTCM register and then triggering a
180 * interrupt (the "request" bit) and waiting for an acknowledgment (the "ack"
181 * bit). The state is cleared by writing the "clear' bit to the GMU interrupt.
182 *
183 * These are used to force the GMU/GPU to stay on during a critical sequence or
184 * for hardware workarounds.
185 */
186
187 enum a6xx_gmu_oob_state {
188 /*
189 * Let the GMU know that a boot or slumber operation has started. The value in
190 * REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are
191 * doing
192 */
193 GMU_OOB_BOOT_SLUMBER = 0,
194 /*
195 * Let the GMU know to not turn off any GPU registers while the CPU is in a
196 * critical section
197 */
198 GMU_OOB_GPU_SET,
199 /*
200 * Set a new power level for the GPU when the CPU is doing frequency scaling
201 */
202 GMU_OOB_DCVS_SET,
203 /*
204 * Used to keep the GPU on for CPU-side reads of performance counters.
205 */
206 GMU_OOB_PERFCOUNTER_SET,
207 };
208
209 void a6xx_hfi_init(struct a6xx_gmu *gmu);
210 int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
211 void a6xx_hfi_stop(struct a6xx_gmu *gmu);
212 int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu);
213 int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, u32 perf_index, u32 bw_index);
214
215 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu);
216 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu);
217 void a6xx_sptprac_disable(struct a6xx_gmu *gmu);
218 int a6xx_sptprac_enable(struct a6xx_gmu *gmu);
219
220 #endif
221