1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013-2014 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
7 */
8
9 #include "adreno_gpu.h"
10 #include "a6xx_gpu.h"
11 #include "a6xx.xml.h"
12 #include "a6xx_gmu.xml.h"
13
14 static const struct adreno_reglist a612_hwcg[] = {
15 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
16 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
17 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081},
18 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
19 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
20 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
21 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
22 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
23 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
24 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
25 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
26 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
27 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
28 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
29 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
30 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
31 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
32 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222},
33 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
34 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
35 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},
36 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
37 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
38 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
39 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
40 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
41 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
42 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
43 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
44 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
45 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
46 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
47 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
48 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
49 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
50 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
51 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
52 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
53 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
54 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
55 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
56 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
57 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
58 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
59 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
60 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
61 {},
62 };
63
64 /* For a615 family (a615, a616, a618 and a619) */
65 static const struct adreno_reglist a615_hwcg[] = {
66 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
67 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
68 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
69 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
70 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
71 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
72 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
73 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
74 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
75 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
76 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
77 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
78 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
79 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
80 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
81 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
82 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
83 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
84 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
85 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
86 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
87 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
88 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
89 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
90 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
91 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
92 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
93 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
94 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
95 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
96 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
97 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
98 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
99 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
100 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
101 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
102 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020},
103 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
104 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
105 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
106 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
107 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
108 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
109 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
110 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
111 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
112 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
113 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
114 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
115 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
116 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
117 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
118 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
119 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
120 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
121 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
122 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
123 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
124 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
125 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
126 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
127 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
128 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
129 {},
130 };
131
132 static const struct adreno_reglist a620_hwcg[] = {
133 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
134 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
135 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
136 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
137 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
138 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
139 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
140 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
141 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
142 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
143 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
144 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
145 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
146 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
147 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
148 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
149 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
150 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
151 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
152 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
153 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
154 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
155 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
156 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
157 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
158 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
159 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
160 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
161 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
162 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
163 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
164 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
165 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
166 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
167 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
168 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
169 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
170 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
171 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
172 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
173 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
174 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
175 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
176 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
177 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
178 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
179 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
180 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
181 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
182 {},
183 };
184
185 static const struct adreno_reglist a630_hwcg[] = {
186 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
187 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
188 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
189 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
190 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
191 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
192 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
193 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
194 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
195 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
196 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
197 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
198 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
199 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
200 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
201 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
202 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
203 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
204 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
205 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
206 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
207 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
208 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
209 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
210 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
211 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
212 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
213 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
214 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
215 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
216 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
217 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
218 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
219 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
220 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
221 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
222 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
223 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
224 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
225 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
226 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
227 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
228 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
229 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
230 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
231 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
232 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
233 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
234 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
235 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
236 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
237 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
238 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
239 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
240 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
241 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
242 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
243 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
244 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
245 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
246 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
247 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
248 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
249 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
250 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
251 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
252 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
253 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
254 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
255 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
256 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
257 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
258 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
259 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
260 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
261 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
262 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
263 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
264 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
265 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
266 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
267 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
268 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
269 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
270 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
271 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
272 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
273 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
274 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
275 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
276 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
277 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
278 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
279 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
280 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
281 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
282 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
283 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
284 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
285 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
286 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
287 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
288 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
289 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
290 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
291 {},
292 };
293
294 static const struct adreno_reglist a640_hwcg[] = {
295 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
296 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
297 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
298 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
299 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
300 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
301 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
302 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
303 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
304 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
305 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
306 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
307 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
308 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
309 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
310 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
311 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
312 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
313 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
314 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
315 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
316 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
317 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
318 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
319 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
320 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
321 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
322 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
323 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
324 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
325 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
326 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
327 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
328 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
329 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
330 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
331 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
332 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
333 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
334 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
335 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
336 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
337 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
338 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
339 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
340 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
341 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
342 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
343 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
344 {},
345 };
346
347 static const struct adreno_reglist a650_hwcg[] = {
348 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
349 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
350 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
351 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
352 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
353 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
354 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
355 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
356 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
357 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
358 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
359 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
360 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
361 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
362 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
363 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
364 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
365 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
366 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
367 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
368 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
369 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
370 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
371 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
372 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
373 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
374 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
375 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
376 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
377 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
378 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
379 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
380 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
381 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
382 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
383 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
384 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
385 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
386 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
387 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
388 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
389 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
390 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
391 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
392 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
393 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
394 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
395 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
396 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
397 {},
398 };
399
400 static const struct adreno_reglist a660_hwcg[] = {
401 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
402 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
403 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
404 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
405 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
406 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
407 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
408 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
409 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
410 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
411 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
412 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
413 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
414 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
415 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
416 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
417 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
418 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
419 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
420 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
421 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
422 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
423 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
424 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
425 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
426 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
427 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
428 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
429 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
430 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
431 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
432 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
433 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
434 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
435 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
436 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
437 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
438 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
439 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
440 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
441 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
442 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
443 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
444 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
445 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
446 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
447 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
448 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
449 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
450 {},
451 };
452
453 static const struct adreno_reglist a690_hwcg[] = {
454 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
455 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
456 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
457 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
458 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
459 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
460 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
461 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
462 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
463 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
464 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
465 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
466 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
467 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
468 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
469 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
470 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
471 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
472 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
473 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
474 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
475 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
476 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
477 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
478 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
479 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
480 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
481 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
482 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
483 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
484 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
485 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
486 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
487 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
488 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
489 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
490 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
491 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
492 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
493 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
494 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
495 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
496 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
497 {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82},
498 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
499 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
500 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
501 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
502 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
503 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
504 {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
505 {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
506 {}
507 };
508
509 /* For a615, a616, a618, a619, a630, a640 and a680 */
510 static const u32 a630_protect_regs[] = {
511 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
512 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
513 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
514 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
515 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
516 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
517 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
518 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
519 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
520 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
521 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
522 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
523 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
524 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
525 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
526 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
527 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
528 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
529 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
530 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
531 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
532 A6XX_PROTECT_NORDWR(0x09e70, 0x0001),
533 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
534 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
535 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
536 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
537 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
538 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
539 A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
540 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
541 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
542 A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */
543 };
544 DECLARE_ADRENO_PROTECT(a630_protect, 32);
545
546 static const u32 a650_protect_regs[] = {
547 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
548 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
549 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
550 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
551 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
552 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
553 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
554 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
555 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
556 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
557 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
558 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
559 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
560 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
561 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
562 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
563 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
564 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
565 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
566 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
567 A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
568 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
569 A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
570 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
571 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
572 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
573 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
574 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
575 A6XX_PROTECT_NORDWR(0x0b608, 0x0007),
576 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
577 A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
578 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
579 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
580 A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
581 A6XX_PROTECT_NORDWR(0x1a800, 0x1fff),
582 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
583 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
584 A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
585 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
586 };
587 DECLARE_ADRENO_PROTECT(a650_protect, 48);
588
589 /* These are for a635 and a660 */
590 static const u32 a660_protect_regs[] = {
591 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
592 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
593 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
594 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
595 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
596 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
597 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
598 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
599 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
600 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
601 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
602 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
603 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
604 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
605 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
606 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
607 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
608 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
609 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
610 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
611 A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
612 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
613 A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
614 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
615 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
616 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
617 A6XX_PROTECT_NORDWR(0x0ae50, 0x012f),
618 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
619 A6XX_PROTECT_NORDWR(0x0b608, 0x0006),
620 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
621 A6XX_PROTECT_NORDWR(0x0be20, 0x015f),
622 A6XX_PROTECT_NORDWR(0x0d000, 0x05ff),
623 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
624 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
625 A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
626 A6XX_PROTECT_NORDWR(0x1a400, 0x1fff),
627 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
628 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
629 A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
630 A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
631 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
632 };
633 DECLARE_ADRENO_PROTECT(a660_protect, 48);
634
635 /* These are for a690 */
636 static const u32 a690_protect_regs[] = {
637 A6XX_PROTECT_RDONLY(0x00000, 0x004ff),
638 A6XX_PROTECT_RDONLY(0x00501, 0x00001),
639 A6XX_PROTECT_RDONLY(0x0050b, 0x002f4),
640 A6XX_PROTECT_NORDWR(0x0050e, 0x00000),
641 A6XX_PROTECT_NORDWR(0x00510, 0x00000),
642 A6XX_PROTECT_NORDWR(0x00534, 0x00000),
643 A6XX_PROTECT_NORDWR(0x00800, 0x00082),
644 A6XX_PROTECT_NORDWR(0x008a0, 0x00008),
645 A6XX_PROTECT_NORDWR(0x008ab, 0x00024),
646 A6XX_PROTECT_RDONLY(0x008de, 0x000ae),
647 A6XX_PROTECT_NORDWR(0x00900, 0x0004d),
648 A6XX_PROTECT_NORDWR(0x0098d, 0x00272),
649 A6XX_PROTECT_NORDWR(0x00e00, 0x00001),
650 A6XX_PROTECT_NORDWR(0x00e03, 0x0000c),
651 A6XX_PROTECT_NORDWR(0x03c00, 0x000c3),
652 A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff),
653 A6XX_PROTECT_NORDWR(0x08630, 0x001cf),
654 A6XX_PROTECT_NORDWR(0x08e00, 0x00000),
655 A6XX_PROTECT_NORDWR(0x08e08, 0x00007),
656 A6XX_PROTECT_NORDWR(0x08e50, 0x0001f),
657 A6XX_PROTECT_NORDWR(0x08e80, 0x0027f),
658 A6XX_PROTECT_NORDWR(0x09624, 0x001db),
659 A6XX_PROTECT_NORDWR(0x09e60, 0x00011),
660 A6XX_PROTECT_NORDWR(0x09e78, 0x00187),
661 A6XX_PROTECT_NORDWR(0x0a630, 0x001cf),
662 A6XX_PROTECT_NORDWR(0x0ae02, 0x00000),
663 A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f),
664 A6XX_PROTECT_NORDWR(0x0b604, 0x00000),
665 A6XX_PROTECT_NORDWR(0x0b608, 0x00006),
666 A6XX_PROTECT_NORDWR(0x0be02, 0x00001),
667 A6XX_PROTECT_NORDWR(0x0be20, 0x0015f),
668 A6XX_PROTECT_NORDWR(0x0d000, 0x005ff),
669 A6XX_PROTECT_NORDWR(0x0f000, 0x00bff),
670 A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff),
671 A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */
672 };
673 DECLARE_ADRENO_PROTECT(a690_protect, 48);
674
675 static const struct adreno_info a6xx_gpus[] = {
676 {
677 .chip_ids = ADRENO_CHIP_IDS(0x06010000),
678 .family = ADRENO_6XX_GEN1,
679 .revn = 610,
680 .fw = {
681 [ADRENO_FW_SQE] = "a630_sqe.fw",
682 },
683 .gmem = (SZ_128K + SZ_4K),
684 .quirks = ADRENO_QUIRK_4GB_VA,
685 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
686 .init = a6xx_gpu_init,
687 .zapfw = "a610_zap.mdt",
688 .a6xx = &(const struct a6xx_info) {
689 .hwcg = a612_hwcg,
690 .protect = &a630_protect,
691 .gmu_cgc_mode = 0x00020202,
692 .prim_fifo_threshold = 0x00080000,
693 },
694 /*
695 * There are (at least) three SoCs implementing A610: SM6125
696 * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does
697 * not have speedbinning, as only a single SKU exists and we
698 * don't support khaje upstream yet. Hence, this matching
699 * table is only valid for bengal.
700 */
701 .speedbins = ADRENO_SPEEDBINS(
702 { 0, 0 },
703 { 206, 1 },
704 { 200, 2 },
705 { 157, 3 },
706 { 127, 4 },
707 ),
708 }, {
709 .chip_ids = ADRENO_CHIP_IDS(0x06010500),
710 .family = ADRENO_6XX_GEN1,
711 .revn = 615,
712 .fw = {
713 [ADRENO_FW_SQE] = "a630_sqe.fw",
714 [ADRENO_FW_GMU] = "a630_gmu.bin",
715 },
716 .gmem = SZ_512K,
717 .quirks = ADRENO_QUIRK_4GB_VA,
718 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
719 .init = a6xx_gpu_init,
720 .zapfw = "a615_zap.mdt",
721 .a6xx = &(const struct a6xx_info) {
722 .hwcg = a615_hwcg,
723 .protect = &a630_protect,
724 .gmu_cgc_mode = 0x00000222,
725 .prim_fifo_threshold = 0x0018000,
726 },
727 .speedbins = ADRENO_SPEEDBINS(
728 /*
729 * The default speed bin (0) has the same values as
730 * speed bin 90 which goes up to 432 MHz.
731 */
732 { 0, 0 },
733 { 90, 0 },
734 { 105, 1 },
735 { 146, 2 },
736 { 163, 3 },
737 ),
738 }, {
739 .machine = "qcom,sm7150",
740 .chip_ids = ADRENO_CHIP_IDS(0x06010800),
741 .family = ADRENO_6XX_GEN1,
742 .fw = {
743 [ADRENO_FW_SQE] = "a630_sqe.fw",
744 [ADRENO_FW_GMU] = "a630_gmu.bin",
745 },
746 .gmem = SZ_512K,
747 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
748 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
749 ADRENO_QUIRK_4GB_VA,
750 .init = a6xx_gpu_init,
751 .zapfw = "a615_zap.mbn",
752 .a6xx = &(const struct a6xx_info) {
753 .hwcg = a615_hwcg,
754 .protect = &a630_protect,
755 .gmu_cgc_mode = 0x00000222,
756 .prim_fifo_threshold = 0x00180000,
757 },
758 .speedbins = ADRENO_SPEEDBINS(
759 { 0, 0 },
760 { 128, 1 },
761 { 146, 2 },
762 { 167, 3 },
763 { 172, 4 },
764 ),
765 }, {
766 .chip_ids = ADRENO_CHIP_IDS(0x06010800),
767 .family = ADRENO_6XX_GEN1,
768 .revn = 618,
769 .fw = {
770 [ADRENO_FW_SQE] = "a630_sqe.fw",
771 [ADRENO_FW_GMU] = "a630_gmu.bin",
772 },
773 .gmem = SZ_512K,
774 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
775 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
776 ADRENO_QUIRK_4GB_VA,
777 .init = a6xx_gpu_init,
778 .a6xx = &(const struct a6xx_info) {
779 .protect = &a630_protect,
780 .gmu_cgc_mode = 0x00000222,
781 .prim_fifo_threshold = 0x00180000,
782 },
783 .speedbins = ADRENO_SPEEDBINS(
784 { 0, 0 },
785 { 169, 1 },
786 { 174, 2 },
787 ),
788 }, {
789 .machine = "qcom,sm4350",
790 .chip_ids = ADRENO_CHIP_IDS(0x06010900),
791 .family = ADRENO_6XX_GEN1,
792 .revn = 619,
793 .fw = {
794 [ADRENO_FW_SQE] = "a630_sqe.fw",
795 [ADRENO_FW_GMU] = "a619_gmu.bin",
796 },
797 .gmem = SZ_512K,
798 .quirks = ADRENO_QUIRK_4GB_VA,
799 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
800 .init = a6xx_gpu_init,
801 .zapfw = "a615_zap.mdt",
802 .a6xx = &(const struct a6xx_info) {
803 .hwcg = a615_hwcg,
804 .protect = &a630_protect,
805 .gmu_cgc_mode = 0x00000222,
806 .prim_fifo_threshold = 0x00018000,
807 },
808 .speedbins = ADRENO_SPEEDBINS(
809 { 0, 0 },
810 { 138, 1 },
811 { 92, 2 },
812 ),
813 }, {
814 .machine = "qcom,sm6375",
815 .chip_ids = ADRENO_CHIP_IDS(0x06010901),
816 .family = ADRENO_6XX_GEN1,
817 .revn = 619,
818 .fw = {
819 [ADRENO_FW_SQE] = "a630_sqe.fw",
820 [ADRENO_FW_GMU] = "a619_gmu.bin",
821 },
822 .gmem = SZ_512K,
823 .quirks = ADRENO_QUIRK_4GB_VA,
824 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
825 .init = a6xx_gpu_init,
826 .zapfw = "a615_zap.mdt",
827 .a6xx = &(const struct a6xx_info) {
828 .hwcg = a615_hwcg,
829 .protect = &a630_protect,
830 .gmu_cgc_mode = 0x00000222,
831 .prim_fifo_threshold = 0x00018000,
832 },
833 .speedbins = ADRENO_SPEEDBINS(
834 { 0, 0 },
835 { 190, 1 },
836 { 177, 2 },
837 ),
838 }, {
839 .chip_ids = ADRENO_CHIP_IDS(0x06010900),
840 .family = ADRENO_6XX_GEN1,
841 .revn = 619,
842 .fw = {
843 [ADRENO_FW_SQE] = "a630_sqe.fw",
844 [ADRENO_FW_GMU] = "a619_gmu.bin",
845 },
846 .gmem = SZ_512K,
847 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
848 ADRENO_QUIRK_4GB_VA,
849 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
850 .init = a6xx_gpu_init,
851 .zapfw = "a615_zap.mdt",
852 .a6xx = &(const struct a6xx_info) {
853 .hwcg = a615_hwcg,
854 .protect = &a630_protect,
855 .gmu_cgc_mode = 0x00000222,
856 .prim_fifo_threshold = 0x00018000,
857 },
858 .speedbins = ADRENO_SPEEDBINS(
859 { 0, 0 },
860 { 120, 4 },
861 { 138, 3 },
862 { 169, 2 },
863 { 180, 1 },
864 ),
865 }, {
866 .chip_ids = ADRENO_CHIP_IDS(0x06020100),
867 .family = ADRENO_6XX_GEN3,
868 .fw = {
869 [ADRENO_FW_SQE] = "a650_sqe.fw",
870 [ADRENO_FW_GMU] = "a621_gmu.bin",
871 },
872 .gmem = SZ_512K,
873 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
874 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
875 ADRENO_QUIRK_HAS_HW_APRIV,
876 .init = a6xx_gpu_init,
877 .zapfw = "a620_zap.mbn",
878 .a6xx = &(const struct a6xx_info) {
879 .hwcg = a620_hwcg,
880 .protect = &a650_protect,
881 .gmu_cgc_mode = 0x00020200,
882 .prim_fifo_threshold = 0x00010000,
883 },
884 .speedbins = ADRENO_SPEEDBINS(
885 { 0, 0 },
886 { 137, 1 },
887 ),
888 }, {
889 .chip_ids = ADRENO_CHIP_IDS(0x06020300),
890 .family = ADRENO_6XX_GEN3,
891 .fw = {
892 [ADRENO_FW_SQE] = "a650_sqe.fw",
893 [ADRENO_FW_GMU] = "a623_gmu.bin",
894 },
895 .gmem = SZ_512K,
896 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
897 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
898 ADRENO_QUIRK_HAS_HW_APRIV,
899 .init = a6xx_gpu_init,
900 .a6xx = &(const struct a6xx_info) {
901 .hwcg = a690_hwcg,
902 .protect = &a650_protect,
903 .gmu_cgc_mode = 0x00020200,
904 .prim_fifo_threshold = 0x00010000,
905 .bcms = (const struct a6xx_bcm[]) {
906 { .name = "SH0", .buswidth = 16 },
907 { .name = "MC0", .buswidth = 4 },
908 {
909 .name = "ACV",
910 .fixed = true,
911 .perfmode = BIT(3),
912 },
913 { /* sentinel */ },
914 },
915 },
916 }, {
917 .chip_ids = ADRENO_CHIP_IDS(
918 0x06030001,
919 0x06030002
920 ),
921 .family = ADRENO_6XX_GEN1,
922 .revn = 630,
923 .fw = {
924 [ADRENO_FW_SQE] = "a630_sqe.fw",
925 [ADRENO_FW_GMU] = "a630_gmu.bin",
926 },
927 .gmem = SZ_1M,
928 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
929 ADRENO_QUIRK_4GB_VA,
930 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
931 .init = a6xx_gpu_init,
932 .zapfw = "a630_zap.mdt",
933 .a6xx = &(const struct a6xx_info) {
934 .hwcg = a630_hwcg,
935 .protect = &a630_protect,
936 .gmu_cgc_mode = 0x00020202,
937 .prim_fifo_threshold = 0x00180000,
938 },
939 }, {
940 .chip_ids = ADRENO_CHIP_IDS(0x06040001),
941 .family = ADRENO_6XX_GEN2,
942 .revn = 640,
943 .fw = {
944 [ADRENO_FW_SQE] = "a630_sqe.fw",
945 [ADRENO_FW_GMU] = "a640_gmu.bin",
946 },
947 .gmem = SZ_1M,
948 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
949 ADRENO_QUIRK_4GB_VA,
950 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
951 .init = a6xx_gpu_init,
952 .zapfw = "a640_zap.mdt",
953 .a6xx = &(const struct a6xx_info) {
954 .hwcg = a640_hwcg,
955 .protect = &a630_protect,
956 .gmu_cgc_mode = 0x00020202,
957 .prim_fifo_threshold = 0x00180000,
958 },
959 .speedbins = ADRENO_SPEEDBINS(
960 { 0, 0 },
961 { 1, 1 },
962 ),
963 }, {
964 .chip_ids = ADRENO_CHIP_IDS(0x06050002),
965 .family = ADRENO_6XX_GEN3,
966 .revn = 650,
967 .fw = {
968 [ADRENO_FW_SQE] = "a650_sqe.fw",
969 [ADRENO_FW_GMU] = "a650_gmu.bin",
970 },
971 .gmem = SZ_1M + SZ_128K,
972 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
973 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
974 ADRENO_QUIRK_HAS_HW_APRIV,
975 .init = a6xx_gpu_init,
976 .zapfw = "a650_zap.mdt",
977 .a6xx = &(const struct a6xx_info) {
978 .hwcg = a650_hwcg,
979 .protect = &a650_protect,
980 .gmu_cgc_mode = 0x00020202,
981 .prim_fifo_threshold = 0x00300200,
982 },
983 .speedbins = ADRENO_SPEEDBINS(
984 { 0, 0 },
985 { 1, 1 },
986 { 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */
987 { 3, 2 },
988 ),
989 }, {
990 .chip_ids = ADRENO_CHIP_IDS(0x06060001),
991 .family = ADRENO_6XX_GEN4,
992 .revn = 660,
993 .fw = {
994 [ADRENO_FW_SQE] = "a660_sqe.fw",
995 [ADRENO_FW_GMU] = "a660_gmu.bin",
996 },
997 .gmem = SZ_1M + SZ_512K,
998 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
999 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1000 ADRENO_QUIRK_HAS_HW_APRIV,
1001 .init = a6xx_gpu_init,
1002 .zapfw = "a660_zap.mdt",
1003 .a6xx = &(const struct a6xx_info) {
1004 .hwcg = a660_hwcg,
1005 .protect = &a660_protect,
1006 .gmu_cgc_mode = 0x00020000,
1007 .prim_fifo_threshold = 0x00300200,
1008 },
1009 }, {
1010 .chip_ids = ADRENO_CHIP_IDS(0x06060300),
1011 .family = ADRENO_6XX_GEN4,
1012 .fw = {
1013 [ADRENO_FW_SQE] = "a660_sqe.fw",
1014 [ADRENO_FW_GMU] = "a663_gmu.bin",
1015 },
1016 .gmem = SZ_1M + SZ_512K,
1017 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1018 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1019 ADRENO_QUIRK_HAS_HW_APRIV,
1020 .init = a6xx_gpu_init,
1021 .a6xx = &(const struct a6xx_info) {
1022 .hwcg = a690_hwcg,
1023 .protect = &a660_protect,
1024 .gmu_cgc_mode = 0x00020200,
1025 .prim_fifo_threshold = 0x00300200,
1026 },
1027 }, {
1028 .chip_ids = ADRENO_CHIP_IDS(0x06030500),
1029 .family = ADRENO_6XX_GEN4,
1030 .fw = {
1031 [ADRENO_FW_SQE] = "a660_sqe.fw",
1032 [ADRENO_FW_GMU] = "a660_gmu.bin",
1033 },
1034 .gmem = SZ_512K,
1035 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1036 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1037 ADRENO_QUIRK_HAS_HW_APRIV,
1038 .init = a6xx_gpu_init,
1039 .zapfw = "a660_zap.mbn",
1040 .a6xx = &(const struct a6xx_info) {
1041 .hwcg = a660_hwcg,
1042 .protect = &a660_protect,
1043 .gmu_cgc_mode = 0x00020202,
1044 .prim_fifo_threshold = 0x00200200,
1045 },
1046 .speedbins = ADRENO_SPEEDBINS(
1047 { 0, 0 },
1048 { 117, 0 },
1049 { 129, 4 },
1050 { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */
1051 { 190, 1 },
1052 ),
1053 }, {
1054 .chip_ids = ADRENO_CHIP_IDS(0x06080001),
1055 .family = ADRENO_6XX_GEN2,
1056 .revn = 680,
1057 .fw = {
1058 [ADRENO_FW_SQE] = "a630_sqe.fw",
1059 [ADRENO_FW_GMU] = "a640_gmu.bin",
1060 },
1061 .gmem = SZ_2M,
1062 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1063 ADRENO_QUIRK_4GB_VA,
1064 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1065 .init = a6xx_gpu_init,
1066 .zapfw = "a640_zap.mdt",
1067 .a6xx = &(const struct a6xx_info) {
1068 .hwcg = a640_hwcg,
1069 .protect = &a630_protect,
1070 .gmu_cgc_mode = 0x00020202,
1071 .prim_fifo_threshold = 0x00200200,
1072 },
1073 }, {
1074 .chip_ids = ADRENO_CHIP_IDS(0x06090000),
1075 .family = ADRENO_6XX_GEN4,
1076 .fw = {
1077 [ADRENO_FW_SQE] = "a660_sqe.fw",
1078 [ADRENO_FW_GMU] = "a660_gmu.bin",
1079 },
1080 .gmem = SZ_4M,
1081 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1082 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1083 ADRENO_QUIRK_HAS_HW_APRIV,
1084 .init = a6xx_gpu_init,
1085 .zapfw = "a690_zap.mdt",
1086 .a6xx = &(const struct a6xx_info) {
1087 .hwcg = a690_hwcg,
1088 .protect = &a690_protect,
1089 .gmu_cgc_mode = 0x00020200,
1090 .prim_fifo_threshold = 0x00800200,
1091 },
1092 }
1093 };
1094 DECLARE_ADRENO_GPULIST(a6xx);
1095
1096 static const struct adreno_reglist a702_hwcg[] = {
1097 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222 },
1098 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220 },
1099 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081 },
1100 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
1101 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222 },
1102 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
1103 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
1104 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222 },
1105 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
1106 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
1107 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
1108 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
1109 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
1110 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
1111 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
1112 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
1113 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
1114 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222 },
1115 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
1116 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 },
1117 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 },
1118 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555 },
1119 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
1120 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 },
1121 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
1122 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
1123 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222 },
1124 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
1125 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
1126 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
1127 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
1128 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
1129 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
1130 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
1131 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
1132 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
1133 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
1134 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
1135 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
1136 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
1137 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
1138 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
1139 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
1140 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
1141 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
1142 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
1143 { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222 },
1144 { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000 },
1145 { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000 },
1146 { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222 },
1147 { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000 },
1148 { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000 },
1149 { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002 },
1150 { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000 },
1151 { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000 },
1152 {}
1153 };
1154
1155 static const struct adreno_reglist a730_hwcg[] = {
1156 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
1157 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 },
1158 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
1159 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
1160 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
1161 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
1162 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
1163 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
1164 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
1165 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
1166 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
1167 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
1168 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
1169 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
1170 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
1171 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
1172 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
1173 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
1174 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
1175 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
1176 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
1177 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
1178 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
1179 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
1180 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
1181 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
1182 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
1183 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
1184 { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
1185 { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
1186 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
1187 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
1188 { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
1189 { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
1190 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
1191 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
1192 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
1193 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
1194 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
1195 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
1196 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
1197 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
1198 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
1199 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
1200 { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
1201 { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000223 },
1202 { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
1203 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
1204 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
1205 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
1206 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
1207 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
1208 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
1209 {},
1210 };
1211
1212 static const struct adreno_reglist a740_hwcg[] = {
1213 { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
1214 { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x22022222 },
1215 { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x003cf3cf },
1216 { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
1217 { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
1218 { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
1219 { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
1220 { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
1221 { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
1222 { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
1223 { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
1224 { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
1225 { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
1226 { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
1227 { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
1228 { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
1229 { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
1230 { REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 },
1231 { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000444 },
1232 { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000222 },
1233 { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
1234 { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
1235 { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
1236 { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
1237 { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
1238 { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
1239 { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
1240 { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
1241 { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
1242 { REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
1243 { REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
1244 { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
1245 { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00222222 },
1246 { REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
1247 { REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
1248 { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
1249 { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
1250 { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
1251 { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 },
1252 { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
1253 { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00000000 },
1254 { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
1255 { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
1256 { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
1257 { REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
1258 { REG_A7XX_RBBM_CLOCK_HYST2_VFD, 0x00000000 },
1259 { REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000222 },
1260 { REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
1261 { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
1262 { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
1263 { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
1264 { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
1265 { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
1266 { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
1267 {},
1268 };
1269
1270 static const u32 a730_protect_regs[] = {
1271 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
1272 A6XX_PROTECT_RDONLY(0x0050b, 0x0058),
1273 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
1274 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
1275 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
1276 A6XX_PROTECT_RDONLY(0x005fb, 0x009d),
1277 A6XX_PROTECT_NORDWR(0x00699, 0x01e9),
1278 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
1279 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
1280 /* 0x008d0-0x008dd and 0x008e0-0x008e6 are unprotected on purpose for tools like perfetto */
1281 A6XX_PROTECT_NORDWR(0x008de, 0x0001),
1282 A6XX_PROTECT_RDONLY(0x008e7, 0x014b),
1283 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
1284 A6XX_PROTECT_NORDWR(0x0098d, 0x00b2),
1285 A6XX_PROTECT_NORDWR(0x00a41, 0x01be),
1286 A6XX_PROTECT_NORDWR(0x00df0, 0x0001),
1287 A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
1288 A6XX_PROTECT_NORDWR(0x00e07, 0x0008),
1289 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
1290 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
1291 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
1292 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
1293 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
1294 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
1295 A6XX_PROTECT_NORDWR(0x08e80, 0x0280),
1296 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
1297 A6XX_PROTECT_NORDWR(0x09e40, 0x0000),
1298 A6XX_PROTECT_NORDWR(0x09e64, 0x000d),
1299 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
1300 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
1301 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
1302 A6XX_PROTECT_NORDWR(0x0ae50, 0x000f),
1303 A6XX_PROTECT_NORDWR(0x0ae66, 0x0003),
1304 A6XX_PROTECT_NORDWR(0x0ae6f, 0x0003),
1305 A6XX_PROTECT_NORDWR(0x0b604, 0x0003),
1306 A6XX_PROTECT_NORDWR(0x0ec00, 0x0fff),
1307 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1308 A6XX_PROTECT_NORDWR(0x18400, 0x0053),
1309 A6XX_PROTECT_RDONLY(0x18454, 0x0004),
1310 A6XX_PROTECT_NORDWR(0x18459, 0x1fff),
1311 A6XX_PROTECT_NORDWR(0x1a459, 0x1fff),
1312 A6XX_PROTECT_NORDWR(0x1c459, 0x1fff),
1313 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
1314 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
1315 A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
1316 A6XX_PROTECT_NORDWR(0x1f878, 0x002a),
1317 /* CP_PROTECT_REG[45, 46] are left untouched! */
1318 0,
1319 0,
1320 A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000),
1321 };
1322 DECLARE_ADRENO_PROTECT(a730_protect, 48);
1323
1324 static const uint32_t a7xx_pwrup_reglist_regs[] = {
1325 REG_A6XX_UCHE_TRAP_BASE,
1326 REG_A6XX_UCHE_TRAP_BASE + 1,
1327 REG_A6XX_UCHE_WRITE_THRU_BASE,
1328 REG_A6XX_UCHE_WRITE_THRU_BASE + 1,
1329 REG_A6XX_UCHE_GMEM_RANGE_MIN,
1330 REG_A6XX_UCHE_GMEM_RANGE_MIN + 1,
1331 REG_A6XX_UCHE_GMEM_RANGE_MAX,
1332 REG_A6XX_UCHE_GMEM_RANGE_MAX + 1,
1333 REG_A6XX_UCHE_CACHE_WAYS,
1334 REG_A6XX_UCHE_MODE_CNTL,
1335 REG_A6XX_RB_NC_MODE_CNTL,
1336 REG_A6XX_RB_CMP_DBG_ECO_CNTL,
1337 REG_A7XX_GRAS_NC_MODE_CNTL,
1338 REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE,
1339 REG_A6XX_UCHE_GBIF_GX_CONFIG,
1340 REG_A6XX_UCHE_CLIENT_PF,
1341 REG_A6XX_TPL1_DBG_ECO_CNTL1,
1342 };
1343
1344 DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist);
1345
1346 static const struct adreno_info a7xx_gpus[] = {
1347 {
1348 .chip_ids = ADRENO_CHIP_IDS(0x07000200),
1349 .family = ADRENO_6XX_GEN1, /* NOT a mistake! */
1350 .fw = {
1351 [ADRENO_FW_SQE] = "a702_sqe.fw",
1352 },
1353 .gmem = SZ_128K,
1354 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1355 .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
1356 .init = a6xx_gpu_init,
1357 .zapfw = "a702_zap.mbn",
1358 .a6xx = &(const struct a6xx_info) {
1359 .hwcg = a702_hwcg,
1360 .protect = &a650_protect,
1361 .gmu_cgc_mode = 0x00020202,
1362 .prim_fifo_threshold = 0x0000c000,
1363 },
1364 .speedbins = ADRENO_SPEEDBINS(
1365 { 0, 0 },
1366 { 236, 1 },
1367 { 178, 2 },
1368 { 142, 3 },
1369 ),
1370 }, {
1371 .chip_ids = ADRENO_CHIP_IDS(0x07030001),
1372 .family = ADRENO_7XX_GEN1,
1373 .fw = {
1374 [ADRENO_FW_SQE] = "a730_sqe.fw",
1375 [ADRENO_FW_GMU] = "gmu_gen70000.bin",
1376 },
1377 .gmem = SZ_2M,
1378 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1379 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1380 ADRENO_QUIRK_HAS_HW_APRIV |
1381 ADRENO_QUIRK_PREEMPTION,
1382 .init = a6xx_gpu_init,
1383 .zapfw = "a730_zap.mdt",
1384 .a6xx = &(const struct a6xx_info) {
1385 .hwcg = a730_hwcg,
1386 .protect = &a730_protect,
1387 .pwrup_reglist = &a7xx_pwrup_reglist,
1388 .gmu_cgc_mode = 0x00020000,
1389 },
1390 .preempt_record_size = 2860 * SZ_1K,
1391 }, {
1392 .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */
1393 .family = ADRENO_7XX_GEN2,
1394 .fw = {
1395 [ADRENO_FW_SQE] = "a740_sqe.fw",
1396 [ADRENO_FW_GMU] = "gmu_gen70200.bin",
1397 },
1398 .gmem = 3 * SZ_1M,
1399 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1400 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1401 ADRENO_QUIRK_HAS_HW_APRIV |
1402 ADRENO_QUIRK_PREEMPTION,
1403 .init = a6xx_gpu_init,
1404 .zapfw = "a740_zap.mdt",
1405 .a6xx = &(const struct a6xx_info) {
1406 .hwcg = a740_hwcg,
1407 .protect = &a730_protect,
1408 .pwrup_reglist = &a7xx_pwrup_reglist,
1409 .gmu_chipid = 0x7020100,
1410 .gmu_cgc_mode = 0x00020202,
1411 .bcms = (const struct a6xx_bcm[]) {
1412 { .name = "SH0", .buswidth = 16 },
1413 { .name = "MC0", .buswidth = 4 },
1414 {
1415 .name = "ACV",
1416 .fixed = true,
1417 .perfmode = BIT(3),
1418 .perfmode_bw = 16500000,
1419 },
1420 { /* sentinel */ },
1421 },
1422 },
1423 .preempt_record_size = 4192 * SZ_1K,
1424 }, {
1425 .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */
1426 .family = ADRENO_7XX_GEN2,
1427 .fw = {
1428 [ADRENO_FW_SQE] = "gen70500_sqe.fw",
1429 [ADRENO_FW_GMU] = "gen70500_gmu.bin",
1430 },
1431 .gmem = 3 * SZ_1M,
1432 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1433 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1434 ADRENO_QUIRK_HAS_HW_APRIV |
1435 ADRENO_QUIRK_PREEMPTION,
1436 .init = a6xx_gpu_init,
1437 .a6xx = &(const struct a6xx_info) {
1438 .hwcg = a740_hwcg,
1439 .protect = &a730_protect,
1440 .pwrup_reglist = &a7xx_pwrup_reglist,
1441 .gmu_chipid = 0x7050001,
1442 .gmu_cgc_mode = 0x00020202,
1443 },
1444 .preempt_record_size = 4192 * SZ_1K,
1445 .speedbins = ADRENO_SPEEDBINS(
1446 { 0, 0 },
1447 { 59, 1 },
1448 { 7, 2 },
1449 { 232, 3 },
1450 { 146, 4 },
1451 ),
1452 }, {
1453 .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
1454 .family = ADRENO_7XX_GEN3,
1455 .fw = {
1456 [ADRENO_FW_SQE] = "gen70900_sqe.fw",
1457 [ADRENO_FW_GMU] = "gmu_gen70900.bin",
1458 },
1459 .gmem = 3 * SZ_1M,
1460 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1461 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1462 ADRENO_QUIRK_HAS_HW_APRIV |
1463 ADRENO_QUIRK_PREEMPTION,
1464 .init = a6xx_gpu_init,
1465 .zapfw = "gen70900_zap.mbn",
1466 .a6xx = &(const struct a6xx_info) {
1467 .protect = &a730_protect,
1468 .pwrup_reglist = &a7xx_pwrup_reglist,
1469 .gmu_chipid = 0x7090100,
1470 .gmu_cgc_mode = 0x00020202,
1471 .bcms = (const struct a6xx_bcm[]) {
1472 { .name = "SH0", .buswidth = 16 },
1473 { .name = "MC0", .buswidth = 4 },
1474 {
1475 .name = "ACV",
1476 .fixed = true,
1477 .perfmode = BIT(2),
1478 .perfmode_bw = 10687500,
1479 },
1480 { /* sentinel */ },
1481 },
1482 },
1483 .preempt_record_size = 3572 * SZ_1K,
1484 }, {
1485 .chip_ids = ADRENO_CHIP_IDS(0x43030c00),
1486 .family = ADRENO_7XX_GEN2,
1487 .fw = {
1488 [ADRENO_FW_SQE] = "gen71500_sqe.fw",
1489 [ADRENO_FW_GMU] = "gen71500_gmu.bin",
1490 },
1491 .gmem = SZ_1M + SZ_512K,
1492 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
1493 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1494 ADRENO_QUIRK_HAS_HW_APRIV |
1495 ADRENO_QUIRK_PREEMPTION,
1496 .init = a6xx_gpu_init,
1497 .a6xx = &(const struct a6xx_info) {
1498 .hwcg = a740_hwcg,
1499 .protect = &a730_protect,
1500 .pwrup_reglist = &a7xx_pwrup_reglist,
1501 .gmu_chipid = 0x70f0000,
1502 .gmu_cgc_mode = 0x00020222,
1503 .bcms = (const struct a6xx_bcm[]) {
1504 { .name = "SH0", .buswidth = 16 },
1505 { .name = "MC0", .buswidth = 4 },
1506 {
1507 .name = "ACV",
1508 .fixed = true,
1509 .perfmode = BIT(3),
1510 .perfmode_bw = 16500000,
1511 },
1512 { /* sentinel */ },
1513 },
1514 },
1515 .preempt_record_size = 4192 * SZ_1K,
1516 .speedbins = ADRENO_SPEEDBINS(
1517 { 0, 0 },
1518 { 294, 1 },
1519 { 263, 2 },
1520 { 233, 3 },
1521 { 141, 4 },
1522 ),
1523 }
1524 };
1525 DECLARE_ADRENO_GPULIST(a7xx);
1526
__build_asserts(void)1527 static inline __always_unused void __build_asserts(void)
1528 {
1529 BUILD_BUG_ON(a630_protect.count > a630_protect.count_max);
1530 BUILD_BUG_ON(a650_protect.count > a650_protect.count_max);
1531 BUILD_BUG_ON(a660_protect.count > a660_protect.count_max);
1532 BUILD_BUG_ON(a690_protect.count > a690_protect.count_max);
1533 BUILD_BUG_ON(a730_protect.count > a730_protect.count_max);
1534 }
1535