1 #ifndef __ARCH_DOVE_MPP_CODED_H
2 #define __ARCH_DOVE_MPP_CODED_H
3 
4 #define MPP(_num, _sel, _in, _out) ( \
5 	/* MPP number */		((_num) & 0xff) | \
6 	/* MPP select value */		(((_sel) & 0xf) << 8) | \
7 	/* may be input signal */	((!!(_in)) << 12) | \
8 	/* may be output signal */	((!!(_out)) << 13))
9 
10 #define MPP0_GPIO0		MPP(0, 0x0, 1, 1)
11 #define MPP0_UA2_RTSn		MPP(0, 0x2, 0, 0)
12 #define MPP0_SDIO0_CD		MPP(0, 0x3, 0, 0)
13 #define MPP0_LCD0_PWM		MPP(0, 0xf, 0, 0)
14 
15 #define MPP1_GPIO1		MPP(1, 0x0, 1, 1)
16 #define MPP1_UA2_CTSn		MPP(1, 0x2, 0, 0)
17 #define MPP1_SDIO0_WP		MPP(1, 0x3, 0, 0)
18 #define MPP1_LCD1_PWM		MPP(1, 0xf, 0, 0)
19 
20 #define MPP2_GPIO2		MPP(2, 0x0, 1, 1)
21 #define MPP2_SATA_PRESENT	MPP(2, 0x1, 0, 0)
22 #define MPP2_UA2_TXD		MPP(2, 0x2, 0, 0)
23 #define MPP2_SDIO0_BUS_POWER	MPP(2, 0x3, 0, 0)
24 #define MPP2_UA_RTSn1		MPP(2, 0x4, 0, 0)
25 
26 #define MPP3_GPIO3		MPP(3, 0x0, 1, 1)
27 #define MPP3_SATA_ACT		MPP(3, 0x1, 0, 0)
28 #define MPP3_UA2_RXD		MPP(3, 0x2, 0, 0)
29 #define MPP3_SDIO0_LED_CTRL	MPP(3, 0x3, 0, 0)
30 #define MPP3_UA_CTSn1		MPP(3, 0x4, 0, 0)
31 #define MPP3_SPI_LCD_CS1	MPP(3, 0xf, 0, 0)
32 
33 #define MPP4_GPIO4		MPP(4, 0x0, 1, 1)
34 #define MPP4_UA3_RTSn		MPP(4, 0x2, 0, 0)
35 #define MPP4_SDIO1_CD		MPP(4, 0x3, 0, 0)
36 #define MPP4_SPI_1_MISO		MPP(4, 0x4, 0, 0)
37 
38 #define MPP5_GPIO5		MPP(5, 0x0, 1, 1)
39 #define MPP5_UA3_CTSn		MPP(5, 0x2, 0, 0)
40 #define MPP5_SDIO1_WP		MPP(5, 0x3, 0, 0)
41 #define MPP5_SPI_1_CS		MPP(5, 0x4, 0, 0)
42 
43 #define MPP6_GPIO6		MPP(6, 0x0, 1, 1)
44 #define MPP6_UA3_TXD		MPP(6, 0x2, 0, 0)
45 #define MPP6_SDIO1_BUS_POWER	MPP(6, 0x3, 0, 0)
46 #define MPP6_SPI_1_MOSI		MPP(6, 0x4, 0, 0)
47 
48 #define MPP7_GPIO7		MPP(7, 0x0, 1, 1)
49 #define MPP7_UA3_RXD		MPP(7, 0x2, 0, 0)
50 #define MPP7_SDIO1_LED_CTRL	MPP(7, 0x3, 0, 0)
51 #define MPP7_SPI_1_SCK		MPP(7, 0x4, 0, 0)
52 
53 #define MPP8_GPIO8		MPP(8, 0x0, 1, 1)
54 #define MPP8_WD_RST_OUT		MPP(8, 0x1, 0, 0)
55 
56 #define MPP9_GPIO9		MPP(9, 0x0, 1, 1)
57 #define MPP9_PEX1_CLKREQn	MPP(9, 0x5, 0, 0)
58 
59 #define MPP10_GPIO10		MPP(10, 0x0, 1, 1)
60 #define MPP10_SSP_SCLK		MPP(10, 0x5, 0, 0)
61 
62 #define MPP11_GPIO11		MPP(11, 0x0, 1, 1)
63 #define MPP11_SATA_PRESENT	MPP(11, 0x1, 0, 0)
64 #define MPP11_SATA_ACT		MPP(11, 0x2, 0, 0)
65 #define MPP11_SDIO0_LED_CTRL	MPP(11, 0x3, 0, 0)
66 #define MPP11_SDIO1_LED_CTRL	MPP(11, 0x4, 0, 0)
67 #define MPP11_PEX0_CLKREQn	MPP(11, 0x5, 0, 0)
68 
69 #define MPP12_GPIO12		MPP(12, 0x0, 1, 1)
70 #define MPP12_SATA_ACT		MPP(12, 0x1, 0, 0)
71 #define MPP12_UA2_RTSn		MPP(12, 0x2, 0, 0)
72 #define MPP12_AD0_I2S_EXT_MCLK	MPP(12, 0x3, 0, 0)
73 #define MPP12_SDIO1_CD		MPP(12, 0x4, 0, 0)
74 
75 #define MPP13_GPIO13		MPP(13, 0x0, 1, 1)
76 #define MPP13_UA2_CTSn		MPP(13, 0x2, 0, 0)
77 #define MPP13_AD1_I2S_EXT_MCLK	MPP(13, 0x3, 0, 0)
78 #define MPP13_SDIO1WP		MPP(13, 0x4, 0, 0)
79 #define MPP13_SSP_EXTCLK	MPP(13, 0x5, 0, 0)
80 
81 #define MPP14_GPIO14		MPP(14, 0x0, 1, 1)
82 #define MPP14_UA2_TXD		MPP(14, 0x2, 0, 0)
83 #define MPP14_SDIO1_BUS_POWER	MPP(14, 0x4, 0, 0)
84 #define MPP14_SSP_RXD		MPP(14, 0x5, 0, 0)
85 
86 #define MPP15_GPIO15		MPP(15, 0x0, 1, 1)
87 #define MPP15_UA2_RXD		MPP(15, 0x2, 0, 0)
88 #define MPP15_SDIO1_LED_CTRL	MPP(15, 0x4, 0, 0)
89 #define MPP15_SSP_SFRM		MPP(15, 0x5, 0, 0)
90 
91 #define MPP16_GPIO16		MPP(16, 0x0, 1, 1)
92 #define MPP16_UA3_RTSn		MPP(16, 0x2, 0, 0)
93 #define MPP16_SDIO0_CD		MPP(16, 0x3, 0, 0)
94 #define MPP16_SPI_LCD_CS1	MPP(16, 0x4, 0, 0)
95 #define MPP16_AC97_SDATA_IN1	MPP(16, 0x5, 0, 0)
96 
97 #define MPP17_GPIO17		MPP(17, 0x0, 1, 1)
98 #define MPP17_AC97_SYSCLK_OUT	MPP(17, 0x1, 0, 0)
99 #define MPP17_UA3_CTSn		MPP(17, 0x2, 0, 0)
100 #define MPP17_SDIO0_WP		MPP(17, 0x3, 0, 0)
101 #define MPP17_TW_SDA2		MPP(17, 0x4, 0, 0)
102 #define MPP17_AC97_SDATA_IN2	MPP(17, 0x5, 0, 0)
103 
104 #define MPP18_GPIO18		MPP(18, 0x0, 1, 1)
105 #define MPP18_UA3_TXD		MPP(18, 0x2, 0, 0)
106 #define MPP18_SDIO0_BUS_POWER	MPP(18, 0x3, 0, 0)
107 #define MPP18_LCD0_PWM		MPP(18, 0x4, 0, 0)
108 #define MPP18_AC_SDATA_IN3	MPP(18, 0x5, 0, 0)
109 
110 #define MPP19_GPIO19		MPP(19, 0x0, 1, 1)
111 #define MPP19_UA3_RXD		MPP(19, 0x2, 0, 0)
112 #define MPP19_SDIO0_LED_CTRL	MPP(19, 0x3, 0, 0)
113 #define MPP19_TW_SCK2		MPP(19, 0x4, 0, 0)
114 
115 #define MPP20_GPIO20		MPP(20, 0x0, 1, 1)
116 #define MPP20_AC97_SYSCLK_OUT	MPP(20, 0x1, 0, 0)
117 #define MPP20_SPI_LCD_MISO	MPP(20, 0x2, 0, 0)
118 #define MPP20_SDIO1_CD		MPP(20, 0x3, 0, 0)
119 #define MPP20_SDIO0_CD		MPP(20, 0x5, 0, 0)
120 #define MPP20_SPI_1_MISO	MPP(20, 0x6, 0, 0)
121 
122 #define MPP21_GPIO21		MPP(21, 0x0, 1, 1)
123 #define MPP21_UA1_RTSn		MPP(21, 0x1, 0, 0)
124 #define MPP21_SPI_LCD_CS0	MPP(21, 0x2, 0, 0)
125 #define MPP21_SDIO1_WP		MPP(21, 0x3, 0, 0)
126 #define MPP21_SSP_SFRM		MPP(21, 0x4, 0, 0)
127 #define MPP21_SDIO0_WP		MPP(21, 0x5, 0, 0)
128 #define MPP21_SPI_1_CS		MPP(21, 0x6, 0, 0)
129 
130 #define MPP22_GPIO22		MPP(22, 0x0, 1, 1)
131 #define MPP22_UA1_CTSn		MPP(22, 0x1, 0, 0)
132 #define MPP22_SPI_LCD_MOSI	MPP(22, 0x2, 0, 0)
133 #define MPP22_SDIO1_BUS_POWER	MPP(22, 0x3, 0, 0)
134 #define MPP22_SSP_TXD		MPP(22, 0x4, 0, 0)
135 #define MPP22_SDIO0_BUS_POWER	MPP(22, 0x5, 0, 0)
136 #define MPP22_SPI_1_MOSI	MPP(22, 0x6, 0, 0)
137 
138 #define MPP23_GPIO23		MPP(23, 0x0, 1, 1)
139 #define MPP23_SPI_LCD_SCK	MPP(23, 0x2, 0, 0)
140 #define MPP23_SDIO1_LED_CTRL	MPP(23, 0x3, 0, 0)
141 #define MPP23_SSP_SCLK		MPP(23, 0x4, 0, 0)
142 #define MPP23_SDIO0_LED_CTRL	MPP(23, 0x5, 0, 0)
143 #define MPP23_SPI_1_SCK		MPP(23, 0x6, 0, 0)
144 
145 #define MPP_MAX			23
146 
147 #define MPP_GRP(_grp, _mode)	MPP((_grp), (_mode), 0, 0)
148 
149 /* for MPP groups _num is a group index */
150 enum dove_mpp_grp_idx {
151 	MPP_24_39 = 2,
152 	MPP_40_45 = 0,
153 	MPP_46_51 = 1,
154 	MPP_58_61 = 5,
155 	MPP_62_63 = 4,
156 	MPP_GRP_MAX = 5,
157 };
158 
159 #define MPP_GRP_24_39_GPIO		MPP_GRP(MPP_24_39, 0x1)
160 #define MPP_GRP_24_39_CAM		MPP_GRP(MPP_24_39, 0x0)
161 
162 #define MPP_GRP_40_45_GPIO		MPP_GRP(MPP_40_45, 0x1)
163 #define MPP_GRP_40_45_SD0		MPP_GRP(MPP_40_45, 0x0)
164 
165 #define MPP_GRP_46_51_GPIO		MPP_GRP(MPP_46_51, 0x1)
166 #define MPP_GRP_46_51_SD1		MPP_GRP(MPP_46_51, 0x0)
167 
168 #define MPP_GRP_58_61_GPIO		MPP_GRP(MPP_58_61, 0x1)
169 #define MPP_GRP_58_61_SPI		MPP_GRP(MPP_58_61, 0x0)
170 
171 #define MPP_GRP_62_63_GPIO		MPP_GRP(MPP_62_63, 0x1)
172 #define MPP_GRP_62_63_UA1		MPP_GRP(MPP_62_63, 0x0)
173 
174 /* The MPP[64:71] control differs from other groups */
175 #define MPP_GRP_NFC_64_71_GPO		0x1
176 #define MPP_GRP_NFC_64_71_NFC		0x0
177 
178 /*
179  * The MPP[52:57] functionality is encoded by 4 bits in different
180  * registers. The _num field in this case encodes those bits in
181  * correspodence with Table 135 of 88AP510 Functional specification
182  */
183 #define MPP_GRP_AU1_52_57_AU1		0x0
184 #define MPP_GRP_AU1_52_57_AU1_GPIO57	0x2
185 #define MPP_GRP_AU1_52_57_GPIO		0xa
186 #define MPP_GRP_AU1_52_57_TW_GPIO	0xb
187 #define MPP_GRP_AU1_52_57_AU1_SSP	0xc
188 #define MPP_GRP_AU1_52_57_SSP_GPIO	0xe
189 #define MPP_GRP_AU1_52_57_SSP_TW	0xf
190 
191 void dove_mpp_conf(unsigned int *mpp_list,
192 		   unsigned int *mpp_grp_list,
193 		   unsigned int grp_au1_52_57,
194 		   unsigned int grp_nfc_64_71);
195 
196 #endif	/* __ARCH_DOVE_MPP_CODED_H */
197