1 /* 2 * Ripped off from arch/arm64/include/asm/sysreg.h 3 * 4 * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com> 5 * 6 * This work is licensed under the terms of the GNU LGPL, version 2. 7 */ 8 #ifndef _ASMARM64_SYSREG_H_ 9 #define _ASMARM64_SYSREG_H_ 10 11 #include <linux/const.h> 12 13 #define sys_reg(op0, op1, crn, crm, op2) \ 14 ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5)) 15 16 #ifdef __ASSEMBLER__ 17 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 18 .equ .L__reg_num_x\num, \num 19 .endr 20 .equ .L__reg_num_xzr, 31 21 22 .macro mrs_s, rt, sreg 23 .inst 0xd5200000|(\sreg)|(.L__reg_num_\rt) 24 .endm 25 26 .macro msr_s, sreg, rt 27 .inst 0xd5000000|(\sreg)|(.L__reg_num_\rt) 28 .endm 29 #else 30 #include <libcflat.h> 31 #include <bitops.h> 32 33 #define read_sysreg(r) ({ \ 34 u64 __val; \ 35 asm volatile("mrs %0, " xstr(r) : "=r" (__val)); \ 36 __val; \ 37 }) 38 39 #define write_sysreg(v, r) do { \ 40 u64 __val = (u64)v; \ 41 asm volatile("msr " xstr(r) ", %x0" : : "rZ" (__val)); \ 42 } while (0) 43 44 #define read_sysreg_s(r) ({ \ 45 u64 __val; \ 46 asm volatile("mrs_s %0, " xstr(r) : "=r" (__val)); \ 47 __val; \ 48 }) 49 50 #define write_sysreg_s(v, r) do { \ 51 u64 __val = (u64)v; \ 52 asm volatile("msr_s " xstr(r) ", %x0" : : "rZ" (__val));\ 53 } while (0) 54 55 #define write_regn_el0(__reg, __n, __val) \ 56 write_sysreg((__val), __reg ## __n ## _el0) 57 58 #define read_regn_el0(__reg, __n) \ 59 read_sysreg(__reg ## __n ## _el0) 60 61 asm( 62 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" 63 " .equ .L__reg_num_x\\num, \\num\n" 64 " .endr\n" 65 " .equ .L__reg_num_xzr, 31\n" 66 "\n" 67 " .macro mrs_s, rt, sreg\n" 68 " .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n" 69 " .endm\n" 70 "\n" 71 " .macro msr_s, sreg, rt\n" 72 " .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n" 73 " .endm\n" 74 ); 75 #endif /* __ASSEMBLER__ */ 76 77 #define ID_AA64ISAR0_EL1_RNDR_SHIFT 60 78 #define ID_AA64PFR1_EL1_MTE_SHIFT 8 79 80 #define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 81 #define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 82 #define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 83 #define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 84 #define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 85 86 #define TFSR_EL1 sys_reg(3, 0, 5, 6, 0) 87 #define TFSR_EL1_TF0 _BITULL(0) 88 #define TFSR_EL1_TF1 _BITULL(1) 89 90 /* System Control Register (SCTLR_EL1) bits */ 91 #define SCTLR_EL1_ATA _BITULL(43) 92 #define SCTLR_EL1_ATA0 _BITULL(42) 93 #define SCTLR_EL1_LSMAOE _BITULL(29) 94 #define SCTLR_EL1_NTLSMD _BITULL(28) 95 #define SCTLR_EL1_EE _BITULL(25) 96 #define SCTLR_EL1_SPAN _BITULL(23) 97 #define SCTLR_EL1_EIS _BITULL(22) 98 #define SCTLR_EL1_TSCXT _BITULL(20) 99 #define SCTLR_EL1_WXN _BITULL(19) 100 #define SCTLR_EL1_I _BITULL(12) 101 #define SCTLR_EL1_EOS _BITULL(11) 102 #define SCTLR_EL1_SED _BITULL(8) 103 #define SCTLR_EL1_ITD _BITULL(7) 104 #define SCTLR_EL1_SA0 _BITULL(4) 105 #define SCTLR_EL1_SA _BITULL(3) 106 #define SCTLR_EL1_C _BITULL(2) 107 #define SCTLR_EL1_A _BITULL(1) 108 #define SCTLR_EL1_M _BITULL(0) 109 110 #define SCTLR_EL1_TCF_SHIFT 40 111 #define SCTLR_EL1_TCF_MASK GENMASK_ULL(41, 40) 112 113 #define SCTLR_EL1_TCF0_SHIFT 38 114 #define SCTLR_EL1_TCF0_MASK GENMASK_ULL(39, 38) 115 116 #define INIT_SCTLR_EL1_MMU_OFF \ 117 (SCTLR_EL1_ITD | SCTLR_EL1_SED | SCTLR_EL1_EOS | \ 118 SCTLR_EL1_TSCXT | SCTLR_EL1_EIS | SCTLR_EL1_SPAN | \ 119 SCTLR_EL1_NTLSMD | SCTLR_EL1_LSMAOE) 120 121 #define ZCR_EL1 S3_0_C1_C2_0 122 #define ZCR_EL1_LEN GENMASK(3, 0) 123 124 #define RNDR S3_3_C2_C4_0 125 126 #endif /* _ASMARM64_SYSREG_H_ */ 127