1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ASM_SH_IO_H
3 #define __ASM_SH_IO_H
4
5 /*
6 * Convention:
7 * read{b,w,l,q}/write{b,w,l,q} are for PCI,
8 * while in{b,w,l}/out{b,w,l} are for ISA
9 *
10 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
11 * and 'string' versions: ins{b,w,l}/outs{b,w,l}
12 *
13 * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
14 * automatically, there are also __raw versions, which do not.
15 */
16 #include <linux/errno.h>
17 #include <asm/cache.h>
18 #include <asm/addrspace.h>
19 #include <asm/machvec.h>
20 #include <asm/page.h>
21 #include <linux/pgtable.h>
22
23 #define __IO_PREFIX generic
24 #include <asm/io_generic.h>
25 #include <asm-generic/pci_iomap.h>
26 #include <mach/mangle-port.h>
27
28 #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
29 #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
30 #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
31 #define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))
32
33 #define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a))
34 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a))
35 #define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a))
36 #define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a))
37
38 #define readb_relaxed(c) ({ u8 __v = ioswabb(__raw_readb(c)); __v; })
39 #define readw_relaxed(c) ({ u16 __v = ioswabw(__raw_readw(c)); __v; })
40 #define readl_relaxed(c) ({ u32 __v = ioswabl(__raw_readl(c)); __v; })
41 #define readq_relaxed(c) ({ u64 __v = ioswabq(__raw_readq(c)); __v; })
42
43 #define writeb_relaxed(v,c) ((void)__raw_writeb((__force u8)ioswabb(v),c))
44 #define writew_relaxed(v,c) ((void)__raw_writew((__force u16)ioswabw(v),c))
45 #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
46 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)ioswabq(v),c))
47
48 #define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; })
49 #define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; })
50 #define readl(a) ({ u32 r_ = readl_relaxed(a); rmb(); r_; })
51 #define readq(a) ({ u64 r_ = readq_relaxed(a); rmb(); r_; })
52
53 #define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); })
54 #define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); })
55 #define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
56 #define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); })
57
58 #define readsb(p,d,l) __raw_readsb(p,d,l)
59 #define readsw(p,d,l) __raw_readsw(p,d,l)
60 #define readsl(p,d,l) __raw_readsl(p,d,l)
61
62 #define writesb(p,d,l) __raw_writesb(p,d,l)
63 #define writesw(p,d,l) __raw_writesw(p,d,l)
64 #define writesl(p,d,l) __raw_writesl(p,d,l)
65
66 #define __BUILD_UNCACHED_IO(bwlq, type) \
67 static inline type read##bwlq##_uncached(unsigned long addr) \
68 { \
69 type ret; \
70 jump_to_uncached(); \
71 ret = __raw_read##bwlq(addr); \
72 back_to_cached(); \
73 return ret; \
74 } \
75 \
76 static inline void write##bwlq##_uncached(type v, unsigned long addr) \
77 { \
78 jump_to_uncached(); \
79 __raw_write##bwlq(v, addr); \
80 back_to_cached(); \
81 }
82
83 __BUILD_UNCACHED_IO(b, u8)
84 __BUILD_UNCACHED_IO(w, u16)
85 __BUILD_UNCACHED_IO(l, u32)
86 __BUILD_UNCACHED_IO(q, u64)
87
88 #define __BUILD_MEMORY_STRING(pfx, bwlq, type) \
89 \
90 static inline void \
91 pfx##writes##bwlq(volatile void __iomem *mem, const void *addr, \
92 unsigned int count) \
93 { \
94 const volatile type *__addr = addr; \
95 \
96 while (count--) { \
97 __raw_write##bwlq(*__addr, mem); \
98 __addr++; \
99 } \
100 } \
101 \
102 static inline void pfx##reads##bwlq(const volatile void __iomem *mem, \
103 void *addr, unsigned int count) \
104 { \
105 volatile type *__addr = addr; \
106 \
107 while (count--) { \
108 *__addr = __raw_read##bwlq(mem); \
109 __addr++; \
110 } \
111 }
112
113 __BUILD_MEMORY_STRING(__raw_, b, u8)
114 __BUILD_MEMORY_STRING(__raw_, w, u16)
115
116 void __raw_writesl(void volatile __iomem *addr, const void *data, int longlen);
117 void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen);
118
119 __BUILD_MEMORY_STRING(__raw_, q, u64)
120
121 #define ioport_map ioport_map
122 #define pci_iounmap pci_iounmap
123
124 #ifdef CONFIG_HAS_IOPORT_MAP
125
126 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
127
128 /*
129 * Slowdown I/O port space accesses for antique hardware.
130 */
131 #undef CONF_SLOWDOWN_IO
132
133 /*
134 * On SuperH I/O ports are memory mapped, so we access them using normal
135 * load/store instructions. sh_io_port_base is the virtual address to
136 * which all ports are being mapped.
137 */
138 extern unsigned long sh_io_port_base;
139
__set_io_port_base(unsigned long pbase)140 static inline void __set_io_port_base(unsigned long pbase)
141 {
142 *(unsigned long *)&sh_io_port_base = pbase;
143 barrier();
144 }
145
146 #ifdef CONFIG_GENERIC_IOMAP
147 #define __ioport_map ioport_map
148 #else
149 extern void __iomem *__ioport_map(unsigned long addr, unsigned int size);
150 #endif
151
152 #ifdef CONF_SLOWDOWN_IO
153 #define SLOW_DOWN_IO __raw_readw(sh_io_port_base)
154 #else
155 #define SLOW_DOWN_IO
156 #endif
157
158 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
159 \
160 static inline void pfx##out##bwlq##p(type val, unsigned long port) \
161 { \
162 volatile type *__addr; \
163 \
164 __addr = (void __iomem *)sh_io_port_base + port; \
165 *__addr = val; \
166 slow; \
167 } \
168 \
169 static inline type pfx##in##bwlq##p(unsigned long port) \
170 { \
171 volatile type *__addr; \
172 type __val; \
173 \
174 __addr = (void __iomem *)sh_io_port_base + port; \
175 __val = *__addr; \
176 slow; \
177 \
178 return __val; \
179 }
180
181 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \
182 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
183 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
184
185 #define BUILDIO_IOPORT(bwlq, type) \
186 __BUILD_IOPORT_PFX(, bwlq, type)
187
188 BUILDIO_IOPORT(b, u8)
189 BUILDIO_IOPORT(w, u16)
190 BUILDIO_IOPORT(l, u32)
191 BUILDIO_IOPORT(q, u64)
192
193 #define __BUILD_IOPORT_STRING(bwlq, type) \
194 \
195 static inline void outs##bwlq(unsigned long port, const void *addr, \
196 unsigned int count) \
197 { \
198 const volatile type *__addr = addr; \
199 \
200 while (count--) { \
201 out##bwlq(*__addr, port); \
202 __addr++; \
203 } \
204 } \
205 \
206 static inline void ins##bwlq(unsigned long port, void *addr, \
207 unsigned int count) \
208 { \
209 volatile type *__addr = addr; \
210 \
211 while (count--) { \
212 *__addr = in##bwlq(port); \
213 __addr++; \
214 } \
215 }
216
217 __BUILD_IOPORT_STRING(b, u8)
218 __BUILD_IOPORT_STRING(w, u16)
219 __BUILD_IOPORT_STRING(l, u32)
220 __BUILD_IOPORT_STRING(q, u64)
221
222 #else /* !CONFIG_HAS_IOPORT_MAP */
223
224 #include <asm/io_noioport.h>
225
226 #endif
227
228 #define inb(addr) inb(addr)
229 #define inw(addr) inw(addr)
230 #define inl(addr) inl(addr)
231 #define outb(x, addr) outb((x), (addr))
232 #define outw(x, addr) outw((x), (addr))
233 #define outl(x, addr) outl((x), (addr))
234
235 #define inb_p(addr) inb(addr)
236 #define inw_p(addr) inw(addr)
237 #define inl_p(addr) inl(addr)
238 #define outb_p(x, addr) outb((x), (addr))
239 #define outw_p(x, addr) outw((x), (addr))
240 #define outl_p(x, addr) outl((x), (addr))
241
242 #define insb insb
243 #define insw insw
244 #define insl insl
245 #define outsb outsb
246 #define outsw outsw
247 #define outsl outsl
248
249 #define IO_SPACE_LIMIT 0xffffffff
250
251 /* We really want to try and get these to memcpy etc */
252 #define memset_io memset_io
253 #define memcpy_fromio memcpy_fromio
254 #define memcpy_toio memcpy_toio
255 void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
256 void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
257 void memset_io(volatile void __iomem *, int, unsigned long);
258
259 /* Quad-word real-mode I/O, don't ask.. */
260 unsigned long long peek_real_address_q(unsigned long long addr);
261 unsigned long long poke_real_address_q(unsigned long long addr,
262 unsigned long long val);
263
264 #if !defined(CONFIG_MMU)
265 #define virt_to_phys(address) ((unsigned long)(address))
266 #define phys_to_virt(address) ((void *)(address))
267 #else
268 #define virt_to_phys(address) (__pa(address))
269 #define phys_to_virt(address) (__va(address))
270 #endif
271
272 #ifdef CONFIG_MMU
273 /*
274 * I/O memory mapping functions.
275 */
276 #define ioremap_prot ioremap_prot
277 #define iounmap iounmap
278
279 #define _PAGE_IOREMAP pgprot_val(PAGE_KERNEL_NOCACHE)
280
281 #define ioremap_cache(addr, size) \
282 ioremap_prot((addr), (size), PAGE_KERNEL)
283 #endif /* CONFIG_MMU */
284
285 #include <asm-generic/io.h>
286
287 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
288 int valid_phys_addr_range(phys_addr_t addr, size_t size);
289 int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
290
291 #endif /* __ASM_SH_IO_H */
292