1 /* 2 * All ripped off from arch/arm64/include/asm/arch_gicv3.h 3 * 4 * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com> 5 * 6 * This work is licensed under the terms of the GNU LGPL, version 2. 7 */ 8 #ifndef _ASMARM64_ARCH_GICV3_H_ 9 #define _ASMARM64_ARCH_GICV3_H_ 10 11 #include <asm/sysreg.h> 12 13 #ifndef __ASSEMBLER__ 14 15 #include <libcflat.h> 16 #include <asm/barrier.h> 17 18 /* 19 * Low-level accessors 20 * 21 * These system registers are 32 bits, but we make sure that the compiler 22 * sets the GP register's most significant bits to 0 with an explicit cast. 23 */ 24 gicv3_write_pmr(u32 val)25static inline void gicv3_write_pmr(u32 val) 26 { 27 asm volatile("msr_s " xstr(ICC_PMR_EL1) ", %0" : : "r" ((u64)val)); 28 } 29 gicv3_write_sgi1r(u64 val)30static inline void gicv3_write_sgi1r(u64 val) 31 { 32 asm volatile("msr_s " xstr(ICC_SGI1R_EL1) ", %0" : : "r" (val)); 33 } 34 gicv3_read_iar(void)35static inline u32 gicv3_read_iar(void) 36 { 37 u64 irqstat; 38 asm volatile("mrs_s %0, " xstr(ICC_IAR1_EL1) : "=r" (irqstat)); 39 dsb(sy); 40 return (u64)irqstat; 41 } 42 gicv3_write_eoir(u32 irq)43static inline void gicv3_write_eoir(u32 irq) 44 { 45 asm volatile("msr_s " xstr(ICC_EOIR1_EL1) ", %0" : : "r" ((u64)irq)); 46 isb(); 47 } 48 gicv3_write_grpen1(u32 val)49static inline void gicv3_write_grpen1(u32 val) 50 { 51 asm volatile("msr_s " xstr(ICC_GRPEN1_EL1) ", %0" : : "r" ((u64)val)); 52 isb(); 53 } 54 55 #define gicv3_read_typer(c) readq(c) 56 57 #endif /* !__ASSEMBLER__ */ 58 #endif /* _ASMARM64_ARCH_GICV3_H_ */ 59