1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * QEMU RISC-V Board Compatible with the Xiangshan Kunminghu 4 * FPGA prototype platform 5 * 6 * Copyright (c) 2025 Beijing Institute of Open Source Chip (BOSC) 7 * 8 */ 9 10 #ifndef HW_XIANGSHAN_KMH_H 11 #define HW_XIANGSHAN_KMH_H 12 13 #include "hw/boards.h" 14 #include "hw/riscv/riscv_hart.h" 15 16 #define XIANGSHAN_KMH_MAX_CPUS 16 17 18 typedef struct XiangshanKmhSoCState { 19 /*< private >*/ 20 DeviceState parent_obj; 21 22 /*< public >*/ 23 RISCVHartArrayState cpus; 24 DeviceState *irqchip; 25 MemoryRegion rom; 26 } XiangshanKmhSoCState; 27 28 #define TYPE_XIANGSHAN_KMH_SOC "xiangshan.kunminghu.soc" 29 DECLARE_INSTANCE_CHECKER(XiangshanKmhSoCState, XIANGSHAN_KMH_SOC, 30 TYPE_XIANGSHAN_KMH_SOC) 31 32 typedef struct XiangshanKmhState { 33 /*< private >*/ 34 MachineState parent_obj; 35 36 /*< public >*/ 37 XiangshanKmhSoCState soc; 38 } XiangshanKmhState; 39 40 #define TYPE_XIANGSHAN_KMH_MACHINE MACHINE_TYPE_NAME("xiangshan-kunminghu") 41 DECLARE_INSTANCE_CHECKER(XiangshanKmhState, XIANGSHAN_KMH_MACHINE, 42 TYPE_XIANGSHAN_KMH_MACHINE) 43 44 enum { 45 XIANGSHAN_KMH_ROM, 46 XIANGSHAN_KMH_UART0, 47 XIANGSHAN_KMH_CLINT, 48 XIANGSHAN_KMH_APLIC_M, 49 XIANGSHAN_KMH_APLIC_S, 50 XIANGSHAN_KMH_IMSIC_M, 51 XIANGSHAN_KMH_IMSIC_S, 52 XIANGSHAN_KMH_DRAM, 53 }; 54 55 enum { 56 XIANGSHAN_KMH_UART0_IRQ = 10, 57 }; 58 59 /* Indicating Timebase-freq (1MHZ) */ 60 #define XIANGSHAN_KMH_CLINT_TIMEBASE_FREQ 1000000 61 62 #define XIANGSHAN_KMH_IMSIC_NUM_IDS 255 63 #define XIANGSHAN_KMH_IMSIC_NUM_GUESTS 7 64 #define XIANGSHAN_KMH_IMSIC_GUEST_BITS 3 65 66 #define XIANGSHAN_KMH_APLIC_NUM_SOURCES 96 67 68 #endif 69