1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014-2021 Intel Corporation 4 */ 5 6 #ifndef _ABI_GUC_ACTIONS_ABI_H 7 #define _ABI_GUC_ACTIONS_ABI_H 8 9 /** 10 * DOC: HOST2GUC_SELF_CFG 11 * 12 * This message is used by Host KMD to setup of the `GuC Self Config KLVs`_. 13 * 14 * This message must be sent as `MMIO HXG Message`_. 15 * 16 * +---+-------+--------------------------------------------------------------+ 17 * | | Bits | Description | 18 * +===+=======+==============================================================+ 19 * | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_HOST_ | 20 * | +-------+--------------------------------------------------------------+ 21 * | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ | 22 * | +-------+--------------------------------------------------------------+ 23 * | | 27:16 | DATA0 = MBZ | 24 * | +-------+--------------------------------------------------------------+ 25 * | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_SELF_CFG` = 0x0508 | 26 * +---+-------+--------------------------------------------------------------+ 27 * | 1 | 31:16 | **KLV_KEY** - KLV key, see `GuC Self Config KLVs`_ | 28 * | +-------+--------------------------------------------------------------+ 29 * | | 15:0 | **KLV_LEN** - KLV length | 30 * | | | | 31 * | | | - 32 bit KLV = 1 | 32 * | | | - 64 bit KLV = 2 | 33 * +---+-------+--------------------------------------------------------------+ 34 * | 2 | 31:0 | **VALUE32** - Bits 31-0 of the KLV value | 35 * +---+-------+--------------------------------------------------------------+ 36 * | 3 | 31:0 | **VALUE64** - Bits 63-32 of the KLV value (**KLV_LEN** = 2) | 37 * +---+-------+--------------------------------------------------------------+ 38 * 39 * +---+-------+--------------------------------------------------------------+ 40 * | | Bits | Description | 41 * +===+=======+==============================================================+ 42 * | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_GUC_ | 43 * | +-------+--------------------------------------------------------------+ 44 * | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_ | 45 * | +-------+--------------------------------------------------------------+ 46 * | | 27:0 | DATA0 = **NUM** - 1 if KLV was parsed, 0 if not recognized | 47 * +---+-------+--------------------------------------------------------------+ 48 */ 49 #define GUC_ACTION_HOST2GUC_SELF_CFG 0x0508 50 51 #define HOST2GUC_SELF_CFG_REQUEST_MSG_LEN (GUC_HXG_REQUEST_MSG_MIN_LEN + 3u) 52 #define HOST2GUC_SELF_CFG_REQUEST_MSG_0_MBZ GUC_HXG_REQUEST_MSG_0_DATA0 53 #define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY (0xffffu << 16) 54 #define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN (0xffffu << 0) 55 #define HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32 GUC_HXG_REQUEST_MSG_n_DATAn 56 #define HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64 GUC_HXG_REQUEST_MSG_n_DATAn 57 58 #define HOST2GUC_SELF_CFG_RESPONSE_MSG_LEN GUC_HXG_RESPONSE_MSG_MIN_LEN 59 #define HOST2GUC_SELF_CFG_RESPONSE_MSG_0_NUM GUC_HXG_RESPONSE_MSG_0_DATA0 60 61 /** 62 * DOC: HOST2GUC_CONTROL_CTB 63 * 64 * This H2G action allows Vf Host to enable or disable H2G and G2H `CT Buffer`_. 65 * 66 * This message must be sent as `MMIO HXG Message`_. 67 * 68 * +---+-------+--------------------------------------------------------------+ 69 * | | Bits | Description | 70 * +===+=======+==============================================================+ 71 * | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_HOST_ | 72 * | +-------+--------------------------------------------------------------+ 73 * | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ | 74 * | +-------+--------------------------------------------------------------+ 75 * | | 27:16 | DATA0 = MBZ | 76 * | +-------+--------------------------------------------------------------+ 77 * | | 15:0 | ACTION = _`GUC_ACTION_HOST2GUC_CONTROL_CTB` = 0x4509 | 78 * +---+-------+--------------------------------------------------------------+ 79 * | 1 | 31:0 | **CONTROL** - control `CTB based communication`_ | 80 * | | | | 81 * | | | - _`GUC_CTB_CONTROL_DISABLE` = 0 | 82 * | | | - _`GUC_CTB_CONTROL_ENABLE` = 1 | 83 * +---+-------+--------------------------------------------------------------+ 84 * 85 * +---+-------+--------------------------------------------------------------+ 86 * | | Bits | Description | 87 * +===+=======+==============================================================+ 88 * | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_GUC_ | 89 * | +-------+--------------------------------------------------------------+ 90 * | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_ | 91 * | +-------+--------------------------------------------------------------+ 92 * | | 27:0 | DATA0 = MBZ | 93 * +---+-------+--------------------------------------------------------------+ 94 */ 95 #define GUC_ACTION_HOST2GUC_CONTROL_CTB 0x4509 96 97 #define HOST2GUC_CONTROL_CTB_REQUEST_MSG_LEN (GUC_HXG_REQUEST_MSG_MIN_LEN + 1u) 98 #define HOST2GUC_CONTROL_CTB_REQUEST_MSG_0_MBZ GUC_HXG_REQUEST_MSG_0_DATA0 99 #define HOST2GUC_CONTROL_CTB_REQUEST_MSG_1_CONTROL GUC_HXG_REQUEST_MSG_n_DATAn 100 #define GUC_CTB_CONTROL_DISABLE 0u 101 #define GUC_CTB_CONTROL_ENABLE 1u 102 103 #define HOST2GUC_CONTROL_CTB_RESPONSE_MSG_LEN GUC_HXG_RESPONSE_MSG_MIN_LEN 104 #define HOST2GUC_CONTROL_CTB_RESPONSE_MSG_0_MBZ GUC_HXG_RESPONSE_MSG_0_DATA0 105 106 /* legacy definitions */ 107 108 enum xe_guc_action { 109 XE_GUC_ACTION_DEFAULT = 0x0, 110 XE_GUC_ACTION_REQUEST_PREEMPTION = 0x2, 111 XE_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3, 112 XE_GUC_ACTION_ALLOCATE_DOORBELL = 0x10, 113 XE_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20, 114 XE_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30, 115 XE_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x40, 116 XE_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302, 117 XE_GUC_ACTION_ENTER_S_STATE = 0x501, 118 XE_GUC_ACTION_EXIT_S_STATE = 0x502, 119 XE_GUC_ACTION_GLOBAL_SCHED_POLICY_CHANGE = 0x506, 120 XE_GUC_ACTION_SCHED_CONTEXT = 0x1000, 121 XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET = 0x1001, 122 XE_GUC_ACTION_SCHED_CONTEXT_MODE_DONE = 0x1002, 123 XE_GUC_ACTION_SCHED_ENGINE_MODE_SET = 0x1003, 124 XE_GUC_ACTION_SCHED_ENGINE_MODE_DONE = 0x1004, 125 XE_GUC_ACTION_SET_CONTEXT_PRIORITY = 0x1005, 126 XE_GUC_ACTION_SET_CONTEXT_EXECUTION_QUANTUM = 0x1006, 127 XE_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007, 128 XE_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008, 129 XE_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009, 130 XE_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES = 0x100B, 131 XE_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, 132 XE_GUC_ACTION_GET_HWCONFIG = 0x4100, 133 XE_GUC_ACTION_REGISTER_CONTEXT = 0x4502, 134 XE_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503, 135 XE_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505, 136 XE_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506, 137 XE_GUC_ACTION_REGISTER_G2G = 0x4507, 138 XE_GUC_ACTION_DEREGISTER_G2G = 0x4508, 139 XE_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600, 140 XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601, 141 XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507, 142 XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A, 143 XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C, 144 XE_GUC_ACTION_SET_FUNCTION_ENGINE_ACTIVITY_BUFFER = 0x550D, 145 XE_GUC_ACTION_OPT_IN_FEATURE_KLV = 0x550E, 146 XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000, 147 XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002, 148 XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003, 149 XE_GUC_ACTION_ACCESS_COUNTER_NOTIFY = 0x6004, 150 XE_GUC_ACTION_TLB_INVALIDATION = 0x7000, 151 XE_GUC_ACTION_TLB_INVALIDATION_DONE = 0x7001, 152 XE_GUC_ACTION_TLB_INVALIDATION_ALL = 0x7002, 153 XE_GUC_ACTION_STATE_CAPTURE_NOTIFICATION = 0x8002, 154 XE_GUC_ACTION_NOTIFY_FLUSH_LOG_BUFFER_TO_FILE = 0x8003, 155 XE_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED = 0x8004, 156 XE_GUC_ACTION_NOTIFY_EXCEPTION = 0x8005, 157 XE_GUC_ACTION_LIMIT 158 }; 159 160 enum xe_guc_preempt_options { 161 XE_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4, 162 XE_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8, 163 }; 164 165 enum xe_guc_register_context_param_offsets { 166 XE_GUC_REGISTER_CONTEXT_DATA_0_MBZ = 0, 167 XE_GUC_REGISTER_CONTEXT_DATA_1_FLAGS, 168 XE_GUC_REGISTER_CONTEXT_DATA_2_CONTEXT_INDEX, 169 XE_GUC_REGISTER_CONTEXT_DATA_3_ENGINE_CLASS, 170 XE_GUC_REGISTER_CONTEXT_DATA_4_ENGINE_SUBMIT_MASK, 171 XE_GUC_REGISTER_CONTEXT_DATA_5_WQ_DESC_ADDR_LOWER, 172 XE_GUC_REGISTER_CONTEXT_DATA_6_WQ_DESC_ADDR_UPPER, 173 XE_GUC_REGISTER_CONTEXT_DATA_7_WQ_BUF_BASE_LOWER, 174 XE_GUC_REGISTER_CONTEXT_DATA_8_WQ_BUF_BASE_UPPER, 175 XE_GUC_REGISTER_CONTEXT_DATA_9_WQ_BUF_SIZE, 176 XE_GUC_REGISTER_CONTEXT_DATA_10_HW_LRC_ADDR, 177 XE_GUC_REGISTER_CONTEXT_MSG_LEN, 178 }; 179 180 enum xe_guc_register_context_multi_lrc_param_offsets { 181 XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_0_MBZ = 0, 182 XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_1_FLAGS, 183 XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_2_PARENT_CONTEXT, 184 XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_3_ENGINE_CLASS, 185 XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_4_ENGINE_SUBMIT_MASK, 186 XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_5_WQ_DESC_ADDR_LOWER, 187 XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_6_WQ_DESC_ADDR_UPPER, 188 XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_7_WQ_BUF_BASE_LOWER, 189 XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_8_WQ_BUF_BASE_UPPER, 190 XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_9_WQ_BUF_SIZE, 191 XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_10_NUM_CTXS, 192 XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_11_HW_LRC_ADDR, 193 XE_GUC_REGISTER_CONTEXT_MULTI_LRC_MSG_MIN_LEN = 11, 194 }; 195 196 enum xe_guc_report_status { 197 XE_GUC_REPORT_STATUS_UNKNOWN = 0x0, 198 XE_GUC_REPORT_STATUS_ACKED = 0x1, 199 XE_GUC_REPORT_STATUS_ERROR = 0x2, 200 XE_GUC_REPORT_STATUS_COMPLETE = 0x4, 201 }; 202 203 enum xe_guc_sleep_state_status { 204 XE_GUC_SLEEP_STATE_SUCCESS = 0x1, 205 XE_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2, 206 XE_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3 207 #define XE_GUC_SLEEP_STATE_INVALID_MASK 0x80000000 208 }; 209 210 #define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0) 211 #define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4 212 #define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT) 213 #define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8) 214 215 enum xe_guc_state_capture_event_status { 216 XE_GUC_STATE_CAPTURE_EVENT_STATUS_SUCCESS = 0x0, 217 XE_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE = 0x1, 218 }; 219 220 #define XE_GUC_STATE_CAPTURE_EVENT_STATUS_MASK 0x000000FF 221 #define XE_GUC_ACTION_STATE_CAPTURE_NOTIFICATION_DATA_LEN 1 222 223 #define XE_GUC_TLB_INVAL_TYPE_SHIFT 0 224 #define XE_GUC_TLB_INVAL_MODE_SHIFT 8 225 /* Flush PPC or SMRO caches along with TLB invalidation request */ 226 #define XE_GUC_TLB_INVAL_FLUSH_CACHE (1 << 31) 227 228 enum xe_guc_tlb_invalidation_type { 229 XE_GUC_TLB_INVAL_FULL = 0x0, 230 XE_GUC_TLB_INVAL_PAGE_SELECTIVE = 0x1, 231 XE_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX = 0x2, 232 XE_GUC_TLB_INVAL_GUC = 0x3, 233 }; 234 235 /* 236 * 0: Heavy mode of Invalidation: 237 * The pipeline of the engine(s) for which the invalidation is targeted to is 238 * blocked, and all the in-flight transactions are guaranteed to be Globally 239 * Observed before completing the TLB invalidation 240 * 1: Lite mode of Invalidation: 241 * TLBs of the targeted engine(s) are immediately invalidated. 242 * In-flight transactions are NOT guaranteed to be Globally Observed before 243 * completing TLB invalidation. 244 * Light Invalidation Mode is to be used only when 245 * it can be guaranteed (by SW) that the address translations remain invariant 246 * for the in-flight transactions across the TLB invalidation. In other words, 247 * this mode can be used when the TLB invalidation is intended to clear out the 248 * stale cached translations that are no longer in use. Light Invalidation Mode 249 * is much faster than the Heavy Invalidation Mode, as it does not wait for the 250 * in-flight transactions to be GOd. 251 */ 252 enum xe_guc_tlb_inval_mode { 253 XE_GUC_TLB_INVAL_MODE_HEAVY = 0x0, 254 XE_GUC_TLB_INVAL_MODE_LITE = 0x1, 255 }; 256 257 /* 258 * GuC to GuC communication (de-)registration fields: 259 */ 260 enum xe_guc_g2g_type { 261 XE_G2G_TYPE_IN = 0x0, 262 XE_G2G_TYPE_OUT, 263 XE_G2G_TYPE_LIMIT, 264 }; 265 266 #define XE_G2G_REGISTER_DEVICE REG_GENMASK(16, 16) 267 #define XE_G2G_REGISTER_TILE REG_GENMASK(15, 12) 268 #define XE_G2G_REGISTER_TYPE REG_GENMASK(11, 8) 269 #define XE_G2G_REGISTER_SIZE REG_GENMASK(7, 0) 270 271 #define XE_G2G_DEREGISTER_DEVICE REG_GENMASK(16, 16) 272 #define XE_G2G_DEREGISTER_TILE REG_GENMASK(15, 12) 273 #define XE_G2G_DEREGISTER_TYPE REG_GENMASK(11, 8) 274 275 /* invalid type for XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR */ 276 #define XE_GUC_CAT_ERR_TYPE_INVALID 0xdeadbeef 277 278 #endif 279