Home
last modified time | relevance | path

Searched defs:XCHAL_HAVE_XLT_CACHEATTR (Results 1 – 10 of 10) sorted by relevance

/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h345 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h407 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h437 #define XCHAL_HAVE_XLT_CACHEATTR 1 /* region prot. w/translation */ macro
/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h456 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h457 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h458 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h558 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/qemu/target/xtensa/core-de212/
H A Dcore-isa.h594 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h615 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h697 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro